1 /*
2  * Copyright (c) 2021 Intel Corporation
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #ifndef ZEPHYR_INCLUDE_ARCH_RISCV_ARCH_INLINES_H_
8 #define ZEPHYR_INCLUDE_ARCH_RISCV_ARCH_INLINES_H_
9 
10 #ifndef _ASMLANGUAGE
11 
12 #include <zephyr/kernel_structs.h>
13 #include "csr.h"
14 #include "reg.h"
15 
arch_proc_id(void)16 static ALWAYS_INLINE uint32_t arch_proc_id(void)
17 {
18 	return csr_read(mhartid) & ((uintptr_t)CONFIG_RISCV_HART_MASK);
19 }
20 
arch_curr_cpu(void)21 static ALWAYS_INLINE _cpu_t *arch_curr_cpu(void)
22 {
23 #if defined(CONFIG_SMP) || defined(CONFIG_USERSPACE)
24 	return (_cpu_t *)csr_read(mscratch);
25 #else
26 	return &_kernel.cpus[0];
27 #endif
28 }
29 
30 #ifdef CONFIG_RISCV_CURRENT_VIA_GP
31 
32 register struct k_thread *__arch_current_thread __asm__("gp");
33 
34 #define arch_current_thread() __arch_current_thread
35 #define arch_current_thread_set(thread) ({ __arch_current_thread = (thread); })
36 
37 #endif /* CONFIG_RISCV_CURRENT_VIA_GP */
38 
arch_num_cpus(void)39 static ALWAYS_INLINE unsigned int arch_num_cpus(void)
40 {
41 	return CONFIG_MP_MAX_NUM_CPUS;
42 }
43 
44 #endif /* !_ASMLANGUAGE */
45 #endif /* ZEPHYR_INCLUDE_ARCH_RISCV_ARCH_INLINES_H_ */
46