1 /*
2  * Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
3  * Copyright (c) 2022 IoT.bzh
4  *
5  * SPDX-License-Identifier: Apache-2.0
6  */
7 
8 #ifndef ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_A_R_ARMV8_TIMER_H_
9 #define ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_A_R_ARMV8_TIMER_H_
10 
11 #ifndef _ASMLANGUAGE
12 
13 #include <zephyr/drivers/timer/arm_arch_timer.h>
14 #include <zephyr/types.h>
15 
16 #ifdef __cplusplus
17 extern "C" {
18 #endif
19 
20 #define ARM_ARCH_TIMER_IRQ	ARM_TIMER_VIRTUAL_IRQ
21 #define ARM_ARCH_TIMER_PRIO	ARM_TIMER_VIRTUAL_PRIO
22 #define ARM_ARCH_TIMER_FLAGS	ARM_TIMER_VIRTUAL_FLAGS
23 
arm_arch_timer_init(void)24 static ALWAYS_INLINE void arm_arch_timer_init(void)
25 {
26 }
27 
arm_arch_timer_set_compare(uint64_t val)28 static ALWAYS_INLINE void arm_arch_timer_set_compare(uint64_t val)
29 {
30 	write_cntv_cval(val);
31 }
32 
arm_arch_timer_enable(unsigned char enable)33 static ALWAYS_INLINE void arm_arch_timer_enable(unsigned char enable)
34 {
35 	uint64_t cntv_ctl;
36 
37 	cntv_ctl = read_cntv_ctl();
38 
39 	if (enable) {
40 		cntv_ctl |= CNTV_CTL_ENABLE_BIT;
41 	} else {
42 		cntv_ctl &= ~CNTV_CTL_ENABLE_BIT;
43 	}
44 
45 	write_cntv_ctl(cntv_ctl);
46 }
47 
arm_arch_timer_set_irq_mask(bool mask)48 static ALWAYS_INLINE void arm_arch_timer_set_irq_mask(bool mask)
49 {
50 	uint64_t cntv_ctl;
51 
52 	cntv_ctl = read_cntv_ctl();
53 
54 	if (mask) {
55 		cntv_ctl |= CNTV_CTL_IMASK_BIT;
56 	} else {
57 		cntv_ctl &= ~CNTV_CTL_IMASK_BIT;
58 	}
59 
60 	write_cntv_ctl(cntv_ctl);
61 }
62 
arm_arch_timer_count(void)63 static ALWAYS_INLINE uint64_t arm_arch_timer_count(void)
64 {
65 	return read_cntvct();
66 }
67 
68 #ifdef __cplusplus
69 }
70 #endif
71 
72 #endif /* _ASMLANGUAGE */
73 
74 #endif /* ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_A_R_ARMV8_TIMER_H_ */
75