1 /* xtruntime-core-state.h - core state save area (used eg. by PSO) */ 2 /* $Id: //depot/rel/Foxhill/dot.8/Xtensa/OS/include/xtensa/xtruntime-core-state.h#1 $ */ 3 4 /* 5 * Copyright (c) 2012-2013 Tensilica Inc. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining 8 * a copy of this software and associated documentation files (the 9 * "Software"), to deal in the Software without restriction, including 10 * without limitation the rights to use, copy, modify, merge, publish, 11 * distribute, sublicense, and/or sell copies of the Software, and to 12 * permit persons to whom the Software is furnished to do so, subject to 13 * the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included 16 * in all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 19 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 21 * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 22 * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25 */ 26 27 #ifndef _XTOS_CORE_STATE_H_ 28 #define _XTOS_CORE_STATE_H_ 29 30 /* Import STRUCT_xxx macros for defining structures: */ 31 #include <xtensa/xtruntime-frames.h> 32 #include <xtensa/config/core.h> 33 #include <xtensa/config/tie.h> 34 #if XCHAL_HAVE_IDMA 35 #include <xtensa/idma.h> 36 #endif 37 38 //#define XTOS_PSO_TEST 1 // uncommented for internal PSO testing only 39 40 #define CORE_STATE_SIGNATURE 0xB1C5AFED // pattern that indicates state was saved 41 42 43 /* 44 * Save area for saving entire core state, such as across Power Shut-Off (PSO). 45 */ 46 47 STRUCT_BEGIN 48 STRUCT_FIELD (long,4,CS_SA_,signature) // for checking whether state was saved 49 STRUCT_FIELD (long,4,CS_SA_,restore_label) 50 STRUCT_FIELD (long,4,CS_SA_,aftersave_label) 51 STRUCT_AFIELD(long,4,CS_SA_,areg,XCHAL_NUM_AREGS) 52 #if XCHAL_HAVE_WINDOWED 53 STRUCT_AFIELD(long,4,CS_SA_,caller_regs,16) // save a max of 16 caller regs 54 STRUCT_FIELD (long,4,CS_SA_,caller_regs_saved) // flag to show if caller regs saved 55 #endif 56 #if XCHAL_HAVE_PSO_CDM 57 STRUCT_FIELD (long,4,CS_SA_,pwrctl) 58 #endif 59 #if XCHAL_HAVE_WINDOWED 60 STRUCT_FIELD (long,4,CS_SA_,windowbase) 61 STRUCT_FIELD (long,4,CS_SA_,windowstart) 62 #endif 63 STRUCT_FIELD (long,4,CS_SA_,sar) 64 #if XCHAL_HAVE_EXCEPTIONS 65 STRUCT_FIELD (long,4,CS_SA_,epc1) 66 STRUCT_FIELD (long,4,CS_SA_,ps) 67 STRUCT_FIELD (long,4,CS_SA_,excsave1) 68 # ifdef XCHAL_DOUBLEEXC_VECTOR_VADDR 69 STRUCT_FIELD (long,4,CS_SA_,depc) 70 # endif 71 #endif 72 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 2 73 STRUCT_AFIELD(long,4,CS_SA_,epc, XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI - 1) 74 STRUCT_AFIELD(long,4,CS_SA_,eps, XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI - 1) 75 STRUCT_AFIELD(long,4,CS_SA_,excsave,XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI - 1) 76 #endif 77 #if XCHAL_HAVE_LOOPS 78 STRUCT_FIELD (long,4,CS_SA_,lcount) 79 STRUCT_FIELD (long,4,CS_SA_,lbeg) 80 STRUCT_FIELD (long,4,CS_SA_,lend) 81 #endif 82 #if XCHAL_HAVE_ABSOLUTE_LITERALS 83 STRUCT_FIELD (long,4,CS_SA_,litbase) 84 #endif 85 #if XCHAL_HAVE_VECBASE 86 STRUCT_FIELD (long,4,CS_SA_,vecbase) 87 #endif 88 #if XCHAL_HAVE_S32C1I && (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RC_2009_0) /* have ATOMCTL ? */ 89 STRUCT_FIELD (long,4,CS_SA_,atomctl) 90 #endif 91 #if XCHAL_HAVE_PREFETCH 92 STRUCT_FIELD (long,4,CS_SA_,prefctl) 93 #endif 94 #if XCHAL_USE_MEMCTL 95 STRUCT_FIELD (long,4,CS_SA_,memctl) 96 #endif 97 #if XCHAL_HAVE_CCOUNT 98 STRUCT_FIELD (long,4,CS_SA_,ccount) 99 STRUCT_AFIELD(long,4,CS_SA_,ccompare, XCHAL_NUM_TIMERS) 100 #endif 101 #if XCHAL_HAVE_INTERRUPTS 102 STRUCT_FIELD (long,4,CS_SA_,intenable) 103 STRUCT_FIELD (long,4,CS_SA_,interrupt) 104 #endif 105 #if XCHAL_HAVE_DEBUG 106 STRUCT_FIELD (long,4,CS_SA_,icount) 107 STRUCT_FIELD (long,4,CS_SA_,icountlevel) 108 STRUCT_FIELD (long,4,CS_SA_,debugcause) 109 // DDR not saved 110 # if XCHAL_NUM_DBREAK 111 STRUCT_AFIELD(long,4,CS_SA_,dbreakc, XCHAL_NUM_DBREAK) 112 STRUCT_AFIELD(long,4,CS_SA_,dbreaka, XCHAL_NUM_DBREAK) 113 # endif 114 # if XCHAL_NUM_IBREAK 115 STRUCT_AFIELD(long,4,CS_SA_,ibreaka, XCHAL_NUM_IBREAK) 116 STRUCT_FIELD (long,4,CS_SA_,ibreakenable) 117 # endif 118 #endif 119 #if XCHAL_NUM_MISC_REGS 120 STRUCT_AFIELD(long,4,CS_SA_,misc,XCHAL_NUM_MISC_REGS) 121 #endif 122 #if XCHAL_HAVE_MEM_ECC_PARITY 123 STRUCT_FIELD (long,4,CS_SA_,mepc) 124 STRUCT_FIELD (long,4,CS_SA_,meps) 125 STRUCT_FIELD (long,4,CS_SA_,mesave) 126 STRUCT_FIELD (long,4,CS_SA_,mesr) 127 STRUCT_FIELD (long,4,CS_SA_,mecr) 128 STRUCT_FIELD (long,4,CS_SA_,mevaddr) 129 #endif 130 131 /* We put this ahead of TLB and other TIE state, 132 to keep it within S32I/L32I offset range. */ 133 #if XCHAL_HAVE_CP 134 STRUCT_FIELD (long,4,CS_SA_,cpenable) 135 #endif 136 137 /* TLB state */ 138 #if XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR 139 STRUCT_AFIELD(long,4,CS_SA_,tlbs,8*2) 140 #endif 141 #if XCHAL_HAVE_PTP_MMU 142 /* Compute number of auto-refill (ARF) entries as max of I and D, 143 to simplify TLB save logic. On the unusual configs with 144 ITLB ARF != DTLB ARF entries, we'll just end up 145 saving/restoring some extra entries redundantly. */ 146 # if XCHAL_DTLB_ARF_ENTRIES_LOG2 + XCHAL_ITLB_ARF_ENTRIES_LOG2 > 4 147 # define ARF_ENTRIES 8 148 # else 149 # define ARF_ENTRIES 4 150 # endif 151 STRUCT_FIELD (long,4,CS_SA_,ptevaddr) 152 STRUCT_FIELD (long,4,CS_SA_,rasid) 153 STRUCT_FIELD (long,4,CS_SA_,dtlbcfg) 154 STRUCT_FIELD (long,4,CS_SA_,itlbcfg) 155 /*** WARNING: past this point, field offsets may be larger than S32I/L32I range ***/ 156 STRUCT_AFIELD(long,4,CS_SA_,tlbs,((4*ARF_ENTRIES+4)*2+3)*2) 157 # if XCHAL_HAVE_SPANNING_WAY /* MMU v3 */ 158 STRUCT_AFIELD(long,4,CS_SA_,tlbs_ways56,(4+8)*2*2) 159 # endif 160 #endif 161 /* MPU state */ 162 #if XCHAL_HAVE_MPU 163 STRUCT_AFIELD(long,4,CS_SA_,mpuentry,8*XCHAL_MPU_ENTRIES) 164 STRUCT_FIELD (long,4,CS_SA_,cacheadrdis) 165 #endif 166 167 #if XCHAL_HAVE_IDMA 168 STRUCT_AFIELD(long,4,CS_SA_,idmaregs, IDMA_PSO_SAVE_SIZE) 169 #endif 170 171 /* TIE state */ 172 /* NOTE: NCP area is aligned to XCHAL_TOTAL_SA_ALIGN not XCHAL_NCP_SA_ALIGN, 173 because the offsets of all subsequent coprocessor save areas are relative 174 to the NCP save area. */ 175 STRUCT_AFIELD_A(char,1,XCHAL_TOTAL_SA_ALIGN,CS_SA_,ncp,XCHAL_NCP_SA_SIZE) 176 #if XCHAL_HAVE_CP 177 #if XCHAL_CP0_SA_SIZE > 0 178 STRUCT_AFIELD_A(char,1,XCHAL_CP0_SA_ALIGN,CS_SA_,cp0,XCHAL_CP0_SA_SIZE) 179 #endif 180 #if XCHAL_CP1_SA_SIZE > 0 181 STRUCT_AFIELD_A(char,1,XCHAL_CP1_SA_ALIGN,CS_SA_,cp1,XCHAL_CP1_SA_SIZE) 182 #endif 183 #if XCHAL_CP2_SA_SIZE > 0 184 STRUCT_AFIELD_A(char,1,XCHAL_CP2_SA_ALIGN,CS_SA_,cp2,XCHAL_CP2_SA_SIZE) 185 #endif 186 #if XCHAL_CP3_SA_SIZE > 0 187 STRUCT_AFIELD_A(char,1,XCHAL_CP3_SA_ALIGN,CS_SA_,cp3,XCHAL_CP3_SA_SIZE) 188 #endif 189 #if XCHAL_CP4_SA_SIZE > 0 190 STRUCT_AFIELD_A(char,1,XCHAL_CP4_SA_ALIGN,CS_SA_,cp4,XCHAL_CP4_SA_SIZE) 191 #endif 192 #if XCHAL_CP5_SA_SIZE > 0 193 STRUCT_AFIELD_A(char,1,XCHAL_CP5_SA_ALIGN,CS_SA_,cp5,XCHAL_CP5_SA_SIZE) 194 #endif 195 #if XCHAL_CP6_SA_SIZE > 0 196 STRUCT_AFIELD_A(char,1,XCHAL_CP6_SA_ALIGN,CS_SA_,cp6,XCHAL_CP6_SA_SIZE) 197 #endif 198 #if XCHAL_CP7_SA_SIZE > 0 199 STRUCT_AFIELD_A(char,1,XCHAL_CP7_SA_ALIGN,CS_SA_,cp7,XCHAL_CP7_SA_SIZE) 200 #endif 201 //STRUCT_AFIELD_A(char,1,XCHAL_CP8_SA_ALIGN,CS_SA_,cp8,XCHAL_CP8_SA_SIZE) 202 //STRUCT_AFIELD_A(char,1,XCHAL_CP9_SA_ALIGN,CS_SA_,cp9,XCHAL_CP9_SA_SIZE) 203 //STRUCT_AFIELD_A(char,1,XCHAL_CP10_SA_ALIGN,CS_SA_,cp10,XCHAL_CP10_SA_SIZE) 204 //STRUCT_AFIELD_A(char,1,XCHAL_CP11_SA_ALIGN,CS_SA_,cp11,XCHAL_CP11_SA_SIZE) 205 //STRUCT_AFIELD_A(char,1,XCHAL_CP12_SA_ALIGN,CS_SA_,cp12,XCHAL_CP12_SA_SIZE) 206 //STRUCT_AFIELD_A(char,1,XCHAL_CP13_SA_ALIGN,CS_SA_,cp13,XCHAL_CP13_SA_SIZE) 207 //STRUCT_AFIELD_A(char,1,XCHAL_CP14_SA_ALIGN,CS_SA_,cp14,XCHAL_CP14_SA_SIZE) 208 //STRUCT_AFIELD_A(char,1,XCHAL_CP15_SA_ALIGN,CS_SA_,cp15,XCHAL_CP15_SA_SIZE) 209 #endif 210 211 STRUCT_END(XtosCoreState) 212 213 214 215 // These are part of non-coprocessor state (ncp): 216 #if XCHAL_HAVE_MAC16 217 //STRUCT_FIELD (long,4,CS_SA_,acclo) 218 //STRUCT_FIELD (long,4,CS_SA_,acchi) 219 //STRUCT_AFIELD(long,4,CS_SA_,mr, 4) 220 #endif 221 #if XCHAL_HAVE_THREADPTR 222 //STRUCT_FIELD (long,4,CS_SA_,threadptr) 223 #endif 224 #if XCHAL_HAVE_S32C1I 225 //STRUCT_FIELD (long,4,CS_SA_,scompare1) 226 #endif 227 #if XCHAL_HAVE_BOOLEANS 228 //STRUCT_FIELD (long,4,CS_SA_,br) 229 #endif 230 231 // Not saved: 232 // EXCCAUSE ?? 233 // DEBUGCAUSE ?? 234 // EXCVADDR ?? 235 // DDR 236 // INTERRUPT 237 // ... locked cache lines ... 238 239 #endif /* _XTOS_CORE_STATE_H_ */ 240 241
