1/* 2 * Copyright (c) 2016 Cadence Design Systems, Inc. 3 * SPDX-License-Identifier: Apache-2.0 4 */ 5 6/** 7 * @file 8 * @brief Linker command/script file 9 * 10 * Linker script for the Xtensa platform. 11 */ 12 13#include <zephyr/linker/sections.h> 14 15#include <zephyr/devicetree.h> 16#include <zephyr/linker/linker-defs.h> 17#include <zephyr/linker/linker-tool.h> 18 19#define RAMABLE_REGION RAM :sram0_phdr 20#define ROMABLE_REGION srom1_seg :srom1_phdr 21 22MEMORY 23{ 24 dram1_0_seg : org = 0x3FFC0000, len = 0x20000 25 dram0_0_seg : org = 0x3FFE0000, len = 0x20000 26 iram0_0_seg : org = 0x40000000, len = 0x178 27 iram0_1_seg : org = 0x40000178, len = 0x8 28 iram0_2_seg : org = 0x40000180, len = 0x38 29 iram0_3_seg : org = 0x400001B8, len = 0x8 30 iram0_4_seg : org = 0x400001C0, len = 0x38 31 iram0_5_seg : org = 0x400001F8, len = 0x8 32 iram0_6_seg : org = 0x40000200, len = 0x38 33 iram0_7_seg : org = 0x40000238, len = 0x8 34 iram0_8_seg : org = 0x40000240, len = 0x38 35 iram0_9_seg : org = 0x40000278, len = 0x8 36 iram0_10_seg : org = 0x40000280, len = 0x38 37 iram0_11_seg : org = 0x400002B8, len = 0x8 38 iram0_12_seg : org = 0x400002C0, len = 0x38 39 iram0_13_seg : org = 0x400002F8, len = 0x8 40 iram0_14_seg : org = 0x40000300, len = 0x38 41 iram0_15_seg : org = 0x40000338, len = 0x8 42 iram0_16_seg : org = 0x40000340, len = 0x38 43 iram0_17_seg : org = 0x40000378, len = 0x48 44 iram0_18_seg : org = 0x400003C0, len = 0x40 45 iram0_19_seg : org = 0x40000400, len = 0x1FC00 46 srom0_seg : org = 0x50000000, len = 0x300 47 srom1_seg : org = 0x50000300, len = 0xFFFD00 48 RAM : org = 0x60000000, len = 0x4000000 49#ifdef CONFIG_GEN_ISR_TABLES 50 IDT_LIST : org = 0x3ffbe000, len = 0x2000 51#endif 52} 53 54PHDRS 55{ 56 dram1_0_phdr PT_LOAD; 57 dram1_0_bss_phdr PT_LOAD; 58 dram0_0_phdr PT_LOAD; 59 dram0_0_bss_phdr PT_LOAD; 60 iram0_0_phdr PT_LOAD; 61 iram0_1_phdr PT_LOAD; 62 iram0_2_phdr PT_LOAD; 63 iram0_3_phdr PT_LOAD; 64 iram0_4_phdr PT_LOAD; 65 iram0_5_phdr PT_LOAD; 66 iram0_6_phdr PT_LOAD; 67 iram0_7_phdr PT_LOAD; 68 iram0_8_phdr PT_LOAD; 69 iram0_9_phdr PT_LOAD; 70 iram0_10_phdr PT_LOAD; 71 iram0_11_phdr PT_LOAD; 72 iram0_12_phdr PT_LOAD; 73 iram0_13_phdr PT_LOAD; 74 iram0_14_phdr PT_LOAD; 75 iram0_15_phdr PT_LOAD; 76 iram0_16_phdr PT_LOAD; 77 iram0_17_phdr PT_LOAD; 78 iram0_18_phdr PT_LOAD; 79 iram0_19_phdr PT_LOAD; 80 srom0_phdr PT_LOAD; 81 srom1_phdr PT_LOAD; 82 sram0_phdr PT_LOAD; 83 sram0_bss_phdr PT_LOAD; 84} 85 86 87/* Default entry point: */ 88ENTRY(CONFIG_KERNEL_ENTRY) 89 90/* Memory boundary addresses: */ 91_memmap_mem_dram1_start = 0x3ffc0000; 92_memmap_mem_dram1_end = 0x3ffe0000; 93_memmap_mem_dram0_start = 0x3ffe0000; 94_memmap_mem_dram0_end = 0x40000000; 95_memmap_mem_iram0_start = 0x40000000; 96_memmap_mem_iram0_end = 0x40020000; 97_memmap_mem_srom_start = 0x50000000; 98_memmap_mem_srom_end = 0x51000000; 99_memmap_mem_sram_start = 0x60000000; 100_memmap_mem_sram_end = 0x64000000; 101 102/* Memory segment boundary addresses: */ 103_memmap_seg_dram1_0_start = 0x3ffc0000; 104_memmap_seg_dram1_0_max = 0x3ffe0000; 105_memmap_seg_dram0_0_start = 0x3ffe0000; 106_memmap_seg_dram0_0_max = 0x40000000; 107_memmap_seg_iram0_0_start = 0x40000000; 108_memmap_seg_iram0_0_max = 0x40000178; 109_memmap_seg_iram0_1_start = 0x40000178; 110_memmap_seg_iram0_1_max = 0x40000180; 111_memmap_seg_iram0_2_start = 0x40000180; 112_memmap_seg_iram0_2_max = 0x400001b8; 113_memmap_seg_iram0_3_start = 0x400001b8; 114_memmap_seg_iram0_3_max = 0x400001c0; 115_memmap_seg_iram0_4_start = 0x400001c0; 116_memmap_seg_iram0_4_max = 0x400001f8; 117_memmap_seg_iram0_5_start = 0x400001f8; 118_memmap_seg_iram0_5_max = 0x40000200; 119_memmap_seg_iram0_6_start = 0x40000200; 120_memmap_seg_iram0_6_max = 0x40000238; 121_memmap_seg_iram0_7_start = 0x40000238; 122_memmap_seg_iram0_7_max = 0x40000240; 123_memmap_seg_iram0_8_start = 0x40000240; 124_memmap_seg_iram0_8_max = 0x40000278; 125_memmap_seg_iram0_9_start = 0x40000278; 126_memmap_seg_iram0_9_max = 0x40000280; 127_memmap_seg_iram0_10_start = 0x40000280; 128_memmap_seg_iram0_10_max = 0x400002b8; 129_memmap_seg_iram0_11_start = 0x400002b8; 130_memmap_seg_iram0_11_max = 0x400002c0; 131_memmap_seg_iram0_12_start = 0x400002c0; 132_memmap_seg_iram0_12_max = 0x400002f8; 133_memmap_seg_iram0_13_start = 0x400002f8; 134_memmap_seg_iram0_13_max = 0x40000300; 135_memmap_seg_iram0_14_start = 0x40000300; 136_memmap_seg_iram0_14_max = 0x40000338; 137_memmap_seg_iram0_15_start = 0x40000338; 138_memmap_seg_iram0_15_max = 0x40000340; 139_memmap_seg_iram0_16_start = 0x40000340; 140_memmap_seg_iram0_16_max = 0x40000378; 141_memmap_seg_iram0_17_start = 0x40000378; 142_memmap_seg_iram0_17_max = 0x400003c0; 143_memmap_seg_iram0_18_start = 0x400003c0; 144_memmap_seg_iram0_18_max = 0x40000400; 145_memmap_seg_iram0_19_start = 0x40000400; 146_memmap_seg_iram0_19_max = 0x40020000; 147_memmap_seg_srom0_start = 0x50000000; 148_memmap_seg_srom0_max = 0x50000300; 149_memmap_seg_srom1_start = 0x50000300; 150_memmap_seg_srom1_max = 0x51000000; 151_memmap_seg_sram0_start = 0x60000000; 152_memmap_seg_sram0_max = 0x64000000; 153 154_rom_store_table = 0; 155PROVIDE(_memmap_vecbase_reset = 0x40000000); 156PROVIDE(_memmap_reset_vector = 0x50000000); 157/* Various memory-map dependent cache attribute settings: */ 158_memmap_cacheattr_wb_base = 0x00001110; 159_memmap_cacheattr_wt_base = 0x00001110; 160_memmap_cacheattr_bp_base = 0x00002220; 161_memmap_cacheattr_unused_mask = 0xFFFF000F; 162_memmap_cacheattr_wb_trapnull = 0x2222111F; 163_memmap_cacheattr_wba_trapnull = 0x2222111F; 164_memmap_cacheattr_wbna_trapnull = 0x2222111F; 165_memmap_cacheattr_wt_trapnull = 0x2222111F; 166_memmap_cacheattr_bp_trapnull = 0x2222222F; 167_memmap_cacheattr_wb_strict = 0xFFFF111F; 168_memmap_cacheattr_wt_strict = 0xFFFF111F; 169_memmap_cacheattr_bp_strict = 0xFFFF222F; 170_memmap_cacheattr_wb_allvalid = 0x22221112; 171_memmap_cacheattr_wt_allvalid = 0x22221112; 172_memmap_cacheattr_bp_allvalid = 0x22222222; 173PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull); 174 175SECTIONS 176{ 177 178#include <zephyr/linker/rel-sections.ld> 179 180#ifdef CONFIG_GEN_ISR_TABLES 181#include <zephyr/linker/intlist.ld> 182#endif 183 184 .dram1.rodata : ALIGN(4) 185 { 186 _dram1_rodata_start = ABSOLUTE(.); 187 *(.dram1.rodata) 188 _dram1_rodata_end = ABSOLUTE(.); 189 } >dram1_0_seg :dram1_0_phdr 190 191 .dram1.literal : ALIGN(4) 192 { 193 _dram1_literal_start = ABSOLUTE(.); 194 *(.dram1.literal) 195 _dram1_literal_end = ABSOLUTE(.); 196 } >dram1_0_seg :dram1_0_phdr 197 198 .dram1.data : ALIGN(4) 199 { 200 _dram1_data_start = ABSOLUTE(.); 201 *(.dram1.data) 202 _dram1_data_end = ABSOLUTE(.); 203 } >dram1_0_seg :dram1_0_phdr 204 205 .dram1.bss (NOLOAD) : ALIGN(8) 206 { 207 . = ALIGN (8); 208 _dram1_bss_start = ABSOLUTE(.); 209 *(.dram1.bss) 210 . = ALIGN (8); 211 _dram1_bss_end = ABSOLUTE(.); 212 _memmap_seg_dram1_0_end = ALIGN(0x8); 213 } >dram1_0_seg :dram1_0_bss_phdr 214 215 .dram0.rodata : ALIGN(4) 216 { 217 _dram0_rodata_start = ABSOLUTE(.); 218 *(.dram0.rodata) 219 _dram0_rodata_end = ABSOLUTE(.); 220 } >dram0_0_seg :dram0_0_phdr 221 222 .dram0.literal : ALIGN(4) 223 { 224 _dram0_literal_start = ABSOLUTE(.); 225 *(.dram0.literal) 226 _dram0_literal_end = ABSOLUTE(.); 227 } >dram0_0_seg :dram0_0_phdr 228 229 .dram0.data : ALIGN(4) 230 { 231 _dram0_data_start = ABSOLUTE(.); 232 *(.dram0.data) 233 _dram0_data_end = ABSOLUTE(.); 234 } >dram0_0_seg :dram0_0_phdr 235 236 .dram0.bss (NOLOAD) : ALIGN(8) 237 { 238 . = ALIGN (8); 239 _dram0_bss_start = ABSOLUTE(.); 240 *(.dram0.bss) 241 . = ALIGN (8); 242 _dram0_bss_end = ABSOLUTE(.); 243 _memmap_seg_dram0_0_end = ALIGN(0x8); 244 } >dram0_0_seg :dram0_0_bss_phdr 245 246 .WindowVectors.text : ALIGN(4) 247 { 248 _WindowVectors_text_start = ABSOLUTE(.); 249 KEEP (*(.WindowVectors.text)) 250 _WindowVectors_text_end = ABSOLUTE(.); 251 _memmap_seg_iram0_0_end = ALIGN(0x8); 252 } >iram0_0_seg :iram0_0_phdr 253 254 .Level2InterruptVector.literal : ALIGN(4) 255 { 256 _Level2InterruptVector_literal_start = ABSOLUTE(.); 257 *(.Level2InterruptVector.literal) 258 _Level2InterruptVector_literal_end = ABSOLUTE(.); 259 _memmap_seg_iram0_1_end = ALIGN(0x8); 260 } >iram0_1_seg :iram0_1_phdr 261 262 .Level2InterruptVector.text : ALIGN(4) 263 { 264 _Level2InterruptVector_text_start = ABSOLUTE(.); 265 KEEP (*(.Level2InterruptVector.text)) 266 _Level2InterruptVector_text_end = ABSOLUTE(.); 267 _memmap_seg_iram0_2_end = ALIGN(0x8); 268 } >iram0_2_seg :iram0_2_phdr 269 270 .Level3InterruptVector.literal : ALIGN(4) 271 { 272 _Level3InterruptVector_literal_start = ABSOLUTE(.); 273 *(.Level3InterruptVector.literal) 274 _Level3InterruptVector_literal_end = ABSOLUTE(.); 275 _memmap_seg_iram0_3_end = ALIGN(0x8); 276 } >iram0_3_seg :iram0_3_phdr 277 278 .Level3InterruptVector.text : ALIGN(4) 279 { 280 _Level3InterruptVector_text_start = ABSOLUTE(.); 281 KEEP (*(.Level3InterruptVector.text)) 282 _Level3InterruptVector_text_end = ABSOLUTE(.); 283 _memmap_seg_iram0_4_end = ALIGN(0x8); 284 } >iram0_4_seg :iram0_4_phdr 285 286 .Level4InterruptVector.literal : ALIGN(4) 287 { 288 _Level4InterruptVector_literal_start = ABSOLUTE(.); 289 *(.Level4InterruptVector.literal) 290 _Level4InterruptVector_literal_end = ABSOLUTE(.); 291 _memmap_seg_iram0_5_end = ALIGN(0x8); 292 } >iram0_5_seg :iram0_5_phdr 293 294 .Level4InterruptVector.text : ALIGN(4) 295 { 296 _Level4InterruptVector_text_start = ABSOLUTE(.); 297 KEEP (*(.Level4InterruptVector.text)) 298 _Level4InterruptVector_text_end = ABSOLUTE(.); 299 _memmap_seg_iram0_6_end = ALIGN(0x8); 300 } >iram0_6_seg :iram0_6_phdr 301 302 .Level5InterruptVector.literal : ALIGN(4) 303 { 304 _Level5InterruptVector_literal_start = ABSOLUTE(.); 305 *(.Level5InterruptVector.literal) 306 _Level5InterruptVector_literal_end = ABSOLUTE(.); 307 _memmap_seg_iram0_7_end = ALIGN(0x8); 308 } >iram0_7_seg :iram0_7_phdr 309 310 .Level5InterruptVector.text : ALIGN(4) 311 { 312 _Level5InterruptVector_text_start = ABSOLUTE(.); 313 KEEP (*(.Level5InterruptVector.text)) 314 _Level5InterruptVector_text_end = ABSOLUTE(.); 315 _memmap_seg_iram0_8_end = ALIGN(0x8); 316 } >iram0_8_seg :iram0_8_phdr 317 318 .DebugExceptionVector.literal : ALIGN(4) 319 { 320 _DebugExceptionVector_literal_start = ABSOLUTE(.); 321 *(.DebugExceptionVector.literal) 322 _DebugExceptionVector_literal_end = ABSOLUTE(.); 323 _memmap_seg_iram0_9_end = ALIGN(0x8); 324 } >iram0_9_seg :iram0_9_phdr 325 326 .DebugExceptionVector.text : ALIGN(4) 327 { 328 _DebugExceptionVector_text_start = ABSOLUTE(.); 329 KEEP (*(.DebugExceptionVector.text)) 330 _DebugExceptionVector_text_end = ABSOLUTE(.); 331 _memmap_seg_iram0_10_end = ALIGN(0x8); 332 } >iram0_10_seg :iram0_10_phdr 333 334 .NMIExceptionVector.literal : ALIGN(4) 335 { 336 _NMIExceptionVector_literal_start = ABSOLUTE(.); 337 *(.NMIExceptionVector.literal) 338 _NMIExceptionVector_literal_end = ABSOLUTE(.); 339 _memmap_seg_iram0_11_end = ALIGN(0x8); 340 } >iram0_11_seg :iram0_11_phdr 341 342 .NMIExceptionVector.text : ALIGN(4) 343 { 344 _NMIExceptionVector_text_start = ABSOLUTE(.); 345 KEEP (*(.NMIExceptionVector.text)) 346 _NMIExceptionVector_text_end = ABSOLUTE(.); 347 _memmap_seg_iram0_12_end = ALIGN(0x8); 348 } >iram0_12_seg :iram0_12_phdr 349 350 .KernelExceptionVector.literal : ALIGN(4) 351 { 352 _KernelExceptionVector_literal_start = ABSOLUTE(.); 353 *(.KernelExceptionVector.literal) 354 _KernelExceptionVector_literal_end = ABSOLUTE(.); 355 _memmap_seg_iram0_13_end = ALIGN(0x8); 356 } >iram0_13_seg :iram0_13_phdr 357 358 .KernelExceptionVector.text : ALIGN(4) 359 { 360 _KernelExceptionVector_text_start = ABSOLUTE(.); 361 KEEP (*(.KernelExceptionVector.text)) 362 _KernelExceptionVector_text_end = ABSOLUTE(.); 363 _memmap_seg_iram0_14_end = ALIGN(0x8); 364 } >iram0_14_seg :iram0_14_phdr 365 366 .UserExceptionVector.literal : ALIGN(4) 367 { 368 _UserExceptionVector_literal_start = ABSOLUTE(.); 369 *(.UserExceptionVector.literal) 370 _UserExceptionVector_literal_end = ABSOLUTE(.); 371 _memmap_seg_iram0_15_end = ALIGN(0x8); 372 } >iram0_15_seg :iram0_15_phdr 373 374 .UserExceptionVector.text : ALIGN(4) 375 { 376 _UserExceptionVector_text_start = ABSOLUTE(.); 377 KEEP (*(.UserExceptionVector.text)) 378 _UserExceptionVector_text_end = ABSOLUTE(.); 379 _memmap_seg_iram0_16_end = ALIGN(0x8); 380 } >iram0_16_seg :iram0_16_phdr 381 382 .DoubleExceptionVector.literal : ALIGN(4) 383 { 384 _DoubleExceptionVector_literal_start = ABSOLUTE(.); 385 *(.DoubleExceptionVector.literal) 386 _DoubleExceptionVector_literal_end = ABSOLUTE(.); 387 _memmap_seg_iram0_17_end = ALIGN(0x8); 388 } >iram0_17_seg :iram0_17_phdr 389 390 .DoubleExceptionVector.text : ALIGN(4) 391 { 392 _DoubleExceptionVector_text_start = ABSOLUTE(.); 393 KEEP (*(.DoubleExceptionVector.text)) 394 _DoubleExceptionVector_text_end = ABSOLUTE(.); 395 _memmap_seg_iram0_18_end = ALIGN(0x8); 396 } >iram0_18_seg :iram0_18_phdr 397 398 .iram0.text : ALIGN(4) 399 { 400 _iram0_text_start = ABSOLUTE(.); 401 *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text) 402 _iram0_text_end = ABSOLUTE(.); 403 _memmap_seg_iram0_19_end = ALIGN(0x8); 404 } >iram0_19_seg :iram0_19_phdr 405 406 .ResetVector.text : ALIGN(4) 407 { 408 __rom_region_start = ABSOLUTE(.); 409 _ResetVector_text_start = ABSOLUTE(.); 410 KEEP (*(.ResetVector.text)) 411 _ResetVector_text_end = ABSOLUTE(.); 412 _memmap_seg_srom0_end = ALIGN(0x8); 413 } >srom0_seg :srom0_phdr 414 415#ifdef CONFIG_CODE_DATA_RELOCATION 416#include <linker_relocate.ld> 417#endif 418 419 .srom.rodata : ALIGN(4) 420 { 421 _srom_rodata_start = ABSOLUTE(.); 422 *(.srom.rodata) 423 _srom_rodata_end = ABSOLUTE(.); 424 } >srom1_seg :srom1_phdr 425 426 .srom.text : ALIGN(4) 427 { 428 _srom_text_start = ABSOLUTE(.); 429 *(.srom.literal .srom.text) 430 _srom_text_end = ABSOLUTE(.); 431 _memmap_seg_srom1_end = ALIGN(0x8); 432 __rom_region_end = ABSOLUTE(.); 433 } >srom1_seg :srom1_phdr 434 435 .sram.rodata : ALIGN(4) 436 { 437 _image_ram_start = ABSOLUTE(.); 438 _sram_rodata_start = ABSOLUTE(.); 439 *(.sram.rodata) 440 _sram_rodata_end = ABSOLUTE(.); 441 } >RAM :sram0_phdr 442 443#include <zephyr/linker/common-rom.ld> 444 445 .rodata : ALIGN(4) 446 { 447 __rodata_region_start = ABSOLUTE(.); 448 *(.rodata) 449 *(.rodata.*) 450 *(.gnu.linkonce.r.*) 451 *(.rodata1) 452 453 . = ALIGN(4); 454 #include <snippets-rodata.ld> 455 . = ALIGN(4); 456 457 __XT_EXCEPTION_TABLE__ = ABSOLUTE(.); 458 KEEP (*(.xt_except_table)) 459 KEEP (*(.gcc_except_table .gcc_except_table.*)) 460 *(.gnu.linkonce.e.*) 461 *(.gnu.version_r) 462 KEEP (*(.eh_frame)) 463 /* C++ constructor and destructor tables, properly ordered: */ 464 KEEP (*crtbegin.o(.ctors)) 465 KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) 466 KEEP (*(SORT(.ctors.*))) 467 KEEP (*(.ctors)) 468 KEEP (*crtbegin.o(.dtors)) 469 KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) 470 KEEP (*(SORT(.dtors.*))) 471 KEEP (*(.dtors)) 472 /* C++ exception handlers table: */ 473 __XT_EXCEPTION_DESCS__ = ABSOLUTE(.); 474 *(.xt_except_desc) 475 *(.gnu.linkonce.h.*) 476 __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); 477 *(.xt_except_desc_end) 478 *(.dynamic) 479 *(.gnu.version_d) 480 . = ALIGN(4); /* this table MUST be 4-byte aligned */ 481 _bss_table_start = ABSOLUTE(.); 482 LONG(_dram1_bss_start) 483 LONG(_dram1_bss_end) 484 LONG(_dram0_bss_start) 485 LONG(_dram0_bss_end) 486 LONG(_bss_start) 487 LONG(_bss_end) 488 _bss_table_end = ABSOLUTE(.); 489 __rodata_region_end = ABSOLUTE(.); 490 } >RAM :sram0_phdr 491 492 .sram.text : ALIGN(4) 493 { 494 _sram_text_start = ABSOLUTE(.); 495 *(.sram.literal .sram.text) 496 _sram_text_end = ABSOLUTE(.); 497 } >RAM :sram0_phdr 498 499 __text_region_start = ALIGN(4); 500 .text : ALIGN(4) 501 { 502 _stext = .; 503 _text_start = ABSOLUTE(.); 504 *(.entry.text) 505 *(.init.literal) 506 KEEP(*(.init)) 507 *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) 508 *(.fini.literal) 509 KEEP(*(.fini)) 510 *(.gnu.version) 511 _text_end = ABSOLUTE(.); 512 _etext = .; 513 } >RAM :sram0_phdr 514 __text_region_end = .; 515 516 .sram.data : ALIGN(4) 517 { 518 _sram_data_start = ABSOLUTE(.); 519 *(.sram.data) 520 _sram_data_end = ABSOLUTE(.); 521 } >RAM :sram0_phdr 522 523 .noinit : ALIGN(4) 524 { 525 *(.noinit) 526 *(.noinit.*) 527 } >RAM :sram0_phdr 528 529#include <snippets-sections.ld> 530 531 .data : ALIGN(4) 532 { 533 __data_start = ABSOLUTE(.); 534 *(.data) 535 *(.data.*) 536 *(.gnu.linkonce.d.*) 537 KEEP(*(.gnu.linkonce.d.*personality*)) 538 *(.data1) 539 *(.sdata) 540 *(.sdata.*) 541 *(.gnu.linkonce.s.*) 542 *(.sdata2) 543 *(.sdata2.*) 544 *(.gnu.linkonce.s2.*) 545 KEEP(*(.jcr)) 546 547 . = ALIGN(4); 548 #include <snippets-rwdata.ld> 549 . = ALIGN(4); 550 551#ifdef CONFIG_CODE_DATA_RELOCATION 552#include <linker_sram_data_relocate.ld> 553#endif 554 . = ALIGN(4); 555 556 __data_end = ABSOLUTE(.); 557 } >RAM :sram0_phdr 558 559#include <snippets-data-sections.ld> 560 561#include <zephyr/linker/common-ram.ld> 562 563 .tm_clone_table : 564 { 565 *(.tm_clone_table) 566 } >RAM :sram0_phdr 567 568#include <snippets-ram-sections.ld> 569 570 .bss (NOLOAD) : ALIGN(8) 571 { 572 . = ALIGN (8); 573 _bss_start = ABSOLUTE(.); 574 *(.dynsbss) 575 *(.sbss) 576 *(.sbss.*) 577 *(.gnu.linkonce.sb.*) 578 *(.scommon) 579 *(.sbss2) 580 *(.sbss2.*) 581 *(.gnu.linkonce.sb2.*) 582 *(.dynbss) 583 *(.bss) 584 *(.bss.*) 585 *(.gnu.linkonce.b.*) 586 *(COMMON) 587 *(.sram.bss) 588#ifdef CONFIG_CODE_DATA_RELOCATION 589#include <linker_sram_bss_relocate.ld> 590#endif 591 . = ALIGN (8); 592 _bss_end = ABSOLUTE(.); 593 _end = ALIGN(0x8); 594 _image_ram_end = ABSOLUTE(.); 595 PROVIDE(end = ALIGN(0x8)); 596 _stack_sentry = ALIGN(0x8); 597 _memmap_seg_sram0_end = ALIGN(0x8); 598 } >RAM :sram0_bss_phdr 599 __stack = 0x64000000; 600 _heap_sentry = 0x64000000; 601 .comment 0 : { *(.comment) } 602 .debug 0 : { *(.debug) } 603 .line 0 : { *(.line) } 604 .debug_srcinfo 0 : { *(.debug_srcinfo) } 605 .debug_sfnames 0 : { *(.debug_sfnames) } 606 .debug_aranges 0 : { *(.debug_aranges) } 607 .debug_pubnames 0 : { *(.debug_pubnames) } 608 .debug_info 0 : { *(.debug_info) } 609 .debug_abbrev 0 : { *(.debug_abbrev) } 610 .debug_line 0 : { *(.debug_line) } 611 .debug_frame 0 : { *(.debug_frame) } 612 .debug_str 0 : { *(.debug_str) } 613 .debug_loc 0 : { *(.debug_loc) } 614 .debug_macinfo 0 : { *(.debug_macinfo) } 615 .debug_weaknames 0 : { *(.debug_weaknames) } 616 .debug_funcnames 0 : { *(.debug_funcnames) } 617 .debug_typenames 0 : { *(.debug_typenames) } 618 .debug_varnames 0 : { *(.debug_varnames) } 619 .debug_ranges 0 : { *(.debug_ranges) } 620 .xtensa.info 0 : { *(.xtensa.info) } 621 .xt.insn 0 : 622 { 623 KEEP (*(.xt.insn)) 624 KEEP (*(.gnu.linkonce.x.*)) 625 } 626 .xt.prop 0 : 627 { 628 KEEP (*(.xt.prop)) 629 KEEP (*(.xt.prop.*)) 630 KEEP (*(.gnu.linkonce.prop.*)) 631 } 632 .xt.lit 0 : 633 { 634 KEEP (*(.xt.lit)) 635 KEEP (*(.xt.lit.*)) 636 KEEP (*(.gnu.linkonce.p.*)) 637 } 638 .debug.xt.callgraph 0 : 639 { 640 KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*)) 641 } 642} 643
