1 /* xer-constants.h -- various constants describing external registers accessed 2 via wer and rer. 3 4 TODO: find a better prefix. Also conditionalize certain constants based 5 on number of cores and interrupts actually present. 6 */ 7 8 /* 9 * Copyright (c) 1999-2008 Tensilica Inc. 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining 12 * a copy of this software and associated documentation files (the 13 * "Software"), to deal in the Software without restriction, including 14 * without limitation the rights to use, copy, modify, merge, publish, 15 * distribute, sublicense, and/or sell copies of the Software, and to 16 * permit persons to whom the Software is furnished to do so, subject to 17 * the following conditions: 18 * 19 * The above copyright notice and this permission notice shall be included 20 * in all copies or substantial portions of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 23 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 25 * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 26 * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 27 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 28 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 29 */ 30 31 #include <xtensa/config/core.h> 32 33 #define NUM_INTERRUPTS 27 34 #define NUM_CORES 4 35 36 /* Routing of NMI (BInterrupt2) and interrupts 0..n-1 (BInterrupt3+) 37 RER reads 38 WER writes 39 */ 40 41 #define XER_MIROUT 0x0000 42 #define XER_MIROUT_LAST (XER_MIROUT + NUM_INTERRUPTS) 43 44 45 /* IPI to core M (all 16 causes). 46 47 RER reads 48 WER clears 49 */ 50 #define XER_MIPICAUSE 0x0100 51 #define XER_MIPICAUSE_FIELD_A_FIRST 0x0 52 #define XER_MIPICAUSE_FIELD_A_LAST 0x0 53 #define XER_MIPICAUSE_FIELD_B_FIRST 0x1 54 #define XER_MIPICAUSE_FIELD_B_LAST 0x3 55 #define XER_MIPICAUSE_FIELD_C_FIRST 0x4 56 #define XER_MIPICAUSE_FIELD_C_LAST 0x7 57 #define XER_MIPICAUSE_FIELD_D_FIRST 0x8 58 #define XER_MIPICAUSE_FIELD_D_LAST 0xF 59 60 61 /* IPI from cause bit 0..15 62 63 RER invalid 64 WER sets 65 */ 66 #define XER_MIPISET 0x0140 67 #define XER_MIPISET_LAST 0x014F 68 69 70 /* Global enable 71 72 RER read 73 WER clear 74 */ 75 #define XER_MIENG 0x0180 76 77 78 /* Global enable 79 80 RER invalid 81 WER set 82 */ 83 #define XER_MIENG_SET 0x0184 84 85 /* Global assert 86 87 RER read 88 WER clear 89 */ 90 #define XER_MIASG 0x0188 91 92 93 /* Global enable 94 95 RER invalid 96 WER set 97 */ 98 #define XER_MIASG_SET 0x018C 99 100 101 /* IPI partition register 102 103 RER read 104 WER write 105 */ 106 #define XER_PART 0x0190 107 #define XER_IPI0 0x0 108 #define XER_IPI1 0x1 109 #define XER_IPI2 0x2 110 #define XER_IPI3 0x3 111 112 #define XER_PART_ROUTE_IPI(NUM, FIELD) ((NUM) << ((FIELD) << 2)) 113 114 #define XER_PART_ROUTE_IPI_CAUSE(TO_A, TO_B, TO_C, TO_D) \ 115 (XER_PART_ROUTE_IPI(TO_A, XER_IPI0) | \ 116 XER_PART_ROUTE_IPI(TO_B, XER_IPI1) | \ 117 XER_PART_ROUTE_IPI(TO_C, XER_IPI2) | \ 118 XER_PART_ROUTE_IPI(TO_D, XER_IPI3)) 119 120 #define XER_IPI_WAKE_EXT_INTERRUPT XCHAL_EXTINT0_NUM 121 #define XER_IPI_WAKE_CAUSE XER_MIPICAUSE_FIELD_C_FIRST 122 #define XER_IPI_WAKE_ADDRESS (XER_MIPISET + XER_IPI_WAKE_CAUSE) 123 #define XER_DEFAULT_IPI_ROUTING XER_PART_ROUTE_IPI_CAUSE(XER_IPI1, XER_IPI0, XER_IPI2, XER_IPI3) 124 125 126 /* System configuration ID 127 128 RER read 129 WER invalid 130 */ 131 #define XER_SYSCFGID 0x01A0 132 133 134 /* RunStall to slave processors 135 136 RER read 137 WER write 138 */ 139 #define XER_MPSCORE 0x0200 140 141 142 /* Cache coherency ON 143 144 RER read 145 WER write 146 */ 147 #define XER_CCON 0x0220 148 149 150
