1 /**
2 * @file xmc_scu.h
3 * @date 2016-03-09
4 *
5 * @cond
6 *********************************************************************************************************************
7 * XMClib v2.1.24 - XMC Peripheral Driver Library
8 *
9 * Copyright (c) 2015-2019, Infineon Technologies AG
10 * All rights reserved.
11 *
12 * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
13 * following conditions are met:
14 *
15 * Redistributions of source code must retain the above copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
19 * disclaimer in the documentation and/or other materials provided with the distribution.
20 *
21 * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
22 * products derived from this software without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
25 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
29 * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
33 * Infineon Technologies AG dave@infineon.com).
34 *********************************************************************************************************************
35 *
36 * Change History
37 * --------------
38 *
39 * 2015-02-20:
40 * - Initial <br>
41 *
42 * 2015-05-20:
43 * - Documentation improved <br>
44 * - XMC_ASSERT() hanging issues have fixed for XMC4 devices. <br>
45 *
46 * 2015-06-20:
47 * - Removed version macros and declaration of GetDriverVersion API
48 * - Removed STATIC_INLINE property for the below APIs and declared as void
49 * XMC_SCU_INTERRUPT_EnableEvent, XMC_SCU_INTERRUPT_DisableEvent,
50 * XMC_SCU_INTERRUPT_TriggerEvent, XMC_SCU_INTERUPT_GetEventStatus,
51 * XMC_SCU_INTERUPT_ClearEventStatus
52 *
53 * 2015-11-30:
54 * - Documentation improved <br>
55 *
56 * 2016-03-09:
57 * - Optimization of write only registers
58 *
59 * @endcond
60 *
61 */
62 #ifndef XMC_SCU_H
63 #define XMC_SCU_H
64
65 /*********************************************************************************************************************
66 * HEADER FILES
67 ********************************************************************************************************************/
68 #include <xmc_common.h>
69
70 /**
71 * @addtogroup XMClib XMC Peripheral Library
72 * @{
73 */
74
75 /**
76 * @addtogroup SCU
77 * @brief System Control Unit(SCU) driver for XMC microcontroller family.
78 *
79 * System control unit is the SoC power, reset and a clock manager with additional responsibility of
80 * providing system stability protection and other auxiliary functions.<br>
81 * SCU provides the following features,
82 * -# Power control
83 \if XMC4
84 * -# Hibernate control
85 \endif
86 * -# Reset control
87 * -# Clock control
88 * -# Miscellaneous control(boot mode, system interrupts etc.)<br><br>
89 *
90 * The SCU driver is divided in to clock control logic, reset control logic, system interrupt control logic
91 \if XMC4
92 * , hibernate control logic, trap control logic, parity control logic
93 \endif
94 * and miscellaneous control logic.<br>
95 *
96 * Clock driver features:
97 * -# Allows clock configuration using the structure XMC_SCU_CLOCK_CONFIG_t and API XMC_SCU_CLOCK_Init()
98 \if XMC4
99 * -# Provides structure XMC_SCU_CLOCK_SYSPLL_CONFIG_t for configuring the system PLL
100 * -# Allows selection of clock source for system PLL, XMC_SCU_CLOCK_GetSystemPllClockSource()
101 * -# Provides APIs for configuring different module clock frequencies XMC_SCU_CLOCK_SetWdtClockDivider(), XMC_SCU_CLOCK_SetUsbClockDivider()
102 * -# Allows selection of clock source for external output, XMC_SCU_CLOCK_SetExternalOutputClockSource()
103 * -# Provides APIs for enabling external high power oscillator and ultra low power oscillator, XMC_SCU_CLOCK_EnableHighPerformanceOscillator(), XMC_SCU_CLOCK_EnableLowPowerOscillator()
104 * -# Provides APIs for getting various clock frequencies XMC_SCU_CLOCK_GetPeripheralClockFrequency(),
105 XMC_SCU_CLOCK_GetCpuClockFrequency(), XMC_SCU_CLOCK_GetSystemClockFrequency()<br>
106 \endif
107 \if XMC1
108 * -# Allows selection of peripheral clock frequency, XMC_SCU_CLOCK_SetFastPeripheralClockSource()
109 * -# Provides API to get the peripheral clock frequency, XMC_SCU_CLOCK_GetFastPeripheralClockFrequency()
110 \endif
111 *
112 * Reset driver features:
113 \if XMC4
114 * -# Allows to handle peripheral reset XMC_SCU_RESET_AssertPeripheralReset(), XMC_SCU_RESET_DeassertPeripheralReset()
115 * -# Allows configuration of NMI generation for selected events, XMC_SCU_INTERRUPT_EnableNmiRequest()
116 \endif
117 \if XMC1
118 * -# Allows to trigger device reset XMC_SCU_RESET_AssertMasterReset()
119 * -# Allows to configure multiple sources for reset, XMC_SCU_RESET_EnableResetRequest()
120 \endif <br>
121 *
122 * Interrupt driver features:
123 * -# Provides APIs for enabling/ disabling interrupt event generation XMC_SCU_INTERRUPT_EnableEvent(),
124 XMC_SCU_INTERRUPT_DisableEvent()
125 * -# Provides API for registering callback function for events XMC_SCU_INTERRUPT_SetEventHandler()<br>
126 *
127 \if XMC4
128 * Hibernate driver features:
129 * -# Allows configuration of hibernate domain XMC_SCU_HIB_EnableHibernateDomain(), XMC_SCU_HIB_DisableHibernateDomain()
130 * -# Allows selection of standby clock source, XMC_SCU_HIB_SetStandbyClockSource()
131 * -# Allows selection of RTC clock source, XMC_SCU_HIB_SetRtcClockSource()
132 * -# Provides API for enabling slow internal clock used for backup clock, XMC_SCU_HIB_EnableInternalSlowClock()<br>
133 *
134 * Trap driver features:
135 * -# Allows handling of trap XMC_SCU_TRAP_Enable(), XMC_SCU_TRAP_GetStatus(), XMC_SCU_TRAP_Trigger()<br>
136 *
137 * Parity driver features:
138 * -# Parity error generated by on-chip RAM can be monitored, XMC_SCU_PARITY_Enable(), XMC_SCU_PARITY_GetStatus()
139 * -# Allows configuration of trap generation on detection of parity error, XMC_SCU_PARITY_EnableTrapGeneration()
140 *
141 * Power driver features:
142 * -# Allows to power the USB module XMC_SCU_POWER_EnableUsb(), XMC_SCU_POWER_DisableUsb()
143 \endif
144 *
145 * Miscellaneous features:
146 * -# Allows to trigger multiple capture compare unit(CCU) channels to be started together XMC_SCU_SetCcuTriggerHigh()
147 \if XMC4
148 * -# Enables configuration of out of range comparator (ORC) XMC_SCU_EnableOutOfRangeComparator()
149 * -# Enables configuration of die temperature sensor XMC_SCU_EnableTemperatureSensor(), XMC_SCU_CalibrateTemperatureSensor()
150 * -# Enables configuration of device boot mode XMC_SCU_SetBootMode()<br>
151 \endif
152 \if XMC1
153 * -# Enables configuration of die temperature sensor XMC_SCU_StartTempMeasurement(), XMC_SCU_SetRawTempLimits()
154 * -# Allows configuring supply monitor unit using the structure XMC_SCU_SUPPLYMONITOR_t and API XMC_SCU_SupplyMonitorInit()
155 * -# Allows handling of protected bits XMC_SCU_LockProtectedBits(), XMC_SCU_UnlockProtectedBits()<br>
156 \endif
157 * @{
158 */
159
160 /*********************************************************************************************************************
161 * MACROS
162 ********************************************************************************************************************/
163
164 /*********************************************************************************************************************
165 * ENUMS
166 ********************************************************************************************************************/
167 /**
168 * Defines the status of SCU API execution, used to verify the SCU related API calls.
169 */
170 typedef enum XMC_SCU_STATUS
171 {
172 XMC_SCU_STATUS_OK = 0UL, /**< SCU related operation successfully completed.*/
173 XMC_SCU_STATUS_ERROR, /**< SCU related operation failed. When API cannot fulfill request, this value is returned. */
174 XMC_SCU_STATUS_BUSY, /**< Cannot execute the SCU related operation request because
175 another operation is in progress. \a XMC_SCU_STATUS_BUSY is returned when API is busy
176 processing another request. */
177 } XMC_SCU_STATUS_t;
178
179
180 /*********************************************************************************************************************
181 * DATA TYPES
182 ********************************************************************************************************************/
183
184 /**
185 * Function pointer type used for registering callback functions on SCU event occurrence.
186 */
187 typedef void (*XMC_SCU_INTERRUPT_EVENT_HANDLER_t)(void);
188
189 /*********************************************************************************************************************
190 * DEVICE EXTENSIONS
191 ********************************************************************************************************************/
192
193 #if (UC_FAMILY == XMC1)
194 #include <xmc1_scu.h>
195 #elif (UC_FAMILY == XMC4)
196 #include <xmc4_scu.h>
197 #else
198 #error "Unspecified chipset"
199 #endif
200
201 /*********************************************************************************************************************
202 * API Prototypes
203 ********************************************************************************************************************/
204
205 #ifdef __cplusplus
206 extern "C" {
207 #endif
208
209
210 /**
211 *
212 * @param trigger CCU slices to be triggered synchronously via software. The value is a bitmask of CCU slice bits
213 * in the register CCUCON. <br>
214 * \b Range: Use type @ref XMC_SCU_CCU_TRIGGER_t for bitmask of individual CCU slices. Multiple slices can be
215 * combined using \a OR operation.
216 *
217 * @return None
218 *
219 * \par<b>Description</b><br>
220 * Generates active edge(low to high) trigger for multiple CCU units at the same time.\n\n
221 * Before executing this API, all the required CCU timers should configure external start.
222 * The edge of the start signal should be selected as active edge.
223 * The input signal for the CCU slice should be selected as SCU input.
224 * The above mentioned configurations can be made using the CCU LLD API XMC_CCU4_SLICE_StartConfig().
225 * CCU timer slice should be started using XMC_CCU4_SLICE_StartTimer() before triggering
226 * the timer using this API.<BR>
227 * \par<b>Related APIs:</b><BR>
228 * XMC_CCU4_SLICE_StartConfig(), XMC_CCU4_SLICE_SetInput(), XMC_SCU_SetCcuTriggerLow()\n\n\n
229 */
XMC_SCU_SetCcuTriggerHigh(const uint32_t trigger)230 __STATIC_INLINE void XMC_SCU_SetCcuTriggerHigh(const uint32_t trigger)
231 {
232 SCU_GENERAL->CCUCON |= (uint32_t)trigger;
233 }
234
235 /**
236 *
237 * @param trigger CCU slices to be triggered synchronously via software. The value is a bitmask of CCU slice bits
238 * in the register CCUCON. <br>
239 * \b Range: Use type @ref XMC_SCU_CCU_TRIGGER_t for bitmask of individual CCU slices. Multiple slices can be
240 * combined using \a OR operation.
241 *
242 * @return None
243 *
244 * \par<b>Description</b><br>
245 * Generates passive edge(high to low) trigger for multiple CCU units at the same time.\n\n
246 * Before executing this API, all the required CCU timers should configure external start.
247 * The edge of the start signal should be selected as passive edge.
248 * The input signal for the CCU slice should be selected as SCU input.
249 * The above mentioned configurations can be made using the CCU LLD API XMC_CCU4_SLICE_StartConfig().
250 * CCU timer slice should be started using XMC_CCU4_SLICE_StartTimer() before triggering
251 * the timer using this API.<BR>
252 * \par<b>Related APIs:</b><BR>
253 * XMC_CCU4_SLICE_StartConfig(), XMC_CCU4_SLICE_SetInput(), XMC_SCU_SetCcuTriggerHigh()\n\n\n
254 */
XMC_SCU_SetCcuTriggerLow(const uint32_t trigger)255 __STATIC_INLINE void XMC_SCU_SetCcuTriggerLow(const uint32_t trigger)
256 {
257 SCU_GENERAL->CCUCON &= (uint32_t)~trigger;
258 }
259
260 /**
261 *
262 * @param config Pointer to structure holding the clock prescaler values and divider values for
263 * configuring clock generators and clock tree.\n
264 * \b Range: Configure the members of structure @ref XMC_SCU_CLOCK_CONFIG_t for various
265 * parameters of clock setup.
266 *
267 * @return None
268 *
269 * \par<b>Description</b><br>
270 * Initializes clock generators and clock tree.\n\n
271 * \if XMC1
272 * Peripheral clock and system clock are configured based on the input configuration \a config.
273 * The system clock frequency is tuned by configuring the FDIV and IDIV values of CLKCR register.
274 * The values of FDIV and IDIV can be provided as part of input configuration.
275 * The PCLK divider determines the ratio of peripheral clock to the system clock.
276 * The source of RTC clock is set based on the input configuration.
277 * \a SystemCoreClock variable will be updated with the value of
278 * system clock frequency. Access to protected bit fields are handled internally.
279 * \endif
280 * \if XMC4
281 * Enables the high precision oscillator(fOHP) input and configures the system and peripheral clock frequencies.
282 * Based on the system clock source selected in \a config, either fPLL or fOFI will be chosen as system clock.
283 * Based on PLL mode(normal or prescaler mode) used, PLL ramps up in steps to achieve target frequency.
284 * The clock dividers for CPU, CCU and peripheral clocks will be set based on the input configuration.
285 * The \a SystemCoreClock variable is set with the value of system clock frequency.
286 * \endif
287 * \par<b>Related APIs:</b><BR>
288 * XMC_SCU_CLOCK_GetPeripheralClockFrequency(), XMC_SCU_CLOCK_GetCpuClockFrequency() \n\n\n
289 */
290 void XMC_SCU_CLOCK_Init(const XMC_SCU_CLOCK_CONFIG_t *const config);
291
292 /**
293 *
294 * @param event Bit mask of the event to enable. \b Range: Use type @ref XMC_SCU_INTERRUPT_EVENT_t
295 * for providing the input value. Multiple events can be combined using the \a OR operation.
296 *
297 * @return None
298 *
299 * \par<b>Description</b><br>
300 * Enables the generation of interrupt for the input events.\n\n
301 * The events are enabled by setting the respective bit fields in the SRMSK register. \n
302 * Note: User should separately enable the NVIC node responsible for handling the SCU interrupt.
303 * The interrupt will be generated when the respective event occurs.
304 * \par<b>Related APIs:</b><BR>
305 * NVIC_EnableIRQ(), XMC_SCU_INTERRUPT_DisableEvent()\n\n\n
306 */
307 void XMC_SCU_INTERRUPT_EnableEvent(const XMC_SCU_INTERRUPT_EVENT_t event);
308
309
310 /**
311 *
312 * @param event Bit mask of the event to disable. \b Range: Use type @ref XMC_SCU_INTERRUPT_EVENT_t
313 * for providing the input value. Multiple events can be combined using the \a OR operation.
314 *
315 * @return None
316 *
317 * \par<b>Description</b><br>
318 * Disables generation of interrupt on occurrence of the input event.\n\n
319 * The events are disabled by resetting the respective bit fields in the SRMSK register. \n
320 * \par<b>Related APIs:</b><BR>
321 * NVIC_DisableIRQ(), XMC_SCU_INTERRUPT_EnableEvent()\n\n\n
322 */
323 void XMC_SCU_INTERRUPT_DisableEvent(const XMC_SCU_INTERRUPT_EVENT_t event);
324
325 /**
326 *
327 * @param event Bit mask of the event to be triggered. \b Range: Use type @ref XMC_SCU_INTERRUPT_EVENT_t
328 * for providing the input value. Multiple events can be combined using the \a OR operation.
329 *
330 * @return None
331 *
332 * \par<b>Description</b><br>
333 * Triggers the event as if the hardware raised it.\n\n
334 * Event will be triggered by setting the respective bitfield in the SRSET register.\n
335 * Note: User should enable the NVIC node that handles the respective event for interrupt generation.
336 * \par<b>Related APIs:</b><BR>
337 * NVIC_EnableIRQ(), XMC_SCU_INTERUPT_GetEventStatus(), XMC_SCU_INTERRUPT_ClearEventStatus() \n\n\n
338 */
339 void XMC_SCU_INTERRUPT_TriggerEvent(const XMC_SCU_INTERRUPT_EVENT_t event);
340
341 /**
342 * @return uint32_t Status of the SCU events.
343 *
344 * \par<b>Description</b><br>
345 * Provides the status of all SCU events.\n\n
346 * The status is read from the SRRAW register. To check the status of a particular
347 * event, the returned value should be masked with the bit mask of the event. The bitmask
348 * of events can be obtained using the type @ref XMC_SCU_INTERRUPT_EVENT_t. Multiple events'
349 * status can be checked by combining the bit masks using \a OR operation.
350 * After detecting the event, the event status should be cleared using software to detect the event again.
351 * \par<b>Related APIs:</b><BR>
352 * XMC_SCU_INTERRUPT_ClearEventStatus(), XMC_SCU_INTERRUPT_TriggerEvent(), XMC_SCU_INTERRUPT_SetEventHandler() \n\n\n
353 */
354 XMC_SCU_INTERRUPT_EVENT_t XMC_SCU_INTERUPT_GetEventStatus(void);
355
356 /**
357 *
358 * @param event Bit mask of the events to clear. \b Range: Use type @ref XMC_SCU_INTERRUPT_EVENT_t
359 * for providing the input value. Multiple events can be combined using the \a OR operation.
360 *
361 * @return None
362 *
363 * \par<b>Description</b><br>
364 * Clears the event status bit in SRRAW register.\n\n
365 * The events are cleared by writing value 1 to their bit positions in the SRCLR register.
366 * The API can be used when polling method is used. After detecting the event, the event status
367 * should be cleared using software to detect the event again.
368 *
369 * \par<b>Related APIs:</b><BR>
370 * XMC_SCU_INTERUPT_GetEventStatus(), XMC_SCU_INTERRUPT_TriggerEvent() \n\n\n
371 */
372 void XMC_SCU_INTERRUPT_ClearEventStatus(const XMC_SCU_INTERRUPT_EVENT_t event);
373
374 /**
375 *
376 * @return uint32_t Status representing the reason for device reset.
377 *
378 * \par<b>Description</b><br>
379 * Provides the value representing the reason for device reset.\n\n
380 * The return value is an encoded word, which can indicate multiple reasons for the last reset. Each bit position of the
381 * returned word is representative of a last reset cause. The returned value should be appropriately masked to check
382 * the cause of reset.
383 * The cause of the last reset gets automatically stored in
384 * the \a SCU_RSTSTAT register. The reset status shall be reset after each
385 * startup in order to ensure consistent source indication after the next reset.
386 * \b Range: The type @ref XMC_SCU_RESET_REASON_t can be used to get the bit masks of the reset cause.
387 *
388 * \par<b>Related APIs:</b><BR>
389 * XMC_SCU_RESET_ClearDeviceResetReason() \n\n\n
390 */
XMC_SCU_RESET_GetDeviceResetReason(void)391 __STATIC_INLINE uint32_t XMC_SCU_RESET_GetDeviceResetReason(void)
392 {
393 return ((SCU_RESET->RSTSTAT) & SCU_RESET_RSTSTAT_RSTSTAT_Msk);
394 }
395 /**
396 * @return None
397 *
398 * \par<b>Description</b><br>
399 * Clears the reset reason bits in the reset status register. \n\n
400 * Clearing of the reset status information in the \a SCU_RSTSTAT register via register bit \a RSTCLR.RSCLR is strongly
401 * recommended to ensure a clear indication of the cause of next reset.
402 *
403 * \par<b>Related APIs:</b><BR>
404 * XMC_SCU_RESET_GetDeviceResetReason() \n\n\n
405 */
XMC_SCU_RESET_ClearDeviceResetReason(void)406 __STATIC_INLINE void XMC_SCU_RESET_ClearDeviceResetReason(void)
407 {
408 /* Clear RSTSTAT.RSTSTAT bitfield */
409 SCU_RESET->RSTCLR = (uint32_t)SCU_RESET_RSTCLR_RSCLR_Msk;
410 }
411
412 /**
413 * @return uint32_t Value of CPU clock frequency.
414 *
415 * \par<b>Description</b><br>
416 * Provides the vlaue of CPU clock frequency.\n\n
417 * The value is stored in a global variable \a \b SystemCoreClock.
418 * It is updated when the clock configuration is done using the SCU LLD APIs.
419 * The value represents the frequency of clock used for CPU operation.
420 * \b Range: Value is of type uint32_t, and gives the value of frequency in Hertz.
421 *
422 * \par<b>Related APIs:</b><BR>
423 * XMC_SCU_CLOCK_GetPeripheralClockFrequency(), XMC_SCU_CLOCK_GatePeripheralClock() \n\n\n
424 */
XMC_SCU_CLOCK_GetCpuClockFrequency(void)425 __STATIC_INLINE uint32_t XMC_SCU_CLOCK_GetCpuClockFrequency(void)
426 {
427 return SystemCoreClock;
428 }
429
430 /**
431 * @return uint32_t Value of peripheral clock frequency in Hertz.
432 *
433 * \par<b>Description</b><br>
434 * Provides the vlaue of clock frequency at which the peripherals are working.\n\n
435 * The value is derived from the CPU frequency. \b Range: Value is of type uint32_t. It is represented in Hertz.
436 * \par<b>Related APIs:</b><BR>
437 * XMC_SCU_CLOCK_GetCpuClockFrequency(),XMC_SCU_CLOCK_GatePeripheralClock() \n\n\n
438 */
439 uint32_t XMC_SCU_CLOCK_GetPeripheralClockFrequency(void);
440
441 #if(UC_SERIES != XMC45)
442
443 /**
444 *
445 * @param peripheral The peripheral for which the clock has to be gated. \b Range: Use type @ref XMC_SCU_PERIPHERAL_CLOCK_t
446 * to identify the peripheral clock to be gated.
447 *
448 * @return None
449 *
450 * \par<b>Description</b><br>
451 * Blocks the supply of clock to the selected peripheral.\n\n
452 * Clock gating helps in reducing the power consumption. User can selectively gate the clocks of unused peripherals.
453 * \if XMC1
454 * fPCLK is the source of clock to various peripherals. Some peripherals support clock gate. Such a gate blocks
455 * the clock supply for the selected peripheral.
456 * Software can request for individual gating of such peripheral clocks by enabling the \a SCU_CGATSET0
457 * register bit field. Every bit in \a SCU_CGATSET0 register is protected by the bit protection scheme. Access to protected
458 * bit fields are handled internally.
459 * \endif
460 * \if XMC4
461 * fPERI is the source of clock to various peripherals. Some peripherals support clock gate. Such a gate blocks
462 * the clock supply for the selected peripheral.
463 * Software can request for individual gating of such peripheral clocks by enabling one of the \a
464 * SCU_CGATSET0, \a SCU_CGATSET1 or \a SCU_CGATSET2 register bitfields.
465 *
466 * \endif
467 * Note: Clock gating shall not be activated unless the module is in reset state. So use \a
468 * XMC_SCU_CLOCK_IsPeripheralClockGated() API before enabling the gating of any peripheral.
469 * \par<b>Related APIs:</b><BR>
470 * XMC_SCU_CLOCK_IsPeripheralClockGated(), XMC_SCU_CLOCK_UngatePeripheralClock() \n\n\n
471 */
472 void XMC_SCU_CLOCK_GatePeripheralClock(const XMC_SCU_PERIPHERAL_CLOCK_t peripheral);
473
474 /**
475 *
476 * @param peripheral The peripheral for which the clock has to be ungated. \b Range: Use type @ref XMC_SCU_PERIPHERAL_CLOCK_t
477 * to identify the peripheral.
478 *
479 * @return None
480 *
481 * \par<b>Description</b><br>
482 * Enables the supply of clock to the selected peripheral.\n\n
483 * By default when the device powers on, the peripheral clock will be gated for the
484 * peripherals that support clock gating.
485 * The peripheral clock should be enabled before using it for any functionality.
486 * \if XMC1
487 * fPCLK is the source of clock to various peripherals. Some peripherals support clock gate.
488 * Software can request for individual ungating of such peripheral clocks by setting respective bits
489 * in the \a SCU_CGATCLR0 register.
490 * \endif
491 * \if XMC4
492 * fPERI is the source of clock to various peripherals. Some peripherals support clock gate.
493 * Software can request for individual ungating of such peripheral clocks by setting the respective bits in one of \a
494 * SCU_CGATCLR0, \a SCU_CGATCLR1 or \a SCU_CGATCLR2 registers.
495 * \endif
496 *
497 * \par<b>Related APIs:</b><BR>
498 * XMC_SCU_CLOCK_IsPeripheralClockGated(), XMC_SCU_CLOCK_GatePeripheralClock() \n\n\n
499 */
500 void XMC_SCU_CLOCK_UngatePeripheralClock(const XMC_SCU_PERIPHERAL_CLOCK_t peripheral);
501
502 /**
503 *
504 * @param peripheral The peripheral for which the check for clock gating has to be done.
505 * \b Range: Use type @ref XMC_SCU_PERIPHERAL_CLOCK_t to identify the peripheral.
506 *
507 * @return bool Status of the peripheral clock gating. \b Range: true if the peripheral clock is gated.
508 * false if the peripheral clock ungated(gate de-asserted).
509 *
510 * \par<b>Description</b><br>
511 * Gives the status of peripheral clock gating.\n\n
512 * \if XMC1
513 * Checks the status of peripheral clock gating using the register CGATSTAT0.
514 * \endif
515 * \if XMC4
516 * Checks the status of peripheral clock gating using one of CGATSTAT0, CGATSTAT1 or CGATSTAT2 registers.
517 * \endif
518 * It is recommended to use this API before
519 * enabling the gating of any peripherals through \a XMC_SCU_CLOCK_GatePeripheralClock() API.
520 *
521 * \par<b>Related APIs:</b><BR>
522 * XMC_SCU_CLOCK_UngatePeripheralClock(), XMC_SCU_CLOCK_GatePeripheralClock() \n\n\n
523 */
524 bool XMC_SCU_CLOCK_IsPeripheralClockGated(const XMC_SCU_PERIPHERAL_CLOCK_t peripheral);
525 #endif
526
527
528 /**
529 * @return uint32_t Status of the register mirror update.\n
530 * \b Range: Use the bit mask of the SCU_GENERAL_MIRRSTS register for the mirror update event of
531 * interest. e.g.: SCU_GENERAL_MIRRSTS_RTC_CTR_Msk. Multiple update events can be combined
532 * using \a OR operation.
533 *
534 * \par<b>Description</b><br>
535 * Provides the status of hibernate domain register update, when the respective mirror registers are changed. \n\n
536 * The hibernate domain is connected to the core domain via SPI serial communication. MIRRSTS is a status register
537 * representing the communication of changed value of a mirror register to its corresponding register in the
538 * hibernate domain. The bit fields of the register indicate
539 * that a corresponding register of the hibernate domain is ready to accept a write or that the communication interface
540 * is busy with executing the previous operation.\n
541 * Note: There is no hibernate domain in XMC1x devices. This register is retained for legacy purpose.
542 */
XMC_SCU_GetMirrorStatus(void)543 __STATIC_INLINE uint32_t XMC_SCU_GetMirrorStatus(void)
544 {
545 return(SCU_GENERAL->MIRRSTS);
546 }
547
548 /**
549 * @param event The event for which the interrupt handler is to be configured. \n
550 * \b Range: Use type @ref XMC_SCU_INTERRUPT_EVENT_t for identifying the event.
551 * @param handler Name of the function to be executed when the event if detected. \n
552 * \b Range: The function accepts no arguments and returns no value.
553 * @return XMC_SCU_STATUS_t Status of configuring the event handler function for the selected event.\n
554 * \b Range: \a XMC_SCU_STATUS_OK if the event handler is successfully configured.\n
555 * \a XMC_SCU_STATUS_ERROR if the input event is invalid.\n
556 * \par<b>Description</b><br>
557 * Assigns the event handler function to be executed on occurrence of the selected event.\n\n
558 * If the input event is valid, the handler function will be assigned to a table to be executed
559 * when the interrupt is generated and the event status is set in the event status register. By using this API,
560 * polling for a particular event can be avoided. This way the CPU utilization will be optimized. Multiple SCU events
561 * can generate a common interrupt. When the interrupt is generated, a common interrupt service routine is executed.
562 * It checks for status flags of events which can generate the interrupt. The handler function will be executed if the
563 * event flag is set.
564 *
565 * \par<b>Related APIs:</b><BR>
566 * XMC_SCU_INTERRUPT_TriggerEvent(), XMC_SCU_INTERUPT_GetEventStatus() \n\n\n
567 */
568 XMC_SCU_STATUS_t XMC_SCU_INTERRUPT_SetEventHandler(const XMC_SCU_INTERRUPT_EVENT_t event, const XMC_SCU_INTERRUPT_EVENT_HANDLER_t handler);
569
570 /**
571 * @param sr_num Service request number identifying the SCU interrupt generated.\n
572 * \b Range: 0 to 2. XMC4x devices have one common SCU interrupt, so the value should be 0.\n
573 * But XMC1x devices support 3 interrupt nodes.
574 * @return None
575 * \par<b>Description</b><br>
576 * A common function to execute callback functions for multiple events.\n\n
577 * It checks for the status of events which can generate the interrupt with the selected service request.
578 * If the event is set, the corresponding callback function will be executed. It also clears the event status bit.\n
579 * \b Note: This is an internal function. It should not be called by the user application.
580 *
581 * \par<b>Related APIs:</b><BR>
582 * XMC_SCU_INTERRUPT_SetEventHandler() \n\n\n
583 */
584 void XMC_SCU_IRQHandler(uint32_t sr_num);
585
586 #ifdef __cplusplus
587 }
588 #endif
589
590 /**
591 * @}
592 */
593
594 /**
595 * @}
596 */
597
598 #endif /* SCU_H */
599
