1 2 /** 3 * @file xmc_hrpwm_map.h 4 * @date 2015-06-20 5 * 6 * @cond 7 ********************************************************************************** 8 * XMClib v2.1.24 - XMC Peripheral Driver Library 9 * 10 * Copyright (c) 2015-2019, Infineon Technologies AG 11 * All rights reserved. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification,are permitted provided that the following conditions are met: 15 * 16 * Redistributions of source code must retain the above copyright notice, 17 * this list of conditions and the following disclaimer. 18 * 19 * Redistributions in binary form must reproduce the above copyright notice, 20 * this list of conditions and the following disclaimer in the documentation 21 * and/or other materials provided with the distribution. 22 * 23 * Neither the name of the copyright holders nor the names of its contributors 24 * may be used to endorse or promote products derived from this software without 25 * specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 28 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 30 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 31 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 * 39 * To improve the quality of the software, users are encouraged to share 40 * modifications, enhancements or bug fixes with Infineon Technologies AG 41 * dave@infineon.com). 42 ********************************************************************************** 43 * 44 * Change History 45 * -------------- 46 * 47 * 2015-06-20: 48 * - Updated copyright and change history section. 49 * 50 * @endcond 51 * 52 */ 53 54 /** 55 * 56 * @brief HRPWM mapping for XMC4 microcontroller family. <br> 57 * 58 */ 59 60 /********************************************************************************************************************* 61 * HEADER FILES 62 ********************************************************************************************************************/ 63 #include "xmc_hrpwm.h" 64 65 #ifndef XMC_HRPWM_MAP_H 66 #define XMC_HRPWM_MAP_H 67 68 #if ((UC_DEVICE == XMC4400) || (UC_DEVICE == XMC4200) || (UC_DEVICE == XMC4100)) 69 /* CSG0 - General input to control Blanking and Switch of the Comparator */ 70 #define XMC_HRPWM_CSG0_BL_P1_4 XMC_HRPWM_CSG_INPUT_SEL_IA 71 #define XMC_HRPWM_CSG0_BL_SCU_GSHR0 XMC_HRPWM_CSG_INPUT_SEL_IB 72 #define XMC_HRPWM_CSG0_BL_CCU80_ST0 XMC_HRPWM_CSG_INPUT_SEL_IC 73 #define XMC_HRPWM_CSG0_BL_CCU80_ST1 XMC_HRPWM_CSG_INPUT_SEL_ID 74 #define XMC_HRPWM_CSG0_BL_CCU80_ST2 XMC_HRPWM_CSG_INPUT_SEL_IE 75 #define XMC_HRPWM_CSG0_BL_CCU80_ST3 XMC_HRPWM_CSG_INPUT_SEL_IF 76 #define XMC_HRPWM_CSG0_BL_CCU40_ST0 XMC_HRPWM_CSG_INPUT_SEL_IG 77 #define XMC_HRPWM_CSG0_BL_CCU41_ST0 XMC_HRPWM_CSG_INPUT_SEL_IH 78 #define XMC_HRPWM_CSG0_BL_HRPWM_QOUT0 XMC_HRPWM_CSG_INPUT_SEL_II 79 #define XMC_HRPWM_CSG0_BL_HRPWM_QOUT1 XMC_HRPWM_CSG_INPUT_SEL_IJ 80 #define XMC_HRPWM_CSG0_BL_CCU40_SR0 XMC_HRPWM_CSG_INPUT_SEL_IK 81 #define XMC_HRPWM_CSG0_BL_CCU41_SR0 XMC_HRPWM_CSG_INPUT_SEL_IL 82 #define XMC_HRPWM_CSG0_BL_HRPWM_SR2 XMC_HRPWM_CSG_INPUT_SEL_IM 83 #define XMC_HRPWM_CSG0_BL_HRPWM_SR3 XMC_HRPWM_CSG_INPUT_SEL_IN 84 #define XMC_HRPWM_CSG0_BL_ERU1_IOUT0 XMC_HRPWM_CSG_INPUT_SEL_IO 85 #define XMC_HRPWM_CSG0_BL_ERU1_IOUT1 XMC_HRPWM_CSG_INPUT_SEL_IP 86 87 /* CSG0 - General input to control start/stop/trigger for Slope Control Logic */ 88 #define XMC_HRPWM_CSG0_SC_SCU_GSHR0 XMC_HRPWM_CSG_INPUT_SEL_IB 89 #define XMC_HRPWM_CSG0_SC_CCU80_ST0 XMC_HRPWM_CSG_INPUT_SEL_IC 90 #define XMC_HRPWM_CSG0_SC_CCU80_ST1 XMC_HRPWM_CSG_INPUT_SEL_ID 91 #define XMC_HRPWM_CSG0_SC_CCU80_ST2 XMC_HRPWM_CSG_INPUT_SEL_IE 92 #define XMC_HRPWM_CSG0_SC_CCU80_ST3 XMC_HRPWM_CSG_INPUT_SEL_IF 93 #define XMC_HRPWM_CSG0_SC_CCU40_ST0 XMC_HRPWM_CSG_INPUT_SEL_IG 94 #define XMC_HRPWM_CSG0_SC_CCU41_ST0 XMC_HRPWM_CSG_INPUT_SEL_IH 95 #define XMC_HRPWM_CSG0_SC_HRPWM_QOUT0 XMC_HRPWM_CSG_INPUT_SEL_II 96 #define XMC_HRPWM_CSG0_SC_HRPWM_QOUT1 XMC_HRPWM_CSG_INPUT_SEL_IJ 97 #define XMC_HRPWM_CSG0_SC_CCU40_SR0 XMC_HRPWM_CSG_INPUT_SEL_IK 98 #define XMC_HRPWM_CSG0_SC_CCU41_SR0 XMC_HRPWM_CSG_INPUT_SEL_IL 99 #define XMC_HRPWM_CSG0_SC_HRPWM_C0O XMC_HRPWM_CSG_INPUT_SEL_IM 100 #define XMC_HRPWM_CSG0_SC_HRPWM_SR3 XMC_HRPWM_CSG_INPUT_SEL_IN 101 #define XMC_HRPWM_CSG0_SC_ERU1_IOUT0 XMC_HRPWM_CSG_INPUT_SEL_IO 102 #define XMC_HRPWM_CSG0_SC_ERU1_IOUT1 XMC_HRPWM_CSG_INPUT_SEL_IP 103 104 /* CSG1 - General input to control Blanking and Switch of the Comparator */ 105 #define XMC_HRPWM_CSG1_BL_P2_4 XMC_HRPWM_CSG_INPUT_SEL_IA 106 #define XMC_HRPWM_CSG1_BL_SCU_GSHR0 XMC_HRPWM_CSG_INPUT_SEL_IB 107 #define XMC_HRPWM_CSG1_BL_CCU80_ST0 XMC_HRPWM_CSG_INPUT_SEL_IC 108 #define XMC_HRPWM_CSG1_BL_CCU80_ST1 XMC_HRPWM_CSG_INPUT_SEL_ID 109 #define XMC_HRPWM_CSG1_BL_CCU80_ST2 XMC_HRPWM_CSG_INPUT_SEL_IE 110 #define XMC_HRPWM_CSG1_BL_CCU80_ST3 XMC_HRPWM_CSG_INPUT_SEL_IF 111 #define XMC_HRPWM_CSG1_BL_CCU40_ST1 XMC_HRPWM_CSG_INPUT_SEL_IG 112 #define XMC_HRPWM_CSG1_BL_CCU41_ST1 XMC_HRPWM_CSG_INPUT_SEL_IH 113 #define XMC_HRPWM_CSG1_BL_HRPWM_QOUT1 XMC_HRPWM_CSG_INPUT_SEL_II 114 #define XMC_HRPWM_CSG1_BL_HRPWM_QOUT2 XMC_HRPWM_CSG_INPUT_SEL_IJ 115 #define XMC_HRPWM_CSG1_BL_CCU40_SR1 XMC_HRPWM_CSG_INPUT_SEL_IK 116 #define XMC_HRPWM_CSG1_BL_CCU41_SR1 XMC_HRPWM_CSG_INPUT_SEL_IL 117 #define XMC_HRPWM_CSG1_BL_HRPWM_SR2 XMC_HRPWM_CSG_INPUT_SEL_IM 118 #define XMC_HRPWM_CSG1_BL_HRPWM_SR3 XMC_HRPWM_CSG_INPUT_SEL_IN 119 #define XMC_HRPWM_CSG1_BL_ERU1_IOUT0 XMC_HRPWM_CSG_INPUT_SEL_IO 120 #define XMC_HRPWM_CSG1_BL_ERU1_IOUT1 XMC_HRPWM_CSG_INPUT_SEL_IP 121 122 /* CSG1 - General input to control start/stop/trigger for Slope Control Logic */ 123 #define XMC_HRPWM_CSG1_SC_SCU_GSHR0 XMC_HRPWM_CSG_INPUT_SEL_IB 124 #define XMC_HRPWM_CSG1_SC_CCU80_ST0 XMC_HRPWM_CSG_INPUT_SEL_IC 125 #define XMC_HRPWM_CSG1_SC_CCU80_ST1 XMC_HRPWM_CSG_INPUT_SEL_ID 126 #define XMC_HRPWM_CSG1_SC_CCU80_ST2 XMC_HRPWM_CSG_INPUT_SEL_IE 127 #define XMC_HRPWM_CSG1_SC_CCU80_ST3 XMC_HRPWM_CSG_INPUT_SEL_IF 128 #define XMC_HRPWM_CSG1_SC_CCU40_ST1 XMC_HRPWM_CSG_INPUT_SEL_IG 129 #define XMC_HRPWM_CSG1_SC_CCU41_ST1 XMC_HRPWM_CSG_INPUT_SEL_IH 130 #define XMC_HRPWM_CSG1_SC_HRPWM_QOUT1 XMC_HRPWM_CSG_INPUT_SEL_II 131 #define XMC_HRPWM_CSG1_SC_HRPWM_QOUT2 XMC_HRPWM_CSG_INPUT_SEL_IJ 132 #define XMC_HRPWM_CSG1_SC_CCU40_SR1 XMC_HRPWM_CSG_INPUT_SEL_IK 133 #define XMC_HRPWM_CSG1_SC_CCU41_SR1 XMC_HRPWM_CSG_INPUT_SEL_IL 134 #define XMC_HRPWM_CSG1_SC_HRPWM_C1O XMC_HRPWM_CSG_INPUT_SEL_IM 135 #define XMC_HRPWM_CSG1_SC_HRPWM_SR3 XMC_HRPWM_CSG_INPUT_SEL_IN 136 #define XMC_HRPWM_CSG1_SC_ERU1_IOUT0 XMC_HRPWM_CSG_INPUT_SEL_IO 137 #define XMC_HRPWM_CSG1_SC_ERU1_IOUT1 XMC_HRPWM_CSG_INPUT_SEL_IP 138 139 /* CSG2 - General input to control Blanking and Switch of the Comparator */ 140 #define XMC_HRPWM_CSG2_BL_P2_5 XMC_HRPWM_CSG_INPUT_SEL_IA 141 #define XMC_HRPWM_CSG2_BL_SCU_GSHR0 XMC_HRPWM_CSG_INPUT_SEL_IB 142 #define XMC_HRPWM_CSG2_BL_CCU80_ST0 XMC_HRPWM_CSG_INPUT_SEL_IC 143 #define XMC_HRPWM_CSG2_BL_CCU80_ST1 XMC_HRPWM_CSG_INPUT_SEL_ID 144 #define XMC_HRPWM_CSG2_BL_CCU80_ST2 XMC_HRPWM_CSG_INPUT_SEL_IE 145 #define XMC_HRPWM_CSG2_BL_CCU80_ST3 XMC_HRPWM_CSG_INPUT_SEL_IF 146 #define XMC_HRPWM_CSG2_BL_CCU40_ST2 XMC_HRPWM_CSG_INPUT_SEL_IG 147 #define XMC_HRPWM_CSG2_BL_CCU41_ST2 XMC_HRPWM_CSG_INPUT_SEL_IH 148 #define XMC_HRPWM_CSG2_BL_HRPWM_QOUT2 XMC_HRPWM_CSG_INPUT_SEL_II 149 #define XMC_HRPWM_CSG2_BL_HRPWM_QOUT3 XMC_HRPWM_CSG_INPUT_SEL_IJ 150 #define XMC_HRPWM_CSG2_BL_CCU40_SR2 XMC_HRPWM_CSG_INPUT_SEL_IK 151 #define XMC_HRPWM_CSG2_BL_CCU41_SR2 XMC_HRPWM_CSG_INPUT_SEL_IL 152 #define XMC_HRPWM_CSG2_BL_HRPWM_SR2 XMC_HRPWM_CSG_INPUT_SEL_IM 153 #define XMC_HRPWM_CSG2_BL_HRPWM_SR3 XMC_HRPWM_CSG_INPUT_SEL_IN 154 #define XMC_HRPWM_CSG2_BL_ERU1_IOUT0 XMC_HRPWM_CSG_INPUT_SEL_IO 155 #define XMC_HRPWM_CSG2_BL_ERU1_IOUT1 XMC_HRPWM_CSG_INPUT_SEL_IP 156 157 /* CSG2 - General input to control start/stop/trigger for Slope Control Logic */ 158 #define XMC_HRPWM_CSG2_SC_SCU_GSHR0 XMC_HRPWM_CSG_INPUT_SEL_IB 159 #define XMC_HRPWM_CSG2_SC_CCU80_ST0 XMC_HRPWM_CSG_INPUT_SEL_IC 160 #define XMC_HRPWM_CSG2_SC_CCU80_ST1 XMC_HRPWM_CSG_INPUT_SEL_ID 161 #define XMC_HRPWM_CSG2_SC_CCU80_ST2 XMC_HRPWM_CSG_INPUT_SEL_IE 162 #define XMC_HRPWM_CSG2_SC_CCU80_ST3 XMC_HRPWM_CSG_INPUT_SEL_IF 163 #define XMC_HRPWM_CSG2_SC_CCU40_ST2 XMC_HRPWM_CSG_INPUT_SEL_IG 164 #define XMC_HRPWM_CSG2_SC_CCU41_ST2 XMC_HRPWM_CSG_INPUT_SEL_IH 165 #define XMC_HRPWM_CSG2_SC_HRPWM_QOUT2 XMC_HRPWM_CSG_INPUT_SEL_II 166 #define XMC_HRPWM_CSG2_SC_HRPWM_QOUT3 XMC_HRPWM_CSG_INPUT_SEL_IJ 167 #define XMC_HRPWM_CSG2_SC_CCU40_SR2 XMC_HRPWM_CSG_INPUT_SEL_IK 168 #define XMC_HRPWM_CSG2_SC_CCU41_SR2 XMC_HRPWM_CSG_INPUT_SEL_IL 169 #define XMC_HRPWM_CSG2_SC_HRPWM_C2O XMC_HRPWM_CSG_INPUT_SEL_IM 170 #define XMC_HRPWM_CSG2_SC_HRPWM_SR3 XMC_HRPWM_CSG_INPUT_SEL_IN 171 #define XMC_HRPWM_CSG2_SC_ERU1_IOUT0 XMC_HRPWM_CSG_INPUT_SEL_IO 172 #define XMC_HRPWM_CSG2_SC_ERU1_IOUT1 XMC_HRPWM_CSG_INPUT_SEL_IP 173 174 #endif 175 176 #endif /* XMC_HRPWM_MAP_H */ 177
