1 /** 2 * @file xmc_ecat_map.h 3 * @date 2016-07-20 4 * 5 * @cond 6 ********************************************************************************************************************* 7 * XMClib v2.1.24 - XMC Peripheral Driver Library 8 * 9 * Copyright (c) 2015-2019, Infineon Technologies AG 10 * All rights reserved. 11 * 12 * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 13 * following conditions are met: 14 * 15 * Redistributions of source code must retain the above copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following 19 * disclaimer in the documentation and/or other materials provided with the distribution. 20 * 21 * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote 22 * products derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, 25 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with 33 * Infineon Technologies AG dave@infineon.com). 34 ********************************************************************************************************************* 35 * 36 * Change History 37 * -------------- 38 * 39 * 2015-09-09: 40 * - Initial 41 * 42 * 2015-07-20: 43 * - Added XMC_ECAT_PORT_CTRL_LATCHIN0_P9_0 and XMC_ECAT_PORT_CTRL_LATCHIN0_P9_1 44 * 45 * @endcond 46 */ 47 48 #ifndef XMC_ECAT_MAP_H 49 #define XMC_ECAT_MAP_H 50 51 /** 52 * ECAT PORT 0 receive data 0 line 53 */ 54 typedef enum XMC_ECAT_PORT0_CTRL_RXD0 55 { 56 XMC_ECAT_PORT0_CTRL_RXD0_P1_4 = 0U, /**< RXD0A receive data line */ 57 XMC_ECAT_PORT0_CTRL_RXD0_P5_0 = 1U, /**< RXD0B receive data line */ 58 XMC_ECAT_PORT0_CTRL_RXD0_P7_4 = 2U, /**< RXD0C receive data line */ 59 } XMC_ECAT_PORT0_CTRL_RXD0_t; 60 61 /** 62 * ECAT PORT 0 receive data 1 line 63 */ 64 typedef enum XMC_ECAT_PORT0_CTRL_RXD1 65 { 66 XMC_ECAT_PORT0_CTRL_RXD1_P1_5 = 0U, /**< RXD1A receive data line */ 67 XMC_ECAT_PORT0_CTRL_RXD1_P5_1 = 1U, /**< RXD1B receive data line */ 68 XMC_ECAT_PORT0_CTRL_RXD1_P7_5 = 2U, /**< RXD1C receive data line */ 69 } XMC_ECAT_PORT0_CTRL_RXD1_t; 70 71 /** 72 * ECAT PORT 0 receive data 2 line 73 */ 74 typedef enum XMC_ECAT_PORT0_CTRL_RXD2 75 { 76 XMC_ECAT_PORT0_CTRL_RXD2_P1_10 = 0U, /**< RXD2A receive data line */ 77 XMC_ECAT_PORT0_CTRL_RXD2_P5_2 = 1U, /**< RXD2B receive data line */ 78 XMC_ECAT_PORT0_CTRL_RXD2_P7_6 = 2U /**< RXD2C receive data line */ 79 } XMC_ECAT_PORT0_CTRL_RXD2_t; 80 81 /** 82 * ECAT PORT 0 receive data 3 line 83 */ 84 typedef enum XMC_ECAT_PORT0_CTRL_RXD3 85 { 86 XMC_ECAT_PORT0_CTRL_RXD3_P1_11 = 0U, /**< RXD3A Receive data line */ 87 XMC_ECAT_PORT0_CTRL_RXD3_P5_7 = 1U, /**< RXD3B Receive data line */ 88 XMC_ECAT_PORT0_CTRL_RXD3_P7_7 = 2U /**< RXD3C Receive data line */ 89 } XMC_ECAT_PORT0_CTRL_RXD3_t; 90 91 /** 92 * ECAT PORT 0 receive error line 93 */ 94 typedef enum XMC_ECAT_PORT0_CTRL_RX_ERR 95 { 96 XMC_ECAT_PORT0_CTRL_RX_ERR_P4_0 = 0U, /**< RX_ERRA Receive error line */ 97 XMC_ECAT_PORT0_CTRL_RX_ERR_P2_6 = 1U, /**< RX_ERRB Receive error line */ 98 XMC_ECAT_PORT0_CTRL_RX_ERR_P7_9 = 2U /**< RX_ERRC Receive error line */ 99 } XMC_ECAT_PORT0_CTRL_RX_ERR_t; 100 101 /** 102 * ECAT PORT 0 receive clock line 103 */ 104 typedef enum XMC_ECAT_PORT0_CTRL_RX_CLK 105 { 106 XMC_ECAT_PORT0_CTRL_RX_CLK_P1_1 = 0U, /**< RX_CLKA Recevive clock */ 107 XMC_ECAT_PORT0_CTRL_RX_CLK_P5_4 = 1U, /**< RX_CLKB Recevive clock */ 108 XMC_ECAT_PORT0_CTRL_RX_CLK_P7_10 = 2U, /**< RX_CLKC Recevive clock */ 109 } XMC_ECAT_PORT0_CTRL_RX_CLK_t; 110 111 /** 112 * ECAT PORT 0 data valid 113 */ 114 typedef enum XMC_ECAT_PORT0_CTRL_RX_DV 115 { 116 XMC_ECAT_PORT0_CTRL_RX_DV_P1_9 = 0U, /**< RX_DVA Receive data valid */ 117 XMC_ECAT_PORT0_CTRL_RX_DV_P5_6 = 1U, /**< RX_DVB Receive data valid */ 118 XMC_ECAT_PORT0_CTRL_RX_DV_P7_11 = 2U, /**< RX_DVC Receive data valid */ 119 } XMC_ECAT_PORT0_CTRL_RX_DV_t; 120 121 /** 122 * ECAT PORT 0 link status 123 */ 124 typedef enum XMC_ECAT_PORT0_CTRL_LINK 125 { 126 XMC_ECAT_PORT0_CTRL_LINK_P4_1 = 0U, /**< LINKA Link status */ 127 XMC_ECAT_PORT0_CTRL_LINK_P1_15 = 1U, /**< LINKB Link status */ 128 XMC_ECAT_PORT0_CTRL_LINK_P9_10 = 2U, /**< LINKC Link status */ 129 } XMC_ECAT_PORT0_CTRL_LINK_t; 130 131 /** 132 * ECAT PORT 0 transmit clock 133 */ 134 typedef enum XMC_ECAT_PORT0_CTRL_TX_CLK 135 { 136 XMC_ECAT_PORT0_CTRL_TX_CLK_P1_0 = 0U, /**< TX_CLKA transmit clock */ 137 XMC_ECAT_PORT0_CTRL_TX_CLK_P5_5 = 1U, /**< TX_CLKB transmit clock */ 138 XMC_ECAT_PORT0_CTRL_TX_CLK_P9_1 = 2U, /**< TX_CLKC transmit clock */ 139 } XMC_ECAT_PORT0_CTRL_TX_CLK_t; 140 141 /** 142 * ECAT PORT 1 receive data 0 line 143 */ 144 typedef enum XMC_ECAT_PORT1_CTRL_RXD0 145 { 146 XMC_ECAT_PORT1_CTRL_RXD0_P0_11 = 0U, /**< RXD0A receive data line */ 147 XMC_ECAT_PORT1_CTRL_RXD0_P14_7 = 1U, /**< RXD0B receive data line */ 148 XMC_ECAT_PORT1_CTRL_RXD0_P8_4 = 2U, /**< RXD0C receive data line */ 149 } XMC_ECAT_PORT1_CTRL_RXD0_t; 150 151 /** 152 * ECAT PORT 1 receive data 1 line 153 */ 154 typedef enum XMC_ECAT_PORT1_CTRL_RXD1 155 { 156 XMC_ECAT_PORT1_CTRL_RXD1_P0_6 = 0U, /**< RXD1A receive data line */ 157 XMC_ECAT_PORT1_CTRL_RXD1_P14_12 = 1U, /**< RXD1B receive data line */ 158 XMC_ECAT_PORT1_CTRL_RXD1_P8_5 = 2U, /**< RXD1C receive data line */ 159 } XMC_ECAT_PORT1_CTRL_RXD1_t; 160 161 /** 162 * ECAT PORT 1 receive data 2 line 163 */ 164 typedef enum XMC_ECAT_PORT1_CTRL_RXD2 165 { 166 XMC_ECAT_PORT1_CTRL_RXD2_P0_5 = 0U, /**< RXD2A receive data line */ 167 XMC_ECAT_PORT1_CTRL_RXD2_P14_13 = 1U, /**< RXD2B receive data line */ 168 XMC_ECAT_PORT1_CTRL_RXD2_P8_6 = 2U /**< RXD2C receive data line */ 169 } XMC_ECAT_PORT1_CTRL_RXD2_t; 170 171 /** 172 * ECAT PORT 1 receive data 3 line 173 */ 174 typedef enum XMC_ECAT_PORT1_CTRL_RXD3 175 { 176 XMC_ECAT_PORT1_CTRL_RXD3_P0_4 = 0U, /**< RXD3A Receive data line */ 177 XMC_ECAT_PORT1_CTRL_RXD3_P14_14 = 1U, /**< RXD3B Receive data line */ 178 XMC_ECAT_PORT1_CTRL_RXD3_P8_7 = 2U /**< RXD3C Receive data line */ 179 } XMC_ECAT_PORT1_CTRL_RXD3_t; 180 181 /** 182 * ECAT PORT 1 receive error line 183 */ 184 typedef enum XMC_ECAT_PORT1_CTRL_RX_ERR 185 { 186 XMC_ECAT_PORT1_CTRL_RX_ERR_P3_5 = 0U, /**< RX_ERRA Receive error line */ 187 XMC_ECAT_PORT1_CTRL_RX_ERR_P15_2 = 1U, /**< RX_ERRB Receive error line */ 188 XMC_ECAT_PORT1_CTRL_RX_ERR_P8_9 = 2U /**< RX_ERRC Receive error line */ 189 } XMC_ECAT_PORT1_CTRL_RX_ERR_t; 190 191 /** 192 * ECAT PORT 1 receive clock line 193 */ 194 typedef enum XMC_ECAT_PORT1_CTRL_RX_CLK 195 { 196 XMC_ECAT_PORT1_CTRL_RX_CLK_P0_1 = 0U, /**< RX_CLKA Recevive clock */ 197 XMC_ECAT_PORT1_CTRL_RX_CLK_P14_6 = 1U, /**< RX_CLKB Recevive clock */ 198 XMC_ECAT_PORT1_CTRL_RX_CLK_P8_10 = 2U, /**< RX_CLKC Recevive clock */ 199 } XMC_ECAT_PORT1_CTRL_RX_CLK_t; 200 201 /** 202 * ECAT PORT 1 data valid 203 */ 204 typedef enum XMC_ECAT_PORT1_CTRL_RX_DV 205 { 206 XMC_ECAT_PORT1_CTRL_RX_DV_P0_9 = 0U, /**< RX_DVA Receive data valid */ 207 XMC_ECAT_PORT1_CTRL_RX_DV_P14_15 = 1U, /**< RX_DVB Receive data valid */ 208 XMC_ECAT_PORT1_CTRL_RX_DV_P8_11 = 2U, /**< RX_DVC Receive data valid */ 209 } XMC_ECAT_PORT1_CTRL_RX_DV_t; 210 211 /** 212 * ECAT PORT 0 link status 213 */ 214 typedef enum XMC_ECAT_PORT1_CTRL_LINK 215 { 216 XMC_ECAT_PORT1_CTRL_LINK_P3_4 = 0U, /**< LINKA Link status */ 217 XMC_ECAT_PORT1_CTRL_LINK_P15_3 = 1U, /**< LINKB Link status */ 218 XMC_ECAT_PORT1_CTRL_LINK_P9_11 = 2U, /**< LINKC Link status */ 219 } XMC_ECAT_PORT1_CTRL_LINK_t; 220 221 /** 222 * ECAT PORT 1 transmit clock 223 */ 224 typedef enum XMC_ECAT_PORT1_CTRL_TX_CLK 225 { 226 XMC_ECAT_PORT1_CTRL_TX_CLK_P0_10 = 0U, /**< TX_CLKA transmit clock */ 227 XMC_ECAT_PORT1_CTRL_TX_CLK_P5_9 = 1U, /**< TX_CLKB transmit clock */ 228 XMC_ECAT_PORT1_CTRL_TX_CLK_P9_0 = 2U, /**< TX_CLKC transmit clock */ 229 } XMC_ECAT_PORT1_CTRL_TX_CLK_t; 230 231 /** 232 * ECAT management data I/O 233 */ 234 typedef enum XMC_ECAT_PORT_CTRL_MDIO 235 { 236 XMC_ECAT_PORT_CTRL_MDIO_P0_12 = 0U, /**< MDIOA management data I/O */ 237 XMC_ECAT_PORT_CTRL_MDIO_P4_2 = 1U, /**< MDIOB management data I/O */ 238 XMC_ECAT_PORT_CTRL_MDIO_P9_7 = 2U /**< MDIOC management data I/O */ 239 } XMC_ECAT_PORT_CTRL_MDIO_t; 240 241 /** 242 * ECAT latch 0 243 */ 244 typedef enum XMC_ECAT_PORT_CTRL_LATCHIN0 245 { 246 XMC_ECAT_PORT_CTRL_LATCHIN0_P14_5 = 0U, /**< LATCH0A line */ 247 XMC_ECAT_PORT_CTRL_LATCHIN0_9_0 = 1U, /**< LATCH0B line @deprecated Please use instead XMC_ECAT_PORT_CTRL_LATCHIN0_P9_0 */ 248 XMC_ECAT_PORT_CTRL_LATCHIN0_P9_0 = 1U, /**< LATCH0B line */ 249 XMC_ECAT_PORT_CTRL_LATCHIN0_ERU0_PDOUT0 = 2U, /**< LATCH0C line */ 250 XMC_ECAT_PORT_CTRL_LATCHIN0_ERU1_PDOUT0 = 3U, /**< LATCH0D line */ 251 } XMC_ECAT_PORT_CTRL_LATCHIN0_t; 252 253 /** 254 * ECAT latch 1 255 */ 256 typedef enum XMC_ECAT_PORT_CTRL_LATCHIN1 257 { 258 XMC_ECAT_PORT_CTRL_LATCHIN1_P14_4 = 0U, /**< LATCH1 A line */ 259 XMC_ECAT_PORT_CTRL_LATCHIN1_9_1 = 1U, /**< LATCH1 B line @deprecated Please use instead XMC_ECAT_PORT_CTRL_LATCHIN1_P9_1 */ 260 XMC_ECAT_PORT_CTRL_LATCHIN1_P9_1 = 1U, /**< LATCH1 B line */ 261 XMC_ECAT_PORT_CTRL_LATCHIN1_ERU0_PDOUT1 = 2U, /**< LATCH1C line */ 262 XMC_ECAT_PORT_CTRL_LATCHIN1_ERU1_PDOUT1 = 3U, /**< LATCH1D line */ 263 } XMC_ECAT_PORT_CTRL_LATCHIN1_t; 264 265 /** 266 * ECAT Port 0 Manual TX Shift configuration 267 */ 268 typedef enum XMC_ECAT_PORT0_CTRL_TX_SHIFT 269 { 270 XMC_ECAT_PORT0_CTRL_TX_SHIFT_0NS = 0U, /**< ECAT Port 0 Manual TX Shift compensation 0 nanoseconds */ 271 XMC_ECAT_PORT0_CTRL_TX_SHIFT_10NS = 1U, /**< ECAT Port 0 Manual TX Shift compensation 10 nanoseconds */ 272 XMC_ECAT_PORT0_CTRL_TX_SHIFT_20NS = 2U, /**< ECAT Port 0 Manual TX Shift compensation 20 nanoseconds */ 273 XMC_ECAT_PORT0_CTRL_TX_SHIFT_30NS = 3U /**< ECAT Port 0 Manual TX Shift compensation 30 nanoseconds */ 274 } XMC_ECAT_PORT0_CTRL_TX_SHIFT_t; 275 276 /** 277 * ECAT Port 1 Manual TX Shift configuration 278 */ 279 typedef enum XMC_ECAT_PORT1_CTRL_TX_SHIFT 280 { 281 XMC_ECAT_PORT1_CTRL_TX_SHIFT_0NS = 0U, /**< ECAT Port 0 Manual TX Shift compensation 0 nanoseconds */ 282 XMC_ECAT_PORT1_CTRL_TX_SHIFT_10NS = 1U, /**< ECAT Port 0 Manual TX Shift compensation 10 nanoseconds */ 283 XMC_ECAT_PORT1_CTRL_TX_SHIFT_20NS = 2U, /**< ECAT Port 0 Manual TX Shift compensation 20 nanoseconds */ 284 XMC_ECAT_PORT1_CTRL_TX_SHIFT_30NS = 3U /**< ECAT Port 0 Manual TX Shift compensation 30 nanoseconds */ 285 } XMC_ECAT_PORT1_CTRL_TX_SHIFT_t; 286 287 #endif 288
