1/*******************************************************************************
2* \file xmc7100d_x4160_cm0plus.icf
3* \version 1.0.0
4*
5* Linker file for the IAR compiler.
6*
7* The main purpose of the linker script is to describe how the sections in the
8* input files should be mapped into the output file, and to control the memory
9* layout of the output file.
10*
11* \note The entry point is fixed and starts at 0x10000000. The valid application
12* image should be placed there.
13*
14* \note The linker files included with the PDL template projects must be generic
15* and handle all common use cases. Your project may not use every section
16* defined in the linker files. In that case you may see warnings during the
17* build process. In your project, you can simply comment out or remove the
18* relevant code in the linker file.
19*
20********************************************************************************
21* \copyright
22* Copyright 2021 Cypress Semiconductor Corporation
23* SPDX-License-Identifier: Apache-2.0
24*
25* Licensed under the Apache License, Version 2.0 (the "License");
26* you may not use this file except in compliance with the License.
27* You may obtain a copy of the License at
28*
29*     http://www.apache.org/licenses/LICENSE-2.0
30*
31* Unless required by applicable law or agreed to in writing, software
32* distributed under the License is distributed on an "AS IS" BASIS,
33* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
34* See the License for the specific language governing permissions and
35* limitations under the License.
36*******************************************************************************/
37define symbol RAMVECTORS_ALIGNMENT              = 128;
38
39define symbol sram_start_reserve                = 0;
40define symbol sram_private_for_srom             = 0x00000800; /* Private SRAM for SROM (e.g. API processing). Reserved at the beginning */
41
42define symbol cm0plus_sram_reserve              = 0x00004000; /* 16K : cm0 sram size */
43define symbol cm0plus_code_flash_reserve        = 0x00080000; /* 512K: cm0 flash size */
44
45define symbol sram_base_address                 = 0x28000000;
46define symbol code_flash_base_address           = 0x10000000;
47
48define symbol ecc_init_width                    = 8; /* Most restrictive native ECC width of all "normal" memories (SRAM, DTCM, ITCM) in any Traveo II derivate is used to keep the code generic */
49
50define symbol cm0plus_heap_reserve              = 0x00001000;
51define symbol cm0plus_stack_reserve             = 0x00001000;
52
53/*###ICF### Section handled by ICF editor, don't touch! ****/
54/*-Editor annotation file-*/
55/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
56/*-Specials-*/
57define symbol __ICFEDIT_intvec_start__ = 0x00000000;
58
59/* The symbols below define the location and size of blocks of memory in the target.
60 * Use these symbols to specify the memory regions available for allocation.
61 */
62
63/* The following symbols control RAM and flash memory allocation for the CM0+ core.
64 * You can change the memory allocation by editing RAM and Flash values.
65 * Using this memory region for other purposes will lead to unexpected behavior.
66 * Your changes must be aligned with the corresponding symbols for CM7 core in 'xx_cm7.icf',
67 * where 'xx' is the device group; for example, 'xmc7100d_x4160_cm7.icf'.
68 * any changes here must also be aligned in file 'xmc7xxx_partition.h'.
69 * after which cm0p core aplication must be build and flashed again.
70 */
71/* RAM */
72define symbol __ICFEDIT_region_RAM_start__ = 0x28000800; // sram_base_address + sram_start_reserve + sram_private_for_srom;
73define symbol __ICFEDIT_region_RAM_end__   = 0x28003FFF; // cm0plus_sram_reserve - 1
74
75/* Flash */
76define symbol __ICFEDIT_region_ROM_start__ = 0x10000000; // code_flash_base_address
77define symbol __ICFEDIT_region_ROM_end__   = 0x1007FFFF; // cm0plus_code_flash_reserve - 1
78
79/*-Sizes-*/
80
81define symbol __ICFEDIT_size_cstack__ = 0x00001000; //cm0plus_stack_reserve
82/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
83define symbol __ICFEDIT_size_heap__ = 0x00001000; //cm0plus_heap_reserve
84
85/**** End of ICF editor section. ###ICF###*/
86
87define symbol heap_reserve                      = __ICFEDIT_size_heap__;
88define symbol stack_reserve                     = (__ICFEDIT_size_cstack__ + (ecc_init_width - 1)) & (~((ecc_init_width - 1))); /* Ensure that stack size is an integer multiple of ECC init width (round up) */
89
90
91define symbol _base_SRAM_CM0P                   = __ICFEDIT_region_RAM_start__;
92define symbol _size_SRAM_CM0P                   = __ICFEDIT_region_RAM_end__ - __ICFEDIT_region_RAM_start__ + 1;
93define symbol _base_CODE_FLASH_CM0P             = __ICFEDIT_region_ROM_start__;
94define symbol _size_CODE_FLASH_CM0P             = __ICFEDIT_region_ROM_end__ - __ICFEDIT_region_ROM_start__ + 1;
95
96/*============================================================
97 * Memory definitions
98 *============================================================
99 */
100
101define memory mem with size = 4G;
102
103define region SRAM                              = mem:[from _base_SRAM_CM0P          size _size_SRAM_CM0P           ];
104define region CODE_FLASH                        = mem:[from _base_CODE_FLASH_CM0P    size _size_CODE_FLASH_CM0P     ];
105
106/*============================================================
107 * Block definitions
108 *============================================================
109 */
110define block CSTACK         with alignment = 8, size = stack_reserve { };
111define block HEAP           with expanding size, alignment = 8, minimum size = heap_reserve { };
112define block HEAP_STACK     { block HEAP, last block CSTACK };
113
114/*============================================================
115 * Initialization
116 *============================================================
117 */
118initialize by copy { readwrite };
119do not initialize  { section .noinit, section .intvec_ram };
120
121/*============================================================
122 * Placement
123 *============================================================
124 */
125
126/* Link location specific assignment of 'readonly' type sections to either SRAM or CODE_FLASH */
127/* Note: .intvec must be the first section in ROM in order for __cm7_vector_base_linker_symbol to be correctly calculated! */
128
129place at start of CODE_FLASH  { section .intvec };
130place in          CODE_FLASH  { readonly };
131
132place in          SRAM  { readwrite };
133place at end   of SRAM  { block HEAP_STACK };
134
135keep {  section .intvec  };
136
137/*============================================================
138 * Symbols for use by application
139 *============================================================
140 */
141/* The start of CM7_0/1 vector table is required by CM0+ application to correctly
142 * set CPUSS->CM7_0/1_VECTOR_TABLE_BASE register before releasing CM7_0 or CM7_1 from reset
143 */
144
145define exported symbol __ecc_init_sram_start_address = start(SRAM);
146define exported symbol __ecc_init_sram_end_address   = end(SRAM);
147
148/* EOF */
149