1 /** 2 * @file xmc4_ccu4_map.h 3 * @date 2019-05-07 4 * 5 * @cond 6 ********************************************************************************************************************* 7 * XMClib v2.1.24 - XMC Peripheral Driver Library 8 * 9 * Copyright (c) 2015-2019, Infineon Technologies AG 10 * All rights reserved. 11 * 12 * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 13 * following conditions are met: 14 * 15 * Redistributions of source code must retain the above copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following 19 * disclaimer in the documentation and/or other materials provided with the distribution. 20 * 21 * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote 22 * products derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, 25 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with 33 * Infineon Technologies AG dave@infineon.com). 34 ********************************************************************************************************************* 35 * 36 * Change History 37 * -------------- 38 * 39 * 2015-08-25: 40 * - Initial version 41 * 42 * 2015-12-07: 43 * - Add XMC4300 support 44 * 45 * 2019-05-07: 46 * - Add missing HRPWM0 inputs for XMC4100, XMC4104 and XMC4200 47 * 48 * @endcond 49 */ 50 51 #ifndef XMC4_CCU4_MAP_H 52 #define XMC4_CCU4_MAP_H 53 54 #define XMC_CCU4_SLICE_INPUT_A (0U) 55 #define XMC_CCU4_SLICE_INPUT_B (1U) 56 #define XMC_CCU4_SLICE_INPUT_C (2U) 57 #define XMC_CCU4_SLICE_INPUT_D (3U) 58 #define XMC_CCU4_SLICE_INPUT_E (4U) 59 #define XMC_CCU4_SLICE_INPUT_F (5U) 60 #define XMC_CCU4_SLICE_INPUT_G (6U) 61 #define XMC_CCU4_SLICE_INPUT_H (7U) 62 #define XMC_CCU4_SLICE_INPUT_I (8U) 63 #define XMC_CCU4_SLICE_INPUT_J (9U) 64 #define XMC_CCU4_SLICE_INPUT_K (10U) 65 #define XMC_CCU4_SLICE_INPUT_L (11U) 66 #define XMC_CCU4_SLICE_INPUT_M (12U) 67 #define XMC_CCU4_SLICE_INPUT_N (13U) 68 #define XMC_CCU4_SLICE_INPUT_O (14U) 69 #define XMC_CCU4_SLICE_INPUT_P (15U) 70 71 #if (UC_DEVICE == XMC4100) && (UC_PACKAGE == LQFP64) 72 #define CCU40_IN0_CAN0_SR7 7 73 #define CCU40_IN0_CCU40_ST0 12 74 #define CCU40_IN0_CCU40_ST1 13 75 #define CCU40_IN0_CCU40_ST2 14 76 #define CCU40_IN0_CCU40_ST3 15 77 #define CCU40_IN0_ERU1_PDOUT0 9 78 #define CCU40_IN0_ERU1_PDOUT1 3 79 #define CCU40_IN0_P1_3 0 80 #define CCU40_IN0_P2_1 2 81 #define CCU40_IN0_P2_8 1 82 #define CCU40_IN0_POSIF0_OUT0 4 83 #define CCU40_IN0_POSIF0_OUT1 5 84 #define CCU40_IN0_POSIF0_OUT3 6 85 #define CCU40_IN0_SCU_ERU1_IOUT0 10 86 #define CCU40_IN0_SCU_GSC40 8 87 #define CCU40_IN0_U0C0_DX2INS 11 88 #define CCU40_IN1_CCU40_ST0 12 89 #define CCU40_IN1_CCU40_ST1 13 90 #define CCU40_IN1_CCU40_ST2 14 91 #define CCU40_IN1_CCU40_ST3 15 92 #define CCU40_IN1_ERU1_PDOUT0 3 93 #define CCU40_IN1_ERU1_PDOUT1 9 94 #define CCU40_IN1_P1_2 0 95 #define CCU40_IN1_P2_0 2 96 #define CCU40_IN1_P2_8 1 97 #define CCU40_IN1_POSIF0_OUT0 4 98 #define CCU40_IN1_POSIF0_OUT1 5 99 #define CCU40_IN1_POSIF0_OUT2 11 100 #define CCU40_IN1_POSIF0_OUT3 6 101 #define CCU40_IN1_POSIF0_OUT4 7 102 #define CCU40_IN1_SCU_ERU1_IOUT1 10 103 #define CCU40_IN1_SCU_GSC40 8 104 #define CCU40_IN2_CCU40_ST0 12 105 #define CCU40_IN2_CCU40_ST1 13 106 #define CCU40_IN2_CCU40_ST2 14 107 #define CCU40_IN2_CCU40_ST3 15 108 #define CCU40_IN2_ERU1_PDOUT0 3 109 #define CCU40_IN2_ERU1_PDOUT2 9 110 #define CCU40_IN2_P1_1 0 111 #define CCU40_IN2_P2_7 2 112 #define CCU40_IN2_P2_8 1 113 #define CCU40_IN2_POSIF0_OUT0 4 114 #define CCU40_IN2_POSIF0_OUT2 5 115 #define CCU40_IN2_POSIF0_OUT3 6 116 #define CCU40_IN2_POSIF0_OUT4 7 117 #define CCU40_IN2_SCU_ERU1_IOUT2 10 118 #define CCU40_IN2_SCU_GSC40 8 119 #define CCU40_IN2_U0C1_DX2INS 11 120 #define CCU40_IN3_CCU40_ST0 12 121 #define CCU40_IN3_CCU40_ST1 13 122 #define CCU40_IN3_CCU40_ST2 14 123 #define CCU40_IN3_CCU40_ST3 15 124 #define CCU40_IN3_CCU80_IGBTO 7 125 #define CCU40_IN3_ERU1_PDOUT0 3 126 #define CCU40_IN3_ERU1_PDOUT3 9 127 #define CCU40_IN3_P1_0 0 128 #define CCU40_IN3_P2_6 2 129 #define CCU40_IN3_P2_8 1 130 #define CCU40_IN3_POSIF0_OUT3 4 131 #define CCU40_IN3_POSIF0_OUT5 5 132 #define CCU40_IN3_SCU_ERU1_IOUT3 10 133 #define CCU40_IN3_SCU_GSC40 8 134 #define CCU40_IN3_U1C0_DX2INS 11 135 #define CCU40_IN3_VADC0_G0ARBCNT 6 136 #define CCU41_IN0_CAN0_SR7 7 137 #define CCU41_IN0_CCU41_ST0 12 138 #define CCU41_IN0_CCU41_ST1 13 139 #define CCU41_IN0_CCU41_ST2 14 140 #define CCU41_IN0_CCU41_ST3 15 141 #define CCU41_IN0_ERU1_PDOUT0 9 142 #define CCU41_IN0_ERU1_PDOUT1 3 143 #define CCU41_IN0_HRPWM0_QOUT0 5 144 #define CCU41_IN0_HRPWM0_QOUT3 6 145 #define CCU41_IN0_P1_4 2 146 #define CCU41_IN0_P2_5 0 147 #define CCU41_IN0_P2_9 1 148 #define CCU41_IN0_SCU_ERU1_IOUT0 10 149 #define CCU41_IN0_SCU_GSC41 8 150 #define CCU41_IN0_VADC0_G0BFL0 11 151 #define CCU41_IN1_CCU41_ST0 12 152 #define CCU41_IN1_CCU41_ST1 13 153 #define CCU41_IN1_CCU41_ST2 14 154 #define CCU41_IN1_CCU41_ST3 15 155 #define CCU41_IN1_ERU1_PDOUT0 3 156 #define CCU41_IN1_ERU1_PDOUT1 9 157 #define CCU41_IN1_HRPWM0_QOUT0 7 158 #define CCU41_IN1_HRPWM0_QOUT1 5 159 #define CCU41_IN1_HRPWM0_QOUT3 6 160 #define CCU41_IN1_P1_5 2 161 #define CCU41_IN1_P2_4 0 162 #define CCU41_IN1_P2_9 1 163 #define CCU41_IN1_SCU_ERU1_IOUT1 10 164 #define CCU41_IN1_SCU_GSC41 8 165 #define CCU41_IN2_CCU41_ST0 12 166 #define CCU41_IN2_CCU41_ST1 13 167 #define CCU41_IN2_CCU41_ST2 14 168 #define CCU41_IN2_CCU41_ST3 15 169 #define CCU41_IN2_ERU1_PDOUT0 3 170 #define CCU41_IN2_ERU1_PDOUT2 9 171 #define CCU41_IN2_HRPWM0_QOUT0 7 172 #define CCU41_IN2_HRPWM0_QOUT2 5 173 #define CCU41_IN2_HRPWM0_QOUT3 6 174 #define CCU41_IN2_P2_3 0 175 #define CCU41_IN2_P2_9 1 176 #define CCU41_IN2_SCU_ERU1_IOUT2 10 177 #define CCU41_IN2_SCU_GSC41 8 178 #define CCU41_IN2_VADC0_G0BFL1 11 179 #define CCU41_IN3_CCU41_ST0 12 180 #define CCU41_IN3_CCU41_ST1 13 181 #define CCU41_IN3_CCU41_ST2 14 182 #define CCU41_IN3_CCU41_ST3 15 183 #define CCU41_IN3_ERU1_PDOUT0 3 184 #define CCU41_IN3_ERU1_PDOUT3 9 185 #define CCU41_IN3_HRPWM0_QOUT0 7 186 #define CCU41_IN3_HRPWM0_QOUT3 5 187 #define CCU41_IN3_P2_2 0 188 #define CCU41_IN3_P2_9 1 189 #define CCU41_IN3_SCU_ERU1_IOUT3 10 190 #define CCU41_IN3_SCU_GSC41 8 191 #define CCU41_IN3_VADC0_G0BFL2 11 192 #define CCU41_IN3_VADC0_G1ARBCNT 6 193 #endif 194 195 196 #if (UC_DEVICE == XMC4100) && (UC_PACKAGE == VQFN48) 197 #define CCU40_IN0_CAN0_SR7 7 198 #define CCU40_IN0_CCU40_ST0 12 199 #define CCU40_IN0_CCU40_ST1 13 200 #define CCU40_IN0_CCU40_ST2 14 201 #define CCU40_IN0_CCU40_ST3 15 202 #define CCU40_IN0_ERU1_PDOUT0 9 203 #define CCU40_IN0_ERU1_PDOUT1 3 204 #define CCU40_IN0_P1_3 0 205 #define CCU40_IN0_P2_1 2 206 #define CCU40_IN0_POSIF0_OUT0 4 207 #define CCU40_IN0_POSIF0_OUT1 5 208 #define CCU40_IN0_POSIF0_OUT3 6 209 #define CCU40_IN0_SCU_ERU1_IOUT0 10 210 #define CCU40_IN0_SCU_GSC40 8 211 #define CCU40_IN0_U0C0_DX2INS 11 212 #define CCU40_IN1_CCU40_ST0 12 213 #define CCU40_IN1_CCU40_ST1 13 214 #define CCU40_IN1_CCU40_ST2 14 215 #define CCU40_IN1_CCU40_ST3 15 216 #define CCU40_IN1_ERU1_PDOUT0 3 217 #define CCU40_IN1_ERU1_PDOUT1 9 218 #define CCU40_IN1_P1_2 0 219 #define CCU40_IN1_P2_0 2 220 #define CCU40_IN1_POSIF0_OUT0 4 221 #define CCU40_IN1_POSIF0_OUT1 5 222 #define CCU40_IN1_POSIF0_OUT2 11 223 #define CCU40_IN1_POSIF0_OUT3 6 224 #define CCU40_IN1_POSIF0_OUT4 7 225 #define CCU40_IN1_SCU_ERU1_IOUT1 10 226 #define CCU40_IN1_SCU_GSC40 8 227 #define CCU40_IN2_CCU40_ST0 12 228 #define CCU40_IN2_CCU40_ST1 13 229 #define CCU40_IN2_CCU40_ST2 14 230 #define CCU40_IN2_CCU40_ST3 15 231 #define CCU40_IN2_ERU1_PDOUT0 3 232 #define CCU40_IN2_ERU1_PDOUT2 9 233 #define CCU40_IN2_P1_1 0 234 #define CCU40_IN2_POSIF0_OUT0 4 235 #define CCU40_IN2_POSIF0_OUT2 5 236 #define CCU40_IN2_POSIF0_OUT3 6 237 #define CCU40_IN2_POSIF0_OUT4 7 238 #define CCU40_IN2_SCU_ERU1_IOUT2 10 239 #define CCU40_IN2_SCU_GSC40 8 240 #define CCU40_IN2_U0C1_DX2INS 11 241 #define CCU40_IN3_CCU40_ST0 12 242 #define CCU40_IN3_CCU40_ST1 13 243 #define CCU40_IN3_CCU40_ST2 14 244 #define CCU40_IN3_CCU40_ST3 15 245 #define CCU40_IN3_CCU80_IGBTO 7 246 #define CCU40_IN3_ERU1_PDOUT0 3 247 #define CCU40_IN3_ERU1_PDOUT3 9 248 #define CCU40_IN3_P1_0 0 249 #define CCU40_IN3_POSIF0_OUT3 4 250 #define CCU40_IN3_POSIF0_OUT5 5 251 #define CCU40_IN3_SCU_ERU1_IOUT3 10 252 #define CCU40_IN3_SCU_GSC40 8 253 #define CCU40_IN3_U1C0_DX2INS 11 254 #define CCU40_IN3_VADC0_G0ARBCNT 6 255 #define CCU41_IN0_CAN0_SR7 7 256 #define CCU41_IN0_CCU41_ST0 12 257 #define CCU41_IN0_CCU41_ST1 13 258 #define CCU41_IN0_CCU41_ST2 14 259 #define CCU41_IN0_CCU41_ST3 15 260 #define CCU41_IN0_ERU1_PDOUT0 9 261 #define CCU41_IN0_ERU1_PDOUT1 3 262 #define CCU41_IN0_HRPWM0_QOUT0 5 263 #define CCU41_IN0_HRPWM0_QOUT3 6 264 #define CCU41_IN0_P1_4 2 265 #define CCU41_IN0_P2_5 0 266 #define CCU41_IN0_SCU_ERU1_IOUT0 10 267 #define CCU41_IN0_SCU_GSC41 8 268 #define CCU41_IN0_VADC0_G0BFL0 11 269 #define CCU41_IN1_CCU41_ST0 12 270 #define CCU41_IN1_CCU41_ST1 13 271 #define CCU41_IN1_CCU41_ST2 14 272 #define CCU41_IN1_CCU41_ST3 15 273 #define CCU41_IN1_ERU1_PDOUT0 3 274 #define CCU41_IN1_ERU1_PDOUT1 9 275 #define CCU41_IN1_HRPWM0_QOUT0 7 276 #define CCU41_IN1_HRPWM0_QOUT1 5 277 #define CCU41_IN1_HRPWM0_QOUT3 6 278 #define CCU41_IN1_P1_5 2 279 #define CCU41_IN1_P2_4 0 280 #define CCU41_IN1_SCU_ERU1_IOUT1 10 281 #define CCU41_IN1_SCU_GSC41 8 282 #define CCU41_IN2_CCU41_ST0 12 283 #define CCU41_IN2_CCU41_ST1 13 284 #define CCU41_IN2_CCU41_ST2 14 285 #define CCU41_IN2_CCU41_ST3 15 286 #define CCU41_IN2_ERU1_PDOUT0 3 287 #define CCU41_IN2_ERU1_PDOUT2 9 288 #define CCU41_IN2_HRPWM0_QOUT0 7 289 #define CCU41_IN2_HRPWM0_QOUT2 5 290 #define CCU41_IN2_HRPWM0_QOUT3 6 291 #define CCU41_IN2_P2_3 0 292 #define CCU41_IN2_SCU_ERU1_IOUT2 10 293 #define CCU41_IN2_SCU_GSC41 8 294 #define CCU41_IN2_VADC0_G0BFL1 11 295 #define CCU41_IN3_CCU41_ST0 12 296 #define CCU41_IN3_CCU41_ST1 13 297 #define CCU41_IN3_CCU41_ST2 14 298 #define CCU41_IN3_CCU41_ST3 15 299 #define CCU41_IN3_ERU1_PDOUT0 3 300 #define CCU41_IN3_ERU1_PDOUT3 9 301 #define CCU41_IN3_HRPWM0_QOUT0 7 302 #define CCU41_IN3_HRPWM0_QOUT3 5 303 #define CCU41_IN3_P2_2 0 304 #define CCU41_IN3_SCU_ERU1_IOUT3 10 305 #define CCU41_IN3_SCU_GSC41 8 306 #define CCU41_IN3_VADC0_G0BFL2 11 307 #define CCU41_IN3_VADC0_G1ARBCNT 6 308 #endif 309 310 311 #if (UC_DEVICE == XMC4104) && (UC_PACKAGE == LQFP64) 312 #define CCU40_IN0_CCU40_ST0 12 313 #define CCU40_IN0_CCU40_ST1 13 314 #define CCU40_IN0_CCU40_ST2 14 315 #define CCU40_IN0_CCU40_ST3 15 316 #define CCU40_IN0_ERU1_PDOUT0 9 317 #define CCU40_IN0_ERU1_PDOUT1 3 318 #define CCU40_IN0_P1_3 0 319 #define CCU40_IN0_P2_1 2 320 #define CCU40_IN0_P2_8 1 321 #define CCU40_IN0_POSIF0_OUT0 4 322 #define CCU40_IN0_POSIF0_OUT1 5 323 #define CCU40_IN0_POSIF0_OUT3 6 324 #define CCU40_IN0_SCU_ERU1_IOUT0 10 325 #define CCU40_IN0_SCU_GSC40 8 326 #define CCU40_IN0_U0C0_DX2INS 11 327 #define CCU40_IN1_CCU40_ST0 12 328 #define CCU40_IN1_CCU40_ST1 13 329 #define CCU40_IN1_CCU40_ST2 14 330 #define CCU40_IN1_CCU40_ST3 15 331 #define CCU40_IN1_ERU1_PDOUT0 3 332 #define CCU40_IN1_ERU1_PDOUT1 9 333 #define CCU40_IN1_P1_2 0 334 #define CCU40_IN1_P2_0 2 335 #define CCU40_IN1_P2_8 1 336 #define CCU40_IN1_POSIF0_OUT0 4 337 #define CCU40_IN1_POSIF0_OUT1 5 338 #define CCU40_IN1_POSIF0_OUT2 11 339 #define CCU40_IN1_POSIF0_OUT3 6 340 #define CCU40_IN1_POSIF0_OUT4 7 341 #define CCU40_IN1_SCU_ERU1_IOUT1 10 342 #define CCU40_IN1_SCU_GSC40 8 343 #define CCU40_IN2_CCU40_ST0 12 344 #define CCU40_IN2_CCU40_ST1 13 345 #define CCU40_IN2_CCU40_ST2 14 346 #define CCU40_IN2_CCU40_ST3 15 347 #define CCU40_IN2_ERU1_PDOUT0 3 348 #define CCU40_IN2_ERU1_PDOUT2 9 349 #define CCU40_IN2_P1_1 0 350 #define CCU40_IN2_P2_7 2 351 #define CCU40_IN2_P2_8 1 352 #define CCU40_IN2_POSIF0_OUT0 4 353 #define CCU40_IN2_POSIF0_OUT2 5 354 #define CCU40_IN2_POSIF0_OUT3 6 355 #define CCU40_IN2_POSIF0_OUT4 7 356 #define CCU40_IN2_SCU_ERU1_IOUT2 10 357 #define CCU40_IN2_SCU_GSC40 8 358 #define CCU40_IN2_U0C1_DX2INS 11 359 #define CCU40_IN3_CCU40_ST0 12 360 #define CCU40_IN3_CCU40_ST1 13 361 #define CCU40_IN3_CCU40_ST2 14 362 #define CCU40_IN3_CCU40_ST3 15 363 #define CCU40_IN3_CCU80_IGBTO 7 364 #define CCU40_IN3_ERU1_PDOUT0 3 365 #define CCU40_IN3_ERU1_PDOUT3 9 366 #define CCU40_IN3_P1_0 0 367 #define CCU40_IN3_P2_6 2 368 #define CCU40_IN3_P2_8 1 369 #define CCU40_IN3_POSIF0_OUT3 4 370 #define CCU40_IN3_POSIF0_OUT5 5 371 #define CCU40_IN3_SCU_ERU1_IOUT3 10 372 #define CCU40_IN3_SCU_GSC40 8 373 #define CCU40_IN3_U1C0_DX2INS 11 374 #define CCU40_IN3_VADC0_G0ARBCNT 6 375 #define CCU41_IN0_CCU41_ST0 12 376 #define CCU41_IN0_CCU41_ST1 13 377 #define CCU41_IN0_CCU41_ST2 14 378 #define CCU41_IN0_CCU41_ST3 15 379 #define CCU41_IN0_ERU1_PDOUT0 9 380 #define CCU41_IN0_ERU1_PDOUT1 3 381 #define CCU41_IN0_HRPWM0_QOUT0 5 382 #define CCU41_IN0_HRPWM0_QOUT3 6 383 #define CCU41_IN0_P1_4 2 384 #define CCU41_IN0_P2_5 0 385 #define CCU41_IN0_P2_9 1 386 #define CCU41_IN0_SCU_ERU1_IOUT0 10 387 #define CCU41_IN0_SCU_GSC41 8 388 #define CCU41_IN0_VADC0_G0BFL0 11 389 #define CCU41_IN1_CCU41_ST0 12 390 #define CCU41_IN1_CCU41_ST1 13 391 #define CCU41_IN1_CCU41_ST2 14 392 #define CCU41_IN1_CCU41_ST3 15 393 #define CCU41_IN1_ERU1_PDOUT0 3 394 #define CCU41_IN1_ERU1_PDOUT1 9 395 #define CCU41_IN1_HRPWM0_QOUT0 7 396 #define CCU41_IN1_HRPWM0_QOUT1 5 397 #define CCU41_IN1_HRPWM0_QOUT3 6 398 #define CCU41_IN1_P1_5 2 399 #define CCU41_IN1_P2_4 0 400 #define CCU41_IN1_P2_9 1 401 #define CCU41_IN1_SCU_ERU1_IOUT1 10 402 #define CCU41_IN1_SCU_GSC41 8 403 #define CCU41_IN2_CCU41_ST0 12 404 #define CCU41_IN2_CCU41_ST1 13 405 #define CCU41_IN2_CCU41_ST2 14 406 #define CCU41_IN2_CCU41_ST3 15 407 #define CCU41_IN2_ERU1_PDOUT0 3 408 #define CCU41_IN2_ERU1_PDOUT2 9 409 #define CCU41_IN2_HRPWM0_QOUT0 7 410 #define CCU41_IN2_HRPWM0_QOUT2 5 411 #define CCU41_IN2_HRPWM0_QOUT3 6 412 #define CCU41_IN2_P2_3 0 413 #define CCU41_IN2_P2_9 1 414 #define CCU41_IN2_SCU_ERU1_IOUT2 10 415 #define CCU41_IN2_SCU_GSC41 8 416 #define CCU41_IN2_VADC0_G0BFL1 11 417 #define CCU41_IN3_CCU41_ST0 12 418 #define CCU41_IN3_CCU41_ST1 13 419 #define CCU41_IN3_CCU41_ST2 14 420 #define CCU41_IN3_CCU41_ST3 15 421 #define CCU41_IN3_ERU1_PDOUT0 3 422 #define CCU41_IN3_ERU1_PDOUT3 9 423 #define CCU41_IN3_HRPWM0_QOUT0 7 424 #define CCU41_IN3_HRPWM0_QOUT3 5 425 #define CCU41_IN3_P2_2 0 426 #define CCU41_IN3_P2_9 1 427 #define CCU41_IN3_SCU_ERU1_IOUT3 10 428 #define CCU41_IN3_SCU_GSC41 8 429 #define CCU41_IN3_VADC0_G0BFL2 11 430 #define CCU41_IN3_VADC0_G1ARBCNT 6 431 #endif 432 433 434 #if (UC_DEVICE == XMC4104) && (UC_PACKAGE == VQFN48) 435 #define CCU40_IN0_CCU40_ST0 12 436 #define CCU40_IN0_CCU40_ST1 13 437 #define CCU40_IN0_CCU40_ST2 14 438 #define CCU40_IN0_CCU40_ST3 15 439 #define CCU40_IN0_ERU1_PDOUT0 9 440 #define CCU40_IN0_ERU1_PDOUT1 3 441 #define CCU40_IN0_P1_3 0 442 #define CCU40_IN0_P2_1 2 443 #define CCU40_IN0_POSIF0_OUT0 4 444 #define CCU40_IN0_POSIF0_OUT1 5 445 #define CCU40_IN0_POSIF0_OUT3 6 446 #define CCU40_IN0_SCU_ERU1_IOUT0 10 447 #define CCU40_IN0_SCU_GSC40 8 448 #define CCU40_IN0_U0C0_DX2INS 11 449 #define CCU40_IN1_CCU40_ST0 12 450 #define CCU40_IN1_CCU40_ST1 13 451 #define CCU40_IN1_CCU40_ST2 14 452 #define CCU40_IN1_CCU40_ST3 15 453 #define CCU40_IN1_ERU1_PDOUT0 3 454 #define CCU40_IN1_ERU1_PDOUT1 9 455 #define CCU40_IN1_P1_2 0 456 #define CCU40_IN1_P2_0 2 457 #define CCU40_IN1_POSIF0_OUT0 4 458 #define CCU40_IN1_POSIF0_OUT1 5 459 #define CCU40_IN1_POSIF0_OUT2 11 460 #define CCU40_IN1_POSIF0_OUT3 6 461 #define CCU40_IN1_POSIF0_OUT4 7 462 #define CCU40_IN1_SCU_ERU1_IOUT1 10 463 #define CCU40_IN1_SCU_GSC40 8 464 #define CCU40_IN2_CCU40_ST0 12 465 #define CCU40_IN2_CCU40_ST1 13 466 #define CCU40_IN2_CCU40_ST2 14 467 #define CCU40_IN2_CCU40_ST3 15 468 #define CCU40_IN2_ERU1_PDOUT0 3 469 #define CCU40_IN2_ERU1_PDOUT2 9 470 #define CCU40_IN2_P1_1 0 471 #define CCU40_IN2_POSIF0_OUT0 4 472 #define CCU40_IN2_POSIF0_OUT2 5 473 #define CCU40_IN2_POSIF0_OUT3 6 474 #define CCU40_IN2_POSIF0_OUT4 7 475 #define CCU40_IN2_SCU_ERU1_IOUT2 10 476 #define CCU40_IN2_SCU_GSC40 8 477 #define CCU40_IN2_U0C1_DX2INS 11 478 #define CCU40_IN3_CCU40_ST0 12 479 #define CCU40_IN3_CCU40_ST1 13 480 #define CCU40_IN3_CCU40_ST2 14 481 #define CCU40_IN3_CCU40_ST3 15 482 #define CCU40_IN3_CCU80_IGBTO 7 483 #define CCU40_IN3_ERU1_PDOUT0 3 484 #define CCU40_IN3_ERU1_PDOUT3 9 485 #define CCU40_IN3_P1_0 0 486 #define CCU40_IN3_POSIF0_OUT3 4 487 #define CCU40_IN3_POSIF0_OUT5 5 488 #define CCU40_IN3_SCU_ERU1_IOUT3 10 489 #define CCU40_IN3_SCU_GSC40 8 490 #define CCU40_IN3_U1C0_DX2INS 11 491 #define CCU40_IN3_VADC0_G0ARBCNT 6 492 #define CCU41_IN0_CCU41_ST0 12 493 #define CCU41_IN0_CCU41_ST1 13 494 #define CCU41_IN0_CCU41_ST2 14 495 #define CCU41_IN0_CCU41_ST3 15 496 #define CCU41_IN0_ERU1_PDOUT0 9 497 #define CCU41_IN0_ERU1_PDOUT1 3 498 #define CCU41_IN0_HRPWM0_QOUT0 5 499 #define CCU41_IN0_HRPWM0_QOUT3 6 500 #define CCU41_IN0_P1_4 2 501 #define CCU41_IN0_P2_5 0 502 #define CCU41_IN0_SCU_ERU1_IOUT0 10 503 #define CCU41_IN0_SCU_GSC41 8 504 #define CCU41_IN0_VADC0_G0BFL0 11 505 #define CCU41_IN1_CCU41_ST0 12 506 #define CCU41_IN1_CCU41_ST1 13 507 #define CCU41_IN1_CCU41_ST2 14 508 #define CCU41_IN1_CCU41_ST3 15 509 #define CCU41_IN1_ERU1_PDOUT0 3 510 #define CCU41_IN1_ERU1_PDOUT1 9 511 #define CCU41_IN1_HRPWM0_QOUT0 7 512 #define CCU41_IN1_HRPWM0_QOUT1 5 513 #define CCU41_IN1_HRPWM0_QOUT3 6 514 #define CCU41_IN1_P1_5 2 515 #define CCU41_IN1_P2_4 0 516 #define CCU41_IN1_SCU_ERU1_IOUT1 10 517 #define CCU41_IN1_SCU_GSC41 8 518 #define CCU41_IN2_CCU41_ST0 12 519 #define CCU41_IN2_CCU41_ST1 13 520 #define CCU41_IN2_CCU41_ST2 14 521 #define CCU41_IN2_CCU41_ST3 15 522 #define CCU41_IN2_ERU1_PDOUT0 3 523 #define CCU41_IN2_ERU1_PDOUT2 9 524 #define CCU41_IN2_HRPWM0_QOUT0 7 525 #define CCU41_IN2_HRPWM0_QOUT2 5 526 #define CCU41_IN2_HRPWM0_QOUT3 6 527 #define CCU41_IN2_P2_3 0 528 #define CCU41_IN2_SCU_ERU1_IOUT2 10 529 #define CCU41_IN2_SCU_GSC41 8 530 #define CCU41_IN2_VADC0_G0BFL1 11 531 #define CCU41_IN3_CCU41_ST0 12 532 #define CCU41_IN3_CCU41_ST1 13 533 #define CCU41_IN3_CCU41_ST2 14 534 #define CCU41_IN3_CCU41_ST3 15 535 #define CCU41_IN3_ERU1_PDOUT0 3 536 #define CCU41_IN3_ERU1_PDOUT3 9 537 #define CCU41_IN3_HRPWM0_QOUT0 7 538 #define CCU41_IN3_HRPWM0_QOUT3 5 539 #define CCU41_IN3_P2_2 0 540 #define CCU41_IN3_SCU_ERU1_IOUT3 10 541 #define CCU41_IN3_SCU_GSC41 8 542 #define CCU41_IN3_VADC0_G0BFL2 11 543 #define CCU41_IN3_VADC0_G1ARBCNT 6 544 #endif 545 546 547 #if (UC_DEVICE == XMC4108) && (UC_PACKAGE == LQFP64) 548 #define CCU40_IN0_CAN0_SR7 7 549 #define CCU40_IN0_CCU40_ST0 12 550 #define CCU40_IN0_CCU40_ST1 13 551 #define CCU40_IN0_CCU40_ST2 14 552 #define CCU40_IN0_CCU40_ST3 15 553 #define CCU40_IN0_ERU1_PDOUT0 9 554 #define CCU40_IN0_ERU1_PDOUT1 3 555 #define CCU40_IN0_P1_3 0 556 #define CCU40_IN0_P2_1 2 557 #define CCU40_IN0_P2_8 1 558 #define CCU40_IN0_POSIF0_OUT0 4 559 #define CCU40_IN0_POSIF0_OUT1 5 560 #define CCU40_IN0_POSIF0_OUT3 6 561 #define CCU40_IN0_SCU_ERU1_IOUT0 10 562 #define CCU40_IN0_SCU_GSC40 8 563 #define CCU40_IN0_U0C0_DX2INS 11 564 #define CCU40_IN1_CCU40_ST0 12 565 #define CCU40_IN1_CCU40_ST1 13 566 #define CCU40_IN1_CCU40_ST2 14 567 #define CCU40_IN1_CCU40_ST3 15 568 #define CCU40_IN1_ERU1_PDOUT0 3 569 #define CCU40_IN1_ERU1_PDOUT1 9 570 #define CCU40_IN1_P1_2 0 571 #define CCU40_IN1_P2_0 2 572 #define CCU40_IN1_P2_8 1 573 #define CCU40_IN1_POSIF0_OUT0 4 574 #define CCU40_IN1_POSIF0_OUT1 5 575 #define CCU40_IN1_POSIF0_OUT2 11 576 #define CCU40_IN1_POSIF0_OUT3 6 577 #define CCU40_IN1_POSIF0_OUT4 7 578 #define CCU40_IN1_SCU_ERU1_IOUT1 10 579 #define CCU40_IN1_SCU_GSC40 8 580 #define CCU40_IN2_CCU40_ST0 12 581 #define CCU40_IN2_CCU40_ST1 13 582 #define CCU40_IN2_CCU40_ST2 14 583 #define CCU40_IN2_CCU40_ST3 15 584 #define CCU40_IN2_ERU1_PDOUT0 3 585 #define CCU40_IN2_ERU1_PDOUT2 9 586 #define CCU40_IN2_P1_1 0 587 #define CCU40_IN2_P2_7 2 588 #define CCU40_IN2_P2_8 1 589 #define CCU40_IN2_POSIF0_OUT0 4 590 #define CCU40_IN2_POSIF0_OUT2 5 591 #define CCU40_IN2_POSIF0_OUT3 6 592 #define CCU40_IN2_POSIF0_OUT4 7 593 #define CCU40_IN2_SCU_ERU1_IOUT2 10 594 #define CCU40_IN2_SCU_GSC40 8 595 #define CCU40_IN2_U0C1_DX2INS 11 596 #define CCU40_IN3_CCU40_ST0 12 597 #define CCU40_IN3_CCU40_ST1 13 598 #define CCU40_IN3_CCU40_ST2 14 599 #define CCU40_IN3_CCU40_ST3 15 600 #define CCU40_IN3_CCU80_IGBTO 7 601 #define CCU40_IN3_ERU1_PDOUT0 3 602 #define CCU40_IN3_ERU1_PDOUT3 9 603 #define CCU40_IN3_P1_0 0 604 #define CCU40_IN3_P2_6 2 605 #define CCU40_IN3_P2_8 1 606 #define CCU40_IN3_POSIF0_OUT3 4 607 #define CCU40_IN3_POSIF0_OUT5 5 608 #define CCU40_IN3_SCU_ERU1_IOUT3 10 609 #define CCU40_IN3_SCU_GSC40 8 610 #define CCU40_IN3_U1C0_DX2INS 11 611 #define CCU40_IN3_VADC0_G0ARBCNT 6 612 #define CCU41_IN0_CAN0_SR7 7 613 #define CCU41_IN0_CCU41_ST0 12 614 #define CCU41_IN0_CCU41_ST1 13 615 #define CCU41_IN0_CCU41_ST2 14 616 #define CCU41_IN0_CCU41_ST3 15 617 #define CCU41_IN0_ERU1_PDOUT0 9 618 #define CCU41_IN0_ERU1_PDOUT1 3 619 #define CCU41_IN0_P1_4 2 620 #define CCU41_IN0_P2_5 0 621 #define CCU41_IN0_P2_9 1 622 #define CCU41_IN0_SCU_ERU1_IOUT0 10 623 #define CCU41_IN0_SCU_GSC41 8 624 #define CCU41_IN0_VADC0_G0BFL0 11 625 #define CCU41_IN1_CCU41_ST0 12 626 #define CCU41_IN1_CCU41_ST1 13 627 #define CCU41_IN1_CCU41_ST2 14 628 #define CCU41_IN1_CCU41_ST3 15 629 #define CCU41_IN1_ERU1_PDOUT0 3 630 #define CCU41_IN1_ERU1_PDOUT1 9 631 #define CCU41_IN1_P1_5 2 632 #define CCU41_IN1_P2_4 0 633 #define CCU41_IN1_P2_9 1 634 #define CCU41_IN1_SCU_ERU1_IOUT1 10 635 #define CCU41_IN1_SCU_GSC41 8 636 #define CCU41_IN2_CCU41_ST0 12 637 #define CCU41_IN2_CCU41_ST1 13 638 #define CCU41_IN2_CCU41_ST2 14 639 #define CCU41_IN2_CCU41_ST3 15 640 #define CCU41_IN2_ERU1_PDOUT0 3 641 #define CCU41_IN2_ERU1_PDOUT2 9 642 #define CCU41_IN2_P2_3 0 643 #define CCU41_IN2_P2_9 1 644 #define CCU41_IN2_SCU_ERU1_IOUT2 10 645 #define CCU41_IN2_SCU_GSC41 8 646 #define CCU41_IN2_VADC0_G0BFL1 11 647 #define CCU41_IN3_CCU41_ST0 12 648 #define CCU41_IN3_CCU41_ST1 13 649 #define CCU41_IN3_CCU41_ST2 14 650 #define CCU41_IN3_CCU41_ST3 15 651 #define CCU41_IN3_ERU1_PDOUT0 3 652 #define CCU41_IN3_ERU1_PDOUT3 9 653 #define CCU41_IN3_P2_2 0 654 #define CCU41_IN3_P2_9 1 655 #define CCU41_IN3_SCU_ERU1_IOUT3 10 656 #define CCU41_IN3_SCU_GSC41 8 657 #define CCU41_IN3_VADC0_G0BFL2 11 658 #define CCU41_IN3_VADC0_G1ARBCNT 6 659 #endif 660 661 662 #if (UC_DEVICE == XMC4108) && (UC_PACKAGE == VQFN48) 663 #define CCU40_IN0_CAN0_SR7 7 664 #define CCU40_IN0_CCU40_ST0 12 665 #define CCU40_IN0_CCU40_ST1 13 666 #define CCU40_IN0_CCU40_ST2 14 667 #define CCU40_IN0_CCU40_ST3 15 668 #define CCU40_IN0_ERU1_PDOUT0 9 669 #define CCU40_IN0_ERU1_PDOUT1 3 670 #define CCU40_IN0_P1_3 0 671 #define CCU40_IN0_P2_1 2 672 #define CCU40_IN0_POSIF0_OUT0 4 673 #define CCU40_IN0_POSIF0_OUT1 5 674 #define CCU40_IN0_POSIF0_OUT3 6 675 #define CCU40_IN0_SCU_ERU1_IOUT0 10 676 #define CCU40_IN0_SCU_GSC40 8 677 #define CCU40_IN0_U0C0_DX2INS 11 678 #define CCU40_IN1_CCU40_ST0 12 679 #define CCU40_IN1_CCU40_ST1 13 680 #define CCU40_IN1_CCU40_ST2 14 681 #define CCU40_IN1_CCU40_ST3 15 682 #define CCU40_IN1_ERU1_PDOUT0 3 683 #define CCU40_IN1_ERU1_PDOUT1 9 684 #define CCU40_IN1_P1_2 0 685 #define CCU40_IN1_P2_0 2 686 #define CCU40_IN1_POSIF0_OUT0 4 687 #define CCU40_IN1_POSIF0_OUT1 5 688 #define CCU40_IN1_POSIF0_OUT2 11 689 #define CCU40_IN1_POSIF0_OUT3 6 690 #define CCU40_IN1_POSIF0_OUT4 7 691 #define CCU40_IN1_SCU_ERU1_IOUT1 10 692 #define CCU40_IN1_SCU_GSC40 8 693 #define CCU40_IN2_CCU40_ST0 12 694 #define CCU40_IN2_CCU40_ST1 13 695 #define CCU40_IN2_CCU40_ST2 14 696 #define CCU40_IN2_CCU40_ST3 15 697 #define CCU40_IN2_ERU1_PDOUT0 3 698 #define CCU40_IN2_ERU1_PDOUT2 9 699 #define CCU40_IN2_P1_1 0 700 #define CCU40_IN2_POSIF0_OUT0 4 701 #define CCU40_IN2_POSIF0_OUT2 5 702 #define CCU40_IN2_POSIF0_OUT3 6 703 #define CCU40_IN2_POSIF0_OUT4 7 704 #define CCU40_IN2_SCU_ERU1_IOUT2 10 705 #define CCU40_IN2_SCU_GSC40 8 706 #define CCU40_IN2_U0C1_DX2INS 11 707 #define CCU40_IN3_CCU40_ST0 12 708 #define CCU40_IN3_CCU40_ST1 13 709 #define CCU40_IN3_CCU40_ST2 14 710 #define CCU40_IN3_CCU40_ST3 15 711 #define CCU40_IN3_CCU80_IGBTO 7 712 #define CCU40_IN3_ERU1_PDOUT0 3 713 #define CCU40_IN3_ERU1_PDOUT3 9 714 #define CCU40_IN3_P1_0 0 715 #define CCU40_IN3_POSIF0_OUT3 4 716 #define CCU40_IN3_POSIF0_OUT5 5 717 #define CCU40_IN3_SCU_ERU1_IOUT3 10 718 #define CCU40_IN3_SCU_GSC40 8 719 #define CCU40_IN3_U1C0_DX2INS 11 720 #define CCU40_IN3_VADC0_G0ARBCNT 6 721 #define CCU41_IN0_CAN0_SR7 7 722 #define CCU41_IN0_CCU41_ST0 12 723 #define CCU41_IN0_CCU41_ST1 13 724 #define CCU41_IN0_CCU41_ST2 14 725 #define CCU41_IN0_CCU41_ST3 15 726 #define CCU41_IN0_ERU1_PDOUT0 9 727 #define CCU41_IN0_ERU1_PDOUT1 3 728 #define CCU41_IN0_P1_4 2 729 #define CCU41_IN0_P2_5 0 730 #define CCU41_IN0_SCU_ERU1_IOUT0 10 731 #define CCU41_IN0_SCU_GSC41 8 732 #define CCU41_IN0_VADC0_G0BFL0 11 733 #define CCU41_IN1_CCU41_ST0 12 734 #define CCU41_IN1_CCU41_ST1 13 735 #define CCU41_IN1_CCU41_ST2 14 736 #define CCU41_IN1_CCU41_ST3 15 737 #define CCU41_IN1_ERU1_PDOUT0 3 738 #define CCU41_IN1_ERU1_PDOUT1 9 739 #define CCU41_IN1_P1_5 2 740 #define CCU41_IN1_P2_4 0 741 #define CCU41_IN1_SCU_ERU1_IOUT1 10 742 #define CCU41_IN1_SCU_GSC41 8 743 #define CCU41_IN2_CCU41_ST0 12 744 #define CCU41_IN2_CCU41_ST1 13 745 #define CCU41_IN2_CCU41_ST2 14 746 #define CCU41_IN2_CCU41_ST3 15 747 #define CCU41_IN2_ERU1_PDOUT0 3 748 #define CCU41_IN2_ERU1_PDOUT2 9 749 #define CCU41_IN2_P2_3 0 750 #define CCU41_IN2_SCU_ERU1_IOUT2 10 751 #define CCU41_IN2_SCU_GSC41 8 752 #define CCU41_IN2_VADC0_G0BFL1 11 753 #define CCU41_IN3_CCU41_ST0 12 754 #define CCU41_IN3_CCU41_ST1 13 755 #define CCU41_IN3_CCU41_ST2 14 756 #define CCU41_IN3_CCU41_ST3 15 757 #define CCU41_IN3_ERU1_PDOUT0 3 758 #define CCU41_IN3_ERU1_PDOUT3 9 759 #define CCU41_IN3_P2_2 0 760 #define CCU41_IN3_SCU_ERU1_IOUT3 10 761 #define CCU41_IN3_SCU_GSC41 8 762 #define CCU41_IN3_VADC0_G0BFL2 11 763 #define CCU41_IN3_VADC0_G1ARBCNT 6 764 #endif 765 766 767 #if (UC_DEVICE == XMC4200) && (UC_PACKAGE == LQFP64) 768 #define CCU40_IN0_CAN0_SR7 7 769 #define CCU40_IN0_CCU40_ST0 12 770 #define CCU40_IN0_CCU40_ST1 13 771 #define CCU40_IN0_CCU40_ST2 14 772 #define CCU40_IN0_CCU40_ST3 15 773 #define CCU40_IN0_ERU1_PDOUT0 9 774 #define CCU40_IN0_ERU1_PDOUT1 3 775 #define CCU40_IN0_P1_3 0 776 #define CCU40_IN0_P2_1 2 777 #define CCU40_IN0_P2_8 1 778 #define CCU40_IN0_POSIF0_OUT0 4 779 #define CCU40_IN0_POSIF0_OUT1 5 780 #define CCU40_IN0_POSIF0_OUT3 6 781 #define CCU40_IN0_SCU_ERU1_IOUT0 10 782 #define CCU40_IN0_SCU_GSC40 8 783 #define CCU40_IN0_U0C0_DX2INS 11 784 #define CCU40_IN1_CCU40_ST0 12 785 #define CCU40_IN1_CCU40_ST1 13 786 #define CCU40_IN1_CCU40_ST2 14 787 #define CCU40_IN1_CCU40_ST3 15 788 #define CCU40_IN1_ERU1_PDOUT0 3 789 #define CCU40_IN1_ERU1_PDOUT1 9 790 #define CCU40_IN1_P1_2 0 791 #define CCU40_IN1_P2_0 2 792 #define CCU40_IN1_P2_8 1 793 #define CCU40_IN1_POSIF0_OUT0 4 794 #define CCU40_IN1_POSIF0_OUT1 5 795 #define CCU40_IN1_POSIF0_OUT2 11 796 #define CCU40_IN1_POSIF0_OUT3 6 797 #define CCU40_IN1_POSIF0_OUT4 7 798 #define CCU40_IN1_SCU_ERU1_IOUT1 10 799 #define CCU40_IN1_SCU_GSC40 8 800 #define CCU40_IN2_CCU40_ST0 12 801 #define CCU40_IN2_CCU40_ST1 13 802 #define CCU40_IN2_CCU40_ST2 14 803 #define CCU40_IN2_CCU40_ST3 15 804 #define CCU40_IN2_ERU1_PDOUT0 3 805 #define CCU40_IN2_ERU1_PDOUT2 9 806 #define CCU40_IN2_P1_1 0 807 #define CCU40_IN2_P2_7 2 808 #define CCU40_IN2_P2_8 1 809 #define CCU40_IN2_POSIF0_OUT0 4 810 #define CCU40_IN2_POSIF0_OUT2 5 811 #define CCU40_IN2_POSIF0_OUT3 6 812 #define CCU40_IN2_POSIF0_OUT4 7 813 #define CCU40_IN2_SCU_ERU1_IOUT2 10 814 #define CCU40_IN2_SCU_GSC40 8 815 #define CCU40_IN2_U0C1_DX2INS 11 816 #define CCU40_IN3_CCU40_ST0 12 817 #define CCU40_IN3_CCU40_ST1 13 818 #define CCU40_IN3_CCU40_ST2 14 819 #define CCU40_IN3_CCU40_ST3 15 820 #define CCU40_IN3_CCU80_IGBTO 7 821 #define CCU40_IN3_ERU1_PDOUT0 3 822 #define CCU40_IN3_ERU1_PDOUT3 9 823 #define CCU40_IN3_P1_0 0 824 #define CCU40_IN3_P2_6 2 825 #define CCU40_IN3_P2_8 1 826 #define CCU40_IN3_POSIF0_OUT3 4 827 #define CCU40_IN3_POSIF0_OUT5 5 828 #define CCU40_IN3_SCU_ERU1_IOUT3 10 829 #define CCU40_IN3_SCU_GSC40 8 830 #define CCU40_IN3_U1C0_DX2INS 11 831 #define CCU40_IN3_VADC0_G0ARBCNT 6 832 #define CCU41_IN0_CAN0_SR7 7 833 #define CCU41_IN0_CCU41_ST0 12 834 #define CCU41_IN0_CCU41_ST1 13 835 #define CCU41_IN0_CCU41_ST2 14 836 #define CCU41_IN0_CCU41_ST3 15 837 #define CCU41_IN0_ERU1_PDOUT0 9 838 #define CCU41_IN0_ERU1_PDOUT1 3 839 #define CCU41_IN0_HRPWM0_QOUT0 5 840 #define CCU41_IN0_HRPWM0_QOUT3 6 841 #define CCU41_IN0_P1_4 2 842 #define CCU41_IN0_P2_5 0 843 #define CCU41_IN0_P2_9 1 844 #define CCU41_IN0_SCU_ERU1_IOUT0 10 845 #define CCU41_IN0_SCU_GSC41 8 846 #define CCU41_IN0_VADC0_G0BFL0 11 847 #define CCU41_IN1_CCU41_ST0 12 848 #define CCU41_IN1_CCU41_ST1 13 849 #define CCU41_IN1_CCU41_ST2 14 850 #define CCU41_IN1_CCU41_ST3 15 851 #define CCU41_IN1_ERU1_PDOUT0 3 852 #define CCU41_IN1_ERU1_PDOUT1 9 853 #define CCU41_IN1_HRPWM0_QOUT0 7 854 #define CCU41_IN1_HRPWM0_QOUT1 5 855 #define CCU41_IN1_HRPWM0_QOUT3 6 856 #define CCU41_IN1_P1_5 2 857 #define CCU41_IN1_P2_4 0 858 #define CCU41_IN1_P2_9 1 859 #define CCU41_IN1_SCU_ERU1_IOUT1 10 860 #define CCU41_IN1_SCU_GSC41 8 861 #define CCU41_IN2_CCU41_ST0 12 862 #define CCU41_IN2_CCU41_ST1 13 863 #define CCU41_IN2_CCU41_ST2 14 864 #define CCU41_IN2_CCU41_ST3 15 865 #define CCU41_IN2_ERU1_PDOUT0 3 866 #define CCU41_IN2_ERU1_PDOUT2 9 867 #define CCU41_IN2_HRPWM0_QOUT0 7 868 #define CCU41_IN2_HRPWM0_QOUT2 5 869 #define CCU41_IN2_HRPWM0_QOUT3 6 870 #define CCU41_IN2_P2_3 0 871 #define CCU41_IN2_P2_9 1 872 #define CCU41_IN2_SCU_ERU1_IOUT2 10 873 #define CCU41_IN2_SCU_GSC41 8 874 #define CCU41_IN2_VADC0_G0BFL1 11 875 #define CCU41_IN3_CCU41_ST0 12 876 #define CCU41_IN3_CCU41_ST1 13 877 #define CCU41_IN3_CCU41_ST2 14 878 #define CCU41_IN3_CCU41_ST3 15 879 #define CCU41_IN3_ERU1_PDOUT0 3 880 #define CCU41_IN3_ERU1_PDOUT3 9 881 #define CCU41_IN3_HRPWM0_QOUT0 7 882 #define CCU41_IN3_HRPWM0_QOUT3 5 883 #define CCU41_IN3_P2_2 0 884 #define CCU41_IN3_P2_9 1 885 #define CCU41_IN3_SCU_ERU1_IOUT3 10 886 #define CCU41_IN3_SCU_GSC41 8 887 #define CCU41_IN3_VADC0_G0BFL2 11 888 #define CCU41_IN3_VADC0_G1ARBCNT 6 889 #endif 890 891 892 #if (UC_DEVICE == XMC4200) && (UC_PACKAGE == VQFN48) 893 #define CCU40_IN0_CAN0_SR7 7 894 #define CCU40_IN0_CCU40_ST0 12 895 #define CCU40_IN0_CCU40_ST1 13 896 #define CCU40_IN0_CCU40_ST2 14 897 #define CCU40_IN0_CCU40_ST3 15 898 #define CCU40_IN0_ERU1_PDOUT0 9 899 #define CCU40_IN0_ERU1_PDOUT1 3 900 #define CCU40_IN0_P1_3 0 901 #define CCU40_IN0_P2_1 2 902 #define CCU40_IN0_POSIF0_OUT0 4 903 #define CCU40_IN0_POSIF0_OUT1 5 904 #define CCU40_IN0_POSIF0_OUT3 6 905 #define CCU40_IN0_SCU_ERU1_IOUT0 10 906 #define CCU40_IN0_SCU_GSC40 8 907 #define CCU40_IN0_U0C0_DX2INS 11 908 #define CCU40_IN1_CCU40_ST0 12 909 #define CCU40_IN1_CCU40_ST1 13 910 #define CCU40_IN1_CCU40_ST2 14 911 #define CCU40_IN1_CCU40_ST3 15 912 #define CCU40_IN1_ERU1_PDOUT0 3 913 #define CCU40_IN1_ERU1_PDOUT1 9 914 #define CCU40_IN1_P1_2 0 915 #define CCU40_IN1_P2_0 2 916 #define CCU40_IN1_POSIF0_OUT0 4 917 #define CCU40_IN1_POSIF0_OUT1 5 918 #define CCU40_IN1_POSIF0_OUT2 11 919 #define CCU40_IN1_POSIF0_OUT3 6 920 #define CCU40_IN1_POSIF0_OUT4 7 921 #define CCU40_IN1_SCU_ERU1_IOUT1 10 922 #define CCU40_IN1_SCU_GSC40 8 923 #define CCU40_IN2_CCU40_ST0 12 924 #define CCU40_IN2_CCU40_ST1 13 925 #define CCU40_IN2_CCU40_ST2 14 926 #define CCU40_IN2_CCU40_ST3 15 927 #define CCU40_IN2_ERU1_PDOUT0 3 928 #define CCU40_IN2_ERU1_PDOUT2 9 929 #define CCU40_IN2_P1_1 0 930 #define CCU40_IN2_POSIF0_OUT0 4 931 #define CCU40_IN2_POSIF0_OUT2 5 932 #define CCU40_IN2_POSIF0_OUT3 6 933 #define CCU40_IN2_POSIF0_OUT4 7 934 #define CCU40_IN2_SCU_ERU1_IOUT2 10 935 #define CCU40_IN2_SCU_GSC40 8 936 #define CCU40_IN2_U0C1_DX2INS 11 937 #define CCU40_IN3_CCU40_ST0 12 938 #define CCU40_IN3_CCU40_ST1 13 939 #define CCU40_IN3_CCU40_ST2 14 940 #define CCU40_IN3_CCU40_ST3 15 941 #define CCU40_IN3_CCU80_IGBTO 7 942 #define CCU40_IN3_ERU1_PDOUT0 3 943 #define CCU40_IN3_ERU1_PDOUT3 9 944 #define CCU40_IN3_P1_0 0 945 #define CCU40_IN3_POSIF0_OUT3 4 946 #define CCU40_IN3_POSIF0_OUT5 5 947 #define CCU40_IN3_SCU_ERU1_IOUT3 10 948 #define CCU40_IN3_SCU_GSC40 8 949 #define CCU40_IN3_U1C0_DX2INS 11 950 #define CCU40_IN3_VADC0_G0ARBCNT 6 951 #define CCU41_IN0_CAN0_SR7 7 952 #define CCU41_IN0_CCU41_ST0 12 953 #define CCU41_IN0_CCU41_ST1 13 954 #define CCU41_IN0_CCU41_ST2 14 955 #define CCU41_IN0_CCU41_ST3 15 956 #define CCU41_IN0_ERU1_PDOUT0 9 957 #define CCU41_IN0_ERU1_PDOUT1 3 958 #define CCU41_IN0_HRPWM0_QOUT0 5 959 #define CCU41_IN0_HRPWM0_QOUT3 6 960 #define CCU41_IN0_P1_4 2 961 #define CCU41_IN0_P2_5 0 962 #define CCU41_IN0_SCU_ERU1_IOUT0 10 963 #define CCU41_IN0_SCU_GSC41 8 964 #define CCU41_IN0_VADC0_G0BFL0 11 965 #define CCU41_IN1_CCU41_ST0 12 966 #define CCU41_IN1_CCU41_ST1 13 967 #define CCU41_IN1_CCU41_ST2 14 968 #define CCU41_IN1_CCU41_ST3 15 969 #define CCU41_IN1_ERU1_PDOUT0 3 970 #define CCU41_IN1_ERU1_PDOUT1 9 971 #define CCU41_IN1_HRPWM0_QOUT0 7 972 #define CCU41_IN1_HRPWM0_QOUT1 5 973 #define CCU41_IN1_HRPWM0_QOUT3 6 974 #define CCU41_IN1_P1_5 2 975 #define CCU41_IN1_P2_4 0 976 #define CCU41_IN1_SCU_ERU1_IOUT1 10 977 #define CCU41_IN1_SCU_GSC41 8 978 #define CCU41_IN2_CCU41_ST0 12 979 #define CCU41_IN2_CCU41_ST1 13 980 #define CCU41_IN2_CCU41_ST2 14 981 #define CCU41_IN2_CCU41_ST3 15 982 #define CCU41_IN2_ERU1_PDOUT0 3 983 #define CCU41_IN2_ERU1_PDOUT2 9 984 #define CCU41_IN2_HRPWM0_QOUT0 7 985 #define CCU41_IN2_HRPWM0_QOUT2 5 986 #define CCU41_IN2_HRPWM0_QOUT3 6 987 #define CCU41_IN2_P2_3 0 988 #define CCU41_IN2_SCU_ERU1_IOUT2 10 989 #define CCU41_IN2_SCU_GSC41 8 990 #define CCU41_IN2_VADC0_G0BFL1 11 991 #define CCU41_IN3_CCU41_ST0 12 992 #define CCU41_IN3_CCU41_ST1 13 993 #define CCU41_IN3_CCU41_ST2 14 994 #define CCU41_IN3_CCU41_ST3 15 995 #define CCU41_IN3_ERU1_PDOUT0 3 996 #define CCU41_IN3_ERU1_PDOUT3 9 997 #define CCU41_IN3_HRPWM0_QOUT0 7 998 #define CCU41_IN3_HRPWM0_QOUT3 5 999 #define CCU41_IN3_P2_2 0 1000 #define CCU41_IN3_SCU_ERU1_IOUT3 10 1001 #define CCU41_IN3_SCU_GSC41 8 1002 #define CCU41_IN3_VADC0_G0BFL2 11 1003 #define CCU41_IN3_VADC0_G1ARBCNT 6 1004 #endif 1005 1006 1007 #if (UC_DEVICE == XMC4300) && (UC_PACKAGE == LQFP100) 1008 #define CCU40_IN0_CAN0_SR7 7 1009 #define CCU40_IN0_CCU40_ST0 12 1010 #define CCU40_IN0_CCU40_ST1 13 1011 #define CCU40_IN0_CCU40_ST2 14 1012 #define CCU40_IN0_CCU40_ST3 15 1013 #define CCU40_IN0_ERU1_PDOUT0 9 1014 #define CCU40_IN0_ERU1_PDOUT1 3 1015 #define CCU40_IN0_P1_3 0 1016 #define CCU40_IN0_P2_1 2 1017 #define CCU40_IN0_P2_8 1 1018 #define CCU40_IN0_SCU_ERU1_IOUT0 10 1019 #define CCU40_IN0_SCU_GSC40 8 1020 #define CCU40_IN0_U0C0_DX2INS 11 1021 #define CCU40_IN1_CCU40_ST0 12 1022 #define CCU40_IN1_CCU40_ST1 13 1023 #define CCU40_IN1_CCU40_ST2 14 1024 #define CCU40_IN1_CCU40_ST3 15 1025 #define CCU40_IN1_ERU1_PDOUT0 3 1026 #define CCU40_IN1_ERU1_PDOUT1 9 1027 #define CCU40_IN1_P1_2 0 1028 #define CCU40_IN1_P2_0 2 1029 #define CCU40_IN1_P2_8 1 1030 #define CCU40_IN1_SCU_ERU1_IOUT1 10 1031 #define CCU40_IN1_SCU_GSC40 8 1032 #define CCU40_IN2_CCU40_ST0 12 1033 #define CCU40_IN2_CCU40_ST1 13 1034 #define CCU40_IN2_CCU40_ST2 14 1035 #define CCU40_IN2_CCU40_ST3 15 1036 #define CCU40_IN2_ERU1_PDOUT0 3 1037 #define CCU40_IN2_ERU1_PDOUT2 9 1038 #define CCU40_IN2_P1_1 0 1039 #define CCU40_IN2_P2_7 2 1040 #define CCU40_IN2_P2_8 1 1041 #define CCU40_IN2_SCU_ERU1_IOUT2 10 1042 #define CCU40_IN2_SCU_GSC40 8 1043 #define CCU40_IN2_U0C1_DX2INS 11 1044 #define CCU40_IN3_CCU40_ST0 12 1045 #define CCU40_IN3_CCU40_ST1 13 1046 #define CCU40_IN3_CCU40_ST2 14 1047 #define CCU40_IN3_CCU40_ST3 15 1048 #define CCU40_IN3_CCU80_IGBTO 7 1049 #define CCU40_IN3_ERU1_PDOUT0 3 1050 #define CCU40_IN3_ERU1_PDOUT3 9 1051 #define CCU40_IN3_P1_0 0 1052 #define CCU40_IN3_P2_6 2 1053 #define CCU40_IN3_P2_8 1 1054 #define CCU40_IN3_SCU_ERU1_IOUT3 10 1055 #define CCU40_IN3_SCU_GSC40 8 1056 #define CCU40_IN3_U1C0_DX2INS 11 1057 #define CCU40_IN3_VADC0_G0ARBCNT 6 1058 #define CCU41_IN0_CAN0_SR7 7 1059 #define CCU41_IN0_CCU41_ST0 12 1060 #define CCU41_IN0_CCU41_ST1 13 1061 #define CCU41_IN0_CCU41_ST2 14 1062 #define CCU41_IN0_CCU41_ST3 15 1063 #define CCU41_IN0_ERU1_PDOUT0 9 1064 #define CCU41_IN0_ERU1_PDOUT1 3 1065 #define CCU41_IN0_P1_4 2 1066 #define CCU41_IN0_P2_5 0 1067 #define CCU41_IN0_P2_9 1 1068 #define CCU41_IN0_SCU_ERU1_IOUT0 10 1069 #define CCU41_IN0_SCU_GSC41 8 1070 #define CCU41_IN0_VADC0_G0BFL0 11 1071 #define CCU41_IN1_CCU41_ST0 12 1072 #define CCU41_IN1_CCU41_ST1 13 1073 #define CCU41_IN1_CCU41_ST2 14 1074 #define CCU41_IN1_CCU41_ST3 15 1075 #define CCU41_IN1_ERU1_PDOUT0 3 1076 #define CCU41_IN1_ERU1_PDOUT1 9 1077 #define CCU41_IN1_P1_5 2 1078 #define CCU41_IN1_P2_4 0 1079 #define CCU41_IN1_P2_9 1 1080 #define CCU41_IN1_SCU_ERU1_IOUT1 10 1081 #define CCU41_IN1_SCU_GSC41 8 1082 #define CCU41_IN2_CCU41_ST0 12 1083 #define CCU41_IN2_CCU41_ST1 13 1084 #define CCU41_IN2_CCU41_ST2 14 1085 #define CCU41_IN2_CCU41_ST3 15 1086 #define CCU41_IN2_ERU1_PDOUT0 3 1087 #define CCU41_IN2_ERU1_PDOUT2 9 1088 #define CCU41_IN2_P1_10 2 1089 #define CCU41_IN2_P2_3 0 1090 #define CCU41_IN2_P2_9 1 1091 #define CCU41_IN2_SCU_ERU1_IOUT2 10 1092 #define CCU41_IN2_SCU_GSC41 8 1093 #define CCU41_IN2_VADC0_G0BFL1 11 1094 #define CCU41_IN3_CCU41_ST0 12 1095 #define CCU41_IN3_CCU41_ST1 13 1096 #define CCU41_IN3_CCU41_ST2 14 1097 #define CCU41_IN3_CCU41_ST3 15 1098 #define CCU41_IN3_ERU1_PDOUT0 3 1099 #define CCU41_IN3_ERU1_PDOUT3 9 1100 #define CCU41_IN3_P1_11 2 1101 #define CCU41_IN3_P2_2 0 1102 #define CCU41_IN3_P2_9 1 1103 #define CCU41_IN3_SCU_ERU1_IOUT3 10 1104 #define CCU41_IN3_SCU_GSC41 8 1105 #define CCU41_IN3_VADC0_G0BFL2 11 1106 #define CCU41_IN3_VADC0_G1ARBCNT 6 1107 #endif 1108 1109 1110 #if (UC_DEVICE == XMC4400) && (UC_PACKAGE == LQFP100) 1111 #define CCU40_IN0_CAN0_SR7 7 1112 #define CCU40_IN0_CCU40_ST0 12 1113 #define CCU40_IN0_CCU40_ST1 13 1114 #define CCU40_IN0_CCU40_ST2 14 1115 #define CCU40_IN0_CCU40_ST3 15 1116 #define CCU40_IN0_ERU1_PDOUT0 9 1117 #define CCU40_IN0_ERU1_PDOUT1 3 1118 #define CCU40_IN0_P1_3 0 1119 #define CCU40_IN0_P2_1 2 1120 #define CCU40_IN0_P2_8 1 1121 #define CCU40_IN0_POSIF0_OUT0 4 1122 #define CCU40_IN0_POSIF0_OUT1 5 1123 #define CCU40_IN0_POSIF0_OUT3 6 1124 #define CCU40_IN0_SCU_ERU1_IOUT0 10 1125 #define CCU40_IN0_SCU_GSC40 8 1126 #define CCU40_IN0_U0C0_DX2INS 11 1127 #define CCU40_IN1_CCU40_ST0 12 1128 #define CCU40_IN1_CCU40_ST1 13 1129 #define CCU40_IN1_CCU40_ST2 14 1130 #define CCU40_IN1_CCU40_ST3 15 1131 #define CCU40_IN1_ERU1_PDOUT0 3 1132 #define CCU40_IN1_ERU1_PDOUT1 9 1133 #define CCU40_IN1_P1_2 0 1134 #define CCU40_IN1_P2_0 2 1135 #define CCU40_IN1_P2_8 1 1136 #define CCU40_IN1_POSIF0_OUT0 4 1137 #define CCU40_IN1_POSIF0_OUT1 5 1138 #define CCU40_IN1_POSIF0_OUT2 11 1139 #define CCU40_IN1_POSIF0_OUT3 6 1140 #define CCU40_IN1_POSIF0_OUT4 7 1141 #define CCU40_IN1_SCU_ERU1_IOUT1 10 1142 #define CCU40_IN1_SCU_GSC40 8 1143 #define CCU40_IN2_CCU40_ST0 12 1144 #define CCU40_IN2_CCU40_ST1 13 1145 #define CCU40_IN2_CCU40_ST2 14 1146 #define CCU40_IN2_CCU40_ST3 15 1147 #define CCU40_IN2_ERU1_PDOUT0 3 1148 #define CCU40_IN2_ERU1_PDOUT2 9 1149 #define CCU40_IN2_P1_1 0 1150 #define CCU40_IN2_P2_7 2 1151 #define CCU40_IN2_P2_8 1 1152 #define CCU40_IN2_POSIF0_OUT0 4 1153 #define CCU40_IN2_POSIF0_OUT2 5 1154 #define CCU40_IN2_POSIF0_OUT3 6 1155 #define CCU40_IN2_POSIF0_OUT4 7 1156 #define CCU40_IN2_SCU_ERU1_IOUT2 10 1157 #define CCU40_IN2_SCU_GSC40 8 1158 #define CCU40_IN2_U0C1_DX2INS 11 1159 #define CCU40_IN3_CCU40_ST0 12 1160 #define CCU40_IN3_CCU40_ST1 13 1161 #define CCU40_IN3_CCU40_ST2 14 1162 #define CCU40_IN3_CCU40_ST3 15 1163 #define CCU40_IN3_CCU80_IGBTO 7 1164 #define CCU40_IN3_ERU1_PDOUT0 3 1165 #define CCU40_IN3_ERU1_PDOUT3 9 1166 #define CCU40_IN3_P1_0 0 1167 #define CCU40_IN3_P2_6 2 1168 #define CCU40_IN3_P2_8 1 1169 #define CCU40_IN3_POSIF0_OUT3 4 1170 #define CCU40_IN3_POSIF0_OUT5 5 1171 #define CCU40_IN3_SCU_ERU1_IOUT3 10 1172 #define CCU40_IN3_SCU_GSC40 8 1173 #define CCU40_IN3_U1C0_DX2INS 11 1174 #define CCU40_IN3_VADC0_G0ARBCNT 6 1175 #define CCU41_IN0_CAN0_SR7 7 1176 #define CCU41_IN0_CCU41_ST0 12 1177 #define CCU41_IN0_CCU41_ST1 13 1178 #define CCU41_IN0_CCU41_ST2 14 1179 #define CCU41_IN0_CCU41_ST3 15 1180 #define CCU41_IN0_ERU1_PDOUT0 9 1181 #define CCU41_IN0_ERU1_PDOUT1 3 1182 #define CCU41_IN0_P1_4 2 1183 #define CCU41_IN0_P2_5 0 1184 #define CCU41_IN0_P2_9 1 1185 #define CCU41_IN0_POSIF1_OUT0 4 1186 #define CCU41_IN0_POSIF1_OUT1 5 1187 #define CCU41_IN0_POSIF1_OUT3 6 1188 #define CCU41_IN0_SCU_ERU1_IOUT0 10 1189 #define CCU41_IN0_SCU_GSC41 8 1190 #define CCU41_IN0_VADC0_G0BFL0 11 1191 #define CCU41_IN1_CCU41_ST0 12 1192 #define CCU41_IN1_CCU41_ST1 13 1193 #define CCU41_IN1_CCU41_ST2 14 1194 #define CCU41_IN1_CCU41_ST3 15 1195 #define CCU41_IN1_ERU1_PDOUT0 3 1196 #define CCU41_IN1_ERU1_PDOUT1 9 1197 #define CCU41_IN1_P1_5 2 1198 #define CCU41_IN1_P2_4 0 1199 #define CCU41_IN1_P2_9 1 1200 #define CCU41_IN1_POSIF1_OUT0 4 1201 #define CCU41_IN1_POSIF1_OUT1 5 1202 #define CCU41_IN1_POSIF1_OUT2 11 1203 #define CCU41_IN1_POSIF1_OUT3 6 1204 #define CCU41_IN1_POSIF1_OUT4 7 1205 #define CCU41_IN1_SCU_ERU1_IOUT1 10 1206 #define CCU41_IN1_SCU_GSC41 8 1207 #define CCU41_IN2_CCU41_ST0 12 1208 #define CCU41_IN2_CCU41_ST1 13 1209 #define CCU41_IN2_CCU41_ST2 14 1210 #define CCU41_IN2_CCU41_ST3 15 1211 #define CCU41_IN2_ERU1_PDOUT0 3 1212 #define CCU41_IN2_ERU1_PDOUT2 9 1213 #define CCU41_IN2_P1_10 2 1214 #define CCU41_IN2_P2_3 0 1215 #define CCU41_IN2_P2_9 1 1216 #define CCU41_IN2_POSIF1_OUT0 4 1217 #define CCU41_IN2_POSIF1_OUT2 5 1218 #define CCU41_IN2_POSIF1_OUT3 6 1219 #define CCU41_IN2_POSIF1_OUT4 7 1220 #define CCU41_IN2_SCU_ERU1_IOUT2 10 1221 #define CCU41_IN2_SCU_GSC41 8 1222 #define CCU41_IN2_VADC0_G0BFL1 11 1223 #define CCU41_IN3_CCU41_ST0 12 1224 #define CCU41_IN3_CCU41_ST1 13 1225 #define CCU41_IN3_CCU41_ST2 14 1226 #define CCU41_IN3_CCU41_ST3 15 1227 #define CCU41_IN3_CCU81_IGBTO 7 1228 #define CCU41_IN3_ERU1_PDOUT0 3 1229 #define CCU41_IN3_ERU1_PDOUT3 9 1230 #define CCU41_IN3_P1_11 2 1231 #define CCU41_IN3_P2_2 0 1232 #define CCU41_IN3_P2_9 1 1233 #define CCU41_IN3_POSIF1_OUT3 4 1234 #define CCU41_IN3_POSIF1_OUT5 5 1235 #define CCU41_IN3_SCU_ERU1_IOUT3 10 1236 #define CCU41_IN3_SCU_GSC41 8 1237 #define CCU41_IN3_VADC0_G0BFL2 11 1238 #define CCU41_IN3_VADC0_G1ARBCNT 6 1239 #define CCU42_IN0_CCU42_ST0 12 1240 #define CCU42_IN0_CCU42_ST1 13 1241 #define CCU42_IN0_CCU42_ST2 14 1242 #define CCU42_IN0_CCU42_ST3 15 1243 #define CCU42_IN0_CCU80_IGBTO 7 1244 #define CCU42_IN0_ERU1_PDOUT0 9 1245 #define CCU42_IN0_ERU1_PDOUT1 3 1246 #define CCU42_IN0_P2_15 1 1247 #define CCU42_IN0_P3_6 0 1248 #define CCU42_IN0_POSIF0_OUT2 4 1249 #define CCU42_IN0_POSIF0_OUT5 5 1250 #define CCU42_IN0_SCU_ERU1_IOUT0 10 1251 #define CCU42_IN0_SCU_GSC42 8 1252 #define CCU42_IN0_U0C0_DX2INS 11 1253 #define CCU42_IN1_CCU42_ST0 12 1254 #define CCU42_IN1_CCU42_ST1 13 1255 #define CCU42_IN1_CCU42_ST2 14 1256 #define CCU42_IN1_CCU42_ST3 15 1257 #define CCU42_IN1_ERU1_PDOUT0 3 1258 #define CCU42_IN1_ERU1_PDOUT1 9 1259 #define CCU42_IN1_HRPWM0_QOUT3 7 1260 #define CCU42_IN1_P2_15 1 1261 #define CCU42_IN1_P3_5 0 1262 #define CCU42_IN1_POSIF0_OUT2 4 1263 #define CCU42_IN1_POSIF0_OUT5 5 1264 #define CCU42_IN1_SCU_ERU1_IOUT1 10 1265 #define CCU42_IN1_SCU_GSC42 8 1266 #define CCU42_IN1_U0C1_DX2INS 11 1267 #define CCU42_IN2_CAN0_SR7 6 1268 #define CCU42_IN2_CCU42_ST0 12 1269 #define CCU42_IN2_CCU42_ST1 13 1270 #define CCU42_IN2_CCU42_ST2 14 1271 #define CCU42_IN2_CCU42_ST3 15 1272 #define CCU42_IN2_ERU1_PDOUT0 3 1273 #define CCU42_IN2_ERU1_PDOUT2 9 1274 #define CCU42_IN2_HRPWM0_QOUT1 7 1275 #define CCU42_IN2_P2_15 1 1276 #define CCU42_IN2_P3_4 0 1277 #define CCU42_IN2_POSIF0_OUT2 4 1278 #define CCU42_IN2_POSIF0_OUT5 5 1279 #define CCU42_IN2_SCU_ERU1_IOUT2 10 1280 #define CCU42_IN2_SCU_GSC42 8 1281 #define CCU42_IN2_U1C0_DX2INS 11 1282 #define CCU42_IN3_CCU42_ST0 12 1283 #define CCU42_IN3_CCU42_ST1 13 1284 #define CCU42_IN3_CCU42_ST2 14 1285 #define CCU42_IN3_CCU42_ST3 15 1286 #define CCU42_IN3_ERU1_PDOUT0 3 1287 #define CCU42_IN3_ERU1_PDOUT3 9 1288 #define CCU42_IN3_HRPWM0_QOUT2 7 1289 #define CCU42_IN3_P2_15 1 1290 #define CCU42_IN3_P3_3 0 1291 #define CCU42_IN3_POSIF0_OUT2 4 1292 #define CCU42_IN3_POSIF0_OUT5 5 1293 #define CCU42_IN3_SCU_ERU1_IOUT3 10 1294 #define CCU42_IN3_SCU_GSC42 8 1295 #define CCU42_IN3_U1C1_DX2INS 11 1296 #define CCU42_IN3_VADC0_G2ARBCNT 6 1297 #define CCU43_IN0_CCU43_ST0 12 1298 #define CCU43_IN0_CCU43_ST1 13 1299 #define CCU43_IN0_CCU43_ST2 14 1300 #define CCU43_IN0_CCU43_ST3 15 1301 #define CCU43_IN0_CCU81_IGBTO 6 1302 #define CCU43_IN0_ERU1_PDOUT0 9 1303 #define CCU43_IN0_ERU1_PDOUT1 3 1304 #define CCU43_IN0_P2_14 1 1305 #define CCU43_IN0_POSIF1_OUT2 4 1306 #define CCU43_IN0_POSIF1_OUT5 5 1307 #define CCU43_IN0_SCU_ERU1_IOUT0 10 1308 #define CCU43_IN0_SCU_GSC43 8 1309 #define CCU43_IN0_U0C0_DX2INS 11 1310 #define CCU43_IN0_VADC0_G0BFL0 7 1311 #define CCU43_IN1_CAN0_SR7 6 1312 #define CCU43_IN1_CCU43_ST0 12 1313 #define CCU43_IN1_CCU43_ST1 13 1314 #define CCU43_IN1_CCU43_ST2 14 1315 #define CCU43_IN1_CCU43_ST3 15 1316 #define CCU43_IN1_ERU1_PDOUT0 3 1317 #define CCU43_IN1_ERU1_PDOUT1 9 1318 #define CCU43_IN1_P2_14 1 1319 #define CCU43_IN1_POSIF1_OUT2 4 1320 #define CCU43_IN1_POSIF1_OUT5 5 1321 #define CCU43_IN1_SCU_ERU1_IOUT1 10 1322 #define CCU43_IN1_SCU_GSC43 8 1323 #define CCU43_IN1_U0C1_DX2INS 11 1324 #define CCU43_IN1_VADC0_G1BFL0 7 1325 #define CCU43_IN2_CCU43_ST0 12 1326 #define CCU43_IN2_CCU43_ST1 13 1327 #define CCU43_IN2_CCU43_ST2 14 1328 #define CCU43_IN2_CCU43_ST3 15 1329 #define CCU43_IN2_ERU1_PDOUT0 3 1330 #define CCU43_IN2_ERU1_PDOUT2 9 1331 #define CCU43_IN2_P2_14 1 1332 #define CCU43_IN2_POSIF1_OUT2 4 1333 #define CCU43_IN2_POSIF1_OUT5 5 1334 #define CCU43_IN2_SCU_ERU1_IOUT2 10 1335 #define CCU43_IN2_SCU_GSC43 8 1336 #define CCU43_IN2_U1C0_DX2INS 11 1337 #define CCU43_IN2_VADC0_G2BFL0 7 1338 #define CCU43_IN3_CCU43_ST0 12 1339 #define CCU43_IN3_CCU43_ST1 13 1340 #define CCU43_IN3_CCU43_ST2 14 1341 #define CCU43_IN3_CCU43_ST3 15 1342 #define CCU43_IN3_ERU1_PDOUT0 3 1343 #define CCU43_IN3_ERU1_PDOUT3 9 1344 #define CCU43_IN3_P2_14 1 1345 #define CCU43_IN3_POSIF1_OUT2 4 1346 #define CCU43_IN3_POSIF1_OUT5 5 1347 #define CCU43_IN3_SCU_ERU1_IOUT3 10 1348 #define CCU43_IN3_SCU_GSC43 8 1349 #define CCU43_IN3_U1C1_DX2INS 11 1350 #define CCU43_IN3_VADC0_G3ARBCNT 6 1351 #define CCU43_IN3_VADC0_G3BFL0 7 1352 #endif 1353 1354 1355 #if (UC_DEVICE == XMC4400) && (UC_PACKAGE == LQFP64) 1356 #define CCU40_IN0_CAN0_SR7 7 1357 #define CCU40_IN0_CCU40_ST0 12 1358 #define CCU40_IN0_CCU40_ST1 13 1359 #define CCU40_IN0_CCU40_ST2 14 1360 #define CCU40_IN0_CCU40_ST3 15 1361 #define CCU40_IN0_ERU1_PDOUT0 9 1362 #define CCU40_IN0_ERU1_PDOUT1 3 1363 #define CCU40_IN0_P1_3 0 1364 #define CCU40_IN0_P2_1 2 1365 #define CCU40_IN0_P2_8 1 1366 #define CCU40_IN0_POSIF0_OUT0 4 1367 #define CCU40_IN0_POSIF0_OUT1 5 1368 #define CCU40_IN0_POSIF0_OUT3 6 1369 #define CCU40_IN0_SCU_ERU1_IOUT0 10 1370 #define CCU40_IN0_SCU_GSC40 8 1371 #define CCU40_IN0_U0C0_DX2INS 11 1372 #define CCU40_IN1_CCU40_ST0 12 1373 #define CCU40_IN1_CCU40_ST1 13 1374 #define CCU40_IN1_CCU40_ST2 14 1375 #define CCU40_IN1_CCU40_ST3 15 1376 #define CCU40_IN1_ERU1_PDOUT0 3 1377 #define CCU40_IN1_ERU1_PDOUT1 9 1378 #define CCU40_IN1_P1_2 0 1379 #define CCU40_IN1_P2_0 2 1380 #define CCU40_IN1_P2_8 1 1381 #define CCU40_IN1_POSIF0_OUT0 4 1382 #define CCU40_IN1_POSIF0_OUT1 5 1383 #define CCU40_IN1_POSIF0_OUT2 11 1384 #define CCU40_IN1_POSIF0_OUT3 6 1385 #define CCU40_IN1_POSIF0_OUT4 7 1386 #define CCU40_IN1_SCU_ERU1_IOUT1 10 1387 #define CCU40_IN1_SCU_GSC40 8 1388 #define CCU40_IN2_CCU40_ST0 12 1389 #define CCU40_IN2_CCU40_ST1 13 1390 #define CCU40_IN2_CCU40_ST2 14 1391 #define CCU40_IN2_CCU40_ST3 15 1392 #define CCU40_IN2_ERU1_PDOUT0 3 1393 #define CCU40_IN2_ERU1_PDOUT2 9 1394 #define CCU40_IN2_P1_1 0 1395 #define CCU40_IN2_P2_7 2 1396 #define CCU40_IN2_P2_8 1 1397 #define CCU40_IN2_POSIF0_OUT0 4 1398 #define CCU40_IN2_POSIF0_OUT2 5 1399 #define CCU40_IN2_POSIF0_OUT3 6 1400 #define CCU40_IN2_POSIF0_OUT4 7 1401 #define CCU40_IN2_SCU_ERU1_IOUT2 10 1402 #define CCU40_IN2_SCU_GSC40 8 1403 #define CCU40_IN2_U0C1_DX2INS 11 1404 #define CCU40_IN3_CCU40_ST0 12 1405 #define CCU40_IN3_CCU40_ST1 13 1406 #define CCU40_IN3_CCU40_ST2 14 1407 #define CCU40_IN3_CCU40_ST3 15 1408 #define CCU40_IN3_CCU80_IGBTO 7 1409 #define CCU40_IN3_ERU1_PDOUT0 3 1410 #define CCU40_IN3_ERU1_PDOUT3 9 1411 #define CCU40_IN3_P1_0 0 1412 #define CCU40_IN3_P2_6 2 1413 #define CCU40_IN3_P2_8 1 1414 #define CCU40_IN3_POSIF0_OUT3 4 1415 #define CCU40_IN3_POSIF0_OUT5 5 1416 #define CCU40_IN3_SCU_ERU1_IOUT3 10 1417 #define CCU40_IN3_SCU_GSC40 8 1418 #define CCU40_IN3_U1C0_DX2INS 11 1419 #define CCU40_IN3_VADC0_G0ARBCNT 6 1420 #define CCU41_IN0_CAN0_SR7 7 1421 #define CCU41_IN0_CCU41_ST0 12 1422 #define CCU41_IN0_CCU41_ST1 13 1423 #define CCU41_IN0_CCU41_ST2 14 1424 #define CCU41_IN0_CCU41_ST3 15 1425 #define CCU41_IN0_ERU1_PDOUT0 9 1426 #define CCU41_IN0_ERU1_PDOUT1 3 1427 #define CCU41_IN0_P1_4 2 1428 #define CCU41_IN0_P2_5 0 1429 #define CCU41_IN0_P2_9 1 1430 #define CCU41_IN0_POSIF1_OUT0 4 1431 #define CCU41_IN0_POSIF1_OUT1 5 1432 #define CCU41_IN0_POSIF1_OUT3 6 1433 #define CCU41_IN0_SCU_ERU1_IOUT0 10 1434 #define CCU41_IN0_SCU_GSC41 8 1435 #define CCU41_IN0_VADC0_G0BFL0 11 1436 #define CCU41_IN1_CCU41_ST0 12 1437 #define CCU41_IN1_CCU41_ST1 13 1438 #define CCU41_IN1_CCU41_ST2 14 1439 #define CCU41_IN1_CCU41_ST3 15 1440 #define CCU41_IN1_ERU1_PDOUT0 3 1441 #define CCU41_IN1_ERU1_PDOUT1 9 1442 #define CCU41_IN1_P1_5 2 1443 #define CCU41_IN1_P2_4 0 1444 #define CCU41_IN1_P2_9 1 1445 #define CCU41_IN1_POSIF1_OUT0 4 1446 #define CCU41_IN1_POSIF1_OUT1 5 1447 #define CCU41_IN1_POSIF1_OUT2 11 1448 #define CCU41_IN1_POSIF1_OUT3 6 1449 #define CCU41_IN1_POSIF1_OUT4 7 1450 #define CCU41_IN1_SCU_ERU1_IOUT1 10 1451 #define CCU41_IN1_SCU_GSC41 8 1452 #define CCU41_IN2_CCU41_ST0 12 1453 #define CCU41_IN2_CCU41_ST1 13 1454 #define CCU41_IN2_CCU41_ST2 14 1455 #define CCU41_IN2_CCU41_ST3 15 1456 #define CCU41_IN2_ERU1_PDOUT0 3 1457 #define CCU41_IN2_ERU1_PDOUT2 9 1458 #define CCU41_IN2_P2_3 0 1459 #define CCU41_IN2_P2_9 1 1460 #define CCU41_IN2_POSIF1_OUT0 4 1461 #define CCU41_IN2_POSIF1_OUT2 5 1462 #define CCU41_IN2_POSIF1_OUT3 6 1463 #define CCU41_IN2_POSIF1_OUT4 7 1464 #define CCU41_IN2_SCU_ERU1_IOUT2 10 1465 #define CCU41_IN2_SCU_GSC41 8 1466 #define CCU41_IN2_VADC0_G0BFL1 11 1467 #define CCU41_IN3_CCU41_ST0 12 1468 #define CCU41_IN3_CCU41_ST1 13 1469 #define CCU41_IN3_CCU41_ST2 14 1470 #define CCU41_IN3_CCU41_ST3 15 1471 #define CCU41_IN3_CCU81_IGBTO 7 1472 #define CCU41_IN3_ERU1_PDOUT0 3 1473 #define CCU41_IN3_ERU1_PDOUT3 9 1474 #define CCU41_IN3_P2_2 0 1475 #define CCU41_IN3_P2_9 1 1476 #define CCU41_IN3_POSIF1_OUT3 4 1477 #define CCU41_IN3_POSIF1_OUT5 5 1478 #define CCU41_IN3_SCU_ERU1_IOUT3 10 1479 #define CCU41_IN3_SCU_GSC41 8 1480 #define CCU41_IN3_VADC0_G0BFL2 11 1481 #define CCU41_IN3_VADC0_G1ARBCNT 6 1482 #define CCU42_IN0_CCU42_ST0 12 1483 #define CCU42_IN0_CCU42_ST1 13 1484 #define CCU42_IN0_CCU42_ST2 14 1485 #define CCU42_IN0_CCU42_ST3 15 1486 #define CCU42_IN0_CCU80_IGBTO 7 1487 #define CCU42_IN0_ERU1_PDOUT0 9 1488 #define CCU42_IN0_ERU1_PDOUT1 3 1489 #define CCU42_IN0_POSIF0_OUT2 4 1490 #define CCU42_IN0_POSIF0_OUT5 5 1491 #define CCU42_IN0_SCU_ERU1_IOUT0 10 1492 #define CCU42_IN0_SCU_GSC42 8 1493 #define CCU42_IN0_U0C0_DX2INS 11 1494 #define CCU42_IN1_CCU42_ST0 12 1495 #define CCU42_IN1_CCU42_ST1 13 1496 #define CCU42_IN1_CCU42_ST2 14 1497 #define CCU42_IN1_CCU42_ST3 15 1498 #define CCU42_IN1_ERU1_PDOUT0 3 1499 #define CCU42_IN1_ERU1_PDOUT1 9 1500 #define CCU42_IN1_HRPWM0_QOUT3 7 1501 #define CCU42_IN1_POSIF0_OUT2 4 1502 #define CCU42_IN1_POSIF0_OUT5 5 1503 #define CCU42_IN1_SCU_ERU1_IOUT1 10 1504 #define CCU42_IN1_SCU_GSC42 8 1505 #define CCU42_IN1_U0C1_DX2INS 11 1506 #define CCU42_IN2_CAN0_SR7 6 1507 #define CCU42_IN2_CCU42_ST0 12 1508 #define CCU42_IN2_CCU42_ST1 13 1509 #define CCU42_IN2_CCU42_ST2 14 1510 #define CCU42_IN2_CCU42_ST3 15 1511 #define CCU42_IN2_ERU1_PDOUT0 3 1512 #define CCU42_IN2_ERU1_PDOUT2 9 1513 #define CCU42_IN2_HRPWM0_QOUT1 7 1514 #define CCU42_IN2_POSIF0_OUT2 4 1515 #define CCU42_IN2_POSIF0_OUT5 5 1516 #define CCU42_IN2_SCU_ERU1_IOUT2 10 1517 #define CCU42_IN2_SCU_GSC42 8 1518 #define CCU42_IN2_U1C0_DX2INS 11 1519 #define CCU42_IN3_CCU42_ST0 12 1520 #define CCU42_IN3_CCU42_ST1 13 1521 #define CCU42_IN3_CCU42_ST2 14 1522 #define CCU42_IN3_CCU42_ST3 15 1523 #define CCU42_IN3_ERU1_PDOUT0 3 1524 #define CCU42_IN3_ERU1_PDOUT3 9 1525 #define CCU42_IN3_HRPWM0_QOUT2 7 1526 #define CCU42_IN3_POSIF0_OUT2 4 1527 #define CCU42_IN3_POSIF0_OUT5 5 1528 #define CCU42_IN3_SCU_ERU1_IOUT3 10 1529 #define CCU42_IN3_SCU_GSC42 8 1530 #define CCU42_IN3_U1C1_DX2INS 11 1531 #define CCU42_IN3_VADC0_G2ARBCNT 6 1532 #define CCU43_IN0_CCU43_ST0 12 1533 #define CCU43_IN0_CCU43_ST1 13 1534 #define CCU43_IN0_CCU43_ST2 14 1535 #define CCU43_IN0_CCU43_ST3 15 1536 #define CCU43_IN0_CCU81_IGBTO 6 1537 #define CCU43_IN0_ERU1_PDOUT0 9 1538 #define CCU43_IN0_ERU1_PDOUT1 3 1539 #define CCU43_IN0_POSIF1_OUT2 4 1540 #define CCU43_IN0_POSIF1_OUT5 5 1541 #define CCU43_IN0_SCU_ERU1_IOUT0 10 1542 #define CCU43_IN0_SCU_GSC43 8 1543 #define CCU43_IN0_U0C0_DX2INS 11 1544 #define CCU43_IN0_VADC0_G0BFL0 7 1545 #define CCU43_IN1_CAN0_SR7 6 1546 #define CCU43_IN1_CCU43_ST0 12 1547 #define CCU43_IN1_CCU43_ST1 13 1548 #define CCU43_IN1_CCU43_ST2 14 1549 #define CCU43_IN1_CCU43_ST3 15 1550 #define CCU43_IN1_ERU1_PDOUT0 3 1551 #define CCU43_IN1_ERU1_PDOUT1 9 1552 #define CCU43_IN1_POSIF1_OUT2 4 1553 #define CCU43_IN1_POSIF1_OUT5 5 1554 #define CCU43_IN1_SCU_ERU1_IOUT1 10 1555 #define CCU43_IN1_SCU_GSC43 8 1556 #define CCU43_IN1_U0C1_DX2INS 11 1557 #define CCU43_IN1_VADC0_G1BFL0 7 1558 #define CCU43_IN2_CCU43_ST0 12 1559 #define CCU43_IN2_CCU43_ST1 13 1560 #define CCU43_IN2_CCU43_ST2 14 1561 #define CCU43_IN2_CCU43_ST3 15 1562 #define CCU43_IN2_ERU1_PDOUT0 3 1563 #define CCU43_IN2_ERU1_PDOUT2 9 1564 #define CCU43_IN2_POSIF1_OUT2 4 1565 #define CCU43_IN2_POSIF1_OUT5 5 1566 #define CCU43_IN2_SCU_ERU1_IOUT2 10 1567 #define CCU43_IN2_SCU_GSC43 8 1568 #define CCU43_IN2_U1C0_DX2INS 11 1569 #define CCU43_IN2_VADC0_G2BFL0 7 1570 #define CCU43_IN3_CCU43_ST0 12 1571 #define CCU43_IN3_CCU43_ST1 13 1572 #define CCU43_IN3_CCU43_ST2 14 1573 #define CCU43_IN3_CCU43_ST3 15 1574 #define CCU43_IN3_ERU1_PDOUT0 3 1575 #define CCU43_IN3_ERU1_PDOUT3 9 1576 #define CCU43_IN3_POSIF1_OUT2 4 1577 #define CCU43_IN3_POSIF1_OUT5 5 1578 #define CCU43_IN3_SCU_ERU1_IOUT3 10 1579 #define CCU43_IN3_SCU_GSC43 8 1580 #define CCU43_IN3_U1C1_DX2INS 11 1581 #define CCU43_IN3_VADC0_G3ARBCNT 6 1582 #define CCU43_IN3_VADC0_G3BFL0 7 1583 #endif 1584 1585 1586 #if (UC_DEVICE == XMC4402) && (UC_PACKAGE == LQFP100) 1587 #define CCU40_IN0_CAN0_SR7 7 1588 #define CCU40_IN0_CCU40_ST0 12 1589 #define CCU40_IN0_CCU40_ST1 13 1590 #define CCU40_IN0_CCU40_ST2 14 1591 #define CCU40_IN0_CCU40_ST3 15 1592 #define CCU40_IN0_ERU1_PDOUT0 9 1593 #define CCU40_IN0_ERU1_PDOUT1 3 1594 #define CCU40_IN0_P1_3 0 1595 #define CCU40_IN0_P2_1 2 1596 #define CCU40_IN0_P2_8 1 1597 #define CCU40_IN0_POSIF0_OUT0 4 1598 #define CCU40_IN0_POSIF0_OUT1 5 1599 #define CCU40_IN0_POSIF0_OUT3 6 1600 #define CCU40_IN0_SCU_ERU1_IOUT0 10 1601 #define CCU40_IN0_SCU_GSC40 8 1602 #define CCU40_IN0_U0C0_DX2INS 11 1603 #define CCU40_IN1_CCU40_ST0 12 1604 #define CCU40_IN1_CCU40_ST1 13 1605 #define CCU40_IN1_CCU40_ST2 14 1606 #define CCU40_IN1_CCU40_ST3 15 1607 #define CCU40_IN1_ERU1_PDOUT0 3 1608 #define CCU40_IN1_ERU1_PDOUT1 9 1609 #define CCU40_IN1_P1_2 0 1610 #define CCU40_IN1_P2_0 2 1611 #define CCU40_IN1_P2_8 1 1612 #define CCU40_IN1_POSIF0_OUT0 4 1613 #define CCU40_IN1_POSIF0_OUT1 5 1614 #define CCU40_IN1_POSIF0_OUT2 11 1615 #define CCU40_IN1_POSIF0_OUT3 6 1616 #define CCU40_IN1_POSIF0_OUT4 7 1617 #define CCU40_IN1_SCU_ERU1_IOUT1 10 1618 #define CCU40_IN1_SCU_GSC40 8 1619 #define CCU40_IN2_CCU40_ST0 12 1620 #define CCU40_IN2_CCU40_ST1 13 1621 #define CCU40_IN2_CCU40_ST2 14 1622 #define CCU40_IN2_CCU40_ST3 15 1623 #define CCU40_IN2_ERU1_PDOUT0 3 1624 #define CCU40_IN2_ERU1_PDOUT2 9 1625 #define CCU40_IN2_P1_1 0 1626 #define CCU40_IN2_P2_7 2 1627 #define CCU40_IN2_P2_8 1 1628 #define CCU40_IN2_POSIF0_OUT0 4 1629 #define CCU40_IN2_POSIF0_OUT2 5 1630 #define CCU40_IN2_POSIF0_OUT3 6 1631 #define CCU40_IN2_POSIF0_OUT4 7 1632 #define CCU40_IN2_SCU_ERU1_IOUT2 10 1633 #define CCU40_IN2_SCU_GSC40 8 1634 #define CCU40_IN2_U0C1_DX2INS 11 1635 #define CCU40_IN3_CCU40_ST0 12 1636 #define CCU40_IN3_CCU40_ST1 13 1637 #define CCU40_IN3_CCU40_ST2 14 1638 #define CCU40_IN3_CCU40_ST3 15 1639 #define CCU40_IN3_CCU80_IGBTO 7 1640 #define CCU40_IN3_ERU1_PDOUT0 3 1641 #define CCU40_IN3_ERU1_PDOUT3 9 1642 #define CCU40_IN3_P1_0 0 1643 #define CCU40_IN3_P2_6 2 1644 #define CCU40_IN3_P2_8 1 1645 #define CCU40_IN3_POSIF0_OUT3 4 1646 #define CCU40_IN3_POSIF0_OUT5 5 1647 #define CCU40_IN3_SCU_ERU1_IOUT3 10 1648 #define CCU40_IN3_SCU_GSC40 8 1649 #define CCU40_IN3_U1C0_DX2INS 11 1650 #define CCU40_IN3_VADC0_G0ARBCNT 6 1651 #define CCU41_IN0_CAN0_SR7 7 1652 #define CCU41_IN0_CCU41_ST0 12 1653 #define CCU41_IN0_CCU41_ST1 13 1654 #define CCU41_IN0_CCU41_ST2 14 1655 #define CCU41_IN0_CCU41_ST3 15 1656 #define CCU41_IN0_ERU1_PDOUT0 9 1657 #define CCU41_IN0_ERU1_PDOUT1 3 1658 #define CCU41_IN0_P1_4 2 1659 #define CCU41_IN0_P2_5 0 1660 #define CCU41_IN0_P2_9 1 1661 #define CCU41_IN0_POSIF1_OUT0 4 1662 #define CCU41_IN0_POSIF1_OUT1 5 1663 #define CCU41_IN0_POSIF1_OUT3 6 1664 #define CCU41_IN0_SCU_ERU1_IOUT0 10 1665 #define CCU41_IN0_SCU_GSC41 8 1666 #define CCU41_IN0_VADC0_G0BFL0 11 1667 #define CCU41_IN1_CCU41_ST0 12 1668 #define CCU41_IN1_CCU41_ST1 13 1669 #define CCU41_IN1_CCU41_ST2 14 1670 #define CCU41_IN1_CCU41_ST3 15 1671 #define CCU41_IN1_ERU1_PDOUT0 3 1672 #define CCU41_IN1_ERU1_PDOUT1 9 1673 #define CCU41_IN1_P1_5 2 1674 #define CCU41_IN1_P2_4 0 1675 #define CCU41_IN1_P2_9 1 1676 #define CCU41_IN1_POSIF1_OUT0 4 1677 #define CCU41_IN1_POSIF1_OUT1 5 1678 #define CCU41_IN1_POSIF1_OUT2 11 1679 #define CCU41_IN1_POSIF1_OUT3 6 1680 #define CCU41_IN1_POSIF1_OUT4 7 1681 #define CCU41_IN1_SCU_ERU1_IOUT1 10 1682 #define CCU41_IN1_SCU_GSC41 8 1683 #define CCU41_IN2_CCU41_ST0 12 1684 #define CCU41_IN2_CCU41_ST1 13 1685 #define CCU41_IN2_CCU41_ST2 14 1686 #define CCU41_IN2_CCU41_ST3 15 1687 #define CCU41_IN2_ERU1_PDOUT0 3 1688 #define CCU41_IN2_ERU1_PDOUT2 9 1689 #define CCU41_IN2_P1_10 2 1690 #define CCU41_IN2_P2_3 0 1691 #define CCU41_IN2_P2_9 1 1692 #define CCU41_IN2_POSIF1_OUT0 4 1693 #define CCU41_IN2_POSIF1_OUT2 5 1694 #define CCU41_IN2_POSIF1_OUT3 6 1695 #define CCU41_IN2_POSIF1_OUT4 7 1696 #define CCU41_IN2_SCU_ERU1_IOUT2 10 1697 #define CCU41_IN2_SCU_GSC41 8 1698 #define CCU41_IN2_VADC0_G0BFL1 11 1699 #define CCU41_IN3_CCU41_ST0 12 1700 #define CCU41_IN3_CCU41_ST1 13 1701 #define CCU41_IN3_CCU41_ST2 14 1702 #define CCU41_IN3_CCU41_ST3 15 1703 #define CCU41_IN3_CCU81_IGBTO 7 1704 #define CCU41_IN3_ERU1_PDOUT0 3 1705 #define CCU41_IN3_ERU1_PDOUT3 9 1706 #define CCU41_IN3_P1_11 2 1707 #define CCU41_IN3_P2_2 0 1708 #define CCU41_IN3_P2_9 1 1709 #define CCU41_IN3_POSIF1_OUT3 4 1710 #define CCU41_IN3_POSIF1_OUT5 5 1711 #define CCU41_IN3_SCU_ERU1_IOUT3 10 1712 #define CCU41_IN3_SCU_GSC41 8 1713 #define CCU41_IN3_VADC0_G0BFL2 11 1714 #define CCU41_IN3_VADC0_G1ARBCNT 6 1715 #define CCU42_IN0_CCU42_ST0 12 1716 #define CCU42_IN0_CCU42_ST1 13 1717 #define CCU42_IN0_CCU42_ST2 14 1718 #define CCU42_IN0_CCU42_ST3 15 1719 #define CCU42_IN0_CCU80_IGBTO 7 1720 #define CCU42_IN0_ERU1_PDOUT0 9 1721 #define CCU42_IN0_ERU1_PDOUT1 3 1722 #define CCU42_IN0_P2_15 1 1723 #define CCU42_IN0_P3_6 0 1724 #define CCU42_IN0_POSIF0_OUT2 4 1725 #define CCU42_IN0_POSIF0_OUT5 5 1726 #define CCU42_IN0_SCU_ERU1_IOUT0 10 1727 #define CCU42_IN0_SCU_GSC42 8 1728 #define CCU42_IN0_U0C0_DX2INS 11 1729 #define CCU42_IN1_CCU42_ST0 12 1730 #define CCU42_IN1_CCU42_ST1 13 1731 #define CCU42_IN1_CCU42_ST2 14 1732 #define CCU42_IN1_CCU42_ST3 15 1733 #define CCU42_IN1_ERU1_PDOUT0 3 1734 #define CCU42_IN1_ERU1_PDOUT1 9 1735 #define CCU42_IN1_HRPWM0_QOUT3 7 1736 #define CCU42_IN1_P2_15 1 1737 #define CCU42_IN1_P3_5 0 1738 #define CCU42_IN1_POSIF0_OUT2 4 1739 #define CCU42_IN1_POSIF0_OUT5 5 1740 #define CCU42_IN1_SCU_ERU1_IOUT1 10 1741 #define CCU42_IN1_SCU_GSC42 8 1742 #define CCU42_IN1_U0C1_DX2INS 11 1743 #define CCU42_IN2_CAN0_SR7 6 1744 #define CCU42_IN2_CCU42_ST0 12 1745 #define CCU42_IN2_CCU42_ST1 13 1746 #define CCU42_IN2_CCU42_ST2 14 1747 #define CCU42_IN2_CCU42_ST3 15 1748 #define CCU42_IN2_ERU1_PDOUT0 3 1749 #define CCU42_IN2_ERU1_PDOUT2 9 1750 #define CCU42_IN2_HRPWM0_QOUT1 7 1751 #define CCU42_IN2_P2_15 1 1752 #define CCU42_IN2_P3_4 0 1753 #define CCU42_IN2_POSIF0_OUT2 4 1754 #define CCU42_IN2_POSIF0_OUT5 5 1755 #define CCU42_IN2_SCU_ERU1_IOUT2 10 1756 #define CCU42_IN2_SCU_GSC42 8 1757 #define CCU42_IN2_U1C0_DX2INS 11 1758 #define CCU42_IN3_CCU42_ST0 12 1759 #define CCU42_IN3_CCU42_ST1 13 1760 #define CCU42_IN3_CCU42_ST2 14 1761 #define CCU42_IN3_CCU42_ST3 15 1762 #define CCU42_IN3_ERU1_PDOUT0 3 1763 #define CCU42_IN3_ERU1_PDOUT3 9 1764 #define CCU42_IN3_HRPWM0_QOUT2 7 1765 #define CCU42_IN3_P2_15 1 1766 #define CCU42_IN3_P3_3 0 1767 #define CCU42_IN3_POSIF0_OUT2 4 1768 #define CCU42_IN3_POSIF0_OUT5 5 1769 #define CCU42_IN3_SCU_ERU1_IOUT3 10 1770 #define CCU42_IN3_SCU_GSC42 8 1771 #define CCU42_IN3_U1C1_DX2INS 11 1772 #define CCU42_IN3_VADC0_G2ARBCNT 6 1773 #define CCU43_IN0_CCU43_ST0 12 1774 #define CCU43_IN0_CCU43_ST1 13 1775 #define CCU43_IN0_CCU43_ST2 14 1776 #define CCU43_IN0_CCU43_ST3 15 1777 #define CCU43_IN0_CCU81_IGBTO 6 1778 #define CCU43_IN0_ERU1_PDOUT0 9 1779 #define CCU43_IN0_ERU1_PDOUT1 3 1780 #define CCU43_IN0_P2_14 1 1781 #define CCU43_IN0_POSIF1_OUT2 4 1782 #define CCU43_IN0_POSIF1_OUT5 5 1783 #define CCU43_IN0_SCU_ERU1_IOUT0 10 1784 #define CCU43_IN0_SCU_GSC43 8 1785 #define CCU43_IN0_U0C0_DX2INS 11 1786 #define CCU43_IN0_VADC0_G0BFL0 7 1787 #define CCU43_IN1_CAN0_SR7 6 1788 #define CCU43_IN1_CCU43_ST0 12 1789 #define CCU43_IN1_CCU43_ST1 13 1790 #define CCU43_IN1_CCU43_ST2 14 1791 #define CCU43_IN1_CCU43_ST3 15 1792 #define CCU43_IN1_ERU1_PDOUT0 3 1793 #define CCU43_IN1_ERU1_PDOUT1 9 1794 #define CCU43_IN1_P2_14 1 1795 #define CCU43_IN1_POSIF1_OUT2 4 1796 #define CCU43_IN1_POSIF1_OUT5 5 1797 #define CCU43_IN1_SCU_ERU1_IOUT1 10 1798 #define CCU43_IN1_SCU_GSC43 8 1799 #define CCU43_IN1_U0C1_DX2INS 11 1800 #define CCU43_IN1_VADC0_G1BFL0 7 1801 #define CCU43_IN2_CCU43_ST0 12 1802 #define CCU43_IN2_CCU43_ST1 13 1803 #define CCU43_IN2_CCU43_ST2 14 1804 #define CCU43_IN2_CCU43_ST3 15 1805 #define CCU43_IN2_ERU1_PDOUT0 3 1806 #define CCU43_IN2_ERU1_PDOUT2 9 1807 #define CCU43_IN2_P2_14 1 1808 #define CCU43_IN2_POSIF1_OUT2 4 1809 #define CCU43_IN2_POSIF1_OUT5 5 1810 #define CCU43_IN2_SCU_ERU1_IOUT2 10 1811 #define CCU43_IN2_SCU_GSC43 8 1812 #define CCU43_IN2_U1C0_DX2INS 11 1813 #define CCU43_IN2_VADC0_G2BFL0 7 1814 #define CCU43_IN3_CCU43_ST0 12 1815 #define CCU43_IN3_CCU43_ST1 13 1816 #define CCU43_IN3_CCU43_ST2 14 1817 #define CCU43_IN3_CCU43_ST3 15 1818 #define CCU43_IN3_ERU1_PDOUT0 3 1819 #define CCU43_IN3_ERU1_PDOUT3 9 1820 #define CCU43_IN3_P2_14 1 1821 #define CCU43_IN3_POSIF1_OUT2 4 1822 #define CCU43_IN3_POSIF1_OUT5 5 1823 #define CCU43_IN3_SCU_ERU1_IOUT3 10 1824 #define CCU43_IN3_SCU_GSC43 8 1825 #define CCU43_IN3_U1C1_DX2INS 11 1826 #define CCU43_IN3_VADC0_G3ARBCNT 6 1827 #define CCU43_IN3_VADC0_G3BFL0 7 1828 #endif 1829 1830 1831 #if (UC_DEVICE == XMC4402) && (UC_PACKAGE == LQFP64) 1832 #define CCU40_IN0_CAN0_SR7 7 1833 #define CCU40_IN0_CCU40_ST0 12 1834 #define CCU40_IN0_CCU40_ST1 13 1835 #define CCU40_IN0_CCU40_ST2 14 1836 #define CCU40_IN0_CCU40_ST3 15 1837 #define CCU40_IN0_ERU1_PDOUT0 9 1838 #define CCU40_IN0_ERU1_PDOUT1 3 1839 #define CCU40_IN0_P1_3 0 1840 #define CCU40_IN0_P2_1 2 1841 #define CCU40_IN0_P2_8 1 1842 #define CCU40_IN0_POSIF0_OUT0 4 1843 #define CCU40_IN0_POSIF0_OUT1 5 1844 #define CCU40_IN0_POSIF0_OUT3 6 1845 #define CCU40_IN0_SCU_ERU1_IOUT0 10 1846 #define CCU40_IN0_SCU_GSC40 8 1847 #define CCU40_IN0_U0C0_DX2INS 11 1848 #define CCU40_IN1_CCU40_ST0 12 1849 #define CCU40_IN1_CCU40_ST1 13 1850 #define CCU40_IN1_CCU40_ST2 14 1851 #define CCU40_IN1_CCU40_ST3 15 1852 #define CCU40_IN1_ERU1_PDOUT0 3 1853 #define CCU40_IN1_ERU1_PDOUT1 9 1854 #define CCU40_IN1_P1_2 0 1855 #define CCU40_IN1_P2_0 2 1856 #define CCU40_IN1_P2_8 1 1857 #define CCU40_IN1_POSIF0_OUT0 4 1858 #define CCU40_IN1_POSIF0_OUT1 5 1859 #define CCU40_IN1_POSIF0_OUT2 11 1860 #define CCU40_IN1_POSIF0_OUT3 6 1861 #define CCU40_IN1_POSIF0_OUT4 7 1862 #define CCU40_IN1_SCU_ERU1_IOUT1 10 1863 #define CCU40_IN1_SCU_GSC40 8 1864 #define CCU40_IN2_CCU40_ST0 12 1865 #define CCU40_IN2_CCU40_ST1 13 1866 #define CCU40_IN2_CCU40_ST2 14 1867 #define CCU40_IN2_CCU40_ST3 15 1868 #define CCU40_IN2_ERU1_PDOUT0 3 1869 #define CCU40_IN2_ERU1_PDOUT2 9 1870 #define CCU40_IN2_P1_1 0 1871 #define CCU40_IN2_P2_7 2 1872 #define CCU40_IN2_P2_8 1 1873 #define CCU40_IN2_POSIF0_OUT0 4 1874 #define CCU40_IN2_POSIF0_OUT2 5 1875 #define CCU40_IN2_POSIF0_OUT3 6 1876 #define CCU40_IN2_POSIF0_OUT4 7 1877 #define CCU40_IN2_SCU_ERU1_IOUT2 10 1878 #define CCU40_IN2_SCU_GSC40 8 1879 #define CCU40_IN2_U0C1_DX2INS 11 1880 #define CCU40_IN3_CCU40_ST0 12 1881 #define CCU40_IN3_CCU40_ST1 13 1882 #define CCU40_IN3_CCU40_ST2 14 1883 #define CCU40_IN3_CCU40_ST3 15 1884 #define CCU40_IN3_CCU80_IGBTO 7 1885 #define CCU40_IN3_ERU1_PDOUT0 3 1886 #define CCU40_IN3_ERU1_PDOUT3 9 1887 #define CCU40_IN3_P1_0 0 1888 #define CCU40_IN3_P2_6 2 1889 #define CCU40_IN3_P2_8 1 1890 #define CCU40_IN3_POSIF0_OUT3 4 1891 #define CCU40_IN3_POSIF0_OUT5 5 1892 #define CCU40_IN3_SCU_ERU1_IOUT3 10 1893 #define CCU40_IN3_SCU_GSC40 8 1894 #define CCU40_IN3_U1C0_DX2INS 11 1895 #define CCU40_IN3_VADC0_G0ARBCNT 6 1896 #define CCU41_IN0_CAN0_SR7 7 1897 #define CCU41_IN0_CCU41_ST0 12 1898 #define CCU41_IN0_CCU41_ST1 13 1899 #define CCU41_IN0_CCU41_ST2 14 1900 #define CCU41_IN0_CCU41_ST3 15 1901 #define CCU41_IN0_ERU1_PDOUT0 9 1902 #define CCU41_IN0_ERU1_PDOUT1 3 1903 #define CCU41_IN0_P1_4 2 1904 #define CCU41_IN0_P2_5 0 1905 #define CCU41_IN0_P2_9 1 1906 #define CCU41_IN0_POSIF1_OUT0 4 1907 #define CCU41_IN0_POSIF1_OUT1 5 1908 #define CCU41_IN0_POSIF1_OUT3 6 1909 #define CCU41_IN0_SCU_ERU1_IOUT0 10 1910 #define CCU41_IN0_SCU_GSC41 8 1911 #define CCU41_IN0_VADC0_G0BFL0 11 1912 #define CCU41_IN1_CCU41_ST0 12 1913 #define CCU41_IN1_CCU41_ST1 13 1914 #define CCU41_IN1_CCU41_ST2 14 1915 #define CCU41_IN1_CCU41_ST3 15 1916 #define CCU41_IN1_ERU1_PDOUT0 3 1917 #define CCU41_IN1_ERU1_PDOUT1 9 1918 #define CCU41_IN1_P1_5 2 1919 #define CCU41_IN1_P2_4 0 1920 #define CCU41_IN1_P2_9 1 1921 #define CCU41_IN1_POSIF1_OUT0 4 1922 #define CCU41_IN1_POSIF1_OUT1 5 1923 #define CCU41_IN1_POSIF1_OUT2 11 1924 #define CCU41_IN1_POSIF1_OUT3 6 1925 #define CCU41_IN1_POSIF1_OUT4 7 1926 #define CCU41_IN1_SCU_ERU1_IOUT1 10 1927 #define CCU41_IN1_SCU_GSC41 8 1928 #define CCU41_IN2_CCU41_ST0 12 1929 #define CCU41_IN2_CCU41_ST1 13 1930 #define CCU41_IN2_CCU41_ST2 14 1931 #define CCU41_IN2_CCU41_ST3 15 1932 #define CCU41_IN2_ERU1_PDOUT0 3 1933 #define CCU41_IN2_ERU1_PDOUT2 9 1934 #define CCU41_IN2_P2_3 0 1935 #define CCU41_IN2_P2_9 1 1936 #define CCU41_IN2_POSIF1_OUT0 4 1937 #define CCU41_IN2_POSIF1_OUT2 5 1938 #define CCU41_IN2_POSIF1_OUT3 6 1939 #define CCU41_IN2_POSIF1_OUT4 7 1940 #define CCU41_IN2_SCU_ERU1_IOUT2 10 1941 #define CCU41_IN2_SCU_GSC41 8 1942 #define CCU41_IN2_VADC0_G0BFL1 11 1943 #define CCU41_IN3_CCU41_ST0 12 1944 #define CCU41_IN3_CCU41_ST1 13 1945 #define CCU41_IN3_CCU41_ST2 14 1946 #define CCU41_IN3_CCU41_ST3 15 1947 #define CCU41_IN3_CCU81_IGBTO 7 1948 #define CCU41_IN3_ERU1_PDOUT0 3 1949 #define CCU41_IN3_ERU1_PDOUT3 9 1950 #define CCU41_IN3_P2_2 0 1951 #define CCU41_IN3_P2_9 1 1952 #define CCU41_IN3_POSIF1_OUT3 4 1953 #define CCU41_IN3_POSIF1_OUT5 5 1954 #define CCU41_IN3_SCU_ERU1_IOUT3 10 1955 #define CCU41_IN3_SCU_GSC41 8 1956 #define CCU41_IN3_VADC0_G0BFL2 11 1957 #define CCU41_IN3_VADC0_G1ARBCNT 6 1958 #define CCU42_IN0_CCU42_ST0 12 1959 #define CCU42_IN0_CCU42_ST1 13 1960 #define CCU42_IN0_CCU42_ST2 14 1961 #define CCU42_IN0_CCU42_ST3 15 1962 #define CCU42_IN0_CCU80_IGBTO 7 1963 #define CCU42_IN0_ERU1_PDOUT0 9 1964 #define CCU42_IN0_ERU1_PDOUT1 3 1965 #define CCU42_IN0_POSIF0_OUT2 4 1966 #define CCU42_IN0_POSIF0_OUT5 5 1967 #define CCU42_IN0_SCU_ERU1_IOUT0 10 1968 #define CCU42_IN0_SCU_GSC42 8 1969 #define CCU42_IN0_U0C0_DX2INS 11 1970 #define CCU42_IN1_CCU42_ST0 12 1971 #define CCU42_IN1_CCU42_ST1 13 1972 #define CCU42_IN1_CCU42_ST2 14 1973 #define CCU42_IN1_CCU42_ST3 15 1974 #define CCU42_IN1_ERU1_PDOUT0 3 1975 #define CCU42_IN1_ERU1_PDOUT1 9 1976 #define CCU42_IN1_HRPWM0_QOUT3 7 1977 #define CCU42_IN1_POSIF0_OUT2 4 1978 #define CCU42_IN1_POSIF0_OUT5 5 1979 #define CCU42_IN1_SCU_ERU1_IOUT1 10 1980 #define CCU42_IN1_SCU_GSC42 8 1981 #define CCU42_IN1_U0C1_DX2INS 11 1982 #define CCU42_IN2_CAN0_SR7 6 1983 #define CCU42_IN2_CCU42_ST0 12 1984 #define CCU42_IN2_CCU42_ST1 13 1985 #define CCU42_IN2_CCU42_ST2 14 1986 #define CCU42_IN2_CCU42_ST3 15 1987 #define CCU42_IN2_ERU1_PDOUT0 3 1988 #define CCU42_IN2_ERU1_PDOUT2 9 1989 #define CCU42_IN2_HRPWM0_QOUT1 7 1990 #define CCU42_IN2_POSIF0_OUT2 4 1991 #define CCU42_IN2_POSIF0_OUT5 5 1992 #define CCU42_IN2_SCU_ERU1_IOUT2 10 1993 #define CCU42_IN2_SCU_GSC42 8 1994 #define CCU42_IN2_U1C0_DX2INS 11 1995 #define CCU42_IN3_CCU42_ST0 12 1996 #define CCU42_IN3_CCU42_ST1 13 1997 #define CCU42_IN3_CCU42_ST2 14 1998 #define CCU42_IN3_CCU42_ST3 15 1999 #define CCU42_IN3_ERU1_PDOUT0 3 2000 #define CCU42_IN3_ERU1_PDOUT3 9 2001 #define CCU42_IN3_HRPWM0_QOUT2 7 2002 #define CCU42_IN3_POSIF0_OUT2 4 2003 #define CCU42_IN3_POSIF0_OUT5 5 2004 #define CCU42_IN3_SCU_ERU1_IOUT3 10 2005 #define CCU42_IN3_SCU_GSC42 8 2006 #define CCU42_IN3_U1C1_DX2INS 11 2007 #define CCU42_IN3_VADC0_G2ARBCNT 6 2008 #define CCU43_IN0_CCU43_ST0 12 2009 #define CCU43_IN0_CCU43_ST1 13 2010 #define CCU43_IN0_CCU43_ST2 14 2011 #define CCU43_IN0_CCU43_ST3 15 2012 #define CCU43_IN0_CCU81_IGBTO 6 2013 #define CCU43_IN0_ERU1_PDOUT0 9 2014 #define CCU43_IN0_ERU1_PDOUT1 3 2015 #define CCU43_IN0_POSIF1_OUT2 4 2016 #define CCU43_IN0_POSIF1_OUT5 5 2017 #define CCU43_IN0_SCU_ERU1_IOUT0 10 2018 #define CCU43_IN0_SCU_GSC43 8 2019 #define CCU43_IN0_U0C0_DX2INS 11 2020 #define CCU43_IN0_VADC0_G0BFL0 7 2021 #define CCU43_IN1_CAN0_SR7 6 2022 #define CCU43_IN1_CCU43_ST0 12 2023 #define CCU43_IN1_CCU43_ST1 13 2024 #define CCU43_IN1_CCU43_ST2 14 2025 #define CCU43_IN1_CCU43_ST3 15 2026 #define CCU43_IN1_ERU1_PDOUT0 3 2027 #define CCU43_IN1_ERU1_PDOUT1 9 2028 #define CCU43_IN1_POSIF1_OUT2 4 2029 #define CCU43_IN1_POSIF1_OUT5 5 2030 #define CCU43_IN1_SCU_ERU1_IOUT1 10 2031 #define CCU43_IN1_SCU_GSC43 8 2032 #define CCU43_IN1_U0C1_DX2INS 11 2033 #define CCU43_IN1_VADC0_G1BFL0 7 2034 #define CCU43_IN2_CCU43_ST0 12 2035 #define CCU43_IN2_CCU43_ST1 13 2036 #define CCU43_IN2_CCU43_ST2 14 2037 #define CCU43_IN2_CCU43_ST3 15 2038 #define CCU43_IN2_ERU1_PDOUT0 3 2039 #define CCU43_IN2_ERU1_PDOUT2 9 2040 #define CCU43_IN2_POSIF1_OUT2 4 2041 #define CCU43_IN2_POSIF1_OUT5 5 2042 #define CCU43_IN2_SCU_ERU1_IOUT2 10 2043 #define CCU43_IN2_SCU_GSC43 8 2044 #define CCU43_IN2_U1C0_DX2INS 11 2045 #define CCU43_IN2_VADC0_G2BFL0 7 2046 #define CCU43_IN3_CCU43_ST0 12 2047 #define CCU43_IN3_CCU43_ST1 13 2048 #define CCU43_IN3_CCU43_ST2 14 2049 #define CCU43_IN3_CCU43_ST3 15 2050 #define CCU43_IN3_ERU1_PDOUT0 3 2051 #define CCU43_IN3_ERU1_PDOUT3 9 2052 #define CCU43_IN3_POSIF1_OUT2 4 2053 #define CCU43_IN3_POSIF1_OUT5 5 2054 #define CCU43_IN3_SCU_ERU1_IOUT3 10 2055 #define CCU43_IN3_SCU_GSC43 8 2056 #define CCU43_IN3_U1C1_DX2INS 11 2057 #define CCU43_IN3_VADC0_G3ARBCNT 6 2058 #define CCU43_IN3_VADC0_G3BFL0 7 2059 #endif 2060 2061 2062 #if (UC_DEVICE == XMC4500) && (UC_PACKAGE == BGA144) 2063 #define CCU40_IN0_CAN0_SR7 7 2064 #define CCU40_IN0_CCU40_ST0 12 2065 #define CCU40_IN0_CCU40_ST1 13 2066 #define CCU40_IN0_CCU40_ST2 14 2067 #define CCU40_IN0_CCU40_ST3 15 2068 #define CCU40_IN0_ERU1_PDOUT0 9 2069 #define CCU40_IN0_ERU1_PDOUT1 3 2070 #define CCU40_IN0_P1_3 0 2071 #define CCU40_IN0_P2_1 2 2072 #define CCU40_IN0_P2_8 1 2073 #define CCU40_IN0_POSIF0_OUT0 4 2074 #define CCU40_IN0_POSIF0_OUT1 5 2075 #define CCU40_IN0_POSIF0_OUT3 6 2076 #define CCU40_IN0_SCU_ERU1_IOUT0 10 2077 #define CCU40_IN0_SCU_GSC40 8 2078 #define CCU40_IN0_U0C0_DX2INS 11 2079 #define CCU40_IN1_CCU40_ST0 12 2080 #define CCU40_IN1_CCU40_ST1 13 2081 #define CCU40_IN1_CCU40_ST2 14 2082 #define CCU40_IN1_CCU40_ST3 15 2083 #define CCU40_IN1_ERU1_PDOUT0 3 2084 #define CCU40_IN1_ERU1_PDOUT1 9 2085 #define CCU40_IN1_P1_2 0 2086 #define CCU40_IN1_P2_0 2 2087 #define CCU40_IN1_P2_8 1 2088 #define CCU40_IN1_POSIF0_OUT0 4 2089 #define CCU40_IN1_POSIF0_OUT1 5 2090 #define CCU40_IN1_POSIF0_OUT2 11 2091 #define CCU40_IN1_POSIF0_OUT3 6 2092 #define CCU40_IN1_POSIF0_OUT4 7 2093 #define CCU40_IN1_SCU_ERU1_IOUT1 10 2094 #define CCU40_IN1_SCU_GSC40 8 2095 #define CCU40_IN2_CCU40_ST0 12 2096 #define CCU40_IN2_CCU40_ST1 13 2097 #define CCU40_IN2_CCU40_ST2 14 2098 #define CCU40_IN2_CCU40_ST3 15 2099 #define CCU40_IN2_ERU1_PDOUT0 3 2100 #define CCU40_IN2_ERU1_PDOUT2 9 2101 #define CCU40_IN2_P1_1 0 2102 #define CCU40_IN2_P2_7 2 2103 #define CCU40_IN2_P2_8 1 2104 #define CCU40_IN2_POSIF0_OUT0 4 2105 #define CCU40_IN2_POSIF0_OUT2 5 2106 #define CCU40_IN2_POSIF0_OUT3 6 2107 #define CCU40_IN2_POSIF0_OUT4 7 2108 #define CCU40_IN2_SCU_ERU1_IOUT2 10 2109 #define CCU40_IN2_SCU_GSC40 8 2110 #define CCU40_IN2_U0C1_DX2INS 11 2111 #define CCU40_IN3_CCU40_ST0 12 2112 #define CCU40_IN3_CCU40_ST1 13 2113 #define CCU40_IN3_CCU40_ST2 14 2114 #define CCU40_IN3_CCU40_ST3 15 2115 #define CCU40_IN3_CCU80_IGBTO 7 2116 #define CCU40_IN3_ERU1_PDOUT0 3 2117 #define CCU40_IN3_ERU1_PDOUT3 9 2118 #define CCU40_IN3_P1_0 0 2119 #define CCU40_IN3_P2_6 2 2120 #define CCU40_IN3_P2_8 1 2121 #define CCU40_IN3_POSIF0_OUT3 4 2122 #define CCU40_IN3_POSIF0_OUT5 5 2123 #define CCU40_IN3_SCU_ERU1_IOUT3 10 2124 #define CCU40_IN3_SCU_GSC40 8 2125 #define CCU40_IN3_U1C0_DX2INS 11 2126 #define CCU40_IN3_VADC0_G0ARBCNT 6 2127 #define CCU41_IN0_CAN0_SR7 7 2128 #define CCU41_IN0_CCU41_ST0 12 2129 #define CCU41_IN0_CCU41_ST1 13 2130 #define CCU41_IN0_CCU41_ST2 14 2131 #define CCU41_IN0_CCU41_ST3 15 2132 #define CCU41_IN0_ERU1_PDOUT0 9 2133 #define CCU41_IN0_ERU1_PDOUT1 3 2134 #define CCU41_IN0_P1_4 2 2135 #define CCU41_IN0_P2_5 0 2136 #define CCU41_IN0_P2_9 1 2137 #define CCU41_IN0_POSIF1_OUT0 4 2138 #define CCU41_IN0_POSIF1_OUT1 5 2139 #define CCU41_IN0_POSIF1_OUT3 6 2140 #define CCU41_IN0_SCU_ERU1_IOUT0 10 2141 #define CCU41_IN0_SCU_GSC41 8 2142 #define CCU41_IN0_VADC0_G0BFL0 11 2143 #define CCU41_IN1_CCU41_ST0 12 2144 #define CCU41_IN1_CCU41_ST1 13 2145 #define CCU41_IN1_CCU41_ST2 14 2146 #define CCU41_IN1_CCU41_ST3 15 2147 #define CCU41_IN1_ERU1_PDOUT0 3 2148 #define CCU41_IN1_ERU1_PDOUT1 9 2149 #define CCU41_IN1_P1_5 2 2150 #define CCU41_IN1_P2_4 0 2151 #define CCU41_IN1_P2_9 1 2152 #define CCU41_IN1_POSIF1_OUT0 4 2153 #define CCU41_IN1_POSIF1_OUT1 5 2154 #define CCU41_IN1_POSIF1_OUT2 11 2155 #define CCU41_IN1_POSIF1_OUT3 6 2156 #define CCU41_IN1_POSIF1_OUT4 7 2157 #define CCU41_IN1_SCU_ERU1_IOUT1 10 2158 #define CCU41_IN1_SCU_GSC41 8 2159 #define CCU41_IN2_CCU41_ST0 12 2160 #define CCU41_IN2_CCU41_ST1 13 2161 #define CCU41_IN2_CCU41_ST2 14 2162 #define CCU41_IN2_CCU41_ST3 15 2163 #define CCU41_IN2_ERU1_PDOUT0 3 2164 #define CCU41_IN2_ERU1_PDOUT2 9 2165 #define CCU41_IN2_P1_10 2 2166 #define CCU41_IN2_P2_3 0 2167 #define CCU41_IN2_P2_9 1 2168 #define CCU41_IN2_POSIF1_OUT0 4 2169 #define CCU41_IN2_POSIF1_OUT2 5 2170 #define CCU41_IN2_POSIF1_OUT3 6 2171 #define CCU41_IN2_POSIF1_OUT4 7 2172 #define CCU41_IN2_SCU_ERU1_IOUT2 10 2173 #define CCU41_IN2_SCU_GSC41 8 2174 #define CCU41_IN2_VADC0_G0BFL1 11 2175 #define CCU41_IN3_CCU41_ST0 12 2176 #define CCU41_IN3_CCU41_ST1 13 2177 #define CCU41_IN3_CCU41_ST2 14 2178 #define CCU41_IN3_CCU41_ST3 15 2179 #define CCU41_IN3_CCU81_IGBTO 7 2180 #define CCU41_IN3_ERU1_PDOUT0 3 2181 #define CCU41_IN3_ERU1_PDOUT3 9 2182 #define CCU41_IN3_P1_11 2 2183 #define CCU41_IN3_P2_2 0 2184 #define CCU41_IN3_P2_9 1 2185 #define CCU41_IN3_POSIF1_OUT3 4 2186 #define CCU41_IN3_POSIF1_OUT5 5 2187 #define CCU41_IN3_SCU_ERU1_IOUT3 10 2188 #define CCU41_IN3_SCU_GSC41 8 2189 #define CCU41_IN3_VADC0_G0BFL2 11 2190 #define CCU41_IN3_VADC0_G1ARBCNT 6 2191 #define CCU42_IN0_CCU42_ST0 12 2192 #define CCU42_IN0_CCU42_ST1 13 2193 #define CCU42_IN0_CCU42_ST2 14 2194 #define CCU42_IN0_CCU42_ST3 15 2195 #define CCU42_IN0_CCU80_IGBTO 7 2196 #define CCU42_IN0_ERU1_PDOUT0 9 2197 #define CCU42_IN0_ERU1_PDOUT1 3 2198 #define CCU42_IN0_P2_15 1 2199 #define CCU42_IN0_P3_15 2 2200 #define CCU42_IN0_P3_6 0 2201 #define CCU42_IN0_POSIF0_OUT2 4 2202 #define CCU42_IN0_POSIF0_OUT5 5 2203 #define CCU42_IN0_SCU_ERU1_IOUT0 10 2204 #define CCU42_IN0_SCU_GSC42 8 2205 #define CCU42_IN0_U0C0_DX2INS 11 2206 #define CCU42_IN1_CCU42_ST0 12 2207 #define CCU42_IN1_CCU42_ST1 13 2208 #define CCU42_IN1_CCU42_ST2 14 2209 #define CCU42_IN1_CCU42_ST3 15 2210 #define CCU42_IN1_ERU1_PDOUT0 3 2211 #define CCU42_IN1_ERU1_PDOUT1 9 2212 #define CCU42_IN1_P2_15 1 2213 #define CCU42_IN1_P3_14 2 2214 #define CCU42_IN1_P3_5 0 2215 #define CCU42_IN1_POSIF0_OUT2 4 2216 #define CCU42_IN1_POSIF0_OUT5 5 2217 #define CCU42_IN1_SCU_ERU1_IOUT1 10 2218 #define CCU42_IN1_SCU_GSC42 8 2219 #define CCU42_IN1_U0C1_DX2INS 11 2220 #define CCU42_IN2_CAN0_SR7 6 2221 #define CCU42_IN2_CCU42_ST0 12 2222 #define CCU42_IN2_CCU42_ST1 13 2223 #define CCU42_IN2_CCU42_ST2 14 2224 #define CCU42_IN2_CCU42_ST3 15 2225 #define CCU42_IN2_ERU1_PDOUT0 3 2226 #define CCU42_IN2_ERU1_PDOUT2 9 2227 #define CCU42_IN2_P0_15 2 2228 #define CCU42_IN2_P2_15 1 2229 #define CCU42_IN2_P3_4 0 2230 #define CCU42_IN2_POSIF0_OUT2 4 2231 #define CCU42_IN2_POSIF0_OUT5 5 2232 #define CCU42_IN2_SCU_ERU1_IOUT2 10 2233 #define CCU42_IN2_SCU_GSC42 8 2234 #define CCU42_IN2_U1C0_DX2INS 11 2235 #define CCU42_IN3_CCU42_ST0 12 2236 #define CCU42_IN3_CCU42_ST1 13 2237 #define CCU42_IN3_CCU42_ST2 14 2238 #define CCU42_IN3_CCU42_ST3 15 2239 #define CCU42_IN3_ERU1_PDOUT0 3 2240 #define CCU42_IN3_ERU1_PDOUT3 9 2241 #define CCU42_IN3_P0_14 2 2242 #define CCU42_IN3_P2_15 1 2243 #define CCU42_IN3_P3_3 0 2244 #define CCU42_IN3_POSIF0_OUT2 4 2245 #define CCU42_IN3_POSIF0_OUT5 5 2246 #define CCU42_IN3_SCU_ERU1_IOUT3 10 2247 #define CCU42_IN3_SCU_GSC42 8 2248 #define CCU42_IN3_U1C1_DX2INS 11 2249 #define CCU42_IN3_VADC0_G2ARBCNT 6 2250 #define CCU43_IN0_CCU43_ST0 12 2251 #define CCU43_IN0_CCU43_ST1 13 2252 #define CCU43_IN0_CCU43_ST2 14 2253 #define CCU43_IN0_CCU43_ST3 15 2254 #define CCU43_IN0_CCU81_IGBTO 6 2255 #define CCU43_IN0_ERU1_PDOUT0 9 2256 #define CCU43_IN0_ERU1_PDOUT1 3 2257 #define CCU43_IN0_P2_14 1 2258 #define CCU43_IN0_P4_6 0 2259 #define CCU43_IN0_P4_7 2 2260 #define CCU43_IN0_POSIF1_OUT2 4 2261 #define CCU43_IN0_POSIF1_OUT5 5 2262 #define CCU43_IN0_SCU_ERU1_IOUT0 10 2263 #define CCU43_IN0_SCU_GSC43 8 2264 #define CCU43_IN0_U0C0_DX2INS 11 2265 #define CCU43_IN0_VADC0_G0BFL0 7 2266 #define CCU43_IN1_CAN0_SR7 6 2267 #define CCU43_IN1_CCU43_ST0 12 2268 #define CCU43_IN1_CCU43_ST1 13 2269 #define CCU43_IN1_CCU43_ST2 14 2270 #define CCU43_IN1_CCU43_ST3 15 2271 #define CCU43_IN1_ERU1_PDOUT0 3 2272 #define CCU43_IN1_ERU1_PDOUT1 9 2273 #define CCU43_IN1_P2_14 1 2274 #define CCU43_IN1_P4_2 2 2275 #define CCU43_IN1_P4_5 0 2276 #define CCU43_IN1_POSIF1_OUT2 4 2277 #define CCU43_IN1_POSIF1_OUT5 5 2278 #define CCU43_IN1_SCU_ERU1_IOUT1 10 2279 #define CCU43_IN1_SCU_GSC43 8 2280 #define CCU43_IN1_U0C1_DX2INS 11 2281 #define CCU43_IN1_VADC0_G1BFL0 7 2282 #define CCU43_IN2_CCU43_ST0 12 2283 #define CCU43_IN2_CCU43_ST1 13 2284 #define CCU43_IN2_CCU43_ST2 14 2285 #define CCU43_IN2_CCU43_ST3 15 2286 #define CCU43_IN2_ERU1_PDOUT0 3 2287 #define CCU43_IN2_ERU1_PDOUT2 9 2288 #define CCU43_IN2_P2_13 2 2289 #define CCU43_IN2_P2_14 1 2290 #define CCU43_IN2_P4_4 0 2291 #define CCU43_IN2_POSIF1_OUT2 4 2292 #define CCU43_IN2_POSIF1_OUT5 5 2293 #define CCU43_IN2_SCU_ERU1_IOUT2 10 2294 #define CCU43_IN2_SCU_GSC43 8 2295 #define CCU43_IN2_U1C0_DX2INS 11 2296 #define CCU43_IN2_VADC0_G2BFL0 7 2297 #define CCU43_IN3_CCU43_ST0 12 2298 #define CCU43_IN3_CCU43_ST1 13 2299 #define CCU43_IN3_CCU43_ST2 14 2300 #define CCU43_IN3_CCU43_ST3 15 2301 #define CCU43_IN3_ERU1_PDOUT0 3 2302 #define CCU43_IN3_ERU1_PDOUT3 9 2303 #define CCU43_IN3_P2_12 2 2304 #define CCU43_IN3_P2_14 1 2305 #define CCU43_IN3_P4_3 0 2306 #define CCU43_IN3_POSIF1_OUT2 4 2307 #define CCU43_IN3_POSIF1_OUT5 5 2308 #define CCU43_IN3_SCU_ERU1_IOUT3 10 2309 #define CCU43_IN3_SCU_GSC43 8 2310 #define CCU43_IN3_U1C1_DX2INS 11 2311 #define CCU43_IN3_VADC0_G3ARBCNT 6 2312 #define CCU43_IN3_VADC0_G3BFL0 7 2313 #endif 2314 2315 2316 #if (UC_DEVICE == XMC4500) && (UC_PACKAGE == LQFP100) 2317 #define CCU40_IN0_CAN0_SR7 7 2318 #define CCU40_IN0_CCU40_ST0 12 2319 #define CCU40_IN0_CCU40_ST1 13 2320 #define CCU40_IN0_CCU40_ST2 14 2321 #define CCU40_IN0_CCU40_ST3 15 2322 #define CCU40_IN0_ERU1_PDOUT0 9 2323 #define CCU40_IN0_ERU1_PDOUT1 3 2324 #define CCU40_IN0_P1_3 0 2325 #define CCU40_IN0_P2_1 2 2326 #define CCU40_IN0_P2_8 1 2327 #define CCU40_IN0_POSIF0_OUT0 4 2328 #define CCU40_IN0_POSIF0_OUT1 5 2329 #define CCU40_IN0_POSIF0_OUT3 6 2330 #define CCU40_IN0_SCU_ERU1_IOUT0 10 2331 #define CCU40_IN0_SCU_GSC40 8 2332 #define CCU40_IN0_U0C0_DX2INS 11 2333 #define CCU40_IN1_CCU40_ST0 12 2334 #define CCU40_IN1_CCU40_ST1 13 2335 #define CCU40_IN1_CCU40_ST2 14 2336 #define CCU40_IN1_CCU40_ST3 15 2337 #define CCU40_IN1_ERU1_PDOUT0 3 2338 #define CCU40_IN1_ERU1_PDOUT1 9 2339 #define CCU40_IN1_P1_2 0 2340 #define CCU40_IN1_P2_0 2 2341 #define CCU40_IN1_P2_8 1 2342 #define CCU40_IN1_POSIF0_OUT0 4 2343 #define CCU40_IN1_POSIF0_OUT1 5 2344 #define CCU40_IN1_POSIF0_OUT2 11 2345 #define CCU40_IN1_POSIF0_OUT3 6 2346 #define CCU40_IN1_POSIF0_OUT4 7 2347 #define CCU40_IN1_SCU_ERU1_IOUT1 10 2348 #define CCU40_IN1_SCU_GSC40 8 2349 #define CCU40_IN2_CCU40_ST0 12 2350 #define CCU40_IN2_CCU40_ST1 13 2351 #define CCU40_IN2_CCU40_ST2 14 2352 #define CCU40_IN2_CCU40_ST3 15 2353 #define CCU40_IN2_ERU1_PDOUT0 3 2354 #define CCU40_IN2_ERU1_PDOUT2 9 2355 #define CCU40_IN2_P1_1 0 2356 #define CCU40_IN2_P2_7 2 2357 #define CCU40_IN2_P2_8 1 2358 #define CCU40_IN2_POSIF0_OUT0 4 2359 #define CCU40_IN2_POSIF0_OUT2 5 2360 #define CCU40_IN2_POSIF0_OUT3 6 2361 #define CCU40_IN2_POSIF0_OUT4 7 2362 #define CCU40_IN2_SCU_ERU1_IOUT2 10 2363 #define CCU40_IN2_SCU_GSC40 8 2364 #define CCU40_IN2_U0C1_DX2INS 11 2365 #define CCU40_IN3_CCU40_ST0 12 2366 #define CCU40_IN3_CCU40_ST1 13 2367 #define CCU40_IN3_CCU40_ST2 14 2368 #define CCU40_IN3_CCU40_ST3 15 2369 #define CCU40_IN3_CCU80_IGBTO 7 2370 #define CCU40_IN3_ERU1_PDOUT0 3 2371 #define CCU40_IN3_ERU1_PDOUT3 9 2372 #define CCU40_IN3_P1_0 0 2373 #define CCU40_IN3_P2_6 2 2374 #define CCU40_IN3_P2_8 1 2375 #define CCU40_IN3_POSIF0_OUT3 4 2376 #define CCU40_IN3_POSIF0_OUT5 5 2377 #define CCU40_IN3_SCU_ERU1_IOUT3 10 2378 #define CCU40_IN3_SCU_GSC40 8 2379 #define CCU40_IN3_U1C0_DX2INS 11 2380 #define CCU40_IN3_VADC0_G0ARBCNT 6 2381 #define CCU41_IN0_CAN0_SR7 7 2382 #define CCU41_IN0_CCU41_ST0 12 2383 #define CCU41_IN0_CCU41_ST1 13 2384 #define CCU41_IN0_CCU41_ST2 14 2385 #define CCU41_IN0_CCU41_ST3 15 2386 #define CCU41_IN0_ERU1_PDOUT0 9 2387 #define CCU41_IN0_ERU1_PDOUT1 3 2388 #define CCU41_IN0_P1_4 2 2389 #define CCU41_IN0_P2_5 0 2390 #define CCU41_IN0_P2_9 1 2391 #define CCU41_IN0_POSIF1_OUT0 4 2392 #define CCU41_IN0_POSIF1_OUT1 5 2393 #define CCU41_IN0_POSIF1_OUT3 6 2394 #define CCU41_IN0_SCU_ERU1_IOUT0 10 2395 #define CCU41_IN0_SCU_GSC41 8 2396 #define CCU41_IN0_VADC0_G0BFL0 11 2397 #define CCU41_IN1_CCU41_ST0 12 2398 #define CCU41_IN1_CCU41_ST1 13 2399 #define CCU41_IN1_CCU41_ST2 14 2400 #define CCU41_IN1_CCU41_ST3 15 2401 #define CCU41_IN1_ERU1_PDOUT0 3 2402 #define CCU41_IN1_ERU1_PDOUT1 9 2403 #define CCU41_IN1_P1_5 2 2404 #define CCU41_IN1_P2_4 0 2405 #define CCU41_IN1_P2_9 1 2406 #define CCU41_IN1_POSIF1_OUT0 4 2407 #define CCU41_IN1_POSIF1_OUT1 5 2408 #define CCU41_IN1_POSIF1_OUT2 11 2409 #define CCU41_IN1_POSIF1_OUT3 6 2410 #define CCU41_IN1_POSIF1_OUT4 7 2411 #define CCU41_IN1_SCU_ERU1_IOUT1 10 2412 #define CCU41_IN1_SCU_GSC41 8 2413 #define CCU41_IN2_CCU41_ST0 12 2414 #define CCU41_IN2_CCU41_ST1 13 2415 #define CCU41_IN2_CCU41_ST2 14 2416 #define CCU41_IN2_CCU41_ST3 15 2417 #define CCU41_IN2_ERU1_PDOUT0 3 2418 #define CCU41_IN2_ERU1_PDOUT2 9 2419 #define CCU41_IN2_P1_10 2 2420 #define CCU41_IN2_P2_3 0 2421 #define CCU41_IN2_P2_9 1 2422 #define CCU41_IN2_POSIF1_OUT0 4 2423 #define CCU41_IN2_POSIF1_OUT2 5 2424 #define CCU41_IN2_POSIF1_OUT3 6 2425 #define CCU41_IN2_POSIF1_OUT4 7 2426 #define CCU41_IN2_SCU_ERU1_IOUT2 10 2427 #define CCU41_IN2_SCU_GSC41 8 2428 #define CCU41_IN2_VADC0_G0BFL1 11 2429 #define CCU41_IN3_CCU41_ST0 12 2430 #define CCU41_IN3_CCU41_ST1 13 2431 #define CCU41_IN3_CCU41_ST2 14 2432 #define CCU41_IN3_CCU41_ST3 15 2433 #define CCU41_IN3_CCU81_IGBTO 7 2434 #define CCU41_IN3_ERU1_PDOUT0 3 2435 #define CCU41_IN3_ERU1_PDOUT3 9 2436 #define CCU41_IN3_P1_11 2 2437 #define CCU41_IN3_P2_2 0 2438 #define CCU41_IN3_P2_9 1 2439 #define CCU41_IN3_POSIF1_OUT3 4 2440 #define CCU41_IN3_POSIF1_OUT5 5 2441 #define CCU41_IN3_SCU_ERU1_IOUT3 10 2442 #define CCU41_IN3_SCU_GSC41 8 2443 #define CCU41_IN3_VADC0_G0BFL2 11 2444 #define CCU41_IN3_VADC0_G1ARBCNT 6 2445 #define CCU42_IN0_CCU42_ST0 12 2446 #define CCU42_IN0_CCU42_ST1 13 2447 #define CCU42_IN0_CCU42_ST2 14 2448 #define CCU42_IN0_CCU42_ST3 15 2449 #define CCU42_IN0_CCU80_IGBTO 7 2450 #define CCU42_IN0_ERU1_PDOUT0 9 2451 #define CCU42_IN0_ERU1_PDOUT1 3 2452 #define CCU42_IN0_P2_15 1 2453 #define CCU42_IN0_P3_6 0 2454 #define CCU42_IN0_POSIF0_OUT2 4 2455 #define CCU42_IN0_POSIF0_OUT5 5 2456 #define CCU42_IN0_SCU_ERU1_IOUT0 10 2457 #define CCU42_IN0_SCU_GSC42 8 2458 #define CCU42_IN0_U0C0_DX2INS 11 2459 #define CCU42_IN1_CCU42_ST0 12 2460 #define CCU42_IN1_CCU42_ST1 13 2461 #define CCU42_IN1_CCU42_ST2 14 2462 #define CCU42_IN1_CCU42_ST3 15 2463 #define CCU42_IN1_ERU1_PDOUT0 3 2464 #define CCU42_IN1_ERU1_PDOUT1 9 2465 #define CCU42_IN1_P2_15 1 2466 #define CCU42_IN1_P3_5 0 2467 #define CCU42_IN1_POSIF0_OUT2 4 2468 #define CCU42_IN1_POSIF0_OUT5 5 2469 #define CCU42_IN1_SCU_ERU1_IOUT1 10 2470 #define CCU42_IN1_SCU_GSC42 8 2471 #define CCU42_IN1_U0C1_DX2INS 11 2472 #define CCU42_IN2_CAN0_SR7 6 2473 #define CCU42_IN2_CCU42_ST0 12 2474 #define CCU42_IN2_CCU42_ST1 13 2475 #define CCU42_IN2_CCU42_ST2 14 2476 #define CCU42_IN2_CCU42_ST3 15 2477 #define CCU42_IN2_ERU1_PDOUT0 3 2478 #define CCU42_IN2_ERU1_PDOUT2 9 2479 #define CCU42_IN2_P2_15 1 2480 #define CCU42_IN2_P3_4 0 2481 #define CCU42_IN2_POSIF0_OUT2 4 2482 #define CCU42_IN2_POSIF0_OUT5 5 2483 #define CCU42_IN2_SCU_ERU1_IOUT2 10 2484 #define CCU42_IN2_SCU_GSC42 8 2485 #define CCU42_IN2_U1C0_DX2INS 11 2486 #define CCU42_IN3_CCU42_ST0 12 2487 #define CCU42_IN3_CCU42_ST1 13 2488 #define CCU42_IN3_CCU42_ST2 14 2489 #define CCU42_IN3_CCU42_ST3 15 2490 #define CCU42_IN3_ERU1_PDOUT0 3 2491 #define CCU42_IN3_ERU1_PDOUT3 9 2492 #define CCU42_IN3_P2_15 1 2493 #define CCU42_IN3_P3_3 0 2494 #define CCU42_IN3_POSIF0_OUT2 4 2495 #define CCU42_IN3_POSIF0_OUT5 5 2496 #define CCU42_IN3_SCU_ERU1_IOUT3 10 2497 #define CCU42_IN3_SCU_GSC42 8 2498 #define CCU42_IN3_U1C1_DX2INS 11 2499 #define CCU42_IN3_VADC0_G2ARBCNT 6 2500 #define CCU43_IN0_CCU43_ST0 12 2501 #define CCU43_IN0_CCU43_ST1 13 2502 #define CCU43_IN0_CCU43_ST2 14 2503 #define CCU43_IN0_CCU43_ST3 15 2504 #define CCU43_IN0_CCU81_IGBTO 6 2505 #define CCU43_IN0_ERU1_PDOUT0 9 2506 #define CCU43_IN0_ERU1_PDOUT1 3 2507 #define CCU43_IN0_P2_14 1 2508 #define CCU43_IN0_POSIF1_OUT2 4 2509 #define CCU43_IN0_POSIF1_OUT5 5 2510 #define CCU43_IN0_SCU_ERU1_IOUT0 10 2511 #define CCU43_IN0_SCU_GSC43 8 2512 #define CCU43_IN0_U0C0_DX2INS 11 2513 #define CCU43_IN0_VADC0_G0BFL0 7 2514 #define CCU43_IN1_CAN0_SR7 6 2515 #define CCU43_IN1_CCU43_ST0 12 2516 #define CCU43_IN1_CCU43_ST1 13 2517 #define CCU43_IN1_CCU43_ST2 14 2518 #define CCU43_IN1_CCU43_ST3 15 2519 #define CCU43_IN1_ERU1_PDOUT0 3 2520 #define CCU43_IN1_ERU1_PDOUT1 9 2521 #define CCU43_IN1_P2_14 1 2522 #define CCU43_IN1_POSIF1_OUT2 4 2523 #define CCU43_IN1_POSIF1_OUT5 5 2524 #define CCU43_IN1_SCU_ERU1_IOUT1 10 2525 #define CCU43_IN1_SCU_GSC43 8 2526 #define CCU43_IN1_U0C1_DX2INS 11 2527 #define CCU43_IN1_VADC0_G1BFL0 7 2528 #define CCU43_IN2_CCU43_ST0 12 2529 #define CCU43_IN2_CCU43_ST1 13 2530 #define CCU43_IN2_CCU43_ST2 14 2531 #define CCU43_IN2_CCU43_ST3 15 2532 #define CCU43_IN2_ERU1_PDOUT0 3 2533 #define CCU43_IN2_ERU1_PDOUT2 9 2534 #define CCU43_IN2_P2_14 1 2535 #define CCU43_IN2_POSIF1_OUT2 4 2536 #define CCU43_IN2_POSIF1_OUT5 5 2537 #define CCU43_IN2_SCU_ERU1_IOUT2 10 2538 #define CCU43_IN2_SCU_GSC43 8 2539 #define CCU43_IN2_U1C0_DX2INS 11 2540 #define CCU43_IN2_VADC0_G2BFL0 7 2541 #define CCU43_IN3_CCU43_ST0 12 2542 #define CCU43_IN3_CCU43_ST1 13 2543 #define CCU43_IN3_CCU43_ST2 14 2544 #define CCU43_IN3_CCU43_ST3 15 2545 #define CCU43_IN3_ERU1_PDOUT0 3 2546 #define CCU43_IN3_ERU1_PDOUT3 9 2547 #define CCU43_IN3_P2_14 1 2548 #define CCU43_IN3_POSIF1_OUT2 4 2549 #define CCU43_IN3_POSIF1_OUT5 5 2550 #define CCU43_IN3_SCU_ERU1_IOUT3 10 2551 #define CCU43_IN3_SCU_GSC43 8 2552 #define CCU43_IN3_U1C1_DX2INS 11 2553 #define CCU43_IN3_VADC0_G3ARBCNT 6 2554 #define CCU43_IN3_VADC0_G3BFL0 7 2555 #endif 2556 2557 2558 #if (UC_DEVICE == XMC4500) && (UC_PACKAGE == LQFP144) 2559 #define CCU40_IN0_CAN0_SR7 7 2560 #define CCU40_IN0_CCU40_ST0 12 2561 #define CCU40_IN0_CCU40_ST1 13 2562 #define CCU40_IN0_CCU40_ST2 14 2563 #define CCU40_IN0_CCU40_ST3 15 2564 #define CCU40_IN0_ERU1_PDOUT0 9 2565 #define CCU40_IN0_ERU1_PDOUT1 3 2566 #define CCU40_IN0_P1_3 0 2567 #define CCU40_IN0_P2_1 2 2568 #define CCU40_IN0_P2_8 1 2569 #define CCU40_IN0_POSIF0_OUT0 4 2570 #define CCU40_IN0_POSIF0_OUT1 5 2571 #define CCU40_IN0_POSIF0_OUT3 6 2572 #define CCU40_IN0_SCU_ERU1_IOUT0 10 2573 #define CCU40_IN0_SCU_GSC40 8 2574 #define CCU40_IN0_U0C0_DX2INS 11 2575 #define CCU40_IN1_CCU40_ST0 12 2576 #define CCU40_IN1_CCU40_ST1 13 2577 #define CCU40_IN1_CCU40_ST2 14 2578 #define CCU40_IN1_CCU40_ST3 15 2579 #define CCU40_IN1_ERU1_PDOUT0 3 2580 #define CCU40_IN1_ERU1_PDOUT1 9 2581 #define CCU40_IN1_P1_2 0 2582 #define CCU40_IN1_P2_0 2 2583 #define CCU40_IN1_P2_8 1 2584 #define CCU40_IN1_POSIF0_OUT0 4 2585 #define CCU40_IN1_POSIF0_OUT1 5 2586 #define CCU40_IN1_POSIF0_OUT2 11 2587 #define CCU40_IN1_POSIF0_OUT3 6 2588 #define CCU40_IN1_POSIF0_OUT4 7 2589 #define CCU40_IN1_SCU_ERU1_IOUT1 10 2590 #define CCU40_IN1_SCU_GSC40 8 2591 #define CCU40_IN2_CCU40_ST0 12 2592 #define CCU40_IN2_CCU40_ST1 13 2593 #define CCU40_IN2_CCU40_ST2 14 2594 #define CCU40_IN2_CCU40_ST3 15 2595 #define CCU40_IN2_ERU1_PDOUT0 3 2596 #define CCU40_IN2_ERU1_PDOUT2 9 2597 #define CCU40_IN2_P1_1 0 2598 #define CCU40_IN2_P2_7 2 2599 #define CCU40_IN2_P2_8 1 2600 #define CCU40_IN2_POSIF0_OUT0 4 2601 #define CCU40_IN2_POSIF0_OUT2 5 2602 #define CCU40_IN2_POSIF0_OUT3 6 2603 #define CCU40_IN2_POSIF0_OUT4 7 2604 #define CCU40_IN2_SCU_ERU1_IOUT2 10 2605 #define CCU40_IN2_SCU_GSC40 8 2606 #define CCU40_IN2_U0C1_DX2INS 11 2607 #define CCU40_IN3_CCU40_ST0 12 2608 #define CCU40_IN3_CCU40_ST1 13 2609 #define CCU40_IN3_CCU40_ST2 14 2610 #define CCU40_IN3_CCU40_ST3 15 2611 #define CCU40_IN3_CCU80_IGBTO 7 2612 #define CCU40_IN3_ERU1_PDOUT0 3 2613 #define CCU40_IN3_ERU1_PDOUT3 9 2614 #define CCU40_IN3_P1_0 0 2615 #define CCU40_IN3_P2_6 2 2616 #define CCU40_IN3_P2_8 1 2617 #define CCU40_IN3_POSIF0_OUT3 4 2618 #define CCU40_IN3_POSIF0_OUT5 5 2619 #define CCU40_IN3_SCU_ERU1_IOUT3 10 2620 #define CCU40_IN3_SCU_GSC40 8 2621 #define CCU40_IN3_U1C0_DX2INS 11 2622 #define CCU40_IN3_VADC0_G0ARBCNT 6 2623 #define CCU41_IN0_CAN0_SR7 7 2624 #define CCU41_IN0_CCU41_ST0 12 2625 #define CCU41_IN0_CCU41_ST1 13 2626 #define CCU41_IN0_CCU41_ST2 14 2627 #define CCU41_IN0_CCU41_ST3 15 2628 #define CCU41_IN0_ERU1_PDOUT0 9 2629 #define CCU41_IN0_ERU1_PDOUT1 3 2630 #define CCU41_IN0_P1_4 2 2631 #define CCU41_IN0_P2_5 0 2632 #define CCU41_IN0_P2_9 1 2633 #define CCU41_IN0_POSIF1_OUT0 4 2634 #define CCU41_IN0_POSIF1_OUT1 5 2635 #define CCU41_IN0_POSIF1_OUT3 6 2636 #define CCU41_IN0_SCU_ERU1_IOUT0 10 2637 #define CCU41_IN0_SCU_GSC41 8 2638 #define CCU41_IN0_VADC0_G0BFL0 11 2639 #define CCU41_IN1_CCU41_ST0 12 2640 #define CCU41_IN1_CCU41_ST1 13 2641 #define CCU41_IN1_CCU41_ST2 14 2642 #define CCU41_IN1_CCU41_ST3 15 2643 #define CCU41_IN1_ERU1_PDOUT0 3 2644 #define CCU41_IN1_ERU1_PDOUT1 9 2645 #define CCU41_IN1_P1_5 2 2646 #define CCU41_IN1_P2_4 0 2647 #define CCU41_IN1_P2_9 1 2648 #define CCU41_IN1_POSIF1_OUT0 4 2649 #define CCU41_IN1_POSIF1_OUT1 5 2650 #define CCU41_IN1_POSIF1_OUT2 11 2651 #define CCU41_IN1_POSIF1_OUT3 6 2652 #define CCU41_IN1_POSIF1_OUT4 7 2653 #define CCU41_IN1_SCU_ERU1_IOUT1 10 2654 #define CCU41_IN1_SCU_GSC41 8 2655 #define CCU41_IN2_CCU41_ST0 12 2656 #define CCU41_IN2_CCU41_ST1 13 2657 #define CCU41_IN2_CCU41_ST2 14 2658 #define CCU41_IN2_CCU41_ST3 15 2659 #define CCU41_IN2_ERU1_PDOUT0 3 2660 #define CCU41_IN2_ERU1_PDOUT2 9 2661 #define CCU41_IN2_P1_10 2 2662 #define CCU41_IN2_P2_3 0 2663 #define CCU41_IN2_P2_9 1 2664 #define CCU41_IN2_POSIF1_OUT0 4 2665 #define CCU41_IN2_POSIF1_OUT2 5 2666 #define CCU41_IN2_POSIF1_OUT3 6 2667 #define CCU41_IN2_POSIF1_OUT4 7 2668 #define CCU41_IN2_SCU_ERU1_IOUT2 10 2669 #define CCU41_IN2_SCU_GSC41 8 2670 #define CCU41_IN2_VADC0_G0BFL1 11 2671 #define CCU41_IN3_CCU41_ST0 12 2672 #define CCU41_IN3_CCU41_ST1 13 2673 #define CCU41_IN3_CCU41_ST2 14 2674 #define CCU41_IN3_CCU41_ST3 15 2675 #define CCU41_IN3_CCU81_IGBTO 7 2676 #define CCU41_IN3_ERU1_PDOUT0 3 2677 #define CCU41_IN3_ERU1_PDOUT3 9 2678 #define CCU41_IN3_P1_11 2 2679 #define CCU41_IN3_P2_2 0 2680 #define CCU41_IN3_P2_9 1 2681 #define CCU41_IN3_POSIF1_OUT3 4 2682 #define CCU41_IN3_POSIF1_OUT5 5 2683 #define CCU41_IN3_SCU_ERU1_IOUT3 10 2684 #define CCU41_IN3_SCU_GSC41 8 2685 #define CCU41_IN3_VADC0_G0BFL2 11 2686 #define CCU41_IN3_VADC0_G1ARBCNT 6 2687 #define CCU42_IN0_CCU42_ST0 12 2688 #define CCU42_IN0_CCU42_ST1 13 2689 #define CCU42_IN0_CCU42_ST2 14 2690 #define CCU42_IN0_CCU42_ST3 15 2691 #define CCU42_IN0_CCU80_IGBTO 7 2692 #define CCU42_IN0_ERU1_PDOUT0 9 2693 #define CCU42_IN0_ERU1_PDOUT1 3 2694 #define CCU42_IN0_P2_15 1 2695 #define CCU42_IN0_P3_15 2 2696 #define CCU42_IN0_P3_6 0 2697 #define CCU42_IN0_POSIF0_OUT2 4 2698 #define CCU42_IN0_POSIF0_OUT5 5 2699 #define CCU42_IN0_SCU_ERU1_IOUT0 10 2700 #define CCU42_IN0_SCU_GSC42 8 2701 #define CCU42_IN0_U0C0_DX2INS 11 2702 #define CCU42_IN1_CCU42_ST0 12 2703 #define CCU42_IN1_CCU42_ST1 13 2704 #define CCU42_IN1_CCU42_ST2 14 2705 #define CCU42_IN1_CCU42_ST3 15 2706 #define CCU42_IN1_ERU1_PDOUT0 3 2707 #define CCU42_IN1_ERU1_PDOUT1 9 2708 #define CCU42_IN1_P2_15 1 2709 #define CCU42_IN1_P3_14 2 2710 #define CCU42_IN1_P3_5 0 2711 #define CCU42_IN1_POSIF0_OUT2 4 2712 #define CCU42_IN1_POSIF0_OUT5 5 2713 #define CCU42_IN1_SCU_ERU1_IOUT1 10 2714 #define CCU42_IN1_SCU_GSC42 8 2715 #define CCU42_IN1_U0C1_DX2INS 11 2716 #define CCU42_IN2_CAN0_SR7 6 2717 #define CCU42_IN2_CCU42_ST0 12 2718 #define CCU42_IN2_CCU42_ST1 13 2719 #define CCU42_IN2_CCU42_ST2 14 2720 #define CCU42_IN2_CCU42_ST3 15 2721 #define CCU42_IN2_ERU1_PDOUT0 3 2722 #define CCU42_IN2_ERU1_PDOUT2 9 2723 #define CCU42_IN2_P0_15 2 2724 #define CCU42_IN2_P2_15 1 2725 #define CCU42_IN2_P3_4 0 2726 #define CCU42_IN2_POSIF0_OUT2 4 2727 #define CCU42_IN2_POSIF0_OUT5 5 2728 #define CCU42_IN2_SCU_ERU1_IOUT2 10 2729 #define CCU42_IN2_SCU_GSC42 8 2730 #define CCU42_IN2_U1C0_DX2INS 11 2731 #define CCU42_IN3_CCU42_ST0 12 2732 #define CCU42_IN3_CCU42_ST1 13 2733 #define CCU42_IN3_CCU42_ST2 14 2734 #define CCU42_IN3_CCU42_ST3 15 2735 #define CCU42_IN3_ERU1_PDOUT0 3 2736 #define CCU42_IN3_ERU1_PDOUT3 9 2737 #define CCU42_IN3_P0_14 2 2738 #define CCU42_IN3_P2_15 1 2739 #define CCU42_IN3_P3_3 0 2740 #define CCU42_IN3_POSIF0_OUT2 4 2741 #define CCU42_IN3_POSIF0_OUT5 5 2742 #define CCU42_IN3_SCU_ERU1_IOUT3 10 2743 #define CCU42_IN3_SCU_GSC42 8 2744 #define CCU42_IN3_U1C1_DX2INS 11 2745 #define CCU42_IN3_VADC0_G2ARBCNT 6 2746 #define CCU43_IN0_CCU43_ST0 12 2747 #define CCU43_IN0_CCU43_ST1 13 2748 #define CCU43_IN0_CCU43_ST2 14 2749 #define CCU43_IN0_CCU43_ST3 15 2750 #define CCU43_IN0_CCU81_IGBTO 6 2751 #define CCU43_IN0_ERU1_PDOUT0 9 2752 #define CCU43_IN0_ERU1_PDOUT1 3 2753 #define CCU43_IN0_P2_14 1 2754 #define CCU43_IN0_P4_6 0 2755 #define CCU43_IN0_P4_7 2 2756 #define CCU43_IN0_POSIF1_OUT2 4 2757 #define CCU43_IN0_POSIF1_OUT5 5 2758 #define CCU43_IN0_SCU_ERU1_IOUT0 10 2759 #define CCU43_IN0_SCU_GSC43 8 2760 #define CCU43_IN0_U0C0_DX2INS 11 2761 #define CCU43_IN0_VADC0_G0BFL0 7 2762 #define CCU43_IN1_CAN0_SR7 6 2763 #define CCU43_IN1_CCU43_ST0 12 2764 #define CCU43_IN1_CCU43_ST1 13 2765 #define CCU43_IN1_CCU43_ST2 14 2766 #define CCU43_IN1_CCU43_ST3 15 2767 #define CCU43_IN1_ERU1_PDOUT0 3 2768 #define CCU43_IN1_ERU1_PDOUT1 9 2769 #define CCU43_IN1_P2_14 1 2770 #define CCU43_IN1_P4_2 2 2771 #define CCU43_IN1_P4_5 0 2772 #define CCU43_IN1_POSIF1_OUT2 4 2773 #define CCU43_IN1_POSIF1_OUT5 5 2774 #define CCU43_IN1_SCU_ERU1_IOUT1 10 2775 #define CCU43_IN1_SCU_GSC43 8 2776 #define CCU43_IN1_U0C1_DX2INS 11 2777 #define CCU43_IN1_VADC0_G1BFL0 7 2778 #define CCU43_IN2_CCU43_ST0 12 2779 #define CCU43_IN2_CCU43_ST1 13 2780 #define CCU43_IN2_CCU43_ST2 14 2781 #define CCU43_IN2_CCU43_ST3 15 2782 #define CCU43_IN2_ERU1_PDOUT0 3 2783 #define CCU43_IN2_ERU1_PDOUT2 9 2784 #define CCU43_IN2_P2_13 2 2785 #define CCU43_IN2_P2_14 1 2786 #define CCU43_IN2_P4_4 0 2787 #define CCU43_IN2_POSIF1_OUT2 4 2788 #define CCU43_IN2_POSIF1_OUT5 5 2789 #define CCU43_IN2_SCU_ERU1_IOUT2 10 2790 #define CCU43_IN2_SCU_GSC43 8 2791 #define CCU43_IN2_U1C0_DX2INS 11 2792 #define CCU43_IN2_VADC0_G2BFL0 7 2793 #define CCU43_IN3_CCU43_ST0 12 2794 #define CCU43_IN3_CCU43_ST1 13 2795 #define CCU43_IN3_CCU43_ST2 14 2796 #define CCU43_IN3_CCU43_ST3 15 2797 #define CCU43_IN3_ERU1_PDOUT0 3 2798 #define CCU43_IN3_ERU1_PDOUT3 9 2799 #define CCU43_IN3_P2_12 2 2800 #define CCU43_IN3_P2_14 1 2801 #define CCU43_IN3_P4_3 0 2802 #define CCU43_IN3_POSIF1_OUT2 4 2803 #define CCU43_IN3_POSIF1_OUT5 5 2804 #define CCU43_IN3_SCU_ERU1_IOUT3 10 2805 #define CCU43_IN3_SCU_GSC43 8 2806 #define CCU43_IN3_U1C1_DX2INS 11 2807 #define CCU43_IN3_VADC0_G3ARBCNT 6 2808 #define CCU43_IN3_VADC0_G3BFL0 7 2809 #endif 2810 2811 2812 #if (UC_DEVICE == XMC4502) && (UC_PACKAGE == LQFP100) 2813 #define CCU40_IN0_CAN0_SR7 7 2814 #define CCU40_IN0_CCU40_ST0 12 2815 #define CCU40_IN0_CCU40_ST1 13 2816 #define CCU40_IN0_CCU40_ST2 14 2817 #define CCU40_IN0_CCU40_ST3 15 2818 #define CCU40_IN0_ERU1_PDOUT0 9 2819 #define CCU40_IN0_ERU1_PDOUT1 3 2820 #define CCU40_IN0_P1_3 0 2821 #define CCU40_IN0_P2_1 2 2822 #define CCU40_IN0_P2_8 1 2823 #define CCU40_IN0_POSIF0_OUT0 4 2824 #define CCU40_IN0_POSIF0_OUT1 5 2825 #define CCU40_IN0_POSIF0_OUT3 6 2826 #define CCU40_IN0_SCU_ERU1_IOUT0 10 2827 #define CCU40_IN0_SCU_GSC40 8 2828 #define CCU40_IN0_U0C0_DX2INS 11 2829 #define CCU40_IN1_CCU40_ST0 12 2830 #define CCU40_IN1_CCU40_ST1 13 2831 #define CCU40_IN1_CCU40_ST2 14 2832 #define CCU40_IN1_CCU40_ST3 15 2833 #define CCU40_IN1_ERU1_PDOUT0 3 2834 #define CCU40_IN1_ERU1_PDOUT1 9 2835 #define CCU40_IN1_P1_2 0 2836 #define CCU40_IN1_P2_0 2 2837 #define CCU40_IN1_P2_8 1 2838 #define CCU40_IN1_POSIF0_OUT0 4 2839 #define CCU40_IN1_POSIF0_OUT1 5 2840 #define CCU40_IN1_POSIF0_OUT2 11 2841 #define CCU40_IN1_POSIF0_OUT3 6 2842 #define CCU40_IN1_POSIF0_OUT4 7 2843 #define CCU40_IN1_SCU_ERU1_IOUT1 10 2844 #define CCU40_IN1_SCU_GSC40 8 2845 #define CCU40_IN2_CCU40_ST0 12 2846 #define CCU40_IN2_CCU40_ST1 13 2847 #define CCU40_IN2_CCU40_ST2 14 2848 #define CCU40_IN2_CCU40_ST3 15 2849 #define CCU40_IN2_ERU1_PDOUT0 3 2850 #define CCU40_IN2_ERU1_PDOUT2 9 2851 #define CCU40_IN2_P1_1 0 2852 #define CCU40_IN2_P2_7 2 2853 #define CCU40_IN2_P2_8 1 2854 #define CCU40_IN2_POSIF0_OUT0 4 2855 #define CCU40_IN2_POSIF0_OUT2 5 2856 #define CCU40_IN2_POSIF0_OUT3 6 2857 #define CCU40_IN2_POSIF0_OUT4 7 2858 #define CCU40_IN2_SCU_ERU1_IOUT2 10 2859 #define CCU40_IN2_SCU_GSC40 8 2860 #define CCU40_IN2_U0C1_DX2INS 11 2861 #define CCU40_IN3_CCU40_ST0 12 2862 #define CCU40_IN3_CCU40_ST1 13 2863 #define CCU40_IN3_CCU40_ST2 14 2864 #define CCU40_IN3_CCU40_ST3 15 2865 #define CCU40_IN3_CCU80_IGBTO 7 2866 #define CCU40_IN3_ERU1_PDOUT0 3 2867 #define CCU40_IN3_ERU1_PDOUT3 9 2868 #define CCU40_IN3_P1_0 0 2869 #define CCU40_IN3_P2_6 2 2870 #define CCU40_IN3_P2_8 1 2871 #define CCU40_IN3_POSIF0_OUT3 4 2872 #define CCU40_IN3_POSIF0_OUT5 5 2873 #define CCU40_IN3_SCU_ERU1_IOUT3 10 2874 #define CCU40_IN3_SCU_GSC40 8 2875 #define CCU40_IN3_U1C0_DX2INS 11 2876 #define CCU40_IN3_VADC0_G0ARBCNT 6 2877 #define CCU41_IN0_CAN0_SR7 7 2878 #define CCU41_IN0_CCU41_ST0 12 2879 #define CCU41_IN0_CCU41_ST1 13 2880 #define CCU41_IN0_CCU41_ST2 14 2881 #define CCU41_IN0_CCU41_ST3 15 2882 #define CCU41_IN0_ERU1_PDOUT0 9 2883 #define CCU41_IN0_ERU1_PDOUT1 3 2884 #define CCU41_IN0_P1_4 2 2885 #define CCU41_IN0_P2_5 0 2886 #define CCU41_IN0_P2_9 1 2887 #define CCU41_IN0_POSIF1_OUT0 4 2888 #define CCU41_IN0_POSIF1_OUT1 5 2889 #define CCU41_IN0_POSIF1_OUT3 6 2890 #define CCU41_IN0_SCU_ERU1_IOUT0 10 2891 #define CCU41_IN0_SCU_GSC41 8 2892 #define CCU41_IN0_VADC0_G0BFL0 11 2893 #define CCU41_IN1_CCU41_ST0 12 2894 #define CCU41_IN1_CCU41_ST1 13 2895 #define CCU41_IN1_CCU41_ST2 14 2896 #define CCU41_IN1_CCU41_ST3 15 2897 #define CCU41_IN1_ERU1_PDOUT0 3 2898 #define CCU41_IN1_ERU1_PDOUT1 9 2899 #define CCU41_IN1_P1_5 2 2900 #define CCU41_IN1_P2_4 0 2901 #define CCU41_IN1_P2_9 1 2902 #define CCU41_IN1_POSIF1_OUT0 4 2903 #define CCU41_IN1_POSIF1_OUT1 5 2904 #define CCU41_IN1_POSIF1_OUT2 11 2905 #define CCU41_IN1_POSIF1_OUT3 6 2906 #define CCU41_IN1_POSIF1_OUT4 7 2907 #define CCU41_IN1_SCU_ERU1_IOUT1 10 2908 #define CCU41_IN1_SCU_GSC41 8 2909 #define CCU41_IN2_CCU41_ST0 12 2910 #define CCU41_IN2_CCU41_ST1 13 2911 #define CCU41_IN2_CCU41_ST2 14 2912 #define CCU41_IN2_CCU41_ST3 15 2913 #define CCU41_IN2_ERU1_PDOUT0 3 2914 #define CCU41_IN2_ERU1_PDOUT2 9 2915 #define CCU41_IN2_P1_10 2 2916 #define CCU41_IN2_P2_3 0 2917 #define CCU41_IN2_P2_9 1 2918 #define CCU41_IN2_POSIF1_OUT0 4 2919 #define CCU41_IN2_POSIF1_OUT2 5 2920 #define CCU41_IN2_POSIF1_OUT3 6 2921 #define CCU41_IN2_POSIF1_OUT4 7 2922 #define CCU41_IN2_SCU_ERU1_IOUT2 10 2923 #define CCU41_IN2_SCU_GSC41 8 2924 #define CCU41_IN2_VADC0_G0BFL1 11 2925 #define CCU41_IN3_CCU41_ST0 12 2926 #define CCU41_IN3_CCU41_ST1 13 2927 #define CCU41_IN3_CCU41_ST2 14 2928 #define CCU41_IN3_CCU41_ST3 15 2929 #define CCU41_IN3_CCU81_IGBTO 7 2930 #define CCU41_IN3_ERU1_PDOUT0 3 2931 #define CCU41_IN3_ERU1_PDOUT3 9 2932 #define CCU41_IN3_P1_11 2 2933 #define CCU41_IN3_P2_2 0 2934 #define CCU41_IN3_P2_9 1 2935 #define CCU41_IN3_POSIF1_OUT3 4 2936 #define CCU41_IN3_POSIF1_OUT5 5 2937 #define CCU41_IN3_SCU_ERU1_IOUT3 10 2938 #define CCU41_IN3_SCU_GSC41 8 2939 #define CCU41_IN3_VADC0_G0BFL2 11 2940 #define CCU41_IN3_VADC0_G1ARBCNT 6 2941 #define CCU42_IN0_CCU42_ST0 12 2942 #define CCU42_IN0_CCU42_ST1 13 2943 #define CCU42_IN0_CCU42_ST2 14 2944 #define CCU42_IN0_CCU42_ST3 15 2945 #define CCU42_IN0_CCU80_IGBTO 7 2946 #define CCU42_IN0_ERU1_PDOUT0 9 2947 #define CCU42_IN0_ERU1_PDOUT1 3 2948 #define CCU42_IN0_P2_15 1 2949 #define CCU42_IN0_P3_6 0 2950 #define CCU42_IN0_POSIF0_OUT2 4 2951 #define CCU42_IN0_POSIF0_OUT5 5 2952 #define CCU42_IN0_SCU_ERU1_IOUT0 10 2953 #define CCU42_IN0_SCU_GSC42 8 2954 #define CCU42_IN0_U0C0_DX2INS 11 2955 #define CCU42_IN1_CCU42_ST0 12 2956 #define CCU42_IN1_CCU42_ST1 13 2957 #define CCU42_IN1_CCU42_ST2 14 2958 #define CCU42_IN1_CCU42_ST3 15 2959 #define CCU42_IN1_ERU1_PDOUT0 3 2960 #define CCU42_IN1_ERU1_PDOUT1 9 2961 #define CCU42_IN1_P2_15 1 2962 #define CCU42_IN1_P3_5 0 2963 #define CCU42_IN1_POSIF0_OUT2 4 2964 #define CCU42_IN1_POSIF0_OUT5 5 2965 #define CCU42_IN1_SCU_ERU1_IOUT1 10 2966 #define CCU42_IN1_SCU_GSC42 8 2967 #define CCU42_IN1_U0C1_DX2INS 11 2968 #define CCU42_IN2_CAN0_SR7 6 2969 #define CCU42_IN2_CCU42_ST0 12 2970 #define CCU42_IN2_CCU42_ST1 13 2971 #define CCU42_IN2_CCU42_ST2 14 2972 #define CCU42_IN2_CCU42_ST3 15 2973 #define CCU42_IN2_ERU1_PDOUT0 3 2974 #define CCU42_IN2_ERU1_PDOUT2 9 2975 #define CCU42_IN2_P2_15 1 2976 #define CCU42_IN2_P3_4 0 2977 #define CCU42_IN2_POSIF0_OUT2 4 2978 #define CCU42_IN2_POSIF0_OUT5 5 2979 #define CCU42_IN2_SCU_ERU1_IOUT2 10 2980 #define CCU42_IN2_SCU_GSC42 8 2981 #define CCU42_IN2_U1C0_DX2INS 11 2982 #define CCU42_IN3_CCU42_ST0 12 2983 #define CCU42_IN3_CCU42_ST1 13 2984 #define CCU42_IN3_CCU42_ST2 14 2985 #define CCU42_IN3_CCU42_ST3 15 2986 #define CCU42_IN3_ERU1_PDOUT0 3 2987 #define CCU42_IN3_ERU1_PDOUT3 9 2988 #define CCU42_IN3_P2_15 1 2989 #define CCU42_IN3_P3_3 0 2990 #define CCU42_IN3_POSIF0_OUT2 4 2991 #define CCU42_IN3_POSIF0_OUT5 5 2992 #define CCU42_IN3_SCU_ERU1_IOUT3 10 2993 #define CCU42_IN3_SCU_GSC42 8 2994 #define CCU42_IN3_U1C1_DX2INS 11 2995 #define CCU42_IN3_VADC0_G2ARBCNT 6 2996 #define CCU43_IN0_CCU43_ST0 12 2997 #define CCU43_IN0_CCU43_ST1 13 2998 #define CCU43_IN0_CCU43_ST2 14 2999 #define CCU43_IN0_CCU43_ST3 15 3000 #define CCU43_IN0_CCU81_IGBTO 6 3001 #define CCU43_IN0_ERU1_PDOUT0 9 3002 #define CCU43_IN0_ERU1_PDOUT1 3 3003 #define CCU43_IN0_P2_14 1 3004 #define CCU43_IN0_POSIF1_OUT2 4 3005 #define CCU43_IN0_POSIF1_OUT5 5 3006 #define CCU43_IN0_SCU_ERU1_IOUT0 10 3007 #define CCU43_IN0_SCU_GSC43 8 3008 #define CCU43_IN0_U0C0_DX2INS 11 3009 #define CCU43_IN0_VADC0_G0BFL0 7 3010 #define CCU43_IN1_CAN0_SR7 6 3011 #define CCU43_IN1_CCU43_ST0 12 3012 #define CCU43_IN1_CCU43_ST1 13 3013 #define CCU43_IN1_CCU43_ST2 14 3014 #define CCU43_IN1_CCU43_ST3 15 3015 #define CCU43_IN1_ERU1_PDOUT0 3 3016 #define CCU43_IN1_ERU1_PDOUT1 9 3017 #define CCU43_IN1_P2_14 1 3018 #define CCU43_IN1_POSIF1_OUT2 4 3019 #define CCU43_IN1_POSIF1_OUT5 5 3020 #define CCU43_IN1_SCU_ERU1_IOUT1 10 3021 #define CCU43_IN1_SCU_GSC43 8 3022 #define CCU43_IN1_U0C1_DX2INS 11 3023 #define CCU43_IN1_VADC0_G1BFL0 7 3024 #define CCU43_IN2_CCU43_ST0 12 3025 #define CCU43_IN2_CCU43_ST1 13 3026 #define CCU43_IN2_CCU43_ST2 14 3027 #define CCU43_IN2_CCU43_ST3 15 3028 #define CCU43_IN2_ERU1_PDOUT0 3 3029 #define CCU43_IN2_ERU1_PDOUT2 9 3030 #define CCU43_IN2_P2_14 1 3031 #define CCU43_IN2_POSIF1_OUT2 4 3032 #define CCU43_IN2_POSIF1_OUT5 5 3033 #define CCU43_IN2_SCU_ERU1_IOUT2 10 3034 #define CCU43_IN2_SCU_GSC43 8 3035 #define CCU43_IN2_U1C0_DX2INS 11 3036 #define CCU43_IN2_VADC0_G2BFL0 7 3037 #define CCU43_IN3_CCU43_ST0 12 3038 #define CCU43_IN3_CCU43_ST1 13 3039 #define CCU43_IN3_CCU43_ST2 14 3040 #define CCU43_IN3_CCU43_ST3 15 3041 #define CCU43_IN3_ERU1_PDOUT0 3 3042 #define CCU43_IN3_ERU1_PDOUT3 9 3043 #define CCU43_IN3_P2_14 1 3044 #define CCU43_IN3_POSIF1_OUT2 4 3045 #define CCU43_IN3_POSIF1_OUT5 5 3046 #define CCU43_IN3_SCU_ERU1_IOUT3 10 3047 #define CCU43_IN3_SCU_GSC43 8 3048 #define CCU43_IN3_U1C1_DX2INS 11 3049 #define CCU43_IN3_VADC0_G3ARBCNT 6 3050 #define CCU43_IN3_VADC0_G3BFL0 7 3051 #endif 3052 3053 3054 #if (UC_DEVICE == XMC4504) && (UC_PACKAGE == LQFP100) 3055 #define CCU40_IN0_CCU40_ST0 12 3056 #define CCU40_IN0_CCU40_ST1 13 3057 #define CCU40_IN0_CCU40_ST2 14 3058 #define CCU40_IN0_CCU40_ST3 15 3059 #define CCU40_IN0_ERU1_PDOUT0 9 3060 #define CCU40_IN0_ERU1_PDOUT1 3 3061 #define CCU40_IN0_P1_3 0 3062 #define CCU40_IN0_P2_1 2 3063 #define CCU40_IN0_P2_8 1 3064 #define CCU40_IN0_POSIF0_OUT0 4 3065 #define CCU40_IN0_POSIF0_OUT1 5 3066 #define CCU40_IN0_POSIF0_OUT3 6 3067 #define CCU40_IN0_SCU_ERU1_IOUT0 10 3068 #define CCU40_IN0_SCU_GSC40 8 3069 #define CCU40_IN0_U0C0_DX2INS 11 3070 #define CCU40_IN1_CCU40_ST0 12 3071 #define CCU40_IN1_CCU40_ST1 13 3072 #define CCU40_IN1_CCU40_ST2 14 3073 #define CCU40_IN1_CCU40_ST3 15 3074 #define CCU40_IN1_ERU1_PDOUT0 3 3075 #define CCU40_IN1_ERU1_PDOUT1 9 3076 #define CCU40_IN1_P1_2 0 3077 #define CCU40_IN1_P2_0 2 3078 #define CCU40_IN1_P2_8 1 3079 #define CCU40_IN1_POSIF0_OUT0 4 3080 #define CCU40_IN1_POSIF0_OUT1 5 3081 #define CCU40_IN1_POSIF0_OUT2 11 3082 #define CCU40_IN1_POSIF0_OUT3 6 3083 #define CCU40_IN1_POSIF0_OUT4 7 3084 #define CCU40_IN1_SCU_ERU1_IOUT1 10 3085 #define CCU40_IN1_SCU_GSC40 8 3086 #define CCU40_IN2_CCU40_ST0 12 3087 #define CCU40_IN2_CCU40_ST1 13 3088 #define CCU40_IN2_CCU40_ST2 14 3089 #define CCU40_IN2_CCU40_ST3 15 3090 #define CCU40_IN2_ERU1_PDOUT0 3 3091 #define CCU40_IN2_ERU1_PDOUT2 9 3092 #define CCU40_IN2_P1_1 0 3093 #define CCU40_IN2_P2_7 2 3094 #define CCU40_IN2_P2_8 1 3095 #define CCU40_IN2_POSIF0_OUT0 4 3096 #define CCU40_IN2_POSIF0_OUT2 5 3097 #define CCU40_IN2_POSIF0_OUT3 6 3098 #define CCU40_IN2_POSIF0_OUT4 7 3099 #define CCU40_IN2_SCU_ERU1_IOUT2 10 3100 #define CCU40_IN2_SCU_GSC40 8 3101 #define CCU40_IN2_U0C1_DX2INS 11 3102 #define CCU40_IN3_CCU40_ST0 12 3103 #define CCU40_IN3_CCU40_ST1 13 3104 #define CCU40_IN3_CCU40_ST2 14 3105 #define CCU40_IN3_CCU40_ST3 15 3106 #define CCU40_IN3_CCU80_IGBTO 7 3107 #define CCU40_IN3_ERU1_PDOUT0 3 3108 #define CCU40_IN3_ERU1_PDOUT3 9 3109 #define CCU40_IN3_P1_0 0 3110 #define CCU40_IN3_P2_6 2 3111 #define CCU40_IN3_P2_8 1 3112 #define CCU40_IN3_POSIF0_OUT3 4 3113 #define CCU40_IN3_POSIF0_OUT5 5 3114 #define CCU40_IN3_SCU_ERU1_IOUT3 10 3115 #define CCU40_IN3_SCU_GSC40 8 3116 #define CCU40_IN3_U1C0_DX2INS 11 3117 #define CCU40_IN3_VADC0_G0ARBCNT 6 3118 #define CCU41_IN0_CCU41_ST0 12 3119 #define CCU41_IN0_CCU41_ST1 13 3120 #define CCU41_IN0_CCU41_ST2 14 3121 #define CCU41_IN0_CCU41_ST3 15 3122 #define CCU41_IN0_ERU1_PDOUT0 9 3123 #define CCU41_IN0_ERU1_PDOUT1 3 3124 #define CCU41_IN0_P1_4 2 3125 #define CCU41_IN0_P2_5 0 3126 #define CCU41_IN0_P2_9 1 3127 #define CCU41_IN0_POSIF1_OUT0 4 3128 #define CCU41_IN0_POSIF1_OUT1 5 3129 #define CCU41_IN0_POSIF1_OUT3 6 3130 #define CCU41_IN0_SCU_ERU1_IOUT0 10 3131 #define CCU41_IN0_SCU_GSC41 8 3132 #define CCU41_IN0_VADC0_G0BFL0 11 3133 #define CCU41_IN1_CCU41_ST0 12 3134 #define CCU41_IN1_CCU41_ST1 13 3135 #define CCU41_IN1_CCU41_ST2 14 3136 #define CCU41_IN1_CCU41_ST3 15 3137 #define CCU41_IN1_ERU1_PDOUT0 3 3138 #define CCU41_IN1_ERU1_PDOUT1 9 3139 #define CCU41_IN1_P1_5 2 3140 #define CCU41_IN1_P2_4 0 3141 #define CCU41_IN1_P2_9 1 3142 #define CCU41_IN1_POSIF1_OUT0 4 3143 #define CCU41_IN1_POSIF1_OUT1 5 3144 #define CCU41_IN1_POSIF1_OUT2 11 3145 #define CCU41_IN1_POSIF1_OUT3 6 3146 #define CCU41_IN1_POSIF1_OUT4 7 3147 #define CCU41_IN1_SCU_ERU1_IOUT1 10 3148 #define CCU41_IN1_SCU_GSC41 8 3149 #define CCU41_IN2_CCU41_ST0 12 3150 #define CCU41_IN2_CCU41_ST1 13 3151 #define CCU41_IN2_CCU41_ST2 14 3152 #define CCU41_IN2_CCU41_ST3 15 3153 #define CCU41_IN2_ERU1_PDOUT0 3 3154 #define CCU41_IN2_ERU1_PDOUT2 9 3155 #define CCU41_IN2_P1_10 2 3156 #define CCU41_IN2_P2_3 0 3157 #define CCU41_IN2_P2_9 1 3158 #define CCU41_IN2_POSIF1_OUT0 4 3159 #define CCU41_IN2_POSIF1_OUT2 5 3160 #define CCU41_IN2_POSIF1_OUT3 6 3161 #define CCU41_IN2_POSIF1_OUT4 7 3162 #define CCU41_IN2_SCU_ERU1_IOUT2 10 3163 #define CCU41_IN2_SCU_GSC41 8 3164 #define CCU41_IN2_VADC0_G0BFL1 11 3165 #define CCU41_IN3_CCU41_ST0 12 3166 #define CCU41_IN3_CCU41_ST1 13 3167 #define CCU41_IN3_CCU41_ST2 14 3168 #define CCU41_IN3_CCU41_ST3 15 3169 #define CCU41_IN3_CCU81_IGBTO 7 3170 #define CCU41_IN3_ERU1_PDOUT0 3 3171 #define CCU41_IN3_ERU1_PDOUT3 9 3172 #define CCU41_IN3_P1_11 2 3173 #define CCU41_IN3_P2_2 0 3174 #define CCU41_IN3_P2_9 1 3175 #define CCU41_IN3_POSIF1_OUT3 4 3176 #define CCU41_IN3_POSIF1_OUT5 5 3177 #define CCU41_IN3_SCU_ERU1_IOUT3 10 3178 #define CCU41_IN3_SCU_GSC41 8 3179 #define CCU41_IN3_VADC0_G0BFL2 11 3180 #define CCU41_IN3_VADC0_G1ARBCNT 6 3181 #define CCU42_IN0_CCU42_ST0 12 3182 #define CCU42_IN0_CCU42_ST1 13 3183 #define CCU42_IN0_CCU42_ST2 14 3184 #define CCU42_IN0_CCU42_ST3 15 3185 #define CCU42_IN0_CCU80_IGBTO 7 3186 #define CCU42_IN0_ERU1_PDOUT0 9 3187 #define CCU42_IN0_ERU1_PDOUT1 3 3188 #define CCU42_IN0_P2_15 1 3189 #define CCU42_IN0_P3_6 0 3190 #define CCU42_IN0_POSIF0_OUT2 4 3191 #define CCU42_IN0_POSIF0_OUT5 5 3192 #define CCU42_IN0_SCU_ERU1_IOUT0 10 3193 #define CCU42_IN0_SCU_GSC42 8 3194 #define CCU42_IN0_U0C0_DX2INS 11 3195 #define CCU42_IN1_CCU42_ST0 12 3196 #define CCU42_IN1_CCU42_ST1 13 3197 #define CCU42_IN1_CCU42_ST2 14 3198 #define CCU42_IN1_CCU42_ST3 15 3199 #define CCU42_IN1_ERU1_PDOUT0 3 3200 #define CCU42_IN1_ERU1_PDOUT1 9 3201 #define CCU42_IN1_P2_15 1 3202 #define CCU42_IN1_P3_5 0 3203 #define CCU42_IN1_POSIF0_OUT2 4 3204 #define CCU42_IN1_POSIF0_OUT5 5 3205 #define CCU42_IN1_SCU_ERU1_IOUT1 10 3206 #define CCU42_IN1_SCU_GSC42 8 3207 #define CCU42_IN1_U0C1_DX2INS 11 3208 #define CCU42_IN2_CCU42_ST0 12 3209 #define CCU42_IN2_CCU42_ST1 13 3210 #define CCU42_IN2_CCU42_ST2 14 3211 #define CCU42_IN2_CCU42_ST3 15 3212 #define CCU42_IN2_ERU1_PDOUT0 3 3213 #define CCU42_IN2_ERU1_PDOUT2 9 3214 #define CCU42_IN2_P2_15 1 3215 #define CCU42_IN2_P3_4 0 3216 #define CCU42_IN2_POSIF0_OUT2 4 3217 #define CCU42_IN2_POSIF0_OUT5 5 3218 #define CCU42_IN2_SCU_ERU1_IOUT2 10 3219 #define CCU42_IN2_SCU_GSC42 8 3220 #define CCU42_IN2_U1C0_DX2INS 11 3221 #define CCU42_IN3_CCU42_ST0 12 3222 #define CCU42_IN3_CCU42_ST1 13 3223 #define CCU42_IN3_CCU42_ST2 14 3224 #define CCU42_IN3_CCU42_ST3 15 3225 #define CCU42_IN3_ERU1_PDOUT0 3 3226 #define CCU42_IN3_ERU1_PDOUT3 9 3227 #define CCU42_IN3_P2_15 1 3228 #define CCU42_IN3_P3_3 0 3229 #define CCU42_IN3_POSIF0_OUT2 4 3230 #define CCU42_IN3_POSIF0_OUT5 5 3231 #define CCU42_IN3_SCU_ERU1_IOUT3 10 3232 #define CCU42_IN3_SCU_GSC42 8 3233 #define CCU42_IN3_U1C1_DX2INS 11 3234 #define CCU42_IN3_VADC0_G2ARBCNT 6 3235 #define CCU43_IN0_CCU43_ST0 12 3236 #define CCU43_IN0_CCU43_ST1 13 3237 #define CCU43_IN0_CCU43_ST2 14 3238 #define CCU43_IN0_CCU43_ST3 15 3239 #define CCU43_IN0_CCU81_IGBTO 6 3240 #define CCU43_IN0_ERU1_PDOUT0 9 3241 #define CCU43_IN0_ERU1_PDOUT1 3 3242 #define CCU43_IN0_P2_14 1 3243 #define CCU43_IN0_POSIF1_OUT2 4 3244 #define CCU43_IN0_POSIF1_OUT5 5 3245 #define CCU43_IN0_SCU_ERU1_IOUT0 10 3246 #define CCU43_IN0_SCU_GSC43 8 3247 #define CCU43_IN0_U0C0_DX2INS 11 3248 #define CCU43_IN0_VADC0_G0BFL0 7 3249 #define CCU43_IN1_CCU43_ST0 12 3250 #define CCU43_IN1_CCU43_ST1 13 3251 #define CCU43_IN1_CCU43_ST2 14 3252 #define CCU43_IN1_CCU43_ST3 15 3253 #define CCU43_IN1_ERU1_PDOUT0 3 3254 #define CCU43_IN1_ERU1_PDOUT1 9 3255 #define CCU43_IN1_P2_14 1 3256 #define CCU43_IN1_POSIF1_OUT2 4 3257 #define CCU43_IN1_POSIF1_OUT5 5 3258 #define CCU43_IN1_SCU_ERU1_IOUT1 10 3259 #define CCU43_IN1_SCU_GSC43 8 3260 #define CCU43_IN1_U0C1_DX2INS 11 3261 #define CCU43_IN1_VADC0_G1BFL0 7 3262 #define CCU43_IN2_CCU43_ST0 12 3263 #define CCU43_IN2_CCU43_ST1 13 3264 #define CCU43_IN2_CCU43_ST2 14 3265 #define CCU43_IN2_CCU43_ST3 15 3266 #define CCU43_IN2_ERU1_PDOUT0 3 3267 #define CCU43_IN2_ERU1_PDOUT2 9 3268 #define CCU43_IN2_P2_14 1 3269 #define CCU43_IN2_POSIF1_OUT2 4 3270 #define CCU43_IN2_POSIF1_OUT5 5 3271 #define CCU43_IN2_SCU_ERU1_IOUT2 10 3272 #define CCU43_IN2_SCU_GSC43 8 3273 #define CCU43_IN2_U1C0_DX2INS 11 3274 #define CCU43_IN2_VADC0_G2BFL0 7 3275 #define CCU43_IN3_CCU43_ST0 12 3276 #define CCU43_IN3_CCU43_ST1 13 3277 #define CCU43_IN3_CCU43_ST2 14 3278 #define CCU43_IN3_CCU43_ST3 15 3279 #define CCU43_IN3_ERU1_PDOUT0 3 3280 #define CCU43_IN3_ERU1_PDOUT3 9 3281 #define CCU43_IN3_P2_14 1 3282 #define CCU43_IN3_POSIF1_OUT2 4 3283 #define CCU43_IN3_POSIF1_OUT5 5 3284 #define CCU43_IN3_SCU_ERU1_IOUT3 10 3285 #define CCU43_IN3_SCU_GSC43 8 3286 #define CCU43_IN3_U1C1_DX2INS 11 3287 #define CCU43_IN3_VADC0_G3ARBCNT 6 3288 #define CCU43_IN3_VADC0_G3BFL0 7 3289 #endif 3290 3291 3292 #if (UC_DEVICE == XMC4504) && (UC_PACKAGE == LQFP144) 3293 #define CCU40_IN0_CCU40_ST0 12 3294 #define CCU40_IN0_CCU40_ST1 13 3295 #define CCU40_IN0_CCU40_ST2 14 3296 #define CCU40_IN0_CCU40_ST3 15 3297 #define CCU40_IN0_ERU1_PDOUT0 9 3298 #define CCU40_IN0_ERU1_PDOUT1 3 3299 #define CCU40_IN0_P1_3 0 3300 #define CCU40_IN0_P2_1 2 3301 #define CCU40_IN0_P2_8 1 3302 #define CCU40_IN0_POSIF0_OUT0 4 3303 #define CCU40_IN0_POSIF0_OUT1 5 3304 #define CCU40_IN0_POSIF0_OUT3 6 3305 #define CCU40_IN0_SCU_ERU1_IOUT0 10 3306 #define CCU40_IN0_SCU_GSC40 8 3307 #define CCU40_IN0_U0C0_DX2INS 11 3308 #define CCU40_IN1_CCU40_ST0 12 3309 #define CCU40_IN1_CCU40_ST1 13 3310 #define CCU40_IN1_CCU40_ST2 14 3311 #define CCU40_IN1_CCU40_ST3 15 3312 #define CCU40_IN1_ERU1_PDOUT0 3 3313 #define CCU40_IN1_ERU1_PDOUT1 9 3314 #define CCU40_IN1_P1_2 0 3315 #define CCU40_IN1_P2_0 2 3316 #define CCU40_IN1_P2_8 1 3317 #define CCU40_IN1_POSIF0_OUT0 4 3318 #define CCU40_IN1_POSIF0_OUT1 5 3319 #define CCU40_IN1_POSIF0_OUT2 11 3320 #define CCU40_IN1_POSIF0_OUT3 6 3321 #define CCU40_IN1_POSIF0_OUT4 7 3322 #define CCU40_IN1_SCU_ERU1_IOUT1 10 3323 #define CCU40_IN1_SCU_GSC40 8 3324 #define CCU40_IN2_CCU40_ST0 12 3325 #define CCU40_IN2_CCU40_ST1 13 3326 #define CCU40_IN2_CCU40_ST2 14 3327 #define CCU40_IN2_CCU40_ST3 15 3328 #define CCU40_IN2_ERU1_PDOUT0 3 3329 #define CCU40_IN2_ERU1_PDOUT2 9 3330 #define CCU40_IN2_P1_1 0 3331 #define CCU40_IN2_P2_7 2 3332 #define CCU40_IN2_P2_8 1 3333 #define CCU40_IN2_POSIF0_OUT0 4 3334 #define CCU40_IN2_POSIF0_OUT2 5 3335 #define CCU40_IN2_POSIF0_OUT3 6 3336 #define CCU40_IN2_POSIF0_OUT4 7 3337 #define CCU40_IN2_SCU_ERU1_IOUT2 10 3338 #define CCU40_IN2_SCU_GSC40 8 3339 #define CCU40_IN2_U0C1_DX2INS 11 3340 #define CCU40_IN3_CCU40_ST0 12 3341 #define CCU40_IN3_CCU40_ST1 13 3342 #define CCU40_IN3_CCU40_ST2 14 3343 #define CCU40_IN3_CCU40_ST3 15 3344 #define CCU40_IN3_CCU80_IGBTO 7 3345 #define CCU40_IN3_ERU1_PDOUT0 3 3346 #define CCU40_IN3_ERU1_PDOUT3 9 3347 #define CCU40_IN3_P1_0 0 3348 #define CCU40_IN3_P2_6 2 3349 #define CCU40_IN3_P2_8 1 3350 #define CCU40_IN3_POSIF0_OUT3 4 3351 #define CCU40_IN3_POSIF0_OUT5 5 3352 #define CCU40_IN3_SCU_ERU1_IOUT3 10 3353 #define CCU40_IN3_SCU_GSC40 8 3354 #define CCU40_IN3_U1C0_DX2INS 11 3355 #define CCU40_IN3_VADC0_G0ARBCNT 6 3356 #define CCU41_IN0_CCU41_ST0 12 3357 #define CCU41_IN0_CCU41_ST1 13 3358 #define CCU41_IN0_CCU41_ST2 14 3359 #define CCU41_IN0_CCU41_ST3 15 3360 #define CCU41_IN0_ERU1_PDOUT0 9 3361 #define CCU41_IN0_ERU1_PDOUT1 3 3362 #define CCU41_IN0_P1_4 2 3363 #define CCU41_IN0_P2_5 0 3364 #define CCU41_IN0_P2_9 1 3365 #define CCU41_IN0_POSIF1_OUT0 4 3366 #define CCU41_IN0_POSIF1_OUT1 5 3367 #define CCU41_IN0_POSIF1_OUT3 6 3368 #define CCU41_IN0_SCU_ERU1_IOUT0 10 3369 #define CCU41_IN0_SCU_GSC41 8 3370 #define CCU41_IN0_VADC0_G0BFL0 11 3371 #define CCU41_IN1_CCU41_ST0 12 3372 #define CCU41_IN1_CCU41_ST1 13 3373 #define CCU41_IN1_CCU41_ST2 14 3374 #define CCU41_IN1_CCU41_ST3 15 3375 #define CCU41_IN1_ERU1_PDOUT0 3 3376 #define CCU41_IN1_ERU1_PDOUT1 9 3377 #define CCU41_IN1_P1_5 2 3378 #define CCU41_IN1_P2_4 0 3379 #define CCU41_IN1_P2_9 1 3380 #define CCU41_IN1_POSIF1_OUT0 4 3381 #define CCU41_IN1_POSIF1_OUT1 5 3382 #define CCU41_IN1_POSIF1_OUT2 11 3383 #define CCU41_IN1_POSIF1_OUT3 6 3384 #define CCU41_IN1_POSIF1_OUT4 7 3385 #define CCU41_IN1_SCU_ERU1_IOUT1 10 3386 #define CCU41_IN1_SCU_GSC41 8 3387 #define CCU41_IN2_CCU41_ST0 12 3388 #define CCU41_IN2_CCU41_ST1 13 3389 #define CCU41_IN2_CCU41_ST2 14 3390 #define CCU41_IN2_CCU41_ST3 15 3391 #define CCU41_IN2_ERU1_PDOUT0 3 3392 #define CCU41_IN2_ERU1_PDOUT2 9 3393 #define CCU41_IN2_P1_10 2 3394 #define CCU41_IN2_P2_3 0 3395 #define CCU41_IN2_P2_9 1 3396 #define CCU41_IN2_POSIF1_OUT0 4 3397 #define CCU41_IN2_POSIF1_OUT2 5 3398 #define CCU41_IN2_POSIF1_OUT3 6 3399 #define CCU41_IN2_POSIF1_OUT4 7 3400 #define CCU41_IN2_SCU_ERU1_IOUT2 10 3401 #define CCU41_IN2_SCU_GSC41 8 3402 #define CCU41_IN2_VADC0_G0BFL1 11 3403 #define CCU41_IN3_CCU41_ST0 12 3404 #define CCU41_IN3_CCU41_ST1 13 3405 #define CCU41_IN3_CCU41_ST2 14 3406 #define CCU41_IN3_CCU41_ST3 15 3407 #define CCU41_IN3_CCU81_IGBTO 7 3408 #define CCU41_IN3_ERU1_PDOUT0 3 3409 #define CCU41_IN3_ERU1_PDOUT3 9 3410 #define CCU41_IN3_P1_11 2 3411 #define CCU41_IN3_P2_2 0 3412 #define CCU41_IN3_P2_9 1 3413 #define CCU41_IN3_POSIF1_OUT3 4 3414 #define CCU41_IN3_POSIF1_OUT5 5 3415 #define CCU41_IN3_SCU_ERU1_IOUT3 10 3416 #define CCU41_IN3_SCU_GSC41 8 3417 #define CCU41_IN3_VADC0_G0BFL2 11 3418 #define CCU41_IN3_VADC0_G1ARBCNT 6 3419 #define CCU42_IN0_CCU42_ST0 12 3420 #define CCU42_IN0_CCU42_ST1 13 3421 #define CCU42_IN0_CCU42_ST2 14 3422 #define CCU42_IN0_CCU42_ST3 15 3423 #define CCU42_IN0_CCU80_IGBTO 7 3424 #define CCU42_IN0_ERU1_PDOUT0 9 3425 #define CCU42_IN0_ERU1_PDOUT1 3 3426 #define CCU42_IN0_P2_15 1 3427 #define CCU42_IN0_P3_15 2 3428 #define CCU42_IN0_P3_6 0 3429 #define CCU42_IN0_POSIF0_OUT2 4 3430 #define CCU42_IN0_POSIF0_OUT5 5 3431 #define CCU42_IN0_SCU_ERU1_IOUT0 10 3432 #define CCU42_IN0_SCU_GSC42 8 3433 #define CCU42_IN0_U0C0_DX2INS 11 3434 #define CCU42_IN1_CCU42_ST0 12 3435 #define CCU42_IN1_CCU42_ST1 13 3436 #define CCU42_IN1_CCU42_ST2 14 3437 #define CCU42_IN1_CCU42_ST3 15 3438 #define CCU42_IN1_ERU1_PDOUT0 3 3439 #define CCU42_IN1_ERU1_PDOUT1 9 3440 #define CCU42_IN1_P2_15 1 3441 #define CCU42_IN1_P3_14 2 3442 #define CCU42_IN1_P3_5 0 3443 #define CCU42_IN1_POSIF0_OUT2 4 3444 #define CCU42_IN1_POSIF0_OUT5 5 3445 #define CCU42_IN1_SCU_ERU1_IOUT1 10 3446 #define CCU42_IN1_SCU_GSC42 8 3447 #define CCU42_IN1_U0C1_DX2INS 11 3448 #define CCU42_IN2_CCU42_ST0 12 3449 #define CCU42_IN2_CCU42_ST1 13 3450 #define CCU42_IN2_CCU42_ST2 14 3451 #define CCU42_IN2_CCU42_ST3 15 3452 #define CCU42_IN2_ERU1_PDOUT0 3 3453 #define CCU42_IN2_ERU1_PDOUT2 9 3454 #define CCU42_IN2_P0_15 2 3455 #define CCU42_IN2_P2_15 1 3456 #define CCU42_IN2_P3_4 0 3457 #define CCU42_IN2_POSIF0_OUT2 4 3458 #define CCU42_IN2_POSIF0_OUT5 5 3459 #define CCU42_IN2_SCU_ERU1_IOUT2 10 3460 #define CCU42_IN2_SCU_GSC42 8 3461 #define CCU42_IN2_U1C0_DX2INS 11 3462 #define CCU42_IN3_CCU42_ST0 12 3463 #define CCU42_IN3_CCU42_ST1 13 3464 #define CCU42_IN3_CCU42_ST2 14 3465 #define CCU42_IN3_CCU42_ST3 15 3466 #define CCU42_IN3_ERU1_PDOUT0 3 3467 #define CCU42_IN3_ERU1_PDOUT3 9 3468 #define CCU42_IN3_P0_14 2 3469 #define CCU42_IN3_P2_15 1 3470 #define CCU42_IN3_P3_3 0 3471 #define CCU42_IN3_POSIF0_OUT2 4 3472 #define CCU42_IN3_POSIF0_OUT5 5 3473 #define CCU42_IN3_SCU_ERU1_IOUT3 10 3474 #define CCU42_IN3_SCU_GSC42 8 3475 #define CCU42_IN3_U1C1_DX2INS 11 3476 #define CCU42_IN3_VADC0_G2ARBCNT 6 3477 #define CCU43_IN0_CCU43_ST0 12 3478 #define CCU43_IN0_CCU43_ST1 13 3479 #define CCU43_IN0_CCU43_ST2 14 3480 #define CCU43_IN0_CCU43_ST3 15 3481 #define CCU43_IN0_CCU81_IGBTO 6 3482 #define CCU43_IN0_ERU1_PDOUT0 9 3483 #define CCU43_IN0_ERU1_PDOUT1 3 3484 #define CCU43_IN0_P2_14 1 3485 #define CCU43_IN0_P4_6 0 3486 #define CCU43_IN0_P4_7 2 3487 #define CCU43_IN0_POSIF1_OUT2 4 3488 #define CCU43_IN0_POSIF1_OUT5 5 3489 #define CCU43_IN0_SCU_ERU1_IOUT0 10 3490 #define CCU43_IN0_SCU_GSC43 8 3491 #define CCU43_IN0_U0C0_DX2INS 11 3492 #define CCU43_IN0_VADC0_G0BFL0 7 3493 #define CCU43_IN1_CCU43_ST0 12 3494 #define CCU43_IN1_CCU43_ST1 13 3495 #define CCU43_IN1_CCU43_ST2 14 3496 #define CCU43_IN1_CCU43_ST3 15 3497 #define CCU43_IN1_ERU1_PDOUT0 3 3498 #define CCU43_IN1_ERU1_PDOUT1 9 3499 #define CCU43_IN1_P2_14 1 3500 #define CCU43_IN1_P4_2 2 3501 #define CCU43_IN1_P4_5 0 3502 #define CCU43_IN1_POSIF1_OUT2 4 3503 #define CCU43_IN1_POSIF1_OUT5 5 3504 #define CCU43_IN1_SCU_ERU1_IOUT1 10 3505 #define CCU43_IN1_SCU_GSC43 8 3506 #define CCU43_IN1_U0C1_DX2INS 11 3507 #define CCU43_IN1_VADC0_G1BFL0 7 3508 #define CCU43_IN2_CCU43_ST0 12 3509 #define CCU43_IN2_CCU43_ST1 13 3510 #define CCU43_IN2_CCU43_ST2 14 3511 #define CCU43_IN2_CCU43_ST3 15 3512 #define CCU43_IN2_ERU1_PDOUT0 3 3513 #define CCU43_IN2_ERU1_PDOUT2 9 3514 #define CCU43_IN2_P2_13 2 3515 #define CCU43_IN2_P2_14 1 3516 #define CCU43_IN2_P4_4 0 3517 #define CCU43_IN2_POSIF1_OUT2 4 3518 #define CCU43_IN2_POSIF1_OUT5 5 3519 #define CCU43_IN2_SCU_ERU1_IOUT2 10 3520 #define CCU43_IN2_SCU_GSC43 8 3521 #define CCU43_IN2_U1C0_DX2INS 11 3522 #define CCU43_IN2_VADC0_G2BFL0 7 3523 #define CCU43_IN3_CCU43_ST0 12 3524 #define CCU43_IN3_CCU43_ST1 13 3525 #define CCU43_IN3_CCU43_ST2 14 3526 #define CCU43_IN3_CCU43_ST3 15 3527 #define CCU43_IN3_ERU1_PDOUT0 3 3528 #define CCU43_IN3_ERU1_PDOUT3 9 3529 #define CCU43_IN3_P2_12 2 3530 #define CCU43_IN3_P2_14 1 3531 #define CCU43_IN3_P4_3 0 3532 #define CCU43_IN3_POSIF1_OUT2 4 3533 #define CCU43_IN3_POSIF1_OUT5 5 3534 #define CCU43_IN3_SCU_ERU1_IOUT3 10 3535 #define CCU43_IN3_SCU_GSC43 8 3536 #define CCU43_IN3_U1C1_DX2INS 11 3537 #define CCU43_IN3_VADC0_G3ARBCNT 6 3538 #define CCU43_IN3_VADC0_G3BFL0 7 3539 #endif 3540 3541 3542 #if (UC_DEVICE == XMC4700) && (UC_PACKAGE == BGA196) 3543 #define CCU40_IN0_CAN0_SR7 7 3544 #define CCU40_IN0_CCU40_ST0 12 3545 #define CCU40_IN0_CCU40_ST1 13 3546 #define CCU40_IN0_CCU40_ST2 14 3547 #define CCU40_IN0_CCU40_ST3 15 3548 #define CCU40_IN0_ERU1_PDOUT0 9 3549 #define CCU40_IN0_ERU1_PDOUT1 3 3550 #define CCU40_IN0_P1_3 0 3551 #define CCU40_IN0_P2_1 2 3552 #define CCU40_IN0_P2_8 1 3553 #define CCU40_IN0_POSIF0_OUT0 4 3554 #define CCU40_IN0_POSIF0_OUT1 5 3555 #define CCU40_IN0_POSIF0_OUT3 6 3556 #define CCU40_IN0_SCU_ERU1_IOUT0 10 3557 #define CCU40_IN0_SCU_GSC40 8 3558 #define CCU40_IN0_U0C0_DX2INS 11 3559 #define CCU40_IN1_CCU40_ST0 12 3560 #define CCU40_IN1_CCU40_ST1 13 3561 #define CCU40_IN1_CCU40_ST2 14 3562 #define CCU40_IN1_CCU40_ST3 15 3563 #define CCU40_IN1_ERU1_PDOUT0 3 3564 #define CCU40_IN1_ERU1_PDOUT1 9 3565 #define CCU40_IN1_P1_2 0 3566 #define CCU40_IN1_P2_0 2 3567 #define CCU40_IN1_P2_8 1 3568 #define CCU40_IN1_POSIF0_OUT0 4 3569 #define CCU40_IN1_POSIF0_OUT1 5 3570 #define CCU40_IN1_POSIF0_OUT2 11 3571 #define CCU40_IN1_POSIF0_OUT3 6 3572 #define CCU40_IN1_POSIF0_OUT4 7 3573 #define CCU40_IN1_SCU_ERU1_IOUT1 10 3574 #define CCU40_IN1_SCU_GSC40 8 3575 #define CCU40_IN2_CCU40_ST0 12 3576 #define CCU40_IN2_CCU40_ST1 13 3577 #define CCU40_IN2_CCU40_ST2 14 3578 #define CCU40_IN2_CCU40_ST3 15 3579 #define CCU40_IN2_ERU1_PDOUT0 3 3580 #define CCU40_IN2_ERU1_PDOUT2 9 3581 #define CCU40_IN2_P1_1 0 3582 #define CCU40_IN2_P2_7 2 3583 #define CCU40_IN2_P2_8 1 3584 #define CCU40_IN2_POSIF0_OUT0 4 3585 #define CCU40_IN2_POSIF0_OUT2 5 3586 #define CCU40_IN2_POSIF0_OUT3 6 3587 #define CCU40_IN2_POSIF0_OUT4 7 3588 #define CCU40_IN2_SCU_ERU1_IOUT2 10 3589 #define CCU40_IN2_SCU_GSC40 8 3590 #define CCU40_IN2_U0C1_DX2INS 11 3591 #define CCU40_IN3_CCU40_ST0 12 3592 #define CCU40_IN3_CCU40_ST1 13 3593 #define CCU40_IN3_CCU40_ST2 14 3594 #define CCU40_IN3_CCU40_ST3 15 3595 #define CCU40_IN3_CCU80_IGBTO 7 3596 #define CCU40_IN3_ERU1_PDOUT0 3 3597 #define CCU40_IN3_ERU1_PDOUT3 9 3598 #define CCU40_IN3_P1_0 0 3599 #define CCU40_IN3_P2_6 2 3600 #define CCU40_IN3_P2_8 1 3601 #define CCU40_IN3_POSIF0_OUT3 4 3602 #define CCU40_IN3_POSIF0_OUT5 5 3603 #define CCU40_IN3_SCU_ERU1_IOUT3 10 3604 #define CCU40_IN3_SCU_GSC40 8 3605 #define CCU40_IN3_U1C0_DX2INS 11 3606 #define CCU40_IN3_VADC0_G0ARBCNT 6 3607 #define CCU41_IN0_CAN0_SR7 7 3608 #define CCU41_IN0_CCU41_ST0 12 3609 #define CCU41_IN0_CCU41_ST1 13 3610 #define CCU41_IN0_CCU41_ST2 14 3611 #define CCU41_IN0_CCU41_ST3 15 3612 #define CCU41_IN0_ERU1_PDOUT0 9 3613 #define CCU41_IN0_ERU1_PDOUT1 3 3614 #define CCU41_IN0_P1_4 2 3615 #define CCU41_IN0_P2_5 0 3616 #define CCU41_IN0_P2_9 1 3617 #define CCU41_IN0_POSIF1_OUT0 4 3618 #define CCU41_IN0_POSIF1_OUT1 5 3619 #define CCU41_IN0_POSIF1_OUT3 6 3620 #define CCU41_IN0_SCU_ERU1_IOUT0 10 3621 #define CCU41_IN0_SCU_GSC41 8 3622 #define CCU41_IN0_VADC0_G0BFL0 11 3623 #define CCU41_IN1_CCU41_ST0 12 3624 #define CCU41_IN1_CCU41_ST1 13 3625 #define CCU41_IN1_CCU41_ST2 14 3626 #define CCU41_IN1_CCU41_ST3 15 3627 #define CCU41_IN1_ERU1_PDOUT0 3 3628 #define CCU41_IN1_ERU1_PDOUT1 9 3629 #define CCU41_IN1_P1_5 2 3630 #define CCU41_IN1_P2_4 0 3631 #define CCU41_IN1_P2_9 1 3632 #define CCU41_IN1_POSIF1_OUT0 4 3633 #define CCU41_IN1_POSIF1_OUT1 5 3634 #define CCU41_IN1_POSIF1_OUT2 11 3635 #define CCU41_IN1_POSIF1_OUT3 6 3636 #define CCU41_IN1_POSIF1_OUT4 7 3637 #define CCU41_IN1_SCU_ERU1_IOUT1 10 3638 #define CCU41_IN1_SCU_GSC41 8 3639 #define CCU41_IN2_CCU41_ST0 12 3640 #define CCU41_IN2_CCU41_ST1 13 3641 #define CCU41_IN2_CCU41_ST2 14 3642 #define CCU41_IN2_CCU41_ST3 15 3643 #define CCU41_IN2_ERU1_PDOUT0 3 3644 #define CCU41_IN2_ERU1_PDOUT2 9 3645 #define CCU41_IN2_P1_10 2 3646 #define CCU41_IN2_P2_3 0 3647 #define CCU41_IN2_P2_9 1 3648 #define CCU41_IN2_POSIF1_OUT0 4 3649 #define CCU41_IN2_POSIF1_OUT2 5 3650 #define CCU41_IN2_POSIF1_OUT3 6 3651 #define CCU41_IN2_POSIF1_OUT4 7 3652 #define CCU41_IN2_SCU_ERU1_IOUT2 10 3653 #define CCU41_IN2_SCU_GSC41 8 3654 #define CCU41_IN2_VADC0_G0BFL1 11 3655 #define CCU41_IN3_CCU41_ST0 12 3656 #define CCU41_IN3_CCU41_ST1 13 3657 #define CCU41_IN3_CCU41_ST2 14 3658 #define CCU41_IN3_CCU41_ST3 15 3659 #define CCU41_IN3_CCU81_IGBTO 7 3660 #define CCU41_IN3_ERU1_PDOUT0 3 3661 #define CCU41_IN3_ERU1_PDOUT3 9 3662 #define CCU41_IN3_P1_11 2 3663 #define CCU41_IN3_P2_2 0 3664 #define CCU41_IN3_P2_9 1 3665 #define CCU41_IN3_POSIF1_OUT3 4 3666 #define CCU41_IN3_POSIF1_OUT5 5 3667 #define CCU41_IN3_SCU_ERU1_IOUT3 10 3668 #define CCU41_IN3_SCU_GSC41 8 3669 #define CCU41_IN3_VADC0_G0BFL2 11 3670 #define CCU41_IN3_VADC0_G1ARBCNT 6 3671 #define CCU42_IN0_CCU42_ST0 12 3672 #define CCU42_IN0_CCU42_ST1 13 3673 #define CCU42_IN0_CCU42_ST2 14 3674 #define CCU42_IN0_CCU42_ST3 15 3675 #define CCU42_IN0_CCU80_IGBTO 7 3676 #define CCU42_IN0_ERU1_PDOUT0 9 3677 #define CCU42_IN0_ERU1_PDOUT1 3 3678 #define CCU42_IN0_P2_15 1 3679 #define CCU42_IN0_P3_15 2 3680 #define CCU42_IN0_P3_6 0 3681 #define CCU42_IN0_POSIF0_OUT2 4 3682 #define CCU42_IN0_POSIF0_OUT5 5 3683 #define CCU42_IN0_SCU_ERU1_IOUT0 10 3684 #define CCU42_IN0_SCU_GSC42 8 3685 #define CCU42_IN0_U0C0_DX2INS 11 3686 #define CCU42_IN1_CCU42_ST0 12 3687 #define CCU42_IN1_CCU42_ST1 13 3688 #define CCU42_IN1_CCU42_ST2 14 3689 #define CCU42_IN1_CCU42_ST3 15 3690 #define CCU42_IN1_ERU1_PDOUT0 3 3691 #define CCU42_IN1_ERU1_PDOUT1 9 3692 #define CCU42_IN1_P2_15 1 3693 #define CCU42_IN1_P3_14 2 3694 #define CCU42_IN1_P3_5 0 3695 #define CCU42_IN1_POSIF0_OUT2 4 3696 #define CCU42_IN1_POSIF0_OUT5 5 3697 #define CCU42_IN1_SCU_ERU1_IOUT1 10 3698 #define CCU42_IN1_SCU_GSC42 8 3699 #define CCU42_IN1_U0C1_DX2INS 11 3700 #define CCU42_IN2_CAN0_SR7 6 3701 #define CCU42_IN2_CCU42_ST0 12 3702 #define CCU42_IN2_CCU42_ST1 13 3703 #define CCU42_IN2_CCU42_ST2 14 3704 #define CCU42_IN2_CCU42_ST3 15 3705 #define CCU42_IN2_ERU1_PDOUT0 3 3706 #define CCU42_IN2_ERU1_PDOUT2 9 3707 #define CCU42_IN2_P0_15 2 3708 #define CCU42_IN2_P2_15 1 3709 #define CCU42_IN2_P3_4 0 3710 #define CCU42_IN2_POSIF0_OUT2 4 3711 #define CCU42_IN2_POSIF0_OUT5 5 3712 #define CCU42_IN2_SCU_ERU1_IOUT2 10 3713 #define CCU42_IN2_SCU_GSC42 8 3714 #define CCU42_IN2_U1C0_DX2INS 11 3715 #define CCU42_IN3_CCU42_ST0 12 3716 #define CCU42_IN3_CCU42_ST1 13 3717 #define CCU42_IN3_CCU42_ST2 14 3718 #define CCU42_IN3_CCU42_ST3 15 3719 #define CCU42_IN3_ERU1_PDOUT0 3 3720 #define CCU42_IN3_ERU1_PDOUT3 9 3721 #define CCU42_IN3_P0_14 2 3722 #define CCU42_IN3_P2_15 1 3723 #define CCU42_IN3_P3_3 0 3724 #define CCU42_IN3_POSIF0_OUT2 4 3725 #define CCU42_IN3_POSIF0_OUT5 5 3726 #define CCU42_IN3_SCU_ERU1_IOUT3 10 3727 #define CCU42_IN3_SCU_GSC42 8 3728 #define CCU42_IN3_U1C1_DX2INS 11 3729 #define CCU42_IN3_VADC0_G2ARBCNT 6 3730 #define CCU43_IN0_CCU43_ST0 12 3731 #define CCU43_IN0_CCU43_ST1 13 3732 #define CCU43_IN0_CCU43_ST2 14 3733 #define CCU43_IN0_CCU43_ST3 15 3734 #define CCU43_IN0_CCU81_IGBTO 6 3735 #define CCU43_IN0_ERU1_PDOUT0 9 3736 #define CCU43_IN0_ERU1_PDOUT1 3 3737 #define CCU43_IN0_P2_14 1 3738 #define CCU43_IN0_P4_6 0 3739 #define CCU43_IN0_P4_7 2 3740 #define CCU43_IN0_POSIF1_OUT2 4 3741 #define CCU43_IN0_POSIF1_OUT5 5 3742 #define CCU43_IN0_SCU_ERU1_IOUT0 10 3743 #define CCU43_IN0_SCU_GSC43 8 3744 #define CCU43_IN0_U0C0_DX2INS 11 3745 #define CCU43_IN0_VADC0_G0BFL0 7 3746 #define CCU43_IN1_CAN0_SR7 6 3747 #define CCU43_IN1_CCU43_ST0 12 3748 #define CCU43_IN1_CCU43_ST1 13 3749 #define CCU43_IN1_CCU43_ST2 14 3750 #define CCU43_IN1_CCU43_ST3 15 3751 #define CCU43_IN1_ERU1_PDOUT0 3 3752 #define CCU43_IN1_ERU1_PDOUT1 9 3753 #define CCU43_IN1_P2_14 1 3754 #define CCU43_IN1_P4_2 2 3755 #define CCU43_IN1_P4_5 0 3756 #define CCU43_IN1_POSIF1_OUT2 4 3757 #define CCU43_IN1_POSIF1_OUT5 5 3758 #define CCU43_IN1_SCU_ERU1_IOUT1 10 3759 #define CCU43_IN1_SCU_GSC43 8 3760 #define CCU43_IN1_U0C1_DX2INS 11 3761 #define CCU43_IN1_VADC0_G1BFL0 7 3762 #define CCU43_IN2_CCU43_ST0 12 3763 #define CCU43_IN2_CCU43_ST1 13 3764 #define CCU43_IN2_CCU43_ST2 14 3765 #define CCU43_IN2_CCU43_ST3 15 3766 #define CCU43_IN2_ERU1_PDOUT0 3 3767 #define CCU43_IN2_ERU1_PDOUT2 9 3768 #define CCU43_IN2_P2_13 2 3769 #define CCU43_IN2_P2_14 1 3770 #define CCU43_IN2_P4_4 0 3771 #define CCU43_IN2_POSIF1_OUT2 4 3772 #define CCU43_IN2_POSIF1_OUT5 5 3773 #define CCU43_IN2_SCU_ERU1_IOUT2 10 3774 #define CCU43_IN2_SCU_GSC43 8 3775 #define CCU43_IN2_U1C0_DX2INS 11 3776 #define CCU43_IN2_VADC0_G2BFL0 7 3777 #define CCU43_IN3_CCU43_ST0 12 3778 #define CCU43_IN3_CCU43_ST1 13 3779 #define CCU43_IN3_CCU43_ST2 14 3780 #define CCU43_IN3_CCU43_ST3 15 3781 #define CCU43_IN3_ERU1_PDOUT0 3 3782 #define CCU43_IN3_ERU1_PDOUT3 9 3783 #define CCU43_IN3_P2_12 2 3784 #define CCU43_IN3_P2_14 1 3785 #define CCU43_IN3_P4_3 0 3786 #define CCU43_IN3_POSIF1_OUT2 4 3787 #define CCU43_IN3_POSIF1_OUT5 5 3788 #define CCU43_IN3_SCU_ERU1_IOUT3 10 3789 #define CCU43_IN3_SCU_GSC43 8 3790 #define CCU43_IN3_U1C1_DX2INS 11 3791 #define CCU43_IN3_VADC0_G3ARBCNT 6 3792 #define CCU43_IN3_VADC0_G3BFL0 7 3793 #endif 3794 3795 3796 #if (UC_DEVICE == XMC4700) && (UC_PACKAGE == LQFP100) 3797 #define CCU40_IN0_CAN0_SR7 7 3798 #define CCU40_IN0_CCU40_ST0 12 3799 #define CCU40_IN0_CCU40_ST1 13 3800 #define CCU40_IN0_CCU40_ST2 14 3801 #define CCU40_IN0_CCU40_ST3 15 3802 #define CCU40_IN0_ERU1_PDOUT0 9 3803 #define CCU40_IN0_ERU1_PDOUT1 3 3804 #define CCU40_IN0_P1_3 0 3805 #define CCU40_IN0_P2_1 2 3806 #define CCU40_IN0_P2_8 1 3807 #define CCU40_IN0_POSIF0_OUT0 4 3808 #define CCU40_IN0_POSIF0_OUT1 5 3809 #define CCU40_IN0_POSIF0_OUT3 6 3810 #define CCU40_IN0_SCU_ERU1_IOUT0 10 3811 #define CCU40_IN0_SCU_GSC40 8 3812 #define CCU40_IN0_U0C0_DX2INS 11 3813 #define CCU40_IN1_CCU40_ST0 12 3814 #define CCU40_IN1_CCU40_ST1 13 3815 #define CCU40_IN1_CCU40_ST2 14 3816 #define CCU40_IN1_CCU40_ST3 15 3817 #define CCU40_IN1_ERU1_PDOUT0 3 3818 #define CCU40_IN1_ERU1_PDOUT1 9 3819 #define CCU40_IN1_P1_2 0 3820 #define CCU40_IN1_P2_0 2 3821 #define CCU40_IN1_P2_8 1 3822 #define CCU40_IN1_POSIF0_OUT0 4 3823 #define CCU40_IN1_POSIF0_OUT1 5 3824 #define CCU40_IN1_POSIF0_OUT2 11 3825 #define CCU40_IN1_POSIF0_OUT3 6 3826 #define CCU40_IN1_POSIF0_OUT4 7 3827 #define CCU40_IN1_SCU_ERU1_IOUT1 10 3828 #define CCU40_IN1_SCU_GSC40 8 3829 #define CCU40_IN2_CCU40_ST0 12 3830 #define CCU40_IN2_CCU40_ST1 13 3831 #define CCU40_IN2_CCU40_ST2 14 3832 #define CCU40_IN2_CCU40_ST3 15 3833 #define CCU40_IN2_ERU1_PDOUT0 3 3834 #define CCU40_IN2_ERU1_PDOUT2 9 3835 #define CCU40_IN2_P1_1 0 3836 #define CCU40_IN2_P2_7 2 3837 #define CCU40_IN2_P2_8 1 3838 #define CCU40_IN2_POSIF0_OUT0 4 3839 #define CCU40_IN2_POSIF0_OUT2 5 3840 #define CCU40_IN2_POSIF0_OUT3 6 3841 #define CCU40_IN2_POSIF0_OUT4 7 3842 #define CCU40_IN2_SCU_ERU1_IOUT2 10 3843 #define CCU40_IN2_SCU_GSC40 8 3844 #define CCU40_IN2_U0C1_DX2INS 11 3845 #define CCU40_IN3_CCU40_ST0 12 3846 #define CCU40_IN3_CCU40_ST1 13 3847 #define CCU40_IN3_CCU40_ST2 14 3848 #define CCU40_IN3_CCU40_ST3 15 3849 #define CCU40_IN3_CCU80_IGBTO 7 3850 #define CCU40_IN3_ERU1_PDOUT0 3 3851 #define CCU40_IN3_ERU1_PDOUT3 9 3852 #define CCU40_IN3_P1_0 0 3853 #define CCU40_IN3_P2_6 2 3854 #define CCU40_IN3_P2_8 1 3855 #define CCU40_IN3_POSIF0_OUT3 4 3856 #define CCU40_IN3_POSIF0_OUT5 5 3857 #define CCU40_IN3_SCU_ERU1_IOUT3 10 3858 #define CCU40_IN3_SCU_GSC40 8 3859 #define CCU40_IN3_U1C0_DX2INS 11 3860 #define CCU40_IN3_VADC0_G0ARBCNT 6 3861 #define CCU41_IN0_CAN0_SR7 7 3862 #define CCU41_IN0_CCU41_ST0 12 3863 #define CCU41_IN0_CCU41_ST1 13 3864 #define CCU41_IN0_CCU41_ST2 14 3865 #define CCU41_IN0_CCU41_ST3 15 3866 #define CCU41_IN0_ERU1_PDOUT0 9 3867 #define CCU41_IN0_ERU1_PDOUT1 3 3868 #define CCU41_IN0_P1_4 2 3869 #define CCU41_IN0_P2_5 0 3870 #define CCU41_IN0_P2_9 1 3871 #define CCU41_IN0_POSIF1_OUT0 4 3872 #define CCU41_IN0_POSIF1_OUT1 5 3873 #define CCU41_IN0_POSIF1_OUT3 6 3874 #define CCU41_IN0_SCU_ERU1_IOUT0 10 3875 #define CCU41_IN0_SCU_GSC41 8 3876 #define CCU41_IN0_VADC0_G0BFL0 11 3877 #define CCU41_IN1_CCU41_ST0 12 3878 #define CCU41_IN1_CCU41_ST1 13 3879 #define CCU41_IN1_CCU41_ST2 14 3880 #define CCU41_IN1_CCU41_ST3 15 3881 #define CCU41_IN1_ERU1_PDOUT0 3 3882 #define CCU41_IN1_ERU1_PDOUT1 9 3883 #define CCU41_IN1_P1_5 2 3884 #define CCU41_IN1_P2_4 0 3885 #define CCU41_IN1_P2_9 1 3886 #define CCU41_IN1_POSIF1_OUT0 4 3887 #define CCU41_IN1_POSIF1_OUT1 5 3888 #define CCU41_IN1_POSIF1_OUT2 11 3889 #define CCU41_IN1_POSIF1_OUT3 6 3890 #define CCU41_IN1_POSIF1_OUT4 7 3891 #define CCU41_IN1_SCU_ERU1_IOUT1 10 3892 #define CCU41_IN1_SCU_GSC41 8 3893 #define CCU41_IN2_CCU41_ST0 12 3894 #define CCU41_IN2_CCU41_ST1 13 3895 #define CCU41_IN2_CCU41_ST2 14 3896 #define CCU41_IN2_CCU41_ST3 15 3897 #define CCU41_IN2_ERU1_PDOUT0 3 3898 #define CCU41_IN2_ERU1_PDOUT2 9 3899 #define CCU41_IN2_P1_10 2 3900 #define CCU41_IN2_P2_3 0 3901 #define CCU41_IN2_P2_9 1 3902 #define CCU41_IN2_POSIF1_OUT0 4 3903 #define CCU41_IN2_POSIF1_OUT2 5 3904 #define CCU41_IN2_POSIF1_OUT3 6 3905 #define CCU41_IN2_POSIF1_OUT4 7 3906 #define CCU41_IN2_SCU_ERU1_IOUT2 10 3907 #define CCU41_IN2_SCU_GSC41 8 3908 #define CCU41_IN2_VADC0_G0BFL1 11 3909 #define CCU41_IN3_CCU41_ST0 12 3910 #define CCU41_IN3_CCU41_ST1 13 3911 #define CCU41_IN3_CCU41_ST2 14 3912 #define CCU41_IN3_CCU41_ST3 15 3913 #define CCU41_IN3_CCU81_IGBTO 7 3914 #define CCU41_IN3_ERU1_PDOUT0 3 3915 #define CCU41_IN3_ERU1_PDOUT3 9 3916 #define CCU41_IN3_P1_11 2 3917 #define CCU41_IN3_P2_2 0 3918 #define CCU41_IN3_P2_9 1 3919 #define CCU41_IN3_POSIF1_OUT3 4 3920 #define CCU41_IN3_POSIF1_OUT5 5 3921 #define CCU41_IN3_SCU_ERU1_IOUT3 10 3922 #define CCU41_IN3_SCU_GSC41 8 3923 #define CCU41_IN3_VADC0_G0BFL2 11 3924 #define CCU41_IN3_VADC0_G1ARBCNT 6 3925 #define CCU42_IN0_CCU42_ST0 12 3926 #define CCU42_IN0_CCU42_ST1 13 3927 #define CCU42_IN0_CCU42_ST2 14 3928 #define CCU42_IN0_CCU42_ST3 15 3929 #define CCU42_IN0_CCU80_IGBTO 7 3930 #define CCU42_IN0_ERU1_PDOUT0 9 3931 #define CCU42_IN0_ERU1_PDOUT1 3 3932 #define CCU42_IN0_P2_15 1 3933 #define CCU42_IN0_P3_6 0 3934 #define CCU42_IN0_POSIF0_OUT2 4 3935 #define CCU42_IN0_POSIF0_OUT5 5 3936 #define CCU42_IN0_SCU_ERU1_IOUT0 10 3937 #define CCU42_IN0_SCU_GSC42 8 3938 #define CCU42_IN0_U0C0_DX2INS 11 3939 #define CCU42_IN1_CCU42_ST0 12 3940 #define CCU42_IN1_CCU42_ST1 13 3941 #define CCU42_IN1_CCU42_ST2 14 3942 #define CCU42_IN1_CCU42_ST3 15 3943 #define CCU42_IN1_ERU1_PDOUT0 3 3944 #define CCU42_IN1_ERU1_PDOUT1 9 3945 #define CCU42_IN1_P2_15 1 3946 #define CCU42_IN1_P3_5 0 3947 #define CCU42_IN1_POSIF0_OUT2 4 3948 #define CCU42_IN1_POSIF0_OUT5 5 3949 #define CCU42_IN1_SCU_ERU1_IOUT1 10 3950 #define CCU42_IN1_SCU_GSC42 8 3951 #define CCU42_IN1_U0C1_DX2INS 11 3952 #define CCU42_IN2_CAN0_SR7 6 3953 #define CCU42_IN2_CCU42_ST0 12 3954 #define CCU42_IN2_CCU42_ST1 13 3955 #define CCU42_IN2_CCU42_ST2 14 3956 #define CCU42_IN2_CCU42_ST3 15 3957 #define CCU42_IN2_ERU1_PDOUT0 3 3958 #define CCU42_IN2_ERU1_PDOUT2 9 3959 #define CCU42_IN2_P2_15 1 3960 #define CCU42_IN2_P3_4 0 3961 #define CCU42_IN2_POSIF0_OUT2 4 3962 #define CCU42_IN2_POSIF0_OUT5 5 3963 #define CCU42_IN2_SCU_ERU1_IOUT2 10 3964 #define CCU42_IN2_SCU_GSC42 8 3965 #define CCU42_IN2_U1C0_DX2INS 11 3966 #define CCU42_IN3_CCU42_ST0 12 3967 #define CCU42_IN3_CCU42_ST1 13 3968 #define CCU42_IN3_CCU42_ST2 14 3969 #define CCU42_IN3_CCU42_ST3 15 3970 #define CCU42_IN3_ERU1_PDOUT0 3 3971 #define CCU42_IN3_ERU1_PDOUT3 9 3972 #define CCU42_IN3_P2_15 1 3973 #define CCU42_IN3_P3_3 0 3974 #define CCU42_IN3_POSIF0_OUT2 4 3975 #define CCU42_IN3_POSIF0_OUT5 5 3976 #define CCU42_IN3_SCU_ERU1_IOUT3 10 3977 #define CCU42_IN3_SCU_GSC42 8 3978 #define CCU42_IN3_U1C1_DX2INS 11 3979 #define CCU42_IN3_VADC0_G2ARBCNT 6 3980 #define CCU43_IN0_CCU43_ST0 12 3981 #define CCU43_IN0_CCU43_ST1 13 3982 #define CCU43_IN0_CCU43_ST2 14 3983 #define CCU43_IN0_CCU43_ST3 15 3984 #define CCU43_IN0_CCU81_IGBTO 6 3985 #define CCU43_IN0_ERU1_PDOUT0 9 3986 #define CCU43_IN0_ERU1_PDOUT1 3 3987 #define CCU43_IN0_P2_14 1 3988 #define CCU43_IN0_POSIF1_OUT2 4 3989 #define CCU43_IN0_POSIF1_OUT5 5 3990 #define CCU43_IN0_SCU_ERU1_IOUT0 10 3991 #define CCU43_IN0_SCU_GSC43 8 3992 #define CCU43_IN0_U0C0_DX2INS 11 3993 #define CCU43_IN0_VADC0_G0BFL0 7 3994 #define CCU43_IN1_CAN0_SR7 6 3995 #define CCU43_IN1_CCU43_ST0 12 3996 #define CCU43_IN1_CCU43_ST1 13 3997 #define CCU43_IN1_CCU43_ST2 14 3998 #define CCU43_IN1_CCU43_ST3 15 3999 #define CCU43_IN1_ERU1_PDOUT0 3 4000 #define CCU43_IN1_ERU1_PDOUT1 9 4001 #define CCU43_IN1_P2_14 1 4002 #define CCU43_IN1_POSIF1_OUT2 4 4003 #define CCU43_IN1_POSIF1_OUT5 5 4004 #define CCU43_IN1_SCU_ERU1_IOUT1 10 4005 #define CCU43_IN1_SCU_GSC43 8 4006 #define CCU43_IN1_U0C1_DX2INS 11 4007 #define CCU43_IN1_VADC0_G1BFL0 7 4008 #define CCU43_IN2_CCU43_ST0 12 4009 #define CCU43_IN2_CCU43_ST1 13 4010 #define CCU43_IN2_CCU43_ST2 14 4011 #define CCU43_IN2_CCU43_ST3 15 4012 #define CCU43_IN2_ERU1_PDOUT0 3 4013 #define CCU43_IN2_ERU1_PDOUT2 9 4014 #define CCU43_IN2_P2_14 1 4015 #define CCU43_IN2_POSIF1_OUT2 4 4016 #define CCU43_IN2_POSIF1_OUT5 5 4017 #define CCU43_IN2_SCU_ERU1_IOUT2 10 4018 #define CCU43_IN2_SCU_GSC43 8 4019 #define CCU43_IN2_U1C0_DX2INS 11 4020 #define CCU43_IN2_VADC0_G2BFL0 7 4021 #define CCU43_IN3_CCU43_ST0 12 4022 #define CCU43_IN3_CCU43_ST1 13 4023 #define CCU43_IN3_CCU43_ST2 14 4024 #define CCU43_IN3_CCU43_ST3 15 4025 #define CCU43_IN3_ERU1_PDOUT0 3 4026 #define CCU43_IN3_ERU1_PDOUT3 9 4027 #define CCU43_IN3_P2_14 1 4028 #define CCU43_IN3_POSIF1_OUT2 4 4029 #define CCU43_IN3_POSIF1_OUT5 5 4030 #define CCU43_IN3_SCU_ERU1_IOUT3 10 4031 #define CCU43_IN3_SCU_GSC43 8 4032 #define CCU43_IN3_U1C1_DX2INS 11 4033 #define CCU43_IN3_VADC0_G3ARBCNT 6 4034 #define CCU43_IN3_VADC0_G3BFL0 7 4035 #endif 4036 4037 4038 #if (UC_DEVICE == XMC4700) && (UC_PACKAGE == LQFP144) 4039 #define CCU40_IN0_CAN0_SR7 7 4040 #define CCU40_IN0_CCU40_ST0 12 4041 #define CCU40_IN0_CCU40_ST1 13 4042 #define CCU40_IN0_CCU40_ST2 14 4043 #define CCU40_IN0_CCU40_ST3 15 4044 #define CCU40_IN0_ERU1_PDOUT0 9 4045 #define CCU40_IN0_ERU1_PDOUT1 3 4046 #define CCU40_IN0_P1_3 0 4047 #define CCU40_IN0_P2_1 2 4048 #define CCU40_IN0_P2_8 1 4049 #define CCU40_IN0_POSIF0_OUT0 4 4050 #define CCU40_IN0_POSIF0_OUT1 5 4051 #define CCU40_IN0_POSIF0_OUT3 6 4052 #define CCU40_IN0_SCU_ERU1_IOUT0 10 4053 #define CCU40_IN0_SCU_GSC40 8 4054 #define CCU40_IN0_U0C0_DX2INS 11 4055 #define CCU40_IN1_CCU40_ST0 12 4056 #define CCU40_IN1_CCU40_ST1 13 4057 #define CCU40_IN1_CCU40_ST2 14 4058 #define CCU40_IN1_CCU40_ST3 15 4059 #define CCU40_IN1_ERU1_PDOUT0 3 4060 #define CCU40_IN1_ERU1_PDOUT1 9 4061 #define CCU40_IN1_P1_2 0 4062 #define CCU40_IN1_P2_0 2 4063 #define CCU40_IN1_P2_8 1 4064 #define CCU40_IN1_POSIF0_OUT0 4 4065 #define CCU40_IN1_POSIF0_OUT1 5 4066 #define CCU40_IN1_POSIF0_OUT2 11 4067 #define CCU40_IN1_POSIF0_OUT3 6 4068 #define CCU40_IN1_POSIF0_OUT4 7 4069 #define CCU40_IN1_SCU_ERU1_IOUT1 10 4070 #define CCU40_IN1_SCU_GSC40 8 4071 #define CCU40_IN2_CCU40_ST0 12 4072 #define CCU40_IN2_CCU40_ST1 13 4073 #define CCU40_IN2_CCU40_ST2 14 4074 #define CCU40_IN2_CCU40_ST3 15 4075 #define CCU40_IN2_ERU1_PDOUT0 3 4076 #define CCU40_IN2_ERU1_PDOUT2 9 4077 #define CCU40_IN2_P1_1 0 4078 #define CCU40_IN2_P2_7 2 4079 #define CCU40_IN2_P2_8 1 4080 #define CCU40_IN2_POSIF0_OUT0 4 4081 #define CCU40_IN2_POSIF0_OUT2 5 4082 #define CCU40_IN2_POSIF0_OUT3 6 4083 #define CCU40_IN2_POSIF0_OUT4 7 4084 #define CCU40_IN2_SCU_ERU1_IOUT2 10 4085 #define CCU40_IN2_SCU_GSC40 8 4086 #define CCU40_IN2_U0C1_DX2INS 11 4087 #define CCU40_IN3_CCU40_ST0 12 4088 #define CCU40_IN3_CCU40_ST1 13 4089 #define CCU40_IN3_CCU40_ST2 14 4090 #define CCU40_IN3_CCU40_ST3 15 4091 #define CCU40_IN3_CCU80_IGBTO 7 4092 #define CCU40_IN3_ERU1_PDOUT0 3 4093 #define CCU40_IN3_ERU1_PDOUT3 9 4094 #define CCU40_IN3_P1_0 0 4095 #define CCU40_IN3_P2_6 2 4096 #define CCU40_IN3_P2_8 1 4097 #define CCU40_IN3_POSIF0_OUT3 4 4098 #define CCU40_IN3_POSIF0_OUT5 5 4099 #define CCU40_IN3_SCU_ERU1_IOUT3 10 4100 #define CCU40_IN3_SCU_GSC40 8 4101 #define CCU40_IN3_U1C0_DX2INS 11 4102 #define CCU40_IN3_VADC0_G0ARBCNT 6 4103 #define CCU41_IN0_CAN0_SR7 7 4104 #define CCU41_IN0_CCU41_ST0 12 4105 #define CCU41_IN0_CCU41_ST1 13 4106 #define CCU41_IN0_CCU41_ST2 14 4107 #define CCU41_IN0_CCU41_ST3 15 4108 #define CCU41_IN0_ERU1_PDOUT0 9 4109 #define CCU41_IN0_ERU1_PDOUT1 3 4110 #define CCU41_IN0_P1_4 2 4111 #define CCU41_IN0_P2_5 0 4112 #define CCU41_IN0_P2_9 1 4113 #define CCU41_IN0_POSIF1_OUT0 4 4114 #define CCU41_IN0_POSIF1_OUT1 5 4115 #define CCU41_IN0_POSIF1_OUT3 6 4116 #define CCU41_IN0_SCU_ERU1_IOUT0 10 4117 #define CCU41_IN0_SCU_GSC41 8 4118 #define CCU41_IN0_VADC0_G0BFL0 11 4119 #define CCU41_IN1_CCU41_ST0 12 4120 #define CCU41_IN1_CCU41_ST1 13 4121 #define CCU41_IN1_CCU41_ST2 14 4122 #define CCU41_IN1_CCU41_ST3 15 4123 #define CCU41_IN1_ERU1_PDOUT0 3 4124 #define CCU41_IN1_ERU1_PDOUT1 9 4125 #define CCU41_IN1_P1_5 2 4126 #define CCU41_IN1_P2_4 0 4127 #define CCU41_IN1_P2_9 1 4128 #define CCU41_IN1_POSIF1_OUT0 4 4129 #define CCU41_IN1_POSIF1_OUT1 5 4130 #define CCU41_IN1_POSIF1_OUT2 11 4131 #define CCU41_IN1_POSIF1_OUT3 6 4132 #define CCU41_IN1_POSIF1_OUT4 7 4133 #define CCU41_IN1_SCU_ERU1_IOUT1 10 4134 #define CCU41_IN1_SCU_GSC41 8 4135 #define CCU41_IN2_CCU41_ST0 12 4136 #define CCU41_IN2_CCU41_ST1 13 4137 #define CCU41_IN2_CCU41_ST2 14 4138 #define CCU41_IN2_CCU41_ST3 15 4139 #define CCU41_IN2_ERU1_PDOUT0 3 4140 #define CCU41_IN2_ERU1_PDOUT2 9 4141 #define CCU41_IN2_P1_10 2 4142 #define CCU41_IN2_P2_3 0 4143 #define CCU41_IN2_P2_9 1 4144 #define CCU41_IN2_POSIF1_OUT0 4 4145 #define CCU41_IN2_POSIF1_OUT2 5 4146 #define CCU41_IN2_POSIF1_OUT3 6 4147 #define CCU41_IN2_POSIF1_OUT4 7 4148 #define CCU41_IN2_SCU_ERU1_IOUT2 10 4149 #define CCU41_IN2_SCU_GSC41 8 4150 #define CCU41_IN2_VADC0_G0BFL1 11 4151 #define CCU41_IN3_CCU41_ST0 12 4152 #define CCU41_IN3_CCU41_ST1 13 4153 #define CCU41_IN3_CCU41_ST2 14 4154 #define CCU41_IN3_CCU41_ST3 15 4155 #define CCU41_IN3_CCU81_IGBTO 7 4156 #define CCU41_IN3_ERU1_PDOUT0 3 4157 #define CCU41_IN3_ERU1_PDOUT3 9 4158 #define CCU41_IN3_P1_11 2 4159 #define CCU41_IN3_P2_2 0 4160 #define CCU41_IN3_P2_9 1 4161 #define CCU41_IN3_POSIF1_OUT3 4 4162 #define CCU41_IN3_POSIF1_OUT5 5 4163 #define CCU41_IN3_SCU_ERU1_IOUT3 10 4164 #define CCU41_IN3_SCU_GSC41 8 4165 #define CCU41_IN3_VADC0_G0BFL2 11 4166 #define CCU41_IN3_VADC0_G1ARBCNT 6 4167 #define CCU42_IN0_CCU42_ST0 12 4168 #define CCU42_IN0_CCU42_ST1 13 4169 #define CCU42_IN0_CCU42_ST2 14 4170 #define CCU42_IN0_CCU42_ST3 15 4171 #define CCU42_IN0_CCU80_IGBTO 7 4172 #define CCU42_IN0_ERU1_PDOUT0 9 4173 #define CCU42_IN0_ERU1_PDOUT1 3 4174 #define CCU42_IN0_P2_15 1 4175 #define CCU42_IN0_P3_15 2 4176 #define CCU42_IN0_P3_6 0 4177 #define CCU42_IN0_POSIF0_OUT2 4 4178 #define CCU42_IN0_POSIF0_OUT5 5 4179 #define CCU42_IN0_SCU_ERU1_IOUT0 10 4180 #define CCU42_IN0_SCU_GSC42 8 4181 #define CCU42_IN0_U0C0_DX2INS 11 4182 #define CCU42_IN1_CCU42_ST0 12 4183 #define CCU42_IN1_CCU42_ST1 13 4184 #define CCU42_IN1_CCU42_ST2 14 4185 #define CCU42_IN1_CCU42_ST3 15 4186 #define CCU42_IN1_ERU1_PDOUT0 3 4187 #define CCU42_IN1_ERU1_PDOUT1 9 4188 #define CCU42_IN1_P2_15 1 4189 #define CCU42_IN1_P3_14 2 4190 #define CCU42_IN1_P3_5 0 4191 #define CCU42_IN1_POSIF0_OUT2 4 4192 #define CCU42_IN1_POSIF0_OUT5 5 4193 #define CCU42_IN1_SCU_ERU1_IOUT1 10 4194 #define CCU42_IN1_SCU_GSC42 8 4195 #define CCU42_IN1_U0C1_DX2INS 11 4196 #define CCU42_IN2_CAN0_SR7 6 4197 #define CCU42_IN2_CCU42_ST0 12 4198 #define CCU42_IN2_CCU42_ST1 13 4199 #define CCU42_IN2_CCU42_ST2 14 4200 #define CCU42_IN2_CCU42_ST3 15 4201 #define CCU42_IN2_ERU1_PDOUT0 3 4202 #define CCU42_IN2_ERU1_PDOUT2 9 4203 #define CCU42_IN2_P0_15 2 4204 #define CCU42_IN2_P2_15 1 4205 #define CCU42_IN2_P3_4 0 4206 #define CCU42_IN2_POSIF0_OUT2 4 4207 #define CCU42_IN2_POSIF0_OUT5 5 4208 #define CCU42_IN2_SCU_ERU1_IOUT2 10 4209 #define CCU42_IN2_SCU_GSC42 8 4210 #define CCU42_IN2_U1C0_DX2INS 11 4211 #define CCU42_IN3_CCU42_ST0 12 4212 #define CCU42_IN3_CCU42_ST1 13 4213 #define CCU42_IN3_CCU42_ST2 14 4214 #define CCU42_IN3_CCU42_ST3 15 4215 #define CCU42_IN3_ERU1_PDOUT0 3 4216 #define CCU42_IN3_ERU1_PDOUT3 9 4217 #define CCU42_IN3_P0_14 2 4218 #define CCU42_IN3_P2_15 1 4219 #define CCU42_IN3_P3_3 0 4220 #define CCU42_IN3_POSIF0_OUT2 4 4221 #define CCU42_IN3_POSIF0_OUT5 5 4222 #define CCU42_IN3_SCU_ERU1_IOUT3 10 4223 #define CCU42_IN3_SCU_GSC42 8 4224 #define CCU42_IN3_U1C1_DX2INS 11 4225 #define CCU42_IN3_VADC0_G2ARBCNT 6 4226 #define CCU43_IN0_CCU43_ST0 12 4227 #define CCU43_IN0_CCU43_ST1 13 4228 #define CCU43_IN0_CCU43_ST2 14 4229 #define CCU43_IN0_CCU43_ST3 15 4230 #define CCU43_IN0_CCU81_IGBTO 6 4231 #define CCU43_IN0_ERU1_PDOUT0 9 4232 #define CCU43_IN0_ERU1_PDOUT1 3 4233 #define CCU43_IN0_P2_14 1 4234 #define CCU43_IN0_P4_6 0 4235 #define CCU43_IN0_P4_7 2 4236 #define CCU43_IN0_POSIF1_OUT2 4 4237 #define CCU43_IN0_POSIF1_OUT5 5 4238 #define CCU43_IN0_SCU_ERU1_IOUT0 10 4239 #define CCU43_IN0_SCU_GSC43 8 4240 #define CCU43_IN0_U0C0_DX2INS 11 4241 #define CCU43_IN0_VADC0_G0BFL0 7 4242 #define CCU43_IN1_CAN0_SR7 6 4243 #define CCU43_IN1_CCU43_ST0 12 4244 #define CCU43_IN1_CCU43_ST1 13 4245 #define CCU43_IN1_CCU43_ST2 14 4246 #define CCU43_IN1_CCU43_ST3 15 4247 #define CCU43_IN1_ERU1_PDOUT0 3 4248 #define CCU43_IN1_ERU1_PDOUT1 9 4249 #define CCU43_IN1_P2_14 1 4250 #define CCU43_IN1_P4_2 2 4251 #define CCU43_IN1_P4_5 0 4252 #define CCU43_IN1_POSIF1_OUT2 4 4253 #define CCU43_IN1_POSIF1_OUT5 5 4254 #define CCU43_IN1_SCU_ERU1_IOUT1 10 4255 #define CCU43_IN1_SCU_GSC43 8 4256 #define CCU43_IN1_U0C1_DX2INS 11 4257 #define CCU43_IN1_VADC0_G1BFL0 7 4258 #define CCU43_IN2_CCU43_ST0 12 4259 #define CCU43_IN2_CCU43_ST1 13 4260 #define CCU43_IN2_CCU43_ST2 14 4261 #define CCU43_IN2_CCU43_ST3 15 4262 #define CCU43_IN2_ERU1_PDOUT0 3 4263 #define CCU43_IN2_ERU1_PDOUT2 9 4264 #define CCU43_IN2_P2_13 2 4265 #define CCU43_IN2_P2_14 1 4266 #define CCU43_IN2_P4_4 0 4267 #define CCU43_IN2_POSIF1_OUT2 4 4268 #define CCU43_IN2_POSIF1_OUT5 5 4269 #define CCU43_IN2_SCU_ERU1_IOUT2 10 4270 #define CCU43_IN2_SCU_GSC43 8 4271 #define CCU43_IN2_U1C0_DX2INS 11 4272 #define CCU43_IN2_VADC0_G2BFL0 7 4273 #define CCU43_IN3_CCU43_ST0 12 4274 #define CCU43_IN3_CCU43_ST1 13 4275 #define CCU43_IN3_CCU43_ST2 14 4276 #define CCU43_IN3_CCU43_ST3 15 4277 #define CCU43_IN3_ERU1_PDOUT0 3 4278 #define CCU43_IN3_ERU1_PDOUT3 9 4279 #define CCU43_IN3_P2_12 2 4280 #define CCU43_IN3_P2_14 1 4281 #define CCU43_IN3_P4_3 0 4282 #define CCU43_IN3_POSIF1_OUT2 4 4283 #define CCU43_IN3_POSIF1_OUT5 5 4284 #define CCU43_IN3_SCU_ERU1_IOUT3 10 4285 #define CCU43_IN3_SCU_GSC43 8 4286 #define CCU43_IN3_U1C1_DX2INS 11 4287 #define CCU43_IN3_VADC0_G3ARBCNT 6 4288 #define CCU43_IN3_VADC0_G3BFL0 7 4289 #endif 4290 4291 4292 #if (UC_DEVICE == XMC4800) && (UC_PACKAGE == BGA196) 4293 #define CCU40_IN0_CAN0_SR7 7 4294 #define CCU40_IN0_CCU40_ST0 12 4295 #define CCU40_IN0_CCU40_ST1 13 4296 #define CCU40_IN0_CCU40_ST2 14 4297 #define CCU40_IN0_CCU40_ST3 15 4298 #define CCU40_IN0_ERU1_PDOUT0 9 4299 #define CCU40_IN0_ERU1_PDOUT1 3 4300 #define CCU40_IN0_P1_3 0 4301 #define CCU40_IN0_P2_1 2 4302 #define CCU40_IN0_P2_8 1 4303 #define CCU40_IN0_POSIF0_OUT0 4 4304 #define CCU40_IN0_POSIF0_OUT1 5 4305 #define CCU40_IN0_POSIF0_OUT3 6 4306 #define CCU40_IN0_SCU_ERU1_IOUT0 10 4307 #define CCU40_IN0_SCU_GSC40 8 4308 #define CCU40_IN0_U0C0_DX2INS 11 4309 #define CCU40_IN1_CCU40_ST0 12 4310 #define CCU40_IN1_CCU40_ST1 13 4311 #define CCU40_IN1_CCU40_ST2 14 4312 #define CCU40_IN1_CCU40_ST3 15 4313 #define CCU40_IN1_ERU1_PDOUT0 3 4314 #define CCU40_IN1_ERU1_PDOUT1 9 4315 #define CCU40_IN1_P1_2 0 4316 #define CCU40_IN1_P2_0 2 4317 #define CCU40_IN1_P2_8 1 4318 #define CCU40_IN1_POSIF0_OUT0 4 4319 #define CCU40_IN1_POSIF0_OUT1 5 4320 #define CCU40_IN1_POSIF0_OUT2 11 4321 #define CCU40_IN1_POSIF0_OUT3 6 4322 #define CCU40_IN1_POSIF0_OUT4 7 4323 #define CCU40_IN1_SCU_ERU1_IOUT1 10 4324 #define CCU40_IN1_SCU_GSC40 8 4325 #define CCU40_IN2_CCU40_ST0 12 4326 #define CCU40_IN2_CCU40_ST1 13 4327 #define CCU40_IN2_CCU40_ST2 14 4328 #define CCU40_IN2_CCU40_ST3 15 4329 #define CCU40_IN2_ERU1_PDOUT0 3 4330 #define CCU40_IN2_ERU1_PDOUT2 9 4331 #define CCU40_IN2_P1_1 0 4332 #define CCU40_IN2_P2_7 2 4333 #define CCU40_IN2_P2_8 1 4334 #define CCU40_IN2_POSIF0_OUT0 4 4335 #define CCU40_IN2_POSIF0_OUT2 5 4336 #define CCU40_IN2_POSIF0_OUT3 6 4337 #define CCU40_IN2_POSIF0_OUT4 7 4338 #define CCU40_IN2_SCU_ERU1_IOUT2 10 4339 #define CCU40_IN2_SCU_GSC40 8 4340 #define CCU40_IN2_U0C1_DX2INS 11 4341 #define CCU40_IN3_CCU40_ST0 12 4342 #define CCU40_IN3_CCU40_ST1 13 4343 #define CCU40_IN3_CCU40_ST2 14 4344 #define CCU40_IN3_CCU40_ST3 15 4345 #define CCU40_IN3_CCU80_IGBTO 7 4346 #define CCU40_IN3_ERU1_PDOUT0 3 4347 #define CCU40_IN3_ERU1_PDOUT3 9 4348 #define CCU40_IN3_P1_0 0 4349 #define CCU40_IN3_P2_6 2 4350 #define CCU40_IN3_P2_8 1 4351 #define CCU40_IN3_POSIF0_OUT3 4 4352 #define CCU40_IN3_POSIF0_OUT5 5 4353 #define CCU40_IN3_SCU_ERU1_IOUT3 10 4354 #define CCU40_IN3_SCU_GSC40 8 4355 #define CCU40_IN3_U1C0_DX2INS 11 4356 #define CCU40_IN3_VADC0_G0ARBCNT 6 4357 #define CCU41_IN0_CAN0_SR7 7 4358 #define CCU41_IN0_CCU41_ST0 12 4359 #define CCU41_IN0_CCU41_ST1 13 4360 #define CCU41_IN0_CCU41_ST2 14 4361 #define CCU41_IN0_CCU41_ST3 15 4362 #define CCU41_IN0_ERU1_PDOUT0 9 4363 #define CCU41_IN0_ERU1_PDOUT1 3 4364 #define CCU41_IN0_P1_4 2 4365 #define CCU41_IN0_P2_5 0 4366 #define CCU41_IN0_P2_9 1 4367 #define CCU41_IN0_POSIF1_OUT0 4 4368 #define CCU41_IN0_POSIF1_OUT1 5 4369 #define CCU41_IN0_POSIF1_OUT3 6 4370 #define CCU41_IN0_SCU_ERU1_IOUT0 10 4371 #define CCU41_IN0_SCU_GSC41 8 4372 #define CCU41_IN0_VADC0_G0BFL0 11 4373 #define CCU41_IN1_CCU41_ST0 12 4374 #define CCU41_IN1_CCU41_ST1 13 4375 #define CCU41_IN1_CCU41_ST2 14 4376 #define CCU41_IN1_CCU41_ST3 15 4377 #define CCU41_IN1_ERU1_PDOUT0 3 4378 #define CCU41_IN1_ERU1_PDOUT1 9 4379 #define CCU41_IN1_P1_5 2 4380 #define CCU41_IN1_P2_4 0 4381 #define CCU41_IN1_P2_9 1 4382 #define CCU41_IN1_POSIF1_OUT0 4 4383 #define CCU41_IN1_POSIF1_OUT1 5 4384 #define CCU41_IN1_POSIF1_OUT2 11 4385 #define CCU41_IN1_POSIF1_OUT3 6 4386 #define CCU41_IN1_POSIF1_OUT4 7 4387 #define CCU41_IN1_SCU_ERU1_IOUT1 10 4388 #define CCU41_IN1_SCU_GSC41 8 4389 #define CCU41_IN2_CCU41_ST0 12 4390 #define CCU41_IN2_CCU41_ST1 13 4391 #define CCU41_IN2_CCU41_ST2 14 4392 #define CCU41_IN2_CCU41_ST3 15 4393 #define CCU41_IN2_ERU1_PDOUT0 3 4394 #define CCU41_IN2_ERU1_PDOUT2 9 4395 #define CCU41_IN2_P1_10 2 4396 #define CCU41_IN2_P2_3 0 4397 #define CCU41_IN2_P2_9 1 4398 #define CCU41_IN2_POSIF1_OUT0 4 4399 #define CCU41_IN2_POSIF1_OUT2 5 4400 #define CCU41_IN2_POSIF1_OUT3 6 4401 #define CCU41_IN2_POSIF1_OUT4 7 4402 #define CCU41_IN2_SCU_ERU1_IOUT2 10 4403 #define CCU41_IN2_SCU_GSC41 8 4404 #define CCU41_IN2_VADC0_G0BFL1 11 4405 #define CCU41_IN3_CCU41_ST0 12 4406 #define CCU41_IN3_CCU41_ST1 13 4407 #define CCU41_IN3_CCU41_ST2 14 4408 #define CCU41_IN3_CCU41_ST3 15 4409 #define CCU41_IN3_CCU81_IGBTO 7 4410 #define CCU41_IN3_ERU1_PDOUT0 3 4411 #define CCU41_IN3_ERU1_PDOUT3 9 4412 #define CCU41_IN3_P1_11 2 4413 #define CCU41_IN3_P2_2 0 4414 #define CCU41_IN3_P2_9 1 4415 #define CCU41_IN3_POSIF1_OUT3 4 4416 #define CCU41_IN3_POSIF1_OUT5 5 4417 #define CCU41_IN3_SCU_ERU1_IOUT3 10 4418 #define CCU41_IN3_SCU_GSC41 8 4419 #define CCU41_IN3_VADC0_G0BFL2 11 4420 #define CCU41_IN3_VADC0_G1ARBCNT 6 4421 #define CCU42_IN0_CCU42_ST0 12 4422 #define CCU42_IN0_CCU42_ST1 13 4423 #define CCU42_IN0_CCU42_ST2 14 4424 #define CCU42_IN0_CCU42_ST3 15 4425 #define CCU42_IN0_CCU80_IGBTO 7 4426 #define CCU42_IN0_ERU1_PDOUT0 9 4427 #define CCU42_IN0_ERU1_PDOUT1 3 4428 #define CCU42_IN0_P2_15 1 4429 #define CCU42_IN0_P3_15 2 4430 #define CCU42_IN0_P3_6 0 4431 #define CCU42_IN0_POSIF0_OUT2 4 4432 #define CCU42_IN0_POSIF0_OUT5 5 4433 #define CCU42_IN0_SCU_ERU1_IOUT0 10 4434 #define CCU42_IN0_SCU_GSC42 8 4435 #define CCU42_IN0_U0C0_DX2INS 11 4436 #define CCU42_IN1_CCU42_ST0 12 4437 #define CCU42_IN1_CCU42_ST1 13 4438 #define CCU42_IN1_CCU42_ST2 14 4439 #define CCU42_IN1_CCU42_ST3 15 4440 #define CCU42_IN1_ERU1_PDOUT0 3 4441 #define CCU42_IN1_ERU1_PDOUT1 9 4442 #define CCU42_IN1_P2_15 1 4443 #define CCU42_IN1_P3_14 2 4444 #define CCU42_IN1_P3_5 0 4445 #define CCU42_IN1_POSIF0_OUT2 4 4446 #define CCU42_IN1_POSIF0_OUT5 5 4447 #define CCU42_IN1_SCU_ERU1_IOUT1 10 4448 #define CCU42_IN1_SCU_GSC42 8 4449 #define CCU42_IN1_U0C1_DX2INS 11 4450 #define CCU42_IN2_CAN0_SR7 6 4451 #define CCU42_IN2_CCU42_ST0 12 4452 #define CCU42_IN2_CCU42_ST1 13 4453 #define CCU42_IN2_CCU42_ST2 14 4454 #define CCU42_IN2_CCU42_ST3 15 4455 #define CCU42_IN2_ERU1_PDOUT0 3 4456 #define CCU42_IN2_ERU1_PDOUT2 9 4457 #define CCU42_IN2_P0_15 2 4458 #define CCU42_IN2_P2_15 1 4459 #define CCU42_IN2_P3_4 0 4460 #define CCU42_IN2_POSIF0_OUT2 4 4461 #define CCU42_IN2_POSIF0_OUT5 5 4462 #define CCU42_IN2_SCU_ERU1_IOUT2 10 4463 #define CCU42_IN2_SCU_GSC42 8 4464 #define CCU42_IN2_U1C0_DX2INS 11 4465 #define CCU42_IN3_CCU42_ST0 12 4466 #define CCU42_IN3_CCU42_ST1 13 4467 #define CCU42_IN3_CCU42_ST2 14 4468 #define CCU42_IN3_CCU42_ST3 15 4469 #define CCU42_IN3_ERU1_PDOUT0 3 4470 #define CCU42_IN3_ERU1_PDOUT3 9 4471 #define CCU42_IN3_P0_14 2 4472 #define CCU42_IN3_P2_15 1 4473 #define CCU42_IN3_P3_3 0 4474 #define CCU42_IN3_POSIF0_OUT2 4 4475 #define CCU42_IN3_POSIF0_OUT5 5 4476 #define CCU42_IN3_SCU_ERU1_IOUT3 10 4477 #define CCU42_IN3_SCU_GSC42 8 4478 #define CCU42_IN3_U1C1_DX2INS 11 4479 #define CCU42_IN3_VADC0_G2ARBCNT 6 4480 #define CCU43_IN0_CCU43_ST0 12 4481 #define CCU43_IN0_CCU43_ST1 13 4482 #define CCU43_IN0_CCU43_ST2 14 4483 #define CCU43_IN0_CCU43_ST3 15 4484 #define CCU43_IN0_CCU81_IGBTO 6 4485 #define CCU43_IN0_ERU1_PDOUT0 9 4486 #define CCU43_IN0_ERU1_PDOUT1 3 4487 #define CCU43_IN0_P2_14 1 4488 #define CCU43_IN0_P4_6 0 4489 #define CCU43_IN0_P4_7 2 4490 #define CCU43_IN0_POSIF1_OUT2 4 4491 #define CCU43_IN0_POSIF1_OUT5 5 4492 #define CCU43_IN0_SCU_ERU1_IOUT0 10 4493 #define CCU43_IN0_SCU_GSC43 8 4494 #define CCU43_IN0_U0C0_DX2INS 11 4495 #define CCU43_IN0_VADC0_G0BFL0 7 4496 #define CCU43_IN1_CAN0_SR7 6 4497 #define CCU43_IN1_CCU43_ST0 12 4498 #define CCU43_IN1_CCU43_ST1 13 4499 #define CCU43_IN1_CCU43_ST2 14 4500 #define CCU43_IN1_CCU43_ST3 15 4501 #define CCU43_IN1_ERU1_PDOUT0 3 4502 #define CCU43_IN1_ERU1_PDOUT1 9 4503 #define CCU43_IN1_P2_14 1 4504 #define CCU43_IN1_P4_2 2 4505 #define CCU43_IN1_P4_5 0 4506 #define CCU43_IN1_POSIF1_OUT2 4 4507 #define CCU43_IN1_POSIF1_OUT5 5 4508 #define CCU43_IN1_SCU_ERU1_IOUT1 10 4509 #define CCU43_IN1_SCU_GSC43 8 4510 #define CCU43_IN1_U0C1_DX2INS 11 4511 #define CCU43_IN1_VADC0_G1BFL0 7 4512 #define CCU43_IN2_CCU43_ST0 12 4513 #define CCU43_IN2_CCU43_ST1 13 4514 #define CCU43_IN2_CCU43_ST2 14 4515 #define CCU43_IN2_CCU43_ST3 15 4516 #define CCU43_IN2_ERU1_PDOUT0 3 4517 #define CCU43_IN2_ERU1_PDOUT2 9 4518 #define CCU43_IN2_P2_13 2 4519 #define CCU43_IN2_P2_14 1 4520 #define CCU43_IN2_P4_4 0 4521 #define CCU43_IN2_POSIF1_OUT2 4 4522 #define CCU43_IN2_POSIF1_OUT5 5 4523 #define CCU43_IN2_SCU_ERU1_IOUT2 10 4524 #define CCU43_IN2_SCU_GSC43 8 4525 #define CCU43_IN2_U1C0_DX2INS 11 4526 #define CCU43_IN2_VADC0_G2BFL0 7 4527 #define CCU43_IN3_CCU43_ST0 12 4528 #define CCU43_IN3_CCU43_ST1 13 4529 #define CCU43_IN3_CCU43_ST2 14 4530 #define CCU43_IN3_CCU43_ST3 15 4531 #define CCU43_IN3_ERU1_PDOUT0 3 4532 #define CCU43_IN3_ERU1_PDOUT3 9 4533 #define CCU43_IN3_P2_12 2 4534 #define CCU43_IN3_P2_14 1 4535 #define CCU43_IN3_P4_3 0 4536 #define CCU43_IN3_POSIF1_OUT2 4 4537 #define CCU43_IN3_POSIF1_OUT5 5 4538 #define CCU43_IN3_SCU_ERU1_IOUT3 10 4539 #define CCU43_IN3_SCU_GSC43 8 4540 #define CCU43_IN3_U1C1_DX2INS 11 4541 #define CCU43_IN3_VADC0_G3ARBCNT 6 4542 #define CCU43_IN3_VADC0_G3BFL0 7 4543 #endif 4544 4545 4546 #if (UC_DEVICE == XMC4800) && (UC_PACKAGE == LQFP100) 4547 #define CCU40_IN0_CAN0_SR7 7 4548 #define CCU40_IN0_CCU40_ST0 12 4549 #define CCU40_IN0_CCU40_ST1 13 4550 #define CCU40_IN0_CCU40_ST2 14 4551 #define CCU40_IN0_CCU40_ST3 15 4552 #define CCU40_IN0_ERU1_PDOUT0 9 4553 #define CCU40_IN0_ERU1_PDOUT1 3 4554 #define CCU40_IN0_P1_3 0 4555 #define CCU40_IN0_P2_1 2 4556 #define CCU40_IN0_P2_8 1 4557 #define CCU40_IN0_POSIF0_OUT0 4 4558 #define CCU40_IN0_POSIF0_OUT1 5 4559 #define CCU40_IN0_POSIF0_OUT3 6 4560 #define CCU40_IN0_SCU_ERU1_IOUT0 10 4561 #define CCU40_IN0_SCU_GSC40 8 4562 #define CCU40_IN0_U0C0_DX2INS 11 4563 #define CCU40_IN1_CCU40_ST0 12 4564 #define CCU40_IN1_CCU40_ST1 13 4565 #define CCU40_IN1_CCU40_ST2 14 4566 #define CCU40_IN1_CCU40_ST3 15 4567 #define CCU40_IN1_ERU1_PDOUT0 3 4568 #define CCU40_IN1_ERU1_PDOUT1 9 4569 #define CCU40_IN1_P1_2 0 4570 #define CCU40_IN1_P2_0 2 4571 #define CCU40_IN1_P2_8 1 4572 #define CCU40_IN1_POSIF0_OUT0 4 4573 #define CCU40_IN1_POSIF0_OUT1 5 4574 #define CCU40_IN1_POSIF0_OUT2 11 4575 #define CCU40_IN1_POSIF0_OUT3 6 4576 #define CCU40_IN1_POSIF0_OUT4 7 4577 #define CCU40_IN1_SCU_ERU1_IOUT1 10 4578 #define CCU40_IN1_SCU_GSC40 8 4579 #define CCU40_IN2_CCU40_ST0 12 4580 #define CCU40_IN2_CCU40_ST1 13 4581 #define CCU40_IN2_CCU40_ST2 14 4582 #define CCU40_IN2_CCU40_ST3 15 4583 #define CCU40_IN2_ERU1_PDOUT0 3 4584 #define CCU40_IN2_ERU1_PDOUT2 9 4585 #define CCU40_IN2_P1_1 0 4586 #define CCU40_IN2_P2_7 2 4587 #define CCU40_IN2_P2_8 1 4588 #define CCU40_IN2_POSIF0_OUT0 4 4589 #define CCU40_IN2_POSIF0_OUT2 5 4590 #define CCU40_IN2_POSIF0_OUT3 6 4591 #define CCU40_IN2_POSIF0_OUT4 7 4592 #define CCU40_IN2_SCU_ERU1_IOUT2 10 4593 #define CCU40_IN2_SCU_GSC40 8 4594 #define CCU40_IN2_U0C1_DX2INS 11 4595 #define CCU40_IN3_CCU40_ST0 12 4596 #define CCU40_IN3_CCU40_ST1 13 4597 #define CCU40_IN3_CCU40_ST2 14 4598 #define CCU40_IN3_CCU40_ST3 15 4599 #define CCU40_IN3_CCU80_IGBTO 7 4600 #define CCU40_IN3_ERU1_PDOUT0 3 4601 #define CCU40_IN3_ERU1_PDOUT3 9 4602 #define CCU40_IN3_P1_0 0 4603 #define CCU40_IN3_P2_6 2 4604 #define CCU40_IN3_P2_8 1 4605 #define CCU40_IN3_POSIF0_OUT3 4 4606 #define CCU40_IN3_POSIF0_OUT5 5 4607 #define CCU40_IN3_SCU_ERU1_IOUT3 10 4608 #define CCU40_IN3_SCU_GSC40 8 4609 #define CCU40_IN3_U1C0_DX2INS 11 4610 #define CCU40_IN3_VADC0_G0ARBCNT 6 4611 #define CCU41_IN0_CAN0_SR7 7 4612 #define CCU41_IN0_CCU41_ST0 12 4613 #define CCU41_IN0_CCU41_ST1 13 4614 #define CCU41_IN0_CCU41_ST2 14 4615 #define CCU41_IN0_CCU41_ST3 15 4616 #define CCU41_IN0_ERU1_PDOUT0 9 4617 #define CCU41_IN0_ERU1_PDOUT1 3 4618 #define CCU41_IN0_P1_4 2 4619 #define CCU41_IN0_P2_5 0 4620 #define CCU41_IN0_P2_9 1 4621 #define CCU41_IN0_POSIF1_OUT0 4 4622 #define CCU41_IN0_POSIF1_OUT1 5 4623 #define CCU41_IN0_POSIF1_OUT3 6 4624 #define CCU41_IN0_SCU_ERU1_IOUT0 10 4625 #define CCU41_IN0_SCU_GSC41 8 4626 #define CCU41_IN0_VADC0_G0BFL0 11 4627 #define CCU41_IN1_CCU41_ST0 12 4628 #define CCU41_IN1_CCU41_ST1 13 4629 #define CCU41_IN1_CCU41_ST2 14 4630 #define CCU41_IN1_CCU41_ST3 15 4631 #define CCU41_IN1_ERU1_PDOUT0 3 4632 #define CCU41_IN1_ERU1_PDOUT1 9 4633 #define CCU41_IN1_P1_5 2 4634 #define CCU41_IN1_P2_4 0 4635 #define CCU41_IN1_P2_9 1 4636 #define CCU41_IN1_POSIF1_OUT0 4 4637 #define CCU41_IN1_POSIF1_OUT1 5 4638 #define CCU41_IN1_POSIF1_OUT2 11 4639 #define CCU41_IN1_POSIF1_OUT3 6 4640 #define CCU41_IN1_POSIF1_OUT4 7 4641 #define CCU41_IN1_SCU_ERU1_IOUT1 10 4642 #define CCU41_IN1_SCU_GSC41 8 4643 #define CCU41_IN2_CCU41_ST0 12 4644 #define CCU41_IN2_CCU41_ST1 13 4645 #define CCU41_IN2_CCU41_ST2 14 4646 #define CCU41_IN2_CCU41_ST3 15 4647 #define CCU41_IN2_ERU1_PDOUT0 3 4648 #define CCU41_IN2_ERU1_PDOUT2 9 4649 #define CCU41_IN2_P1_10 2 4650 #define CCU41_IN2_P2_3 0 4651 #define CCU41_IN2_P2_9 1 4652 #define CCU41_IN2_POSIF1_OUT0 4 4653 #define CCU41_IN2_POSIF1_OUT2 5 4654 #define CCU41_IN2_POSIF1_OUT3 6 4655 #define CCU41_IN2_POSIF1_OUT4 7 4656 #define CCU41_IN2_SCU_ERU1_IOUT2 10 4657 #define CCU41_IN2_SCU_GSC41 8 4658 #define CCU41_IN2_VADC0_G0BFL1 11 4659 #define CCU41_IN3_CCU41_ST0 12 4660 #define CCU41_IN3_CCU41_ST1 13 4661 #define CCU41_IN3_CCU41_ST2 14 4662 #define CCU41_IN3_CCU41_ST3 15 4663 #define CCU41_IN3_CCU81_IGBTO 7 4664 #define CCU41_IN3_ERU1_PDOUT0 3 4665 #define CCU41_IN3_ERU1_PDOUT3 9 4666 #define CCU41_IN3_P1_11 2 4667 #define CCU41_IN3_P2_2 0 4668 #define CCU41_IN3_P2_9 1 4669 #define CCU41_IN3_POSIF1_OUT3 4 4670 #define CCU41_IN3_POSIF1_OUT5 5 4671 #define CCU41_IN3_SCU_ERU1_IOUT3 10 4672 #define CCU41_IN3_SCU_GSC41 8 4673 #define CCU41_IN3_VADC0_G0BFL2 11 4674 #define CCU41_IN3_VADC0_G1ARBCNT 6 4675 #define CCU42_IN0_CCU42_ST0 12 4676 #define CCU42_IN0_CCU42_ST1 13 4677 #define CCU42_IN0_CCU42_ST2 14 4678 #define CCU42_IN0_CCU42_ST3 15 4679 #define CCU42_IN0_CCU80_IGBTO 7 4680 #define CCU42_IN0_ERU1_PDOUT0 9 4681 #define CCU42_IN0_ERU1_PDOUT1 3 4682 #define CCU42_IN0_P2_15 1 4683 #define CCU42_IN0_P3_6 0 4684 #define CCU42_IN0_POSIF0_OUT2 4 4685 #define CCU42_IN0_POSIF0_OUT5 5 4686 #define CCU42_IN0_SCU_ERU1_IOUT0 10 4687 #define CCU42_IN0_SCU_GSC42 8 4688 #define CCU42_IN0_U0C0_DX2INS 11 4689 #define CCU42_IN1_CCU42_ST0 12 4690 #define CCU42_IN1_CCU42_ST1 13 4691 #define CCU42_IN1_CCU42_ST2 14 4692 #define CCU42_IN1_CCU42_ST3 15 4693 #define CCU42_IN1_ERU1_PDOUT0 3 4694 #define CCU42_IN1_ERU1_PDOUT1 9 4695 #define CCU42_IN1_P2_15 1 4696 #define CCU42_IN1_P3_5 0 4697 #define CCU42_IN1_POSIF0_OUT2 4 4698 #define CCU42_IN1_POSIF0_OUT5 5 4699 #define CCU42_IN1_SCU_ERU1_IOUT1 10 4700 #define CCU42_IN1_SCU_GSC42 8 4701 #define CCU42_IN1_U0C1_DX2INS 11 4702 #define CCU42_IN2_CAN0_SR7 6 4703 #define CCU42_IN2_CCU42_ST0 12 4704 #define CCU42_IN2_CCU42_ST1 13 4705 #define CCU42_IN2_CCU42_ST2 14 4706 #define CCU42_IN2_CCU42_ST3 15 4707 #define CCU42_IN2_ERU1_PDOUT0 3 4708 #define CCU42_IN2_ERU1_PDOUT2 9 4709 #define CCU42_IN2_P2_15 1 4710 #define CCU42_IN2_P3_4 0 4711 #define CCU42_IN2_POSIF0_OUT2 4 4712 #define CCU42_IN2_POSIF0_OUT5 5 4713 #define CCU42_IN2_SCU_ERU1_IOUT2 10 4714 #define CCU42_IN2_SCU_GSC42 8 4715 #define CCU42_IN2_U1C0_DX2INS 11 4716 #define CCU42_IN3_CCU42_ST0 12 4717 #define CCU42_IN3_CCU42_ST1 13 4718 #define CCU42_IN3_CCU42_ST2 14 4719 #define CCU42_IN3_CCU42_ST3 15 4720 #define CCU42_IN3_ERU1_PDOUT0 3 4721 #define CCU42_IN3_ERU1_PDOUT3 9 4722 #define CCU42_IN3_P2_15 1 4723 #define CCU42_IN3_P3_3 0 4724 #define CCU42_IN3_POSIF0_OUT2 4 4725 #define CCU42_IN3_POSIF0_OUT5 5 4726 #define CCU42_IN3_SCU_ERU1_IOUT3 10 4727 #define CCU42_IN3_SCU_GSC42 8 4728 #define CCU42_IN3_U1C1_DX2INS 11 4729 #define CCU42_IN3_VADC0_G2ARBCNT 6 4730 #define CCU43_IN0_CCU43_ST0 12 4731 #define CCU43_IN0_CCU43_ST1 13 4732 #define CCU43_IN0_CCU43_ST2 14 4733 #define CCU43_IN0_CCU43_ST3 15 4734 #define CCU43_IN0_CCU81_IGBTO 6 4735 #define CCU43_IN0_ERU1_PDOUT0 9 4736 #define CCU43_IN0_ERU1_PDOUT1 3 4737 #define CCU43_IN0_P2_14 1 4738 #define CCU43_IN0_POSIF1_OUT2 4 4739 #define CCU43_IN0_POSIF1_OUT5 5 4740 #define CCU43_IN0_SCU_ERU1_IOUT0 10 4741 #define CCU43_IN0_SCU_GSC43 8 4742 #define CCU43_IN0_U0C0_DX2INS 11 4743 #define CCU43_IN0_VADC0_G0BFL0 7 4744 #define CCU43_IN1_CAN0_SR7 6 4745 #define CCU43_IN1_CCU43_ST0 12 4746 #define CCU43_IN1_CCU43_ST1 13 4747 #define CCU43_IN1_CCU43_ST2 14 4748 #define CCU43_IN1_CCU43_ST3 15 4749 #define CCU43_IN1_ERU1_PDOUT0 3 4750 #define CCU43_IN1_ERU1_PDOUT1 9 4751 #define CCU43_IN1_P2_14 1 4752 #define CCU43_IN1_POSIF1_OUT2 4 4753 #define CCU43_IN1_POSIF1_OUT5 5 4754 #define CCU43_IN1_SCU_ERU1_IOUT1 10 4755 #define CCU43_IN1_SCU_GSC43 8 4756 #define CCU43_IN1_U0C1_DX2INS 11 4757 #define CCU43_IN1_VADC0_G1BFL0 7 4758 #define CCU43_IN2_CCU43_ST0 12 4759 #define CCU43_IN2_CCU43_ST1 13 4760 #define CCU43_IN2_CCU43_ST2 14 4761 #define CCU43_IN2_CCU43_ST3 15 4762 #define CCU43_IN2_ERU1_PDOUT0 3 4763 #define CCU43_IN2_ERU1_PDOUT2 9 4764 #define CCU43_IN2_P2_14 1 4765 #define CCU43_IN2_POSIF1_OUT2 4 4766 #define CCU43_IN2_POSIF1_OUT5 5 4767 #define CCU43_IN2_SCU_ERU1_IOUT2 10 4768 #define CCU43_IN2_SCU_GSC43 8 4769 #define CCU43_IN2_U1C0_DX2INS 11 4770 #define CCU43_IN2_VADC0_G2BFL0 7 4771 #define CCU43_IN3_CCU43_ST0 12 4772 #define CCU43_IN3_CCU43_ST1 13 4773 #define CCU43_IN3_CCU43_ST2 14 4774 #define CCU43_IN3_CCU43_ST3 15 4775 #define CCU43_IN3_ERU1_PDOUT0 3 4776 #define CCU43_IN3_ERU1_PDOUT3 9 4777 #define CCU43_IN3_P2_14 1 4778 #define CCU43_IN3_POSIF1_OUT2 4 4779 #define CCU43_IN3_POSIF1_OUT5 5 4780 #define CCU43_IN3_SCU_ERU1_IOUT3 10 4781 #define CCU43_IN3_SCU_GSC43 8 4782 #define CCU43_IN3_U1C1_DX2INS 11 4783 #define CCU43_IN3_VADC0_G3ARBCNT 6 4784 #define CCU43_IN3_VADC0_G3BFL0 7 4785 #endif 4786 4787 4788 #if (UC_DEVICE == XMC4800) && (UC_PACKAGE == LQFP144) 4789 #define CCU40_IN0_CAN0_SR7 7 4790 #define CCU40_IN0_CCU40_ST0 12 4791 #define CCU40_IN0_CCU40_ST1 13 4792 #define CCU40_IN0_CCU40_ST2 14 4793 #define CCU40_IN0_CCU40_ST3 15 4794 #define CCU40_IN0_ERU1_PDOUT0 9 4795 #define CCU40_IN0_ERU1_PDOUT1 3 4796 #define CCU40_IN0_P1_3 0 4797 #define CCU40_IN0_P2_1 2 4798 #define CCU40_IN0_P2_8 1 4799 #define CCU40_IN0_POSIF0_OUT0 4 4800 #define CCU40_IN0_POSIF0_OUT1 5 4801 #define CCU40_IN0_POSIF0_OUT3 6 4802 #define CCU40_IN0_SCU_ERU1_IOUT0 10 4803 #define CCU40_IN0_SCU_GSC40 8 4804 #define CCU40_IN0_U0C0_DX2INS 11 4805 #define CCU40_IN1_CCU40_ST0 12 4806 #define CCU40_IN1_CCU40_ST1 13 4807 #define CCU40_IN1_CCU40_ST2 14 4808 #define CCU40_IN1_CCU40_ST3 15 4809 #define CCU40_IN1_ERU1_PDOUT0 3 4810 #define CCU40_IN1_ERU1_PDOUT1 9 4811 #define CCU40_IN1_P1_2 0 4812 #define CCU40_IN1_P2_0 2 4813 #define CCU40_IN1_P2_8 1 4814 #define CCU40_IN1_POSIF0_OUT0 4 4815 #define CCU40_IN1_POSIF0_OUT1 5 4816 #define CCU40_IN1_POSIF0_OUT2 11 4817 #define CCU40_IN1_POSIF0_OUT3 6 4818 #define CCU40_IN1_POSIF0_OUT4 7 4819 #define CCU40_IN1_SCU_ERU1_IOUT1 10 4820 #define CCU40_IN1_SCU_GSC40 8 4821 #define CCU40_IN2_CCU40_ST0 12 4822 #define CCU40_IN2_CCU40_ST1 13 4823 #define CCU40_IN2_CCU40_ST2 14 4824 #define CCU40_IN2_CCU40_ST3 15 4825 #define CCU40_IN2_ERU1_PDOUT0 3 4826 #define CCU40_IN2_ERU1_PDOUT2 9 4827 #define CCU40_IN2_P1_1 0 4828 #define CCU40_IN2_P2_7 2 4829 #define CCU40_IN2_P2_8 1 4830 #define CCU40_IN2_POSIF0_OUT0 4 4831 #define CCU40_IN2_POSIF0_OUT2 5 4832 #define CCU40_IN2_POSIF0_OUT3 6 4833 #define CCU40_IN2_POSIF0_OUT4 7 4834 #define CCU40_IN2_SCU_ERU1_IOUT2 10 4835 #define CCU40_IN2_SCU_GSC40 8 4836 #define CCU40_IN2_U0C1_DX2INS 11 4837 #define CCU40_IN3_CCU40_ST0 12 4838 #define CCU40_IN3_CCU40_ST1 13 4839 #define CCU40_IN3_CCU40_ST2 14 4840 #define CCU40_IN3_CCU40_ST3 15 4841 #define CCU40_IN3_CCU80_IGBTO 7 4842 #define CCU40_IN3_ERU1_PDOUT0 3 4843 #define CCU40_IN3_ERU1_PDOUT3 9 4844 #define CCU40_IN3_P1_0 0 4845 #define CCU40_IN3_P2_6 2 4846 #define CCU40_IN3_P2_8 1 4847 #define CCU40_IN3_POSIF0_OUT3 4 4848 #define CCU40_IN3_POSIF0_OUT5 5 4849 #define CCU40_IN3_SCU_ERU1_IOUT3 10 4850 #define CCU40_IN3_SCU_GSC40 8 4851 #define CCU40_IN3_U1C0_DX2INS 11 4852 #define CCU40_IN3_VADC0_G0ARBCNT 6 4853 #define CCU41_IN0_CAN0_SR7 7 4854 #define CCU41_IN0_CCU41_ST0 12 4855 #define CCU41_IN0_CCU41_ST1 13 4856 #define CCU41_IN0_CCU41_ST2 14 4857 #define CCU41_IN0_CCU41_ST3 15 4858 #define CCU41_IN0_ERU1_PDOUT0 9 4859 #define CCU41_IN0_ERU1_PDOUT1 3 4860 #define CCU41_IN0_P1_4 2 4861 #define CCU41_IN0_P2_5 0 4862 #define CCU41_IN0_P2_9 1 4863 #define CCU41_IN0_POSIF1_OUT0 4 4864 #define CCU41_IN0_POSIF1_OUT1 5 4865 #define CCU41_IN0_POSIF1_OUT3 6 4866 #define CCU41_IN0_SCU_ERU1_IOUT0 10 4867 #define CCU41_IN0_SCU_GSC41 8 4868 #define CCU41_IN0_VADC0_G0BFL0 11 4869 #define CCU41_IN1_CCU41_ST0 12 4870 #define CCU41_IN1_CCU41_ST1 13 4871 #define CCU41_IN1_CCU41_ST2 14 4872 #define CCU41_IN1_CCU41_ST3 15 4873 #define CCU41_IN1_ERU1_PDOUT0 3 4874 #define CCU41_IN1_ERU1_PDOUT1 9 4875 #define CCU41_IN1_P1_5 2 4876 #define CCU41_IN1_P2_4 0 4877 #define CCU41_IN1_P2_9 1 4878 #define CCU41_IN1_POSIF1_OUT0 4 4879 #define CCU41_IN1_POSIF1_OUT1 5 4880 #define CCU41_IN1_POSIF1_OUT2 11 4881 #define CCU41_IN1_POSIF1_OUT3 6 4882 #define CCU41_IN1_POSIF1_OUT4 7 4883 #define CCU41_IN1_SCU_ERU1_IOUT1 10 4884 #define CCU41_IN1_SCU_GSC41 8 4885 #define CCU41_IN2_CCU41_ST0 12 4886 #define CCU41_IN2_CCU41_ST1 13 4887 #define CCU41_IN2_CCU41_ST2 14 4888 #define CCU41_IN2_CCU41_ST3 15 4889 #define CCU41_IN2_ERU1_PDOUT0 3 4890 #define CCU41_IN2_ERU1_PDOUT2 9 4891 #define CCU41_IN2_P1_10 2 4892 #define CCU41_IN2_P2_3 0 4893 #define CCU41_IN2_P2_9 1 4894 #define CCU41_IN2_POSIF1_OUT0 4 4895 #define CCU41_IN2_POSIF1_OUT2 5 4896 #define CCU41_IN2_POSIF1_OUT3 6 4897 #define CCU41_IN2_POSIF1_OUT4 7 4898 #define CCU41_IN2_SCU_ERU1_IOUT2 10 4899 #define CCU41_IN2_SCU_GSC41 8 4900 #define CCU41_IN2_VADC0_G0BFL1 11 4901 #define CCU41_IN3_CCU41_ST0 12 4902 #define CCU41_IN3_CCU41_ST1 13 4903 #define CCU41_IN3_CCU41_ST2 14 4904 #define CCU41_IN3_CCU41_ST3 15 4905 #define CCU41_IN3_CCU81_IGBTO 7 4906 #define CCU41_IN3_ERU1_PDOUT0 3 4907 #define CCU41_IN3_ERU1_PDOUT3 9 4908 #define CCU41_IN3_P1_11 2 4909 #define CCU41_IN3_P2_2 0 4910 #define CCU41_IN3_P2_9 1 4911 #define CCU41_IN3_POSIF1_OUT3 4 4912 #define CCU41_IN3_POSIF1_OUT5 5 4913 #define CCU41_IN3_SCU_ERU1_IOUT3 10 4914 #define CCU41_IN3_SCU_GSC41 8 4915 #define CCU41_IN3_VADC0_G0BFL2 11 4916 #define CCU41_IN3_VADC0_G1ARBCNT 6 4917 #define CCU42_IN0_CCU42_ST0 12 4918 #define CCU42_IN0_CCU42_ST1 13 4919 #define CCU42_IN0_CCU42_ST2 14 4920 #define CCU42_IN0_CCU42_ST3 15 4921 #define CCU42_IN0_CCU80_IGBTO 7 4922 #define CCU42_IN0_ERU1_PDOUT0 9 4923 #define CCU42_IN0_ERU1_PDOUT1 3 4924 #define CCU42_IN0_P2_15 1 4925 #define CCU42_IN0_P3_15 2 4926 #define CCU42_IN0_P3_6 0 4927 #define CCU42_IN0_POSIF0_OUT2 4 4928 #define CCU42_IN0_POSIF0_OUT5 5 4929 #define CCU42_IN0_SCU_ERU1_IOUT0 10 4930 #define CCU42_IN0_SCU_GSC42 8 4931 #define CCU42_IN0_U0C0_DX2INS 11 4932 #define CCU42_IN1_CCU42_ST0 12 4933 #define CCU42_IN1_CCU42_ST1 13 4934 #define CCU42_IN1_CCU42_ST2 14 4935 #define CCU42_IN1_CCU42_ST3 15 4936 #define CCU42_IN1_ERU1_PDOUT0 3 4937 #define CCU42_IN1_ERU1_PDOUT1 9 4938 #define CCU42_IN1_P2_15 1 4939 #define CCU42_IN1_P3_14 2 4940 #define CCU42_IN1_P3_5 0 4941 #define CCU42_IN1_POSIF0_OUT2 4 4942 #define CCU42_IN1_POSIF0_OUT5 5 4943 #define CCU42_IN1_SCU_ERU1_IOUT1 10 4944 #define CCU42_IN1_SCU_GSC42 8 4945 #define CCU42_IN1_U0C1_DX2INS 11 4946 #define CCU42_IN2_CAN0_SR7 6 4947 #define CCU42_IN2_CCU42_ST0 12 4948 #define CCU42_IN2_CCU42_ST1 13 4949 #define CCU42_IN2_CCU42_ST2 14 4950 #define CCU42_IN2_CCU42_ST3 15 4951 #define CCU42_IN2_ERU1_PDOUT0 3 4952 #define CCU42_IN2_ERU1_PDOUT2 9 4953 #define CCU42_IN2_P0_15 2 4954 #define CCU42_IN2_P2_15 1 4955 #define CCU42_IN2_P3_4 0 4956 #define CCU42_IN2_POSIF0_OUT2 4 4957 #define CCU42_IN2_POSIF0_OUT5 5 4958 #define CCU42_IN2_SCU_ERU1_IOUT2 10 4959 #define CCU42_IN2_SCU_GSC42 8 4960 #define CCU42_IN2_U1C0_DX2INS 11 4961 #define CCU42_IN3_CCU42_ST0 12 4962 #define CCU42_IN3_CCU42_ST1 13 4963 #define CCU42_IN3_CCU42_ST2 14 4964 #define CCU42_IN3_CCU42_ST3 15 4965 #define CCU42_IN3_ERU1_PDOUT0 3 4966 #define CCU42_IN3_ERU1_PDOUT3 9 4967 #define CCU42_IN3_P0_14 2 4968 #define CCU42_IN3_P2_15 1 4969 #define CCU42_IN3_P3_3 0 4970 #define CCU42_IN3_POSIF0_OUT2 4 4971 #define CCU42_IN3_POSIF0_OUT5 5 4972 #define CCU42_IN3_SCU_ERU1_IOUT3 10 4973 #define CCU42_IN3_SCU_GSC42 8 4974 #define CCU42_IN3_U1C1_DX2INS 11 4975 #define CCU42_IN3_VADC0_G2ARBCNT 6 4976 #define CCU43_IN0_CCU43_ST0 12 4977 #define CCU43_IN0_CCU43_ST1 13 4978 #define CCU43_IN0_CCU43_ST2 14 4979 #define CCU43_IN0_CCU43_ST3 15 4980 #define CCU43_IN0_CCU81_IGBTO 6 4981 #define CCU43_IN0_ERU1_PDOUT0 9 4982 #define CCU43_IN0_ERU1_PDOUT1 3 4983 #define CCU43_IN0_P2_14 1 4984 #define CCU43_IN0_P4_6 0 4985 #define CCU43_IN0_P4_7 2 4986 #define CCU43_IN0_POSIF1_OUT2 4 4987 #define CCU43_IN0_POSIF1_OUT5 5 4988 #define CCU43_IN0_SCU_ERU1_IOUT0 10 4989 #define CCU43_IN0_SCU_GSC43 8 4990 #define CCU43_IN0_U0C0_DX2INS 11 4991 #define CCU43_IN0_VADC0_G0BFL0 7 4992 #define CCU43_IN1_CAN0_SR7 6 4993 #define CCU43_IN1_CCU43_ST0 12 4994 #define CCU43_IN1_CCU43_ST1 13 4995 #define CCU43_IN1_CCU43_ST2 14 4996 #define CCU43_IN1_CCU43_ST3 15 4997 #define CCU43_IN1_ERU1_PDOUT0 3 4998 #define CCU43_IN1_ERU1_PDOUT1 9 4999 #define CCU43_IN1_P2_14 1 5000 #define CCU43_IN1_P4_2 2 5001 #define CCU43_IN1_P4_5 0 5002 #define CCU43_IN1_POSIF1_OUT2 4 5003 #define CCU43_IN1_POSIF1_OUT5 5 5004 #define CCU43_IN1_SCU_ERU1_IOUT1 10 5005 #define CCU43_IN1_SCU_GSC43 8 5006 #define CCU43_IN1_U0C1_DX2INS 11 5007 #define CCU43_IN1_VADC0_G1BFL0 7 5008 #define CCU43_IN2_CCU43_ST0 12 5009 #define CCU43_IN2_CCU43_ST1 13 5010 #define CCU43_IN2_CCU43_ST2 14 5011 #define CCU43_IN2_CCU43_ST3 15 5012 #define CCU43_IN2_ERU1_PDOUT0 3 5013 #define CCU43_IN2_ERU1_PDOUT2 9 5014 #define CCU43_IN2_P2_13 2 5015 #define CCU43_IN2_P2_14 1 5016 #define CCU43_IN2_P4_4 0 5017 #define CCU43_IN2_POSIF1_OUT2 4 5018 #define CCU43_IN2_POSIF1_OUT5 5 5019 #define CCU43_IN2_SCU_ERU1_IOUT2 10 5020 #define CCU43_IN2_SCU_GSC43 8 5021 #define CCU43_IN2_U1C0_DX2INS 11 5022 #define CCU43_IN2_VADC0_G2BFL0 7 5023 #define CCU43_IN3_CCU43_ST0 12 5024 #define CCU43_IN3_CCU43_ST1 13 5025 #define CCU43_IN3_CCU43_ST2 14 5026 #define CCU43_IN3_CCU43_ST3 15 5027 #define CCU43_IN3_ERU1_PDOUT0 3 5028 #define CCU43_IN3_ERU1_PDOUT3 9 5029 #define CCU43_IN3_P2_12 2 5030 #define CCU43_IN3_P2_14 1 5031 #define CCU43_IN3_P4_3 0 5032 #define CCU43_IN3_POSIF1_OUT2 4 5033 #define CCU43_IN3_POSIF1_OUT5 5 5034 #define CCU43_IN3_SCU_ERU1_IOUT3 10 5035 #define CCU43_IN3_SCU_GSC43 8 5036 #define CCU43_IN3_U1C1_DX2INS 11 5037 #define CCU43_IN3_VADC0_G3ARBCNT 6 5038 #define CCU43_IN3_VADC0_G3BFL0 7 5039 #endif 5040 5041 #endif /* XMC4_CCU4_MAP_H */ 5042
