1 /** 2 * @file xmc1_eru_map.h 3 * @date 2019-07-30 4 * 5 * @cond 6 ********************************************************************************************************************* 7 * XMClib v2.1.24 - XMC Peripheral Driver Library 8 * 9 * Copyright (c) 2015-2019, Infineon Technologies AG 10 * All rights reserved. 11 * 12 * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 13 * following conditions are met: 14 * 15 * Redistributions of source code must retain the above copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following 19 * disclaimer in the documentation and/or other materials provided with the distribution. 20 * 21 * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote 22 * products derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, 25 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with 33 * Infineon Technologies AG dave@infineon.com). 34 ********************************************************************************************************************* 35 * 36 * Change History 37 * -------------- 38 * 39 * 2015-02-20: 40 * - Initial version 41 * 42 * 2015-08-25: 43 * - Added support for XMC1400 devices 44 * 45 * 2019-07-30: 46 * - Added support for XMC1404-Q040 47 * 48 * @endcond 49 */ 50 #ifndef XMC1_ERU_MAP_H 51 #define XMC1_ERU_MAP_H 52 53 /********************************************************************************************************************* 54 * MACROS 55 *********************************************************************************************************************/ 56 #define ERU0_ETL0 XMC_ERU0, 0 57 #define ERU0_ETL1 XMC_ERU0, 1 58 #define ERU0_ETL2 XMC_ERU0, 2 59 #define ERU0_ETL3 XMC_ERU0, 3 60 61 #define ERU0_OGU0 XMC_ERU0, 0 62 #define ERU0_OGU1 XMC_ERU0, 1 63 #define ERU0_OGU2 XMC_ERU0, 2 64 #define ERU0_OGU3 XMC_ERU0, 3 65 66 #if defined(ERU1) 67 #define ERU1_ETL0 XMC_ERU1, 0 68 #define ERU1_ETL1 XMC_ERU1, 1 69 #define ERU1_ETL2 XMC_ERU1, 2 70 #define ERU1_ETL3 XMC_ERU1, 3 71 72 #define ERU1_OGU0 XMC_ERU1, 0 73 #define ERU1_OGU1 XMC_ERU1, 1 74 #define ERU1_OGU2 XMC_ERU1, 2 75 #define ERU1_OGU3 XMC_ERU1, 3 76 #endif 77 78 #if (UC_DEVICE == XMC1100) && (UC_PACKAGE == VQFN24) 79 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 80 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1 81 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 82 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 83 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 84 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 85 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 86 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 87 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 88 89 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 90 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 91 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 92 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 93 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 94 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 95 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 96 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 97 #endif 98 99 100 #if (UC_DEVICE == XMC1100) && (UC_PACKAGE == VQFN40) 101 #define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1 102 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 103 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1 104 #define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1 105 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 106 #define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1 107 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 108 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 109 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 110 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 111 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 112 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 113 114 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 115 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 116 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 117 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 118 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 119 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 120 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 121 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 122 #endif 123 124 125 #if (UC_DEVICE == XMC1100) && (UC_PACKAGE == TSSOP16) 126 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 127 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 128 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 129 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 130 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 131 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 132 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 133 134 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 135 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 136 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 137 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 138 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 139 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 140 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 141 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 142 #endif 143 144 145 #if (UC_DEVICE == XMC1100) && (UC_PACKAGE == TSSOP38) 146 #define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1 147 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 148 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1 149 #define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1 150 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 151 #define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1 152 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 153 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 154 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 155 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 156 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 157 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 158 159 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 160 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 161 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 162 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 163 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 164 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 165 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 166 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 167 #endif 168 169 170 #if (UC_DEVICE == XMC1200) && (UC_PACKAGE == TSSOP38) 171 #define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0 172 #define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2 173 #define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1 174 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3 175 #define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2 176 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 177 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1 178 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3 179 #define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0 180 #define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2 181 #define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1 182 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3 183 #define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2 184 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 185 #define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1 186 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3 187 #define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0 188 #define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2 189 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 190 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3 191 #define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2 192 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 193 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 194 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3 195 #define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2 196 #define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0 197 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 198 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3 199 #define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2 200 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 201 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 202 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3 203 204 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 205 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 206 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 207 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 208 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 209 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 210 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 211 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 212 #endif 213 214 215 #if (UC_DEVICE == XMC1201) && (UC_PACKAGE == VQFN40) 216 #define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2 217 #define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1 218 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3 219 #define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2 220 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 221 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1 222 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3 223 #define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2 224 #define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1 225 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3 226 #define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2 227 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 228 #define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1 229 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3 230 #define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2 231 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 232 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3 233 #define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2 234 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 235 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 236 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3 237 #define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2 238 #define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0 239 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 240 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3 241 #define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2 242 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 243 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 244 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3 245 246 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 247 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 248 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 249 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 250 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 251 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 252 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 253 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 254 #endif 255 256 257 #if (UC_DEVICE == XMC1201) && (UC_PACKAGE == TSSOP28) 258 #define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2 259 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3 260 #define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2 261 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 262 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1 263 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3 264 #define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2 265 #define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1 266 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3 267 #define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2 268 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 269 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3 270 #define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2 271 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 272 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3 273 #define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2 274 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 275 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 276 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3 277 #define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2 278 #define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0 279 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 280 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3 281 #define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2 282 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 283 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 284 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3 285 286 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 287 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 288 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 289 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 290 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 291 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 292 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 293 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 294 #endif 295 296 297 #if (UC_DEVICE == XMC1201) && (UC_PACKAGE == TSSOP38) 298 #define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2 299 #define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1 300 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3 301 #define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2 302 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 303 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1 304 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3 305 #define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2 306 #define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1 307 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3 308 #define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2 309 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 310 #define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1 311 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3 312 #define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2 313 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 314 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3 315 #define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2 316 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 317 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 318 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3 319 #define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2 320 #define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0 321 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 322 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3 323 #define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2 324 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 325 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 326 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3 327 328 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 329 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 330 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 331 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 332 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 333 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 334 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 335 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 336 #endif 337 338 339 #if (UC_DEVICE == XMC1202) && (UC_PACKAGE == VQFN24) 340 #define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0 341 #define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2 342 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3 343 #define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2 344 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 345 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1 346 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3 347 #define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0 348 #define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2 349 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3 350 #define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2 351 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 352 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3 353 #define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0 354 #define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2 355 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 356 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3 357 #define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2 358 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 359 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 360 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3 361 #define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2 362 #define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0 363 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 364 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3 365 #define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2 366 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 367 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 368 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3 369 370 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 371 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 372 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 373 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 374 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 375 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 376 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 377 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 378 #endif 379 380 381 #if (UC_DEVICE == XMC1202) && (UC_PACKAGE == VQFN40) 382 #define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0 383 #define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2 384 #define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1 385 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3 386 #define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2 387 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 388 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1 389 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3 390 #define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0 391 #define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2 392 #define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1 393 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3 394 #define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2 395 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 396 #define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1 397 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3 398 #define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0 399 #define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2 400 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 401 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3 402 #define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2 403 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 404 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 405 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3 406 #define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2 407 #define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0 408 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 409 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3 410 #define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2 411 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 412 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 413 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3 414 415 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 416 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 417 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 418 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 419 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 420 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 421 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 422 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 423 #endif 424 425 426 #if (UC_DEVICE == XMC1202) && (UC_PACKAGE == TSSOP16) 427 #define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0 428 #define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2 429 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3 430 #define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2 431 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 432 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3 433 #define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0 434 #define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2 435 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3 436 #define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2 437 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3 438 #define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2 439 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 440 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3 441 #define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2 442 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 443 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 444 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3 445 #define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2 446 #define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0 447 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 448 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3 449 #define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2 450 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 451 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 452 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3 453 454 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 455 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 456 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 457 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 458 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 459 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 460 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 461 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 462 #endif 463 464 465 #if (UC_DEVICE == XMC1202) && (UC_PACKAGE == TSSOP28) 466 #define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0 467 #define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2 468 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3 469 #define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2 470 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 471 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1 472 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3 473 #define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0 474 #define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2 475 #define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1 476 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3 477 #define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2 478 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 479 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3 480 #define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0 481 #define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2 482 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 483 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3 484 #define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2 485 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 486 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 487 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3 488 #define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2 489 #define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0 490 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 491 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3 492 #define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2 493 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 494 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 495 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3 496 497 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 498 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 499 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 500 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 501 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 502 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 503 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 504 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 505 #endif 506 507 508 #if (UC_DEVICE == XMC1301) && (UC_PACKAGE == VQFN24) 509 #define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0 510 #define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2 511 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3 512 #define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2 513 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 514 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1 515 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3 516 #define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0 517 #define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2 518 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3 519 #define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2 520 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 521 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3 522 #define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0 523 #define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2 524 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 525 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3 526 #define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2 527 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 528 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 529 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3 530 #define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2 531 #define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0 532 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 533 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3 534 #define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2 535 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 536 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 537 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3 538 539 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 540 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 541 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 542 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 543 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 544 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 545 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 546 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 547 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 548 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 549 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 550 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 551 #endif 552 553 554 #if (UC_DEVICE == XMC1301) && (UC_PACKAGE == VQFN40) 555 #define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0 556 #define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2 557 #define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1 558 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3 559 #define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2 560 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 561 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1 562 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3 563 #define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0 564 #define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2 565 #define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1 566 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3 567 #define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2 568 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 569 #define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1 570 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3 571 #define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0 572 #define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2 573 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 574 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3 575 #define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2 576 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 577 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 578 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3 579 #define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2 580 #define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0 581 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 582 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3 583 #define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2 584 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 585 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 586 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3 587 588 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 589 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 590 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 591 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 592 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 593 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 594 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 595 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 596 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 597 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 598 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 599 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 600 #endif 601 602 603 #if (UC_DEVICE == XMC1301) && (UC_PACKAGE == TSSOP16) 604 #define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0 605 #define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2 606 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3 607 #define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2 608 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 609 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3 610 #define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0 611 #define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2 612 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3 613 #define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2 614 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3 615 #define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2 616 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 617 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3 618 #define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2 619 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 620 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 621 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3 622 #define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2 623 #define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0 624 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 625 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3 626 #define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2 627 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 628 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 629 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3 630 631 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 632 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 633 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 634 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 635 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 636 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 637 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 638 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 639 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 640 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 641 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 642 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 643 #endif 644 645 646 #if (UC_DEVICE == XMC1301) && (UC_PACKAGE == TSSOP38) 647 #define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0 648 #define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2 649 #define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1 650 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3 651 #define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2 652 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 653 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1 654 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3 655 #define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0 656 #define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2 657 #define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1 658 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3 659 #define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2 660 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 661 #define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1 662 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3 663 #define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0 664 #define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2 665 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 666 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3 667 #define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2 668 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 669 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 670 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3 671 #define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2 672 #define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0 673 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 674 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3 675 #define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2 676 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 677 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 678 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3 679 680 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 681 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 682 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 683 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 684 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 685 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 686 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 687 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 688 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 689 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 690 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 691 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 692 #endif 693 694 695 #if (UC_DEVICE == XMC1302) && (UC_PACKAGE == VQFN24) 696 #define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0 697 #define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2 698 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3 699 #define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2 700 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 701 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1 702 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3 703 #define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0 704 #define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2 705 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3 706 #define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2 707 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 708 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3 709 #define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0 710 #define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2 711 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 712 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3 713 #define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2 714 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 715 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 716 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3 717 #define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2 718 #define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0 719 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 720 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3 721 #define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2 722 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 723 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 724 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3 725 726 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 727 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 728 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 729 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 730 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 731 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 732 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 733 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 734 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 735 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 736 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 737 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 738 #endif 739 740 741 #if (UC_DEVICE == XMC1302) && (UC_PACKAGE == VQFN40) 742 #define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0 743 #define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2 744 #define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1 745 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3 746 #define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2 747 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 748 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1 749 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3 750 #define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0 751 #define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2 752 #define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1 753 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3 754 #define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2 755 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 756 #define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1 757 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3 758 #define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0 759 #define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2 760 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 761 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3 762 #define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2 763 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 764 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 765 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3 766 #define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2 767 #define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0 768 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 769 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3 770 #define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2 771 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 772 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 773 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3 774 775 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 776 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 777 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 778 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 779 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 780 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 781 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 782 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 783 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 784 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 785 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 786 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 787 #endif 788 789 790 #if (UC_DEVICE == XMC1302) && (UC_PACKAGE == TSSOP16) 791 #define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0 792 #define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2 793 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3 794 #define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2 795 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 796 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3 797 #define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0 798 #define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2 799 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3 800 #define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2 801 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3 802 #define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2 803 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 804 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3 805 #define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2 806 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 807 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 808 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3 809 #define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2 810 #define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0 811 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 812 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3 813 #define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2 814 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 815 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 816 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3 817 818 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 819 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 820 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 821 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 822 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 823 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 824 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 825 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 826 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 827 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 828 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 829 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 830 #endif 831 832 833 #if (UC_DEVICE == XMC1302) && (UC_PACKAGE == TSSOP28) 834 #define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0 835 #define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2 836 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3 837 #define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2 838 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 839 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1 840 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3 841 #define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0 842 #define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2 843 #define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1 844 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3 845 #define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2 846 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 847 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3 848 #define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0 849 #define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2 850 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 851 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3 852 #define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2 853 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 854 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 855 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3 856 #define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2 857 #define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0 858 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 859 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3 860 #define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2 861 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 862 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 863 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3 864 865 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 866 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 867 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 868 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 869 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 870 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 871 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 872 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 873 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 874 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 875 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 876 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 877 #endif 878 879 880 #if (UC_DEVICE == XMC1302) && (UC_PACKAGE == TSSOP38) 881 #define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0 882 #define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2 883 #define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1 884 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3 885 #define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2 886 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 887 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1 888 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3 889 #define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0 890 #define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2 891 #define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1 892 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3 893 #define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2 894 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 895 #define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1 896 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3 897 #define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0 898 #define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2 899 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 900 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3 901 #define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2 902 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 903 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 904 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3 905 #define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2 906 #define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0 907 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 908 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3 909 #define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2 910 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 911 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 912 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3 913 914 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 915 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 916 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 917 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 918 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 919 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 920 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 921 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 922 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 923 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 924 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 925 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 926 #endif 927 928 929 #if (UC_DEVICE == XMC1401) && (UC_PACKAGE == LQFP64) 930 #define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1 931 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3 932 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 933 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1 934 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3 935 #define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1 936 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3 937 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 938 #define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1 939 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3 940 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 941 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3 942 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 943 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 944 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3 945 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 946 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3 947 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 948 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 949 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3 950 #define ERU1_ETL0_INPUTA_P3_0 XMC_ERU_ETL_INPUT_A1 951 #define ERU1_ETL0_INPUTA_P4_4 XMC_ERU_ETL_INPUT_A2 952 #define ERU1_ETL0_INPUTA_P4_7 XMC_ERU_ETL_INPUT_A3 953 #define ERU1_ETL0_INPUTB_CCU40_ST0 XMC_ERU_ETL_INPUT_B0 954 #define ERU1_ETL0_INPUTB_CCU41_ST0 XMC_ERU_ETL_INPUT_B1 955 #define ERU1_ETL0_INPUTB_CCU81_ST0 XMC_ERU_ETL_INPUT_B3 956 #define ERU1_ETL1_INPUTA_P3_1 XMC_ERU_ETL_INPUT_A1 957 #define ERU1_ETL1_INPUTA_P3_3 XMC_ERU_ETL_INPUT_A3 958 #define ERU1_ETL1_INPUTA_P4_5 XMC_ERU_ETL_INPUT_A2 959 #define ERU1_ETL1_INPUTB_CCU40_ST1 XMC_ERU_ETL_INPUT_B0 960 #define ERU1_ETL1_INPUTB_CCU41_ST1 XMC_ERU_ETL_INPUT_B1 961 #define ERU1_ETL1_INPUTB_CCU81_ST3 XMC_ERU_ETL_INPUT_B3 962 #define ERU1_ETL2_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 963 #define ERU1_ETL2_INPUTA_P3_4 XMC_ERU_ETL_INPUT_A3 964 #define ERU1_ETL2_INPUTA_P4_6 XMC_ERU_ETL_INPUT_A2 965 #define ERU1_ETL2_INPUTB_CCU40_ST2 XMC_ERU_ETL_INPUT_B0 966 #define ERU1_ETL2_INPUTB_CCU41_ST2 XMC_ERU_ETL_INPUT_B1 967 #define ERU1_ETL2_INPUTB_CCU81_ST1 XMC_ERU_ETL_INPUT_B3 968 #define ERU1_ETL3_INPUTA_P2_12 XMC_ERU_ETL_INPUT_A2 969 #define ERU1_ETL3_INPUTA_P2_13 XMC_ERU_ETL_INPUT_A3 970 #define ERU1_ETL3_INPUTB_CCU40_ST3 XMC_ERU_ETL_INPUT_B0 971 #define ERU1_ETL3_INPUTB_CCU41_ST3 XMC_ERU_ETL_INPUT_B1 972 973 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 974 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 975 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 976 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 977 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 978 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 979 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 980 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 981 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU41_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 982 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 983 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU41_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 984 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU41_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 985 #endif 986 987 988 #if (UC_DEVICE == XMC1401) && (UC_PACKAGE == VQFN48) 989 #define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1 990 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3 991 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 992 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1 993 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3 994 #define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1 995 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3 996 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 997 #define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1 998 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3 999 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 1000 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3 1001 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 1002 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 1003 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3 1004 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 1005 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3 1006 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 1007 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 1008 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3 1009 #define ERU1_ETL0_INPUTA_P3_0 XMC_ERU_ETL_INPUT_A1 1010 #define ERU1_ETL0_INPUTA_P4_4 XMC_ERU_ETL_INPUT_A2 1011 #define ERU1_ETL0_INPUTA_P4_7 XMC_ERU_ETL_INPUT_A3 1012 #define ERU1_ETL0_INPUTB_CCU40_ST0 XMC_ERU_ETL_INPUT_B0 1013 #define ERU1_ETL0_INPUTB_CCU41_ST0 XMC_ERU_ETL_INPUT_B1 1014 #define ERU1_ETL1_INPUTA_P4_5 XMC_ERU_ETL_INPUT_A2 1015 #define ERU1_ETL1_INPUTB_CCU40_ST1 XMC_ERU_ETL_INPUT_B0 1016 #define ERU1_ETL1_INPUTB_CCU41_ST1 XMC_ERU_ETL_INPUT_B1 1017 #define ERU1_ETL2_INPUTA_P4_6 XMC_ERU_ETL_INPUT_A2 1018 #define ERU1_ETL2_INPUTB_CCU40_ST2 XMC_ERU_ETL_INPUT_B0 1019 #define ERU1_ETL2_INPUTB_CCU41_ST2 XMC_ERU_ETL_INPUT_B1 1020 #define ERU1_ETL3_INPUTA_P2_12 XMC_ERU_ETL_INPUT_A2 1021 #define ERU1_ETL3_INPUTA_P2_13 XMC_ERU_ETL_INPUT_A3 1022 #define ERU1_ETL3_INPUTB_CCU40_ST3 XMC_ERU_ETL_INPUT_B0 1023 #define ERU1_ETL3_INPUTB_CCU41_ST3 XMC_ERU_ETL_INPUT_B1 1024 1025 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1026 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1027 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1028 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1029 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1030 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1031 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1032 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1033 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU41_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1034 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1035 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU41_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1036 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU41_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1037 #endif 1038 1039 1040 #if (UC_DEVICE == XMC1402) && (UC_PACKAGE == LQFP64) 1041 #define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0 1042 #define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2 1043 #define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1 1044 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3 1045 #define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2 1046 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 1047 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1 1048 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3 1049 #define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0 1050 #define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2 1051 #define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1 1052 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3 1053 #define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2 1054 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 1055 #define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1 1056 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3 1057 #define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0 1058 #define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2 1059 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 1060 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3 1061 #define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2 1062 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 1063 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 1064 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3 1065 #define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2 1066 #define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0 1067 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 1068 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3 1069 #define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2 1070 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 1071 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 1072 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3 1073 #define ERU1_ETL0_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0 1074 #define ERU1_ETL0_INPUTA_P3_0 XMC_ERU_ETL_INPUT_A1 1075 #define ERU1_ETL0_INPUTA_P4_4 XMC_ERU_ETL_INPUT_A2 1076 #define ERU1_ETL0_INPUTA_P4_7 XMC_ERU_ETL_INPUT_A3 1077 #define ERU1_ETL0_INPUTB_CCU40_ST0 XMC_ERU_ETL_INPUT_B0 1078 #define ERU1_ETL0_INPUTB_CCU41_ST0 XMC_ERU_ETL_INPUT_B1 1079 #define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B2 1080 #define ERU1_ETL0_INPUTB_CCU81_ST0 XMC_ERU_ETL_INPUT_B3 1081 #define ERU1_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A0 1082 #define ERU1_ETL1_INPUTA_P3_1 XMC_ERU_ETL_INPUT_A1 1083 #define ERU1_ETL1_INPUTA_P3_3 XMC_ERU_ETL_INPUT_A3 1084 #define ERU1_ETL1_INPUTA_P4_5 XMC_ERU_ETL_INPUT_A2 1085 #define ERU1_ETL1_INPUTB_CCU40_ST1 XMC_ERU_ETL_INPUT_B0 1086 #define ERU1_ETL1_INPUTB_CCU41_ST1 XMC_ERU_ETL_INPUT_B1 1087 #define ERU1_ETL1_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B2 1088 #define ERU1_ETL1_INPUTB_CCU81_ST3 XMC_ERU_ETL_INPUT_B3 1089 #define ERU1_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0 1090 #define ERU1_ETL2_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 1091 #define ERU1_ETL2_INPUTA_P3_4 XMC_ERU_ETL_INPUT_A3 1092 #define ERU1_ETL2_INPUTA_P4_6 XMC_ERU_ETL_INPUT_A2 1093 #define ERU1_ETL2_INPUTB_CCU40_ST2 XMC_ERU_ETL_INPUT_B0 1094 #define ERU1_ETL2_INPUTB_CCU41_ST2 XMC_ERU_ETL_INPUT_B1 1095 #define ERU1_ETL2_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B2 1096 #define ERU1_ETL2_INPUTB_CCU81_ST1 XMC_ERU_ETL_INPUT_B3 1097 #define ERU1_ETL3_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0 1098 #define ERU1_ETL3_INPUTA_P2_12 XMC_ERU_ETL_INPUT_A2 1099 #define ERU1_ETL3_INPUTA_P2_13 XMC_ERU_ETL_INPUT_A3 1100 #define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 1101 #define ERU1_ETL3_INPUTB_CCU40_ST3 XMC_ERU_ETL_INPUT_B0 1102 #define ERU1_ETL3_INPUTB_CCU41_ST3 XMC_ERU_ETL_INPUT_B1 1103 #define ERU1_ETL3_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B2 1104 #define ERU1_ETL3_INPUTB_CCU81_ST2 XMC_ERU_ETL_INPUT_B3 1105 1106 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1107 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1108 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1109 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1110 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1111 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1112 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1113 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1114 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1115 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1116 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1117 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1118 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU41_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1119 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU81_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1120 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1121 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU81_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1122 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU41_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1123 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1124 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU41_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1125 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1126 #endif 1127 1128 1129 #if (UC_DEVICE == XMC1402) && (UC_PACKAGE == VQFN40) 1130 #define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0 1131 #define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2 1132 #define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1 1133 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3 1134 #define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2 1135 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 1136 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1 1137 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3 1138 #define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0 1139 #define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2 1140 #define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1 1141 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3 1142 #define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2 1143 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 1144 #define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1 1145 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3 1146 #define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0 1147 #define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2 1148 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 1149 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3 1150 #define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2 1151 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 1152 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 1153 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3 1154 #define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2 1155 #define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0 1156 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 1157 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3 1158 #define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2 1159 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 1160 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 1161 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3 1162 #define ERU1_ETL0_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0 1163 #define ERU1_ETL0_INPUTB_CCU40_ST0 XMC_ERU_ETL_INPUT_B0 1164 #define ERU1_ETL0_INPUTB_CCU41_ST0 XMC_ERU_ETL_INPUT_B1 1165 #define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B2 1166 #define ERU1_ETL0_INPUTB_CCU81_ST0 XMC_ERU_ETL_INPUT_B3 1167 #define ERU1_ETL1_INPUTB_CCU40_ST1 XMC_ERU_ETL_INPUT_B0 1168 #define ERU1_ETL1_INPUTB_CCU41_ST1 XMC_ERU_ETL_INPUT_B1 1169 #define ERU1_ETL1_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B2 1170 #define ERU1_ETL1_INPUTB_CCU81_ST3 XMC_ERU_ETL_INPUT_B3 1171 #define ERU1_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0 1172 #define ERU1_ETL2_INPUTB_CCU40_ST2 XMC_ERU_ETL_INPUT_B0 1173 #define ERU1_ETL2_INPUTB_CCU41_ST2 XMC_ERU_ETL_INPUT_B1 1174 #define ERU1_ETL2_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B2 1175 #define ERU1_ETL2_INPUTB_CCU81_ST1 XMC_ERU_ETL_INPUT_B3 1176 #define ERU1_ETL3_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0 1177 #define ERU1_ETL3_INPUTB_CCU40_ST3 XMC_ERU_ETL_INPUT_B0 1178 #define ERU1_ETL3_INPUTB_CCU41_ST3 XMC_ERU_ETL_INPUT_B1 1179 #define ERU1_ETL3_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B2 1180 #define ERU1_ETL3_INPUTB_CCU81_ST2 XMC_ERU_ETL_INPUT_B3 1181 1182 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1183 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1184 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1185 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1186 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1187 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1188 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1189 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1190 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1191 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1192 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1193 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1194 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU41_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1195 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU81_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1196 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1197 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU81_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1198 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU41_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1199 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1200 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU41_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1201 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1202 #endif 1203 1204 1205 #if (UC_DEVICE == XMC1402) && (UC_PACKAGE == VQFN48) 1206 #define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0 1207 #define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2 1208 #define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1 1209 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3 1210 #define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2 1211 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 1212 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1 1213 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3 1214 #define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0 1215 #define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2 1216 #define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1 1217 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3 1218 #define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2 1219 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 1220 #define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1 1221 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3 1222 #define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0 1223 #define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2 1224 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 1225 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3 1226 #define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2 1227 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 1228 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 1229 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3 1230 #define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2 1231 #define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0 1232 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 1233 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3 1234 #define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2 1235 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 1236 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 1237 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3 1238 #define ERU1_ETL0_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0 1239 #define ERU1_ETL0_INPUTA_P3_0 XMC_ERU_ETL_INPUT_A1 1240 #define ERU1_ETL0_INPUTA_P4_4 XMC_ERU_ETL_INPUT_A2 1241 #define ERU1_ETL0_INPUTA_P4_7 XMC_ERU_ETL_INPUT_A3 1242 #define ERU1_ETL0_INPUTB_CCU40_ST0 XMC_ERU_ETL_INPUT_B0 1243 #define ERU1_ETL0_INPUTB_CCU41_ST0 XMC_ERU_ETL_INPUT_B1 1244 #define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B2 1245 #define ERU1_ETL0_INPUTB_CCU81_ST0 XMC_ERU_ETL_INPUT_B3 1246 #define ERU1_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A0 1247 #define ERU1_ETL1_INPUTA_P4_5 XMC_ERU_ETL_INPUT_A2 1248 #define ERU1_ETL1_INPUTB_CCU40_ST1 XMC_ERU_ETL_INPUT_B0 1249 #define ERU1_ETL1_INPUTB_CCU41_ST1 XMC_ERU_ETL_INPUT_B1 1250 #define ERU1_ETL1_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B2 1251 #define ERU1_ETL1_INPUTB_CCU81_ST3 XMC_ERU_ETL_INPUT_B3 1252 #define ERU1_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0 1253 #define ERU1_ETL2_INPUTA_P4_6 XMC_ERU_ETL_INPUT_A2 1254 #define ERU1_ETL2_INPUTB_CCU40_ST2 XMC_ERU_ETL_INPUT_B0 1255 #define ERU1_ETL2_INPUTB_CCU41_ST2 XMC_ERU_ETL_INPUT_B1 1256 #define ERU1_ETL2_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B2 1257 #define ERU1_ETL2_INPUTB_CCU81_ST1 XMC_ERU_ETL_INPUT_B3 1258 #define ERU1_ETL3_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0 1259 #define ERU1_ETL3_INPUTA_P2_12 XMC_ERU_ETL_INPUT_A2 1260 #define ERU1_ETL3_INPUTA_P2_13 XMC_ERU_ETL_INPUT_A3 1261 #define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 1262 #define ERU1_ETL3_INPUTB_CCU40_ST3 XMC_ERU_ETL_INPUT_B0 1263 #define ERU1_ETL3_INPUTB_CCU41_ST3 XMC_ERU_ETL_INPUT_B1 1264 #define ERU1_ETL3_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B2 1265 #define ERU1_ETL3_INPUTB_CCU81_ST2 XMC_ERU_ETL_INPUT_B3 1266 1267 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1268 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1269 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1270 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1271 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1272 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1273 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1274 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1275 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1276 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1277 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1278 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1279 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU41_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1280 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU81_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1281 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1282 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU81_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1283 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU41_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1284 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1285 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU41_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1286 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1287 #endif 1288 1289 1290 #if (UC_DEVICE == XMC1402) && (UC_PACKAGE == VQFN64) 1291 #define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0 1292 #define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2 1293 #define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1 1294 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3 1295 #define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2 1296 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 1297 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1 1298 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3 1299 #define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0 1300 #define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2 1301 #define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1 1302 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3 1303 #define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2 1304 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 1305 #define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1 1306 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3 1307 #define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0 1308 #define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2 1309 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 1310 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3 1311 #define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2 1312 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 1313 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 1314 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3 1315 #define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2 1316 #define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0 1317 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 1318 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3 1319 #define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2 1320 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 1321 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 1322 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3 1323 #define ERU1_ETL0_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0 1324 #define ERU1_ETL0_INPUTA_P3_0 XMC_ERU_ETL_INPUT_A1 1325 #define ERU1_ETL0_INPUTA_P4_4 XMC_ERU_ETL_INPUT_A2 1326 #define ERU1_ETL0_INPUTA_P4_7 XMC_ERU_ETL_INPUT_A3 1327 #define ERU1_ETL0_INPUTB_CCU40_ST0 XMC_ERU_ETL_INPUT_B0 1328 #define ERU1_ETL0_INPUTB_CCU41_ST0 XMC_ERU_ETL_INPUT_B1 1329 #define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B2 1330 #define ERU1_ETL0_INPUTB_CCU81_ST0 XMC_ERU_ETL_INPUT_B3 1331 #define ERU1_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A0 1332 #define ERU1_ETL1_INPUTA_P3_1 XMC_ERU_ETL_INPUT_A1 1333 #define ERU1_ETL1_INPUTA_P3_3 XMC_ERU_ETL_INPUT_A3 1334 #define ERU1_ETL1_INPUTA_P4_5 XMC_ERU_ETL_INPUT_A2 1335 #define ERU1_ETL1_INPUTB_CCU40_ST1 XMC_ERU_ETL_INPUT_B0 1336 #define ERU1_ETL1_INPUTB_CCU41_ST1 XMC_ERU_ETL_INPUT_B1 1337 #define ERU1_ETL1_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B2 1338 #define ERU1_ETL1_INPUTB_CCU81_ST3 XMC_ERU_ETL_INPUT_B3 1339 #define ERU1_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0 1340 #define ERU1_ETL2_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 1341 #define ERU1_ETL2_INPUTA_P3_4 XMC_ERU_ETL_INPUT_A3 1342 #define ERU1_ETL2_INPUTA_P4_6 XMC_ERU_ETL_INPUT_A2 1343 #define ERU1_ETL2_INPUTB_CCU40_ST2 XMC_ERU_ETL_INPUT_B0 1344 #define ERU1_ETL2_INPUTB_CCU41_ST2 XMC_ERU_ETL_INPUT_B1 1345 #define ERU1_ETL2_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B2 1346 #define ERU1_ETL2_INPUTB_CCU81_ST1 XMC_ERU_ETL_INPUT_B3 1347 #define ERU1_ETL3_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0 1348 #define ERU1_ETL3_INPUTA_P2_12 XMC_ERU_ETL_INPUT_A2 1349 #define ERU1_ETL3_INPUTA_P2_13 XMC_ERU_ETL_INPUT_A3 1350 #define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 1351 #define ERU1_ETL3_INPUTB_CCU40_ST3 XMC_ERU_ETL_INPUT_B0 1352 #define ERU1_ETL3_INPUTB_CCU41_ST3 XMC_ERU_ETL_INPUT_B1 1353 #define ERU1_ETL3_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B2 1354 #define ERU1_ETL3_INPUTB_CCU81_ST2 XMC_ERU_ETL_INPUT_B3 1355 1356 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1357 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1358 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1359 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1360 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1361 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1362 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1363 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1364 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1365 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1366 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1367 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1368 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU41_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1369 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU81_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1370 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1371 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU81_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1372 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU41_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1373 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1374 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU41_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1375 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1376 #endif 1377 1378 1379 #if (UC_DEVICE == XMC1402) && (UC_PACKAGE == TSSOP38) 1380 #define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0 1381 #define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2 1382 #define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1 1383 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3 1384 #define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2 1385 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 1386 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1 1387 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3 1388 #define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0 1389 #define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2 1390 #define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1 1391 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3 1392 #define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2 1393 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 1394 #define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1 1395 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3 1396 #define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0 1397 #define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2 1398 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 1399 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3 1400 #define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2 1401 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 1402 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 1403 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3 1404 #define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2 1405 #define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0 1406 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 1407 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3 1408 #define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2 1409 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 1410 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 1411 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3 1412 #define ERU1_ETL0_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0 1413 #define ERU1_ETL0_INPUTB_CCU40_ST0 XMC_ERU_ETL_INPUT_B0 1414 #define ERU1_ETL0_INPUTB_CCU41_ST0 XMC_ERU_ETL_INPUT_B1 1415 #define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B2 1416 #define ERU1_ETL0_INPUTB_CCU81_ST0 XMC_ERU_ETL_INPUT_B3 1417 #define ERU1_ETL1_INPUTB_CCU40_ST1 XMC_ERU_ETL_INPUT_B0 1418 #define ERU1_ETL1_INPUTB_CCU41_ST1 XMC_ERU_ETL_INPUT_B1 1419 #define ERU1_ETL1_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B2 1420 #define ERU1_ETL1_INPUTB_CCU81_ST3 XMC_ERU_ETL_INPUT_B3 1421 #define ERU1_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0 1422 #define ERU1_ETL2_INPUTB_CCU40_ST2 XMC_ERU_ETL_INPUT_B0 1423 #define ERU1_ETL2_INPUTB_CCU41_ST2 XMC_ERU_ETL_INPUT_B1 1424 #define ERU1_ETL2_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B2 1425 #define ERU1_ETL2_INPUTB_CCU81_ST1 XMC_ERU_ETL_INPUT_B3 1426 #define ERU1_ETL3_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0 1427 #define ERU1_ETL3_INPUTB_CCU40_ST3 XMC_ERU_ETL_INPUT_B0 1428 #define ERU1_ETL3_INPUTB_CCU41_ST3 XMC_ERU_ETL_INPUT_B1 1429 #define ERU1_ETL3_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B2 1430 #define ERU1_ETL3_INPUTB_CCU81_ST2 XMC_ERU_ETL_INPUT_B3 1431 1432 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1433 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1434 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1435 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1436 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1437 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1438 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1439 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1440 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1441 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1442 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1443 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1444 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU41_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1445 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU81_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1446 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1447 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU81_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1448 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU41_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1449 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1450 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU41_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1451 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1452 #endif 1453 1454 1455 #if (UC_DEVICE == XMC1403) && (UC_PACKAGE == VQFN40) 1456 #define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1 1457 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3 1458 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 1459 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1 1460 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3 1461 #define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1 1462 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3 1463 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 1464 #define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1 1465 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3 1466 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 1467 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3 1468 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 1469 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 1470 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3 1471 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 1472 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3 1473 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 1474 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 1475 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3 1476 #define ERU1_ETL0_INPUTB_CCU40_ST0 XMC_ERU_ETL_INPUT_B0 1477 #define ERU1_ETL0_INPUTB_CCU41_ST0 XMC_ERU_ETL_INPUT_B1 1478 #define ERU1_ETL1_INPUTB_CCU40_ST1 XMC_ERU_ETL_INPUT_B0 1479 #define ERU1_ETL1_INPUTB_CCU41_ST1 XMC_ERU_ETL_INPUT_B1 1480 #define ERU1_ETL2_INPUTB_CCU40_ST2 XMC_ERU_ETL_INPUT_B0 1481 #define ERU1_ETL2_INPUTB_CCU41_ST2 XMC_ERU_ETL_INPUT_B1 1482 #define ERU1_ETL3_INPUTB_CCU40_ST3 XMC_ERU_ETL_INPUT_B0 1483 #define ERU1_ETL3_INPUTB_CCU41_ST3 XMC_ERU_ETL_INPUT_B1 1484 1485 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1486 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1487 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1488 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1489 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1490 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1491 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1492 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1493 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CAN0_SR4 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1494 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU41_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1495 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CAN0_SR5 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1496 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1497 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CAN0_SR6 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1498 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU41_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1499 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CAN0_SR7 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1500 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU41_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1501 #endif 1502 1503 1504 #if (UC_DEVICE == XMC1403) && (UC_PACKAGE == VQFN48) 1505 #define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1 1506 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3 1507 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 1508 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1 1509 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3 1510 #define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1 1511 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3 1512 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 1513 #define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1 1514 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3 1515 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 1516 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3 1517 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 1518 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 1519 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3 1520 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 1521 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3 1522 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 1523 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 1524 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3 1525 #define ERU1_ETL0_INPUTA_P3_0 XMC_ERU_ETL_INPUT_A1 1526 #define ERU1_ETL0_INPUTA_P4_4 XMC_ERU_ETL_INPUT_A2 1527 #define ERU1_ETL0_INPUTA_P4_7 XMC_ERU_ETL_INPUT_A3 1528 #define ERU1_ETL0_INPUTB_CCU40_ST0 XMC_ERU_ETL_INPUT_B0 1529 #define ERU1_ETL0_INPUTB_CCU41_ST0 XMC_ERU_ETL_INPUT_B1 1530 #define ERU1_ETL1_INPUTA_P4_5 XMC_ERU_ETL_INPUT_A2 1531 #define ERU1_ETL1_INPUTB_CCU40_ST1 XMC_ERU_ETL_INPUT_B0 1532 #define ERU1_ETL1_INPUTB_CCU41_ST1 XMC_ERU_ETL_INPUT_B1 1533 #define ERU1_ETL2_INPUTA_P4_6 XMC_ERU_ETL_INPUT_A2 1534 #define ERU1_ETL2_INPUTB_CCU40_ST2 XMC_ERU_ETL_INPUT_B0 1535 #define ERU1_ETL2_INPUTB_CCU41_ST2 XMC_ERU_ETL_INPUT_B1 1536 #define ERU1_ETL3_INPUTA_P2_12 XMC_ERU_ETL_INPUT_A2 1537 #define ERU1_ETL3_INPUTA_P2_13 XMC_ERU_ETL_INPUT_A3 1538 #define ERU1_ETL3_INPUTB_CCU40_ST3 XMC_ERU_ETL_INPUT_B0 1539 #define ERU1_ETL3_INPUTB_CCU41_ST3 XMC_ERU_ETL_INPUT_B1 1540 1541 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1542 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1543 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1544 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1545 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1546 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1547 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1548 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1549 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CAN0_SR4 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1550 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU41_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1551 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CAN0_SR5 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1552 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1553 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CAN0_SR6 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1554 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU41_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1555 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CAN0_SR7 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1556 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU41_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1557 #endif 1558 1559 1560 #if (UC_DEVICE == XMC1403) && (UC_PACKAGE == VQFN64) 1561 #define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1 1562 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3 1563 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 1564 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1 1565 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3 1566 #define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1 1567 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3 1568 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 1569 #define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1 1570 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3 1571 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 1572 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3 1573 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 1574 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 1575 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3 1576 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 1577 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3 1578 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 1579 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 1580 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3 1581 #define ERU1_ETL0_INPUTA_P3_0 XMC_ERU_ETL_INPUT_A1 1582 #define ERU1_ETL0_INPUTA_P4_4 XMC_ERU_ETL_INPUT_A2 1583 #define ERU1_ETL0_INPUTA_P4_7 XMC_ERU_ETL_INPUT_A3 1584 #define ERU1_ETL0_INPUTB_CCU40_ST0 XMC_ERU_ETL_INPUT_B0 1585 #define ERU1_ETL0_INPUTB_CCU41_ST0 XMC_ERU_ETL_INPUT_B1 1586 #define ERU1_ETL0_INPUTB_CCU81_ST0 XMC_ERU_ETL_INPUT_B3 1587 #define ERU1_ETL1_INPUTA_P3_1 XMC_ERU_ETL_INPUT_A1 1588 #define ERU1_ETL1_INPUTA_P3_3 XMC_ERU_ETL_INPUT_A3 1589 #define ERU1_ETL1_INPUTA_P4_5 XMC_ERU_ETL_INPUT_A2 1590 #define ERU1_ETL1_INPUTB_CCU40_ST1 XMC_ERU_ETL_INPUT_B0 1591 #define ERU1_ETL1_INPUTB_CCU41_ST1 XMC_ERU_ETL_INPUT_B1 1592 #define ERU1_ETL1_INPUTB_CCU81_ST3 XMC_ERU_ETL_INPUT_B3 1593 #define ERU1_ETL2_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 1594 #define ERU1_ETL2_INPUTA_P3_4 XMC_ERU_ETL_INPUT_A3 1595 #define ERU1_ETL2_INPUTA_P4_6 XMC_ERU_ETL_INPUT_A2 1596 #define ERU1_ETL2_INPUTB_CCU40_ST2 XMC_ERU_ETL_INPUT_B0 1597 #define ERU1_ETL2_INPUTB_CCU41_ST2 XMC_ERU_ETL_INPUT_B1 1598 #define ERU1_ETL2_INPUTB_CCU81_ST1 XMC_ERU_ETL_INPUT_B3 1599 #define ERU1_ETL3_INPUTA_P2_12 XMC_ERU_ETL_INPUT_A2 1600 #define ERU1_ETL3_INPUTA_P2_13 XMC_ERU_ETL_INPUT_A3 1601 #define ERU1_ETL3_INPUTB_CCU40_ST3 XMC_ERU_ETL_INPUT_B0 1602 #define ERU1_ETL3_INPUTB_CCU41_ST3 XMC_ERU_ETL_INPUT_B1 1603 1604 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1605 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1606 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1607 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1608 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1609 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1610 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1611 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1612 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CAN0_SR4 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1613 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU41_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1614 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CAN0_SR5 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1615 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1616 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CAN0_SR6 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1617 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU41_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1618 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CAN0_SR7 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1619 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU41_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1620 #endif 1621 1622 1623 #if (UC_DEVICE == XMC1404) && (UC_PACKAGE == LQFP64) 1624 #define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0 1625 #define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2 1626 #define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1 1627 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3 1628 #define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2 1629 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 1630 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1 1631 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3 1632 #define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0 1633 #define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2 1634 #define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1 1635 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3 1636 #define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2 1637 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 1638 #define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1 1639 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3 1640 #define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0 1641 #define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2 1642 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 1643 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3 1644 #define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2 1645 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 1646 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 1647 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3 1648 #define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2 1649 #define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0 1650 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 1651 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3 1652 #define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2 1653 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 1654 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 1655 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3 1656 #define ERU1_ETL0_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0 1657 #define ERU1_ETL0_INPUTA_P3_0 XMC_ERU_ETL_INPUT_A1 1658 #define ERU1_ETL0_INPUTA_P4_4 XMC_ERU_ETL_INPUT_A2 1659 #define ERU1_ETL0_INPUTA_P4_7 XMC_ERU_ETL_INPUT_A3 1660 #define ERU1_ETL0_INPUTB_CCU40_ST0 XMC_ERU_ETL_INPUT_B0 1661 #define ERU1_ETL0_INPUTB_CCU41_ST0 XMC_ERU_ETL_INPUT_B1 1662 #define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B2 1663 #define ERU1_ETL0_INPUTB_CCU81_ST0 XMC_ERU_ETL_INPUT_B3 1664 #define ERU1_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A0 1665 #define ERU1_ETL1_INPUTA_P3_1 XMC_ERU_ETL_INPUT_A1 1666 #define ERU1_ETL1_INPUTA_P3_3 XMC_ERU_ETL_INPUT_A3 1667 #define ERU1_ETL1_INPUTA_P4_5 XMC_ERU_ETL_INPUT_A2 1668 #define ERU1_ETL1_INPUTB_CCU40_ST1 XMC_ERU_ETL_INPUT_B0 1669 #define ERU1_ETL1_INPUTB_CCU41_ST1 XMC_ERU_ETL_INPUT_B1 1670 #define ERU1_ETL1_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B2 1671 #define ERU1_ETL1_INPUTB_CCU81_ST3 XMC_ERU_ETL_INPUT_B3 1672 #define ERU1_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0 1673 #define ERU1_ETL2_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 1674 #define ERU1_ETL2_INPUTA_P3_4 XMC_ERU_ETL_INPUT_A3 1675 #define ERU1_ETL2_INPUTA_P4_6 XMC_ERU_ETL_INPUT_A2 1676 #define ERU1_ETL2_INPUTB_CCU40_ST2 XMC_ERU_ETL_INPUT_B0 1677 #define ERU1_ETL2_INPUTB_CCU41_ST2 XMC_ERU_ETL_INPUT_B1 1678 #define ERU1_ETL2_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B2 1679 #define ERU1_ETL2_INPUTB_CCU81_ST1 XMC_ERU_ETL_INPUT_B3 1680 #define ERU1_ETL3_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0 1681 #define ERU1_ETL3_INPUTA_P2_12 XMC_ERU_ETL_INPUT_A2 1682 #define ERU1_ETL3_INPUTA_P2_13 XMC_ERU_ETL_INPUT_A3 1683 #define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 1684 #define ERU1_ETL3_INPUTB_CCU40_ST3 XMC_ERU_ETL_INPUT_B0 1685 #define ERU1_ETL3_INPUTB_CCU41_ST3 XMC_ERU_ETL_INPUT_B1 1686 #define ERU1_ETL3_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B2 1687 #define ERU1_ETL3_INPUTB_CCU81_ST2 XMC_ERU_ETL_INPUT_B3 1688 1689 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1690 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1691 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1692 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1693 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1694 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1695 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1696 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1697 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1698 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1699 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1700 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1701 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CAN0_SR4 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1702 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU41_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1703 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU81_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1704 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CAN0_SR5 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1705 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1706 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU81_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1707 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CAN0_SR6 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1708 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU41_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1709 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1710 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CAN0_SR7 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1711 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU41_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1712 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1713 #endif 1714 1715 #if (UC_DEVICE == XMC1404) && (UC_PACKAGE == VQFN40) 1716 #define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0 1717 #define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2 1718 #define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1 1719 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3 1720 #define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2 1721 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 1722 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1 1723 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3 1724 #define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0 1725 #define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2 1726 #define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1 1727 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3 1728 #define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2 1729 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 1730 #define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1 1731 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3 1732 #define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0 1733 #define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2 1734 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 1735 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3 1736 #define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2 1737 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 1738 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 1739 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3 1740 #define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2 1741 #define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0 1742 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 1743 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3 1744 #define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2 1745 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 1746 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 1747 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3 1748 #define ERU1_ETL0_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0 1749 #define ERU1_ETL0_INPUTB_CCU40_ST0 XMC_ERU_ETL_INPUT_B0 1750 #define ERU1_ETL0_INPUTB_CCU41_ST0 XMC_ERU_ETL_INPUT_B1 1751 #define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B2 1752 #define ERU1_ETL0_INPUTB_CCU81_ST0 XMC_ERU_ETL_INPUT_B3 1753 #define ERU1_ETL1_INPUTB_CCU40_ST1 XMC_ERU_ETL_INPUT_B0 1754 #define ERU1_ETL1_INPUTB_CCU41_ST1 XMC_ERU_ETL_INPUT_B1 1755 #define ERU1_ETL1_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B2 1756 #define ERU1_ETL1_INPUTB_CCU81_ST3 XMC_ERU_ETL_INPUT_B3 1757 #define ERU1_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0 1758 #define ERU1_ETL2_INPUTB_CCU40_ST2 XMC_ERU_ETL_INPUT_B0 1759 #define ERU1_ETL2_INPUTB_CCU41_ST2 XMC_ERU_ETL_INPUT_B1 1760 #define ERU1_ETL2_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B2 1761 #define ERU1_ETL2_INPUTB_CCU81_ST1 XMC_ERU_ETL_INPUT_B3 1762 #define ERU1_ETL3_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0 1763 #define ERU1_ETL3_INPUTB_CCU40_ST3 XMC_ERU_ETL_INPUT_B0 1764 #define ERU1_ETL3_INPUTB_CCU41_ST3 XMC_ERU_ETL_INPUT_B1 1765 #define ERU1_ETL3_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B2 1766 #define ERU1_ETL3_INPUTB_CCU81_ST2 XMC_ERU_ETL_INPUT_B3 1767 1768 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1769 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1770 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1771 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1772 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1773 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1774 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1775 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1776 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1777 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1778 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1779 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1780 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU41_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1781 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU81_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1782 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1783 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU81_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1784 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU41_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1785 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1786 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU41_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1787 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1788 #endif 1789 1790 #if (UC_DEVICE == XMC1404) && (UC_PACKAGE == VQFN48) 1791 #define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0 1792 #define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2 1793 #define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1 1794 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3 1795 #define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2 1796 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 1797 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1 1798 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3 1799 #define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0 1800 #define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2 1801 #define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1 1802 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3 1803 #define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2 1804 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 1805 #define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1 1806 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3 1807 #define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0 1808 #define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2 1809 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 1810 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3 1811 #define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2 1812 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 1813 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 1814 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3 1815 #define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2 1816 #define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0 1817 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 1818 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3 1819 #define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2 1820 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 1821 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 1822 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3 1823 #define ERU1_ETL0_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0 1824 #define ERU1_ETL0_INPUTA_P3_0 XMC_ERU_ETL_INPUT_A1 1825 #define ERU1_ETL0_INPUTA_P4_4 XMC_ERU_ETL_INPUT_A2 1826 #define ERU1_ETL0_INPUTA_P4_7 XMC_ERU_ETL_INPUT_A3 1827 #define ERU1_ETL0_INPUTB_CCU40_ST0 XMC_ERU_ETL_INPUT_B0 1828 #define ERU1_ETL0_INPUTB_CCU41_ST0 XMC_ERU_ETL_INPUT_B1 1829 #define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B2 1830 #define ERU1_ETL0_INPUTB_CCU81_ST0 XMC_ERU_ETL_INPUT_B3 1831 #define ERU1_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A0 1832 #define ERU1_ETL1_INPUTA_P4_5 XMC_ERU_ETL_INPUT_A2 1833 #define ERU1_ETL1_INPUTB_CCU40_ST1 XMC_ERU_ETL_INPUT_B0 1834 #define ERU1_ETL1_INPUTB_CCU41_ST1 XMC_ERU_ETL_INPUT_B1 1835 #define ERU1_ETL1_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B2 1836 #define ERU1_ETL1_INPUTB_CCU81_ST3 XMC_ERU_ETL_INPUT_B3 1837 #define ERU1_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0 1838 #define ERU1_ETL2_INPUTA_P4_6 XMC_ERU_ETL_INPUT_A2 1839 #define ERU1_ETL2_INPUTB_CCU40_ST2 XMC_ERU_ETL_INPUT_B0 1840 #define ERU1_ETL2_INPUTB_CCU41_ST2 XMC_ERU_ETL_INPUT_B1 1841 #define ERU1_ETL2_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B2 1842 #define ERU1_ETL2_INPUTB_CCU81_ST1 XMC_ERU_ETL_INPUT_B3 1843 #define ERU1_ETL3_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0 1844 #define ERU1_ETL3_INPUTA_P2_12 XMC_ERU_ETL_INPUT_A2 1845 #define ERU1_ETL3_INPUTA_P2_13 XMC_ERU_ETL_INPUT_A3 1846 #define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 1847 #define ERU1_ETL3_INPUTB_CCU40_ST3 XMC_ERU_ETL_INPUT_B0 1848 #define ERU1_ETL3_INPUTB_CCU41_ST3 XMC_ERU_ETL_INPUT_B1 1849 #define ERU1_ETL3_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B2 1850 #define ERU1_ETL3_INPUTB_CCU81_ST2 XMC_ERU_ETL_INPUT_B3 1851 1852 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1853 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1854 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1855 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1856 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1857 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1858 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1859 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1860 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1861 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1862 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1863 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1864 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CAN0_SR4 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1865 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU41_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1866 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU81_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1867 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CAN0_SR5 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1868 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1869 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU81_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1870 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CAN0_SR6 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1871 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU41_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1872 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1873 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CAN0_SR7 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1874 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU41_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1875 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1876 #endif 1877 1878 1879 #if (UC_DEVICE == XMC1404) && (UC_PACKAGE == VQFN64) 1880 #define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0 1881 #define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2 1882 #define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1 1883 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3 1884 #define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2 1885 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 1886 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1 1887 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3 1888 #define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0 1889 #define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2 1890 #define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1 1891 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3 1892 #define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2 1893 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 1894 #define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1 1895 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3 1896 #define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0 1897 #define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2 1898 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 1899 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3 1900 #define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2 1901 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 1902 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 1903 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3 1904 #define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2 1905 #define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0 1906 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 1907 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3 1908 #define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2 1909 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 1910 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 1911 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3 1912 #define ERU1_ETL0_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0 1913 #define ERU1_ETL0_INPUTA_P3_0 XMC_ERU_ETL_INPUT_A1 1914 #define ERU1_ETL0_INPUTA_P4_4 XMC_ERU_ETL_INPUT_A2 1915 #define ERU1_ETL0_INPUTA_P4_7 XMC_ERU_ETL_INPUT_A3 1916 #define ERU1_ETL0_INPUTB_CCU40_ST0 XMC_ERU_ETL_INPUT_B0 1917 #define ERU1_ETL0_INPUTB_CCU41_ST0 XMC_ERU_ETL_INPUT_B1 1918 #define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B2 1919 #define ERU1_ETL0_INPUTB_CCU81_ST0 XMC_ERU_ETL_INPUT_B3 1920 #define ERU1_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A0 1921 #define ERU1_ETL1_INPUTA_P3_1 XMC_ERU_ETL_INPUT_A1 1922 #define ERU1_ETL1_INPUTA_P3_3 XMC_ERU_ETL_INPUT_A3 1923 #define ERU1_ETL1_INPUTA_P4_5 XMC_ERU_ETL_INPUT_A2 1924 #define ERU1_ETL1_INPUTB_CCU40_ST1 XMC_ERU_ETL_INPUT_B0 1925 #define ERU1_ETL1_INPUTB_CCU41_ST1 XMC_ERU_ETL_INPUT_B1 1926 #define ERU1_ETL1_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B2 1927 #define ERU1_ETL1_INPUTB_CCU81_ST3 XMC_ERU_ETL_INPUT_B3 1928 #define ERU1_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0 1929 #define ERU1_ETL2_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 1930 #define ERU1_ETL2_INPUTA_P3_4 XMC_ERU_ETL_INPUT_A3 1931 #define ERU1_ETL2_INPUTA_P4_6 XMC_ERU_ETL_INPUT_A2 1932 #define ERU1_ETL2_INPUTB_CCU40_ST2 XMC_ERU_ETL_INPUT_B0 1933 #define ERU1_ETL2_INPUTB_CCU41_ST2 XMC_ERU_ETL_INPUT_B1 1934 #define ERU1_ETL2_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B2 1935 #define ERU1_ETL2_INPUTB_CCU81_ST1 XMC_ERU_ETL_INPUT_B3 1936 #define ERU1_ETL3_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0 1937 #define ERU1_ETL3_INPUTA_P2_12 XMC_ERU_ETL_INPUT_A2 1938 #define ERU1_ETL3_INPUTA_P2_13 XMC_ERU_ETL_INPUT_A3 1939 #define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 1940 #define ERU1_ETL3_INPUTB_CCU40_ST3 XMC_ERU_ETL_INPUT_B0 1941 #define ERU1_ETL3_INPUTB_CCU41_ST3 XMC_ERU_ETL_INPUT_B1 1942 #define ERU1_ETL3_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B2 1943 #define ERU1_ETL3_INPUTB_CCU81_ST2 XMC_ERU_ETL_INPUT_B3 1944 1945 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1946 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1947 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1948 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1949 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1950 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1951 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1952 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1953 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1954 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1955 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1956 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1957 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CAN0_SR4 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1958 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU41_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1959 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU81_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1960 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CAN0_SR5 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1961 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1962 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU81_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1963 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CAN0_SR6 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1964 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU41_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1965 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1966 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CAN0_SR7 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 1967 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU41_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 1968 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 1969 #endif 1970 1971 #endif /* XMC1_ERU_MAP_H */ 1972
