1 /** 2 * @file xmc1_ccu4_map.h 3 * @date 2019-07-30 4 * 5 * @cond 6 ********************************************************************************************************************* 7 * XMClib v2.1.24 - XMC Peripheral Driver Library 8 * 9 * Copyright (c) 2015-2019, Infineon Technologies AG 10 * All rights reserved. 11 * 12 * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 13 * following conditions are met: 14 * 15 * Redistributions of source code must retain the above copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following 19 * disclaimer in the documentation and/or other materials provided with the distribution. 20 * 21 * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote 22 * products derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, 25 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with 33 * Infineon Technologies AG dave@infineon.com). 34 ********************************************************************************************************************* 35 * 36 * Change History 37 * -------------- 38 * 39 * 2015-08-25: 40 * - Initial version 41 * 42 * 2019-05-07: 43 * - Add missing CCU41_IN3_CCU41_GP00 macros for XMC14 44 * 45 * 2019-07-30: 46 * - Added support for XMC1404-Q040 47 * 48 * @endcond 49 */ 50 51 #ifndef XMC1_CCU4_MAP_H 52 #define XMC1_CCU4_MAP_H 53 54 #if UC_SERIES != XMC14 55 #define XMC_CCU4_SLICE_INPUT_A (0U) 56 #define XMC_CCU4_SLICE_INPUT_B (1U) 57 #define XMC_CCU4_SLICE_INPUT_C (2U) 58 #define XMC_CCU4_SLICE_INPUT_D (3U) 59 #define XMC_CCU4_SLICE_INPUT_E (4U) 60 #define XMC_CCU4_SLICE_INPUT_F (5U) 61 #define XMC_CCU4_SLICE_INPUT_G (6U) 62 #define XMC_CCU4_SLICE_INPUT_H (7U) 63 #define XMC_CCU4_SLICE_INPUT_I (8U) 64 #define XMC_CCU4_SLICE_INPUT_J (9U) 65 #define XMC_CCU4_SLICE_INPUT_K (10U) 66 #define XMC_CCU4_SLICE_INPUT_L (11U) 67 #define XMC_CCU4_SLICE_INPUT_M (12U) 68 #define XMC_CCU4_SLICE_INPUT_N (13U) 69 #define XMC_CCU4_SLICE_INPUT_O (14U) 70 #define XMC_CCU4_SLICE_INPUT_P (15U) 71 #else 72 #define XMC_CCU4_SLICE_INPUT_AA (0U) 73 #define XMC_CCU4_SLICE_INPUT_AB (1U) 74 #define XMC_CCU4_SLICE_INPUT_AC (2U) 75 #define XMC_CCU4_SLICE_INPUT_AD (3U) 76 #define XMC_CCU4_SLICE_INPUT_AE (4U) 77 #define XMC_CCU4_SLICE_INPUT_AF (5U) 78 #define XMC_CCU4_SLICE_INPUT_AG (6U) 79 #define XMC_CCU4_SLICE_INPUT_AH (7U) 80 #define XMC_CCU4_SLICE_INPUT_AI (8U) 81 #define XMC_CCU4_SLICE_INPUT_AJ (9U) 82 #define XMC_CCU4_SLICE_INPUT_AK (10U) 83 #define XMC_CCU4_SLICE_INPUT_AL (11U) 84 #define XMC_CCU4_SLICE_INPUT_AM (12U) 85 #define XMC_CCU4_SLICE_INPUT_AN (13U) 86 #define XMC_CCU4_SLICE_INPUT_AO (14U) 87 #define XMC_CCU4_SLICE_INPUT_AP (15U) 88 #define XMC_CCU4_SLICE_INPUT_AQ (16U) 89 #define XMC_CCU4_SLICE_INPUT_AR (17U) 90 #define XMC_CCU4_SLICE_INPUT_AS (18U) 91 #define XMC_CCU4_SLICE_INPUT_AT (19U) 92 #define XMC_CCU4_SLICE_INPUT_AU (20U) 93 #define XMC_CCU4_SLICE_INPUT_AV (21U) 94 #define XMC_CCU4_SLICE_INPUT_AW (22U) 95 #define XMC_CCU4_SLICE_INPUT_AX (23U) 96 #define XMC_CCU4_SLICE_INPUT_AY (24U) 97 #define XMC_CCU4_SLICE_INPUT_AZ (25U) 98 #define XMC_CCU4_SLICE_INPUT_BA (26U) 99 #define XMC_CCU4_SLICE_INPUT_BB (27U) 100 #define XMC_CCU4_SLICE_INPUT_BC (28U) 101 #define XMC_CCU4_SLICE_INPUT_BD (29U) 102 #define XMC_CCU4_SLICE_INPUT_BE (30U) 103 #define XMC_CCU4_SLICE_INPUT_BF (31U) 104 #define XMC_CCU4_SLICE_INPUT_BG (32U) 105 #define XMC_CCU4_SLICE_INPUT_BH (33U) 106 #define XMC_CCU4_SLICE_INPUT_BI (34U) 107 #define XMC_CCU4_SLICE_INPUT_BJ (35U) 108 #define XMC_CCU4_SLICE_INPUT_BK (36U) 109 #define XMC_CCU4_SLICE_INPUT_BL (37U) 110 #define XMC_CCU4_SLICE_INPUT_BM (38U) 111 #define XMC_CCU4_SLICE_INPUT_BN (39U) 112 #define XMC_CCU4_SLICE_INPUT_BO (40U) 113 #define XMC_CCU4_SLICE_INPUT_BP (41U) 114 #define XMC_CCU4_SLICE_INPUT_BQ (42U) 115 #define XMC_CCU4_SLICE_INPUT_BR (43U) 116 #define XMC_CCU4_SLICE_INPUT_BS (44U) 117 #define XMC_CCU4_SLICE_INPUT_BT (45U) 118 #define XMC_CCU4_SLICE_INPUT_BU (46U) 119 #define XMC_CCU4_SLICE_INPUT_BV (47U) 120 #endif 121 122 #if (UC_DEVICE == XMC1100) && (UC_PACKAGE == VQFN24) 123 #define CCU40_IN0_CCU40_GP01 12 124 #define CCU40_IN0_CCU40_ST1 13 125 #define CCU40_IN0_CCU40_ST2 14 126 #define CCU40_IN0_CCU40_ST3 15 127 #define CCU40_IN0_ERU0_IOUT0 10 128 #define CCU40_IN0_ERU0_PDOUT0 9 129 #define CCU40_IN0_ERU0_PDOUT1 3 130 #define CCU40_IN0_P0_0 2 131 #define CCU40_IN0_P0_12 0 132 #define CCU40_IN0_P0_6 1 133 #define CCU40_IN0_SCU_GSC40 8 134 #define CCU40_IN0_U0C0_DX2INS 11 135 #define CCU40_IN1_CCU40_GP02 12 136 #define CCU40_IN1_CCU40_ST0 13 137 #define CCU40_IN1_CCU40_ST2 14 138 #define CCU40_IN1_CCU40_ST3 15 139 #define CCU40_IN1_ERU0_IOUT1 10 140 #define CCU40_IN1_ERU0_PDOUT0 3 141 #define CCU40_IN1_ERU0_PDOUT1 9 142 #define CCU40_IN1_P0_12 0 143 #define CCU40_IN1_P0_7 1 144 #define CCU40_IN1_SCU_GSC40 8 145 #define CCU40_IN1_U0C1_DX2INS 11 146 #define CCU40_IN2_CCU40_GP03 12 147 #define CCU40_IN2_CCU40_ST0 13 148 #define CCU40_IN2_CCU40_ST1 14 149 #define CCU40_IN2_CCU40_ST3 15 150 #define CCU40_IN2_ERU0_IOUT2 10 151 #define CCU40_IN2_ERU0_PDOUT2 9 152 #define CCU40_IN2_ERU0_PDOUT3 3 153 #define CCU40_IN2_P0_12 0 154 #define CCU40_IN2_P0_8 1 155 #define CCU40_IN2_SCU_GSC40 8 156 #define CCU40_IN3_CCU40_GP00 12 157 #define CCU40_IN3_CCU40_ST0 13 158 #define CCU40_IN3_CCU40_ST1 14 159 #define CCU40_IN3_CCU40_ST2 15 160 #define CCU40_IN3_ERU0_IOUT3 10 161 #define CCU40_IN3_ERU0_PDOUT2 3 162 #define CCU40_IN3_ERU0_PDOUT3 9 163 #define CCU40_IN3_P0_12 0 164 #define CCU40_IN3_P0_9 1 165 #define CCU40_IN3_SCU_GSC40 8 166 #define CCU40_IN3_VADC0_G0ARBCNT 6 167 #endif 168 169 170 #if (UC_DEVICE == XMC1100) && (UC_PACKAGE == VQFN40) 171 #define CCU40_IN0_CCU40_GP01 12 172 #define CCU40_IN0_CCU40_ST1 13 173 #define CCU40_IN0_CCU40_ST2 14 174 #define CCU40_IN0_CCU40_ST3 15 175 #define CCU40_IN0_ERU0_IOUT0 10 176 #define CCU40_IN0_ERU0_PDOUT0 9 177 #define CCU40_IN0_ERU0_PDOUT1 3 178 #define CCU40_IN0_P0_0 2 179 #define CCU40_IN0_P0_12 0 180 #define CCU40_IN0_P0_6 1 181 #define CCU40_IN0_SCU_GSC40 8 182 #define CCU40_IN0_U0C0_DX2INS 11 183 #define CCU40_IN1_CCU40_GP02 12 184 #define CCU40_IN1_CCU40_ST0 13 185 #define CCU40_IN1_CCU40_ST2 14 186 #define CCU40_IN1_CCU40_ST3 15 187 #define CCU40_IN1_ERU0_IOUT1 10 188 #define CCU40_IN1_ERU0_PDOUT0 3 189 #define CCU40_IN1_ERU0_PDOUT1 9 190 #define CCU40_IN1_P0_1 2 191 #define CCU40_IN1_P0_12 0 192 #define CCU40_IN1_P0_7 1 193 #define CCU40_IN1_SCU_GSC40 8 194 #define CCU40_IN1_U0C1_DX2INS 11 195 #define CCU40_IN2_CCU40_GP03 12 196 #define CCU40_IN2_CCU40_ST0 13 197 #define CCU40_IN2_CCU40_ST1 14 198 #define CCU40_IN2_CCU40_ST3 15 199 #define CCU40_IN2_ERU0_IOUT2 10 200 #define CCU40_IN2_ERU0_PDOUT2 9 201 #define CCU40_IN2_ERU0_PDOUT3 3 202 #define CCU40_IN2_P0_12 0 203 #define CCU40_IN2_P0_2 2 204 #define CCU40_IN2_P0_8 1 205 #define CCU40_IN2_SCU_GSC40 8 206 #define CCU40_IN3_CCU40_GP00 12 207 #define CCU40_IN3_CCU40_ST0 13 208 #define CCU40_IN3_CCU40_ST1 14 209 #define CCU40_IN3_CCU40_ST2 15 210 #define CCU40_IN3_ERU0_IOUT3 10 211 #define CCU40_IN3_ERU0_PDOUT2 3 212 #define CCU40_IN3_ERU0_PDOUT3 9 213 #define CCU40_IN3_P0_12 0 214 #define CCU40_IN3_P0_3 2 215 #define CCU40_IN3_P0_9 1 216 #define CCU40_IN3_SCU_GSC40 8 217 #define CCU40_IN3_VADC0_G0ARBCNT 6 218 #endif 219 220 221 #if (UC_DEVICE == XMC1100) && (UC_PACKAGE == TSSOP16) 222 #define CCU40_IN0_CCU40_GP01 12 223 #define CCU40_IN0_CCU40_ST1 13 224 #define CCU40_IN0_CCU40_ST2 14 225 #define CCU40_IN0_CCU40_ST3 15 226 #define CCU40_IN0_ERU0_IOUT0 10 227 #define CCU40_IN0_ERU0_PDOUT0 9 228 #define CCU40_IN0_ERU0_PDOUT1 3 229 #define CCU40_IN0_P0_0 2 230 #define CCU40_IN0_P0_6 1 231 #define CCU40_IN0_SCU_GSC40 8 232 #define CCU40_IN0_U0C0_DX2INS 11 233 #define CCU40_IN1_CCU40_GP02 12 234 #define CCU40_IN1_CCU40_ST0 13 235 #define CCU40_IN1_CCU40_ST2 14 236 #define CCU40_IN1_CCU40_ST3 15 237 #define CCU40_IN1_ERU0_IOUT1 10 238 #define CCU40_IN1_ERU0_PDOUT0 3 239 #define CCU40_IN1_ERU0_PDOUT1 9 240 #define CCU40_IN1_P0_7 1 241 #define CCU40_IN1_SCU_GSC40 8 242 #define CCU40_IN1_U0C1_DX2INS 11 243 #define CCU40_IN2_CCU40_GP03 12 244 #define CCU40_IN2_CCU40_ST0 13 245 #define CCU40_IN2_CCU40_ST1 14 246 #define CCU40_IN2_CCU40_ST3 15 247 #define CCU40_IN2_ERU0_IOUT2 10 248 #define CCU40_IN2_ERU0_PDOUT2 9 249 #define CCU40_IN2_ERU0_PDOUT3 3 250 #define CCU40_IN2_P0_8 1 251 #define CCU40_IN2_SCU_GSC40 8 252 #define CCU40_IN3_CCU40_GP00 12 253 #define CCU40_IN3_CCU40_ST0 13 254 #define CCU40_IN3_CCU40_ST1 14 255 #define CCU40_IN3_CCU40_ST2 15 256 #define CCU40_IN3_ERU0_IOUT3 10 257 #define CCU40_IN3_ERU0_PDOUT2 3 258 #define CCU40_IN3_ERU0_PDOUT3 9 259 #define CCU40_IN3_P0_9 1 260 #define CCU40_IN3_SCU_GSC40 8 261 #endif 262 263 264 #if (UC_DEVICE == XMC1100) && (UC_PACKAGE == TSSOP38) 265 #define CCU40_IN0_CCU40_GP01 12 266 #define CCU40_IN0_CCU40_ST1 13 267 #define CCU40_IN0_CCU40_ST2 14 268 #define CCU40_IN0_CCU40_ST3 15 269 #define CCU40_IN0_ERU0_IOUT0 10 270 #define CCU40_IN0_ERU0_PDOUT0 9 271 #define CCU40_IN0_ERU0_PDOUT1 3 272 #define CCU40_IN0_P0_0 2 273 #define CCU40_IN0_P0_12 0 274 #define CCU40_IN0_P0_6 1 275 #define CCU40_IN0_SCU_GSC40 8 276 #define CCU40_IN0_U0C0_DX2INS 11 277 #define CCU40_IN1_CCU40_GP02 12 278 #define CCU40_IN1_CCU40_ST0 13 279 #define CCU40_IN1_CCU40_ST2 14 280 #define CCU40_IN1_CCU40_ST3 15 281 #define CCU40_IN1_ERU0_IOUT1 10 282 #define CCU40_IN1_ERU0_PDOUT0 3 283 #define CCU40_IN1_ERU0_PDOUT1 9 284 #define CCU40_IN1_P0_1 2 285 #define CCU40_IN1_P0_12 0 286 #define CCU40_IN1_P0_7 1 287 #define CCU40_IN1_SCU_GSC40 8 288 #define CCU40_IN1_U0C1_DX2INS 11 289 #define CCU40_IN2_CCU40_GP03 12 290 #define CCU40_IN2_CCU40_ST0 13 291 #define CCU40_IN2_CCU40_ST1 14 292 #define CCU40_IN2_CCU40_ST3 15 293 #define CCU40_IN2_ERU0_IOUT2 10 294 #define CCU40_IN2_ERU0_PDOUT2 9 295 #define CCU40_IN2_ERU0_PDOUT3 3 296 #define CCU40_IN2_P0_12 0 297 #define CCU40_IN2_P0_2 2 298 #define CCU40_IN2_P0_8 1 299 #define CCU40_IN2_SCU_GSC40 8 300 #define CCU40_IN3_CCU40_GP00 12 301 #define CCU40_IN3_CCU40_ST0 13 302 #define CCU40_IN3_CCU40_ST1 14 303 #define CCU40_IN3_CCU40_ST2 15 304 #define CCU40_IN3_ERU0_IOUT3 10 305 #define CCU40_IN3_ERU0_PDOUT2 3 306 #define CCU40_IN3_ERU0_PDOUT3 9 307 #define CCU40_IN3_P0_12 0 308 #define CCU40_IN3_P0_3 2 309 #define CCU40_IN3_P0_9 1 310 #define CCU40_IN3_SCU_GSC40 8 311 #define CCU40_IN3_VADC0_G0ARBCNT 6 312 #endif 313 314 315 #if (UC_DEVICE == XMC1200) && (UC_PACKAGE == TSSOP38) 316 #define CCU40_IN0_CCU40_GP01 12 317 #define CCU40_IN0_CCU40_ST1 13 318 #define CCU40_IN0_CCU40_ST2 14 319 #define CCU40_IN0_CCU40_ST3 15 320 #define CCU40_IN0_ERU0_IOUT0 10 321 #define CCU40_IN0_ERU0_PDOUT0 9 322 #define CCU40_IN0_ERU0_PDOUT1 3 323 #define CCU40_IN0_P0_0 2 324 #define CCU40_IN0_P0_12 0 325 #define CCU40_IN0_P0_6 1 326 #define CCU40_IN0_SCU_GSC40 8 327 #define CCU40_IN0_U0C0_DX2INS 11 328 #define CCU40_IN1_CCU40_GP02 12 329 #define CCU40_IN1_CCU40_ST0 13 330 #define CCU40_IN1_CCU40_ST2 14 331 #define CCU40_IN1_CCU40_ST3 15 332 #define CCU40_IN1_ERU0_IOUT1 10 333 #define CCU40_IN1_ERU0_PDOUT0 3 334 #define CCU40_IN1_ERU0_PDOUT1 9 335 #define CCU40_IN1_P0_1 2 336 #define CCU40_IN1_P0_12 0 337 #define CCU40_IN1_P0_7 1 338 #define CCU40_IN1_SCU_GSC40 8 339 #define CCU40_IN1_U0C1_DX2INS 11 340 #define CCU40_IN2_CCU40_GP03 12 341 #define CCU40_IN2_CCU40_ST0 13 342 #define CCU40_IN2_CCU40_ST1 14 343 #define CCU40_IN2_CCU40_ST3 15 344 #define CCU40_IN2_ERU0_IOUT2 10 345 #define CCU40_IN2_ERU0_PDOUT2 9 346 #define CCU40_IN2_ERU0_PDOUT3 3 347 #define CCU40_IN2_LEDTSledts_SR0 11 348 #define CCU40_IN2_P0_12 0 349 #define CCU40_IN2_P0_2 2 350 #define CCU40_IN2_P0_8 1 351 #define CCU40_IN2_SCU_GSC40 8 352 #define CCU40_IN3_CCU40_GP00 12 353 #define CCU40_IN3_CCU40_ST0 13 354 #define CCU40_IN3_CCU40_ST1 14 355 #define CCU40_IN3_CCU40_ST2 15 356 #define CCU40_IN3_ERU0_IOUT3 10 357 #define CCU40_IN3_ERU0_PDOUT2 3 358 #define CCU40_IN3_ERU0_PDOUT3 9 359 #define CCU40_IN3_LEDTSledts_SR0 11 360 #define CCU40_IN3_P0_12 0 361 #define CCU40_IN3_P0_3 2 362 #define CCU40_IN3_P0_9 1 363 #define CCU40_IN3_SCU_GSC40 8 364 #define CCU40_IN3_VADC0_G0ARBCNT 6 365 #endif 366 367 368 #if (UC_DEVICE == XMC1201) && (UC_PACKAGE == VQFN40) 369 #define CCU40_IN0_CCU40_GP01 12 370 #define CCU40_IN0_CCU40_ST1 13 371 #define CCU40_IN0_CCU40_ST2 14 372 #define CCU40_IN0_CCU40_ST3 15 373 #define CCU40_IN0_ERU0_IOUT0 10 374 #define CCU40_IN0_ERU0_PDOUT0 9 375 #define CCU40_IN0_ERU0_PDOUT1 3 376 #define CCU40_IN0_P0_0 2 377 #define CCU40_IN0_P0_12 0 378 #define CCU40_IN0_P0_6 1 379 #define CCU40_IN0_SCU_GSC40 8 380 #define CCU40_IN0_U0C0_DX2INS 11 381 #define CCU40_IN1_CCU40_GP02 12 382 #define CCU40_IN1_CCU40_ST0 13 383 #define CCU40_IN1_CCU40_ST2 14 384 #define CCU40_IN1_CCU40_ST3 15 385 #define CCU40_IN1_ERU0_IOUT1 10 386 #define CCU40_IN1_ERU0_PDOUT0 3 387 #define CCU40_IN1_ERU0_PDOUT1 9 388 #define CCU40_IN1_P0_1 2 389 #define CCU40_IN1_P0_12 0 390 #define CCU40_IN1_P0_7 1 391 #define CCU40_IN1_SCU_GSC40 8 392 #define CCU40_IN1_U0C1_DX2INS 11 393 #define CCU40_IN2_CCU40_GP03 12 394 #define CCU40_IN2_CCU40_ST0 13 395 #define CCU40_IN2_CCU40_ST1 14 396 #define CCU40_IN2_CCU40_ST3 15 397 #define CCU40_IN2_ERU0_IOUT2 10 398 #define CCU40_IN2_ERU0_PDOUT2 9 399 #define CCU40_IN2_ERU0_PDOUT3 3 400 #define CCU40_IN2_LEDTSledts_SR0 11 401 #define CCU40_IN2_P0_12 0 402 #define CCU40_IN2_P0_2 2 403 #define CCU40_IN2_P0_8 1 404 #define CCU40_IN2_SCU_GSC40 8 405 #define CCU40_IN3_CCU40_GP00 12 406 #define CCU40_IN3_CCU40_ST0 13 407 #define CCU40_IN3_CCU40_ST1 14 408 #define CCU40_IN3_CCU40_ST2 15 409 #define CCU40_IN3_ERU0_IOUT3 10 410 #define CCU40_IN3_ERU0_PDOUT2 3 411 #define CCU40_IN3_ERU0_PDOUT3 9 412 #define CCU40_IN3_LEDTSledts_SR0 11 413 #define CCU40_IN3_P0_12 0 414 #define CCU40_IN3_P0_3 2 415 #define CCU40_IN3_P0_9 1 416 #define CCU40_IN3_SCU_GSC40 8 417 #define CCU40_IN3_VADC0_G0ARBCNT 6 418 #endif 419 420 421 #if (UC_DEVICE == XMC1201) && (UC_PACKAGE == TSSOP28) 422 #define CCU40_IN0_CCU40_GP01 12 423 #define CCU40_IN0_CCU40_ST1 13 424 #define CCU40_IN0_CCU40_ST2 14 425 #define CCU40_IN0_CCU40_ST3 15 426 #define CCU40_IN0_ERU0_IOUT0 10 427 #define CCU40_IN0_ERU0_PDOUT0 9 428 #define CCU40_IN0_ERU0_PDOUT1 3 429 #define CCU40_IN0_P0_0 2 430 #define CCU40_IN0_P0_12 0 431 #define CCU40_IN0_P0_6 1 432 #define CCU40_IN0_SCU_GSC40 8 433 #define CCU40_IN0_U0C0_DX2INS 11 434 #define CCU40_IN1_CCU40_GP02 12 435 #define CCU40_IN1_CCU40_ST0 13 436 #define CCU40_IN1_CCU40_ST2 14 437 #define CCU40_IN1_CCU40_ST3 15 438 #define CCU40_IN1_ERU0_IOUT1 10 439 #define CCU40_IN1_ERU0_PDOUT0 3 440 #define CCU40_IN1_ERU0_PDOUT1 9 441 #define CCU40_IN1_P0_12 0 442 #define CCU40_IN1_P0_7 1 443 #define CCU40_IN1_SCU_GSC40 8 444 #define CCU40_IN1_U0C1_DX2INS 11 445 #define CCU40_IN2_CCU40_GP03 12 446 #define CCU40_IN2_CCU40_ST0 13 447 #define CCU40_IN2_CCU40_ST1 14 448 #define CCU40_IN2_CCU40_ST3 15 449 #define CCU40_IN2_ERU0_IOUT2 10 450 #define CCU40_IN2_ERU0_PDOUT2 9 451 #define CCU40_IN2_ERU0_PDOUT3 3 452 #define CCU40_IN2_LEDTSledts_SR0 11 453 #define CCU40_IN2_P0_12 0 454 #define CCU40_IN2_P0_8 1 455 #define CCU40_IN2_SCU_GSC40 8 456 #define CCU40_IN3_CCU40_GP00 12 457 #define CCU40_IN3_CCU40_ST0 13 458 #define CCU40_IN3_CCU40_ST1 14 459 #define CCU40_IN3_CCU40_ST2 15 460 #define CCU40_IN3_ERU0_IOUT3 10 461 #define CCU40_IN3_ERU0_PDOUT2 3 462 #define CCU40_IN3_ERU0_PDOUT3 9 463 #define CCU40_IN3_LEDTSledts_SR0 11 464 #define CCU40_IN3_P0_12 0 465 #define CCU40_IN3_P0_9 1 466 #define CCU40_IN3_SCU_GSC40 8 467 #define CCU40_IN3_VADC0_G0ARBCNT 6 468 #endif 469 470 471 #if (UC_DEVICE == XMC1201) && (UC_PACKAGE == TSSOP38) 472 #define CCU40_IN0_CCU40_GP01 12 473 #define CCU40_IN0_CCU40_ST1 13 474 #define CCU40_IN0_CCU40_ST2 14 475 #define CCU40_IN0_CCU40_ST3 15 476 #define CCU40_IN0_ERU0_IOUT0 10 477 #define CCU40_IN0_ERU0_PDOUT0 9 478 #define CCU40_IN0_ERU0_PDOUT1 3 479 #define CCU40_IN0_P0_0 2 480 #define CCU40_IN0_P0_12 0 481 #define CCU40_IN0_P0_6 1 482 #define CCU40_IN0_SCU_GSC40 8 483 #define CCU40_IN0_U0C0_DX2INS 11 484 #define CCU40_IN1_CCU40_GP02 12 485 #define CCU40_IN1_CCU40_ST0 13 486 #define CCU40_IN1_CCU40_ST2 14 487 #define CCU40_IN1_CCU40_ST3 15 488 #define CCU40_IN1_ERU0_IOUT1 10 489 #define CCU40_IN1_ERU0_PDOUT0 3 490 #define CCU40_IN1_ERU0_PDOUT1 9 491 #define CCU40_IN1_P0_1 2 492 #define CCU40_IN1_P0_12 0 493 #define CCU40_IN1_P0_7 1 494 #define CCU40_IN1_SCU_GSC40 8 495 #define CCU40_IN1_U0C1_DX2INS 11 496 #define CCU40_IN2_CCU40_GP03 12 497 #define CCU40_IN2_CCU40_ST0 13 498 #define CCU40_IN2_CCU40_ST1 14 499 #define CCU40_IN2_CCU40_ST3 15 500 #define CCU40_IN2_ERU0_IOUT2 10 501 #define CCU40_IN2_ERU0_PDOUT2 9 502 #define CCU40_IN2_ERU0_PDOUT3 3 503 #define CCU40_IN2_LEDTSledts_SR0 11 504 #define CCU40_IN2_P0_12 0 505 #define CCU40_IN2_P0_2 2 506 #define CCU40_IN2_P0_8 1 507 #define CCU40_IN2_SCU_GSC40 8 508 #define CCU40_IN3_CCU40_GP00 12 509 #define CCU40_IN3_CCU40_ST0 13 510 #define CCU40_IN3_CCU40_ST1 14 511 #define CCU40_IN3_CCU40_ST2 15 512 #define CCU40_IN3_ERU0_IOUT3 10 513 #define CCU40_IN3_ERU0_PDOUT2 3 514 #define CCU40_IN3_ERU0_PDOUT3 9 515 #define CCU40_IN3_LEDTSledts_SR0 11 516 #define CCU40_IN3_P0_12 0 517 #define CCU40_IN3_P0_3 2 518 #define CCU40_IN3_P0_9 1 519 #define CCU40_IN3_SCU_GSC40 8 520 #define CCU40_IN3_VADC0_G0ARBCNT 6 521 #endif 522 523 524 #if (UC_DEVICE == XMC1202) && (UC_PACKAGE == VQFN24) 525 #define CCU40_IN0_CCU40_GP01 12 526 #define CCU40_IN0_CCU40_ST1 13 527 #define CCU40_IN0_CCU40_ST2 14 528 #define CCU40_IN0_CCU40_ST3 15 529 #define CCU40_IN0_ERU0_IOUT0 10 530 #define CCU40_IN0_ERU0_PDOUT0 9 531 #define CCU40_IN0_ERU0_PDOUT1 3 532 #define CCU40_IN0_P0_0 2 533 #define CCU40_IN0_P0_12 0 534 #define CCU40_IN0_P0_6 1 535 #define CCU40_IN0_SCU_GSC40 8 536 #define CCU40_IN0_U0C0_DX2INS 11 537 #define CCU40_IN1_CCU40_GP02 12 538 #define CCU40_IN1_CCU40_ST0 13 539 #define CCU40_IN1_CCU40_ST2 14 540 #define CCU40_IN1_CCU40_ST3 15 541 #define CCU40_IN1_ERU0_IOUT1 10 542 #define CCU40_IN1_ERU0_PDOUT0 3 543 #define CCU40_IN1_ERU0_PDOUT1 9 544 #define CCU40_IN1_P0_12 0 545 #define CCU40_IN1_P0_7 1 546 #define CCU40_IN1_SCU_GSC40 8 547 #define CCU40_IN1_U0C1_DX2INS 11 548 #define CCU40_IN2_CCU40_GP03 12 549 #define CCU40_IN2_CCU40_ST0 13 550 #define CCU40_IN2_CCU40_ST1 14 551 #define CCU40_IN2_CCU40_ST3 15 552 #define CCU40_IN2_ERU0_IOUT2 10 553 #define CCU40_IN2_ERU0_PDOUT2 9 554 #define CCU40_IN2_ERU0_PDOUT3 3 555 #define CCU40_IN2_P0_12 0 556 #define CCU40_IN2_P0_8 1 557 #define CCU40_IN2_SCU_GSC40 8 558 #define CCU40_IN3_CCU40_GP00 12 559 #define CCU40_IN3_CCU40_ST0 13 560 #define CCU40_IN3_CCU40_ST1 14 561 #define CCU40_IN3_CCU40_ST2 15 562 #define CCU40_IN3_ERU0_IOUT3 10 563 #define CCU40_IN3_ERU0_PDOUT2 3 564 #define CCU40_IN3_ERU0_PDOUT3 9 565 #define CCU40_IN3_P0_12 0 566 #define CCU40_IN3_P0_9 1 567 #define CCU40_IN3_SCU_GSC40 8 568 #define CCU40_IN3_VADC0_G0ARBCNT 6 569 #endif 570 571 572 #if (UC_DEVICE == XMC1202) && (UC_PACKAGE == VQFN40) 573 #define CCU40_IN0_CCU40_GP01 12 574 #define CCU40_IN0_CCU40_ST1 13 575 #define CCU40_IN0_CCU40_ST2 14 576 #define CCU40_IN0_CCU40_ST3 15 577 #define CCU40_IN0_ERU0_IOUT0 10 578 #define CCU40_IN0_ERU0_PDOUT0 9 579 #define CCU40_IN0_ERU0_PDOUT1 3 580 #define CCU40_IN0_P0_0 2 581 #define CCU40_IN0_P0_12 0 582 #define CCU40_IN0_P0_6 1 583 #define CCU40_IN0_SCU_GSC40 8 584 #define CCU40_IN0_U0C0_DX2INS 11 585 #define CCU40_IN1_CCU40_GP02 12 586 #define CCU40_IN1_CCU40_ST0 13 587 #define CCU40_IN1_CCU40_ST2 14 588 #define CCU40_IN1_CCU40_ST3 15 589 #define CCU40_IN1_ERU0_IOUT1 10 590 #define CCU40_IN1_ERU0_PDOUT0 3 591 #define CCU40_IN1_ERU0_PDOUT1 9 592 #define CCU40_IN1_P0_1 2 593 #define CCU40_IN1_P0_12 0 594 #define CCU40_IN1_P0_7 1 595 #define CCU40_IN1_SCU_GSC40 8 596 #define CCU40_IN1_U0C1_DX2INS 11 597 #define CCU40_IN2_CCU40_GP03 12 598 #define CCU40_IN2_CCU40_ST0 13 599 #define CCU40_IN2_CCU40_ST1 14 600 #define CCU40_IN2_CCU40_ST3 15 601 #define CCU40_IN2_ERU0_IOUT2 10 602 #define CCU40_IN2_ERU0_PDOUT2 9 603 #define CCU40_IN2_ERU0_PDOUT3 3 604 #define CCU40_IN2_P0_12 0 605 #define CCU40_IN2_P0_2 2 606 #define CCU40_IN2_P0_8 1 607 #define CCU40_IN2_SCU_GSC40 8 608 #define CCU40_IN3_CCU40_GP00 12 609 #define CCU40_IN3_CCU40_ST0 13 610 #define CCU40_IN3_CCU40_ST1 14 611 #define CCU40_IN3_CCU40_ST2 15 612 #define CCU40_IN3_ERU0_IOUT3 10 613 #define CCU40_IN3_ERU0_PDOUT2 3 614 #define CCU40_IN3_ERU0_PDOUT3 9 615 #define CCU40_IN3_P0_12 0 616 #define CCU40_IN3_P0_3 2 617 #define CCU40_IN3_P0_9 1 618 #define CCU40_IN3_SCU_GSC40 8 619 #define CCU40_IN3_VADC0_G0ARBCNT 6 620 #endif 621 622 623 #if (UC_DEVICE == XMC1202) && (UC_PACKAGE == TSSOP16) 624 #define CCU40_IN0_CCU40_GP01 12 625 #define CCU40_IN0_CCU40_ST1 13 626 #define CCU40_IN0_CCU40_ST2 14 627 #define CCU40_IN0_CCU40_ST3 15 628 #define CCU40_IN0_ERU0_IOUT0 10 629 #define CCU40_IN0_ERU0_PDOUT0 9 630 #define CCU40_IN0_ERU0_PDOUT1 3 631 #define CCU40_IN0_P0_0 2 632 #define CCU40_IN0_P0_6 1 633 #define CCU40_IN0_SCU_GSC40 8 634 #define CCU40_IN0_U0C0_DX2INS 11 635 #define CCU40_IN1_CCU40_GP02 12 636 #define CCU40_IN1_CCU40_ST0 13 637 #define CCU40_IN1_CCU40_ST2 14 638 #define CCU40_IN1_CCU40_ST3 15 639 #define CCU40_IN1_ERU0_IOUT1 10 640 #define CCU40_IN1_ERU0_PDOUT0 3 641 #define CCU40_IN1_ERU0_PDOUT1 9 642 #define CCU40_IN1_P0_7 1 643 #define CCU40_IN1_SCU_GSC40 8 644 #define CCU40_IN1_U0C1_DX2INS 11 645 #define CCU40_IN2_CCU40_GP03 12 646 #define CCU40_IN2_CCU40_ST0 13 647 #define CCU40_IN2_CCU40_ST1 14 648 #define CCU40_IN2_CCU40_ST3 15 649 #define CCU40_IN2_ERU0_IOUT2 10 650 #define CCU40_IN2_ERU0_PDOUT2 9 651 #define CCU40_IN2_ERU0_PDOUT3 3 652 #define CCU40_IN2_P0_8 1 653 #define CCU40_IN2_SCU_GSC40 8 654 #define CCU40_IN3_CCU40_GP00 12 655 #define CCU40_IN3_CCU40_ST0 13 656 #define CCU40_IN3_CCU40_ST1 14 657 #define CCU40_IN3_CCU40_ST2 15 658 #define CCU40_IN3_ERU0_IOUT3 10 659 #define CCU40_IN3_ERU0_PDOUT2 3 660 #define CCU40_IN3_ERU0_PDOUT3 9 661 #define CCU40_IN3_P0_9 1 662 #define CCU40_IN3_SCU_GSC40 8 663 #define CCU40_IN3_VADC0_G0ARBCNT 6 664 #endif 665 666 667 #if (UC_DEVICE == XMC1202) && (UC_PACKAGE == TSSOP28) 668 #define CCU40_IN0_CCU40_GP01 12 669 #define CCU40_IN0_CCU40_ST1 13 670 #define CCU40_IN0_CCU40_ST2 14 671 #define CCU40_IN0_CCU40_ST3 15 672 #define CCU40_IN0_ERU0_IOUT0 10 673 #define CCU40_IN0_ERU0_PDOUT0 9 674 #define CCU40_IN0_ERU0_PDOUT1 3 675 #define CCU40_IN0_P0_0 2 676 #define CCU40_IN0_P0_12 0 677 #define CCU40_IN0_P0_6 1 678 #define CCU40_IN0_SCU_GSC40 8 679 #define CCU40_IN0_U0C0_DX2INS 11 680 #define CCU40_IN1_CCU40_GP02 12 681 #define CCU40_IN1_CCU40_ST0 13 682 #define CCU40_IN1_CCU40_ST2 14 683 #define CCU40_IN1_CCU40_ST3 15 684 #define CCU40_IN1_ERU0_IOUT1 10 685 #define CCU40_IN1_ERU0_PDOUT0 3 686 #define CCU40_IN1_ERU0_PDOUT1 9 687 #define CCU40_IN1_P0_12 0 688 #define CCU40_IN1_P0_7 1 689 #define CCU40_IN1_SCU_GSC40 8 690 #define CCU40_IN1_U0C1_DX2INS 11 691 #define CCU40_IN2_CCU40_GP03 12 692 #define CCU40_IN2_CCU40_ST0 13 693 #define CCU40_IN2_CCU40_ST1 14 694 #define CCU40_IN2_CCU40_ST3 15 695 #define CCU40_IN2_ERU0_IOUT2 10 696 #define CCU40_IN2_ERU0_PDOUT2 9 697 #define CCU40_IN2_ERU0_PDOUT3 3 698 #define CCU40_IN2_P0_12 0 699 #define CCU40_IN2_P0_8 1 700 #define CCU40_IN2_SCU_GSC40 8 701 #define CCU40_IN3_CCU40_GP00 12 702 #define CCU40_IN3_CCU40_ST0 13 703 #define CCU40_IN3_CCU40_ST1 14 704 #define CCU40_IN3_CCU40_ST2 15 705 #define CCU40_IN3_ERU0_IOUT3 10 706 #define CCU40_IN3_ERU0_PDOUT2 3 707 #define CCU40_IN3_ERU0_PDOUT3 9 708 #define CCU40_IN3_P0_12 0 709 #define CCU40_IN3_P0_9 1 710 #define CCU40_IN3_SCU_GSC40 8 711 #define CCU40_IN3_VADC0_G0ARBCNT 6 712 #endif 713 714 715 #if (UC_DEVICE == XMC1301) && (UC_PACKAGE == VQFN24) 716 #define CCU40_IN0_CCU40_GP01 12 717 #define CCU40_IN0_CCU40_ST1 13 718 #define CCU40_IN0_CCU40_ST2 14 719 #define CCU40_IN0_CCU40_ST3 15 720 #define CCU40_IN0_CCU80_ST3 7 721 #define CCU40_IN0_ERU0_IOUT0 10 722 #define CCU40_IN0_ERU0_PDOUT0 9 723 #define CCU40_IN0_ERU0_PDOUT1 3 724 #define CCU40_IN0_P0_0 2 725 #define CCU40_IN0_P0_12 0 726 #define CCU40_IN0_P0_6 1 727 #define CCU40_IN0_POSIF0_OUT0 4 728 #define CCU40_IN0_POSIF0_OUT1 5 729 #define CCU40_IN0_POSIF0_OUT3 6 730 #define CCU40_IN0_SCU_GSC40 8 731 #define CCU40_IN0_U0C0_DX2INS 11 732 #define CCU40_IN1_CCU40_GP02 12 733 #define CCU40_IN1_CCU40_ST0 13 734 #define CCU40_IN1_CCU40_ST2 14 735 #define CCU40_IN1_CCU40_ST3 15 736 #define CCU40_IN1_ERU0_IOUT1 10 737 #define CCU40_IN1_ERU0_PDOUT0 3 738 #define CCU40_IN1_ERU0_PDOUT1 9 739 #define CCU40_IN1_P0_12 0 740 #define CCU40_IN1_P0_7 1 741 #define CCU40_IN1_POSIF0_OUT0 4 742 #define CCU40_IN1_POSIF0_OUT1 5 743 #define CCU40_IN1_POSIF0_OUT3 6 744 #define CCU40_IN1_POSIF0_OUT4 7 745 #define CCU40_IN1_SCU_GSC40 8 746 #define CCU40_IN1_U0C1_DX2INS 11 747 #define CCU40_IN2_CCU40_GP03 12 748 #define CCU40_IN2_CCU40_ST0 13 749 #define CCU40_IN2_CCU40_ST1 14 750 #define CCU40_IN2_CCU40_ST3 15 751 #define CCU40_IN2_ERU0_IOUT2 10 752 #define CCU40_IN2_ERU0_PDOUT2 9 753 #define CCU40_IN2_ERU0_PDOUT3 3 754 #define CCU40_IN2_P0_12 0 755 #define CCU40_IN2_P0_8 1 756 #define CCU40_IN2_POSIF0_OUT1 4 757 #define CCU40_IN2_POSIF0_OUT2 5 758 #define CCU40_IN2_POSIF0_OUT3 6 759 #define CCU40_IN2_POSIF0_OUT4 7 760 #define CCU40_IN2_SCU_GSC40 8 761 #define CCU40_IN3_CCU40_GP00 12 762 #define CCU40_IN3_CCU40_ST0 13 763 #define CCU40_IN3_CCU40_ST1 14 764 #define CCU40_IN3_CCU40_ST2 15 765 #define CCU40_IN3_CCU80_IGBTO 7 766 #define CCU40_IN3_ERU0_IOUT3 10 767 #define CCU40_IN3_ERU0_PDOUT2 3 768 #define CCU40_IN3_ERU0_PDOUT3 9 769 #define CCU40_IN3_P0_12 0 770 #define CCU40_IN3_P0_9 1 771 #define CCU40_IN3_POSIF0_OUT3 4 772 #define CCU40_IN3_POSIF0_OUT5 5 773 #define CCU40_IN3_SCU_GSC40 8 774 #define CCU40_IN3_VADC0_G0ARBCNT 6 775 #endif 776 777 778 #if (UC_DEVICE == XMC1301) && (UC_PACKAGE == VQFN40) 779 #define CCU40_IN0_CCU40_GP01 12 780 #define CCU40_IN0_CCU40_ST1 13 781 #define CCU40_IN0_CCU40_ST2 14 782 #define CCU40_IN0_CCU40_ST3 15 783 #define CCU40_IN0_CCU80_ST3 7 784 #define CCU40_IN0_ERU0_IOUT0 10 785 #define CCU40_IN0_ERU0_PDOUT0 9 786 #define CCU40_IN0_ERU0_PDOUT1 3 787 #define CCU40_IN0_P0_0 2 788 #define CCU40_IN0_P0_12 0 789 #define CCU40_IN0_P0_6 1 790 #define CCU40_IN0_POSIF0_OUT0 4 791 #define CCU40_IN0_POSIF0_OUT1 5 792 #define CCU40_IN0_POSIF0_OUT3 6 793 #define CCU40_IN0_SCU_GSC40 8 794 #define CCU40_IN0_U0C0_DX2INS 11 795 #define CCU40_IN1_CCU40_GP02 12 796 #define CCU40_IN1_CCU40_ST0 13 797 #define CCU40_IN1_CCU40_ST2 14 798 #define CCU40_IN1_CCU40_ST3 15 799 #define CCU40_IN1_ERU0_IOUT1 10 800 #define CCU40_IN1_ERU0_PDOUT0 3 801 #define CCU40_IN1_ERU0_PDOUT1 9 802 #define CCU40_IN1_P0_1 2 803 #define CCU40_IN1_P0_12 0 804 #define CCU40_IN1_P0_7 1 805 #define CCU40_IN1_POSIF0_OUT0 4 806 #define CCU40_IN1_POSIF0_OUT1 5 807 #define CCU40_IN1_POSIF0_OUT3 6 808 #define CCU40_IN1_POSIF0_OUT4 7 809 #define CCU40_IN1_SCU_GSC40 8 810 #define CCU40_IN1_U0C1_DX2INS 11 811 #define CCU40_IN2_CCU40_GP03 12 812 #define CCU40_IN2_CCU40_ST0 13 813 #define CCU40_IN2_CCU40_ST1 14 814 #define CCU40_IN2_CCU40_ST3 15 815 #define CCU40_IN2_ERU0_IOUT2 10 816 #define CCU40_IN2_ERU0_PDOUT2 9 817 #define CCU40_IN2_ERU0_PDOUT3 3 818 #define CCU40_IN2_P0_12 0 819 #define CCU40_IN2_P0_2 2 820 #define CCU40_IN2_P0_8 1 821 #define CCU40_IN2_POSIF0_OUT1 4 822 #define CCU40_IN2_POSIF0_OUT2 5 823 #define CCU40_IN2_POSIF0_OUT3 6 824 #define CCU40_IN2_POSIF0_OUT4 7 825 #define CCU40_IN2_SCU_GSC40 8 826 #define CCU40_IN3_CCU40_GP00 12 827 #define CCU40_IN3_CCU40_ST0 13 828 #define CCU40_IN3_CCU40_ST1 14 829 #define CCU40_IN3_CCU40_ST2 15 830 #define CCU40_IN3_CCU80_IGBTO 7 831 #define CCU40_IN3_ERU0_IOUT3 10 832 #define CCU40_IN3_ERU0_PDOUT2 3 833 #define CCU40_IN3_ERU0_PDOUT3 9 834 #define CCU40_IN3_P0_12 0 835 #define CCU40_IN3_P0_3 2 836 #define CCU40_IN3_P0_9 1 837 #define CCU40_IN3_POSIF0_OUT3 4 838 #define CCU40_IN3_POSIF0_OUT5 5 839 #define CCU40_IN3_SCU_GSC40 8 840 #define CCU40_IN3_VADC0_G0ARBCNT 6 841 #endif 842 843 844 #if (UC_DEVICE == XMC1301) && (UC_PACKAGE == TSSOP16) 845 #define CCU40_IN0_CCU40_GP01 12 846 #define CCU40_IN0_CCU40_ST1 13 847 #define CCU40_IN0_CCU40_ST2 14 848 #define CCU40_IN0_CCU40_ST3 15 849 #define CCU40_IN0_CCU80_ST3 7 850 #define CCU40_IN0_ERU0_IOUT0 10 851 #define CCU40_IN0_ERU0_PDOUT0 9 852 #define CCU40_IN0_ERU0_PDOUT1 3 853 #define CCU40_IN0_P0_0 2 854 #define CCU40_IN0_P0_6 1 855 #define CCU40_IN0_POSIF0_OUT0 4 856 #define CCU40_IN0_POSIF0_OUT1 5 857 #define CCU40_IN0_POSIF0_OUT3 6 858 #define CCU40_IN0_SCU_GSC40 8 859 #define CCU40_IN0_U0C0_DX2INS 11 860 #define CCU40_IN1_CCU40_GP02 12 861 #define CCU40_IN1_CCU40_ST0 13 862 #define CCU40_IN1_CCU40_ST2 14 863 #define CCU40_IN1_CCU40_ST3 15 864 #define CCU40_IN1_ERU0_IOUT1 10 865 #define CCU40_IN1_ERU0_PDOUT0 3 866 #define CCU40_IN1_ERU0_PDOUT1 9 867 #define CCU40_IN1_P0_7 1 868 #define CCU40_IN1_POSIF0_OUT0 4 869 #define CCU40_IN1_POSIF0_OUT1 5 870 #define CCU40_IN1_POSIF0_OUT3 6 871 #define CCU40_IN1_POSIF0_OUT4 7 872 #define CCU40_IN1_SCU_GSC40 8 873 #define CCU40_IN1_U0C1_DX2INS 11 874 #define CCU40_IN2_CCU40_GP03 12 875 #define CCU40_IN2_CCU40_ST0 13 876 #define CCU40_IN2_CCU40_ST1 14 877 #define CCU40_IN2_CCU40_ST3 15 878 #define CCU40_IN2_ERU0_IOUT2 10 879 #define CCU40_IN2_ERU0_PDOUT2 9 880 #define CCU40_IN2_ERU0_PDOUT3 3 881 #define CCU40_IN2_P0_8 1 882 #define CCU40_IN2_POSIF0_OUT1 4 883 #define CCU40_IN2_POSIF0_OUT2 5 884 #define CCU40_IN2_POSIF0_OUT3 6 885 #define CCU40_IN2_POSIF0_OUT4 7 886 #define CCU40_IN2_SCU_GSC40 8 887 #define CCU40_IN3_CCU40_GP00 12 888 #define CCU40_IN3_CCU40_ST0 13 889 #define CCU40_IN3_CCU40_ST1 14 890 #define CCU40_IN3_CCU40_ST2 15 891 #define CCU40_IN3_CCU80_IGBTO 7 892 #define CCU40_IN3_ERU0_IOUT3 10 893 #define CCU40_IN3_ERU0_PDOUT2 3 894 #define CCU40_IN3_ERU0_PDOUT3 9 895 #define CCU40_IN3_P0_9 1 896 #define CCU40_IN3_POSIF0_OUT3 4 897 #define CCU40_IN3_POSIF0_OUT5 5 898 #define CCU40_IN3_SCU_GSC40 8 899 #define CCU40_IN3_VADC0_G0ARBCNT 6 900 #endif 901 902 903 #if (UC_DEVICE == XMC1301) && (UC_PACKAGE == TSSOP38) 904 #define CCU40_IN0_CCU40_GP01 12 905 #define CCU40_IN0_CCU40_ST1 13 906 #define CCU40_IN0_CCU40_ST2 14 907 #define CCU40_IN0_CCU40_ST3 15 908 #define CCU40_IN0_CCU80_ST3 7 909 #define CCU40_IN0_ERU0_IOUT0 10 910 #define CCU40_IN0_ERU0_PDOUT0 9 911 #define CCU40_IN0_ERU0_PDOUT1 3 912 #define CCU40_IN0_P0_0 2 913 #define CCU40_IN0_P0_12 0 914 #define CCU40_IN0_P0_6 1 915 #define CCU40_IN0_POSIF0_OUT0 4 916 #define CCU40_IN0_POSIF0_OUT1 5 917 #define CCU40_IN0_POSIF0_OUT3 6 918 #define CCU40_IN0_SCU_GSC40 8 919 #define CCU40_IN0_U0C0_DX2INS 11 920 #define CCU40_IN1_CCU40_GP02 12 921 #define CCU40_IN1_CCU40_ST0 13 922 #define CCU40_IN1_CCU40_ST2 14 923 #define CCU40_IN1_CCU40_ST3 15 924 #define CCU40_IN1_ERU0_IOUT1 10 925 #define CCU40_IN1_ERU0_PDOUT0 3 926 #define CCU40_IN1_ERU0_PDOUT1 9 927 #define CCU40_IN1_P0_1 2 928 #define CCU40_IN1_P0_12 0 929 #define CCU40_IN1_P0_7 1 930 #define CCU40_IN1_POSIF0_OUT0 4 931 #define CCU40_IN1_POSIF0_OUT1 5 932 #define CCU40_IN1_POSIF0_OUT3 6 933 #define CCU40_IN1_POSIF0_OUT4 7 934 #define CCU40_IN1_SCU_GSC40 8 935 #define CCU40_IN1_U0C1_DX2INS 11 936 #define CCU40_IN2_CCU40_GP03 12 937 #define CCU40_IN2_CCU40_ST0 13 938 #define CCU40_IN2_CCU40_ST1 14 939 #define CCU40_IN2_CCU40_ST3 15 940 #define CCU40_IN2_ERU0_IOUT2 10 941 #define CCU40_IN2_ERU0_PDOUT2 9 942 #define CCU40_IN2_ERU0_PDOUT3 3 943 #define CCU40_IN2_P0_12 0 944 #define CCU40_IN2_P0_2 2 945 #define CCU40_IN2_P0_8 1 946 #define CCU40_IN2_POSIF0_OUT1 4 947 #define CCU40_IN2_POSIF0_OUT2 5 948 #define CCU40_IN2_POSIF0_OUT3 6 949 #define CCU40_IN2_POSIF0_OUT4 7 950 #define CCU40_IN2_SCU_GSC40 8 951 #define CCU40_IN3_CCU40_GP00 12 952 #define CCU40_IN3_CCU40_ST0 13 953 #define CCU40_IN3_CCU40_ST1 14 954 #define CCU40_IN3_CCU40_ST2 15 955 #define CCU40_IN3_CCU80_IGBTO 7 956 #define CCU40_IN3_ERU0_IOUT3 10 957 #define CCU40_IN3_ERU0_PDOUT2 3 958 #define CCU40_IN3_ERU0_PDOUT3 9 959 #define CCU40_IN3_P0_12 0 960 #define CCU40_IN3_P0_3 2 961 #define CCU40_IN3_P0_9 1 962 #define CCU40_IN3_POSIF0_OUT3 4 963 #define CCU40_IN3_POSIF0_OUT5 5 964 #define CCU40_IN3_SCU_GSC40 8 965 #define CCU40_IN3_VADC0_G0ARBCNT 6 966 #endif 967 968 969 #if (UC_DEVICE == XMC1302) && (UC_PACKAGE == VQFN24) 970 #define CCU40_IN0_CCU40_GP01 12 971 #define CCU40_IN0_CCU40_ST1 13 972 #define CCU40_IN0_CCU40_ST2 14 973 #define CCU40_IN0_CCU40_ST3 15 974 #define CCU40_IN0_CCU80_ST3 7 975 #define CCU40_IN0_ERU0_IOUT0 10 976 #define CCU40_IN0_ERU0_PDOUT0 9 977 #define CCU40_IN0_ERU0_PDOUT1 3 978 #define CCU40_IN0_P0_0 2 979 #define CCU40_IN0_P0_12 0 980 #define CCU40_IN0_P0_6 1 981 #define CCU40_IN0_POSIF0_OUT0 4 982 #define CCU40_IN0_POSIF0_OUT1 5 983 #define CCU40_IN0_POSIF0_OUT3 6 984 #define CCU40_IN0_SCU_GSC40 8 985 #define CCU40_IN0_U0C0_DX2INS 11 986 #define CCU40_IN1_CCU40_GP02 12 987 #define CCU40_IN1_CCU40_ST0 13 988 #define CCU40_IN1_CCU40_ST2 14 989 #define CCU40_IN1_CCU40_ST3 15 990 #define CCU40_IN1_ERU0_IOUT1 10 991 #define CCU40_IN1_ERU0_PDOUT0 3 992 #define CCU40_IN1_ERU0_PDOUT1 9 993 #define CCU40_IN1_P0_12 0 994 #define CCU40_IN1_P0_7 1 995 #define CCU40_IN1_POSIF0_OUT0 4 996 #define CCU40_IN1_POSIF0_OUT1 5 997 #define CCU40_IN1_POSIF0_OUT3 6 998 #define CCU40_IN1_POSIF0_OUT4 7 999 #define CCU40_IN1_SCU_GSC40 8 1000 #define CCU40_IN1_U0C1_DX2INS 11 1001 #define CCU40_IN2_CCU40_GP03 12 1002 #define CCU40_IN2_CCU40_ST0 13 1003 #define CCU40_IN2_CCU40_ST1 14 1004 #define CCU40_IN2_CCU40_ST3 15 1005 #define CCU40_IN2_ERU0_IOUT2 10 1006 #define CCU40_IN2_ERU0_PDOUT2 9 1007 #define CCU40_IN2_ERU0_PDOUT3 3 1008 #define CCU40_IN2_P0_12 0 1009 #define CCU40_IN2_P0_8 1 1010 #define CCU40_IN2_POSIF0_OUT1 4 1011 #define CCU40_IN2_POSIF0_OUT2 5 1012 #define CCU40_IN2_POSIF0_OUT3 6 1013 #define CCU40_IN2_POSIF0_OUT4 7 1014 #define CCU40_IN2_SCU_GSC40 8 1015 #define CCU40_IN3_CCU40_GP00 12 1016 #define CCU40_IN3_CCU40_ST0 13 1017 #define CCU40_IN3_CCU40_ST1 14 1018 #define CCU40_IN3_CCU40_ST2 15 1019 #define CCU40_IN3_CCU80_IGBTO 7 1020 #define CCU40_IN3_ERU0_IOUT3 10 1021 #define CCU40_IN3_ERU0_PDOUT2 3 1022 #define CCU40_IN3_ERU0_PDOUT3 9 1023 #define CCU40_IN3_P0_12 0 1024 #define CCU40_IN3_P0_9 1 1025 #define CCU40_IN3_POSIF0_OUT3 4 1026 #define CCU40_IN3_POSIF0_OUT5 5 1027 #define CCU40_IN3_SCU_GSC40 8 1028 #define CCU40_IN3_VADC0_G0ARBCNT 6 1029 #endif 1030 1031 1032 #if (UC_DEVICE == XMC1302) && (UC_PACKAGE == VQFN40) 1033 #define CCU40_IN0_CCU40_GP01 12 1034 #define CCU40_IN0_CCU40_ST1 13 1035 #define CCU40_IN0_CCU40_ST2 14 1036 #define CCU40_IN0_CCU40_ST3 15 1037 #define CCU40_IN0_CCU80_ST3 7 1038 #define CCU40_IN0_ERU0_IOUT0 10 1039 #define CCU40_IN0_ERU0_PDOUT0 9 1040 #define CCU40_IN0_ERU0_PDOUT1 3 1041 #define CCU40_IN0_P0_0 2 1042 #define CCU40_IN0_P0_12 0 1043 #define CCU40_IN0_P0_6 1 1044 #define CCU40_IN0_POSIF0_OUT0 4 1045 #define CCU40_IN0_POSIF0_OUT1 5 1046 #define CCU40_IN0_POSIF0_OUT3 6 1047 #define CCU40_IN0_SCU_GSC40 8 1048 #define CCU40_IN0_U0C0_DX2INS 11 1049 #define CCU40_IN1_CCU40_GP02 12 1050 #define CCU40_IN1_CCU40_ST0 13 1051 #define CCU40_IN1_CCU40_ST2 14 1052 #define CCU40_IN1_CCU40_ST3 15 1053 #define CCU40_IN1_ERU0_IOUT1 10 1054 #define CCU40_IN1_ERU0_PDOUT0 3 1055 #define CCU40_IN1_ERU0_PDOUT1 9 1056 #define CCU40_IN1_P0_1 2 1057 #define CCU40_IN1_P0_12 0 1058 #define CCU40_IN1_P0_7 1 1059 #define CCU40_IN1_POSIF0_OUT0 4 1060 #define CCU40_IN1_POSIF0_OUT1 5 1061 #define CCU40_IN1_POSIF0_OUT3 6 1062 #define CCU40_IN1_POSIF0_OUT4 7 1063 #define CCU40_IN1_SCU_GSC40 8 1064 #define CCU40_IN1_U0C1_DX2INS 11 1065 #define CCU40_IN2_CCU40_GP03 12 1066 #define CCU40_IN2_CCU40_ST0 13 1067 #define CCU40_IN2_CCU40_ST1 14 1068 #define CCU40_IN2_CCU40_ST3 15 1069 #define CCU40_IN2_ERU0_IOUT2 10 1070 #define CCU40_IN2_ERU0_PDOUT2 9 1071 #define CCU40_IN2_ERU0_PDOUT3 3 1072 #define CCU40_IN2_P0_12 0 1073 #define CCU40_IN2_P0_2 2 1074 #define CCU40_IN2_P0_8 1 1075 #define CCU40_IN2_POSIF0_OUT1 4 1076 #define CCU40_IN2_POSIF0_OUT2 5 1077 #define CCU40_IN2_POSIF0_OUT3 6 1078 #define CCU40_IN2_POSIF0_OUT4 7 1079 #define CCU40_IN2_SCU_GSC40 8 1080 #define CCU40_IN3_CCU40_GP00 12 1081 #define CCU40_IN3_CCU40_ST0 13 1082 #define CCU40_IN3_CCU40_ST1 14 1083 #define CCU40_IN3_CCU40_ST2 15 1084 #define CCU40_IN3_CCU80_IGBTO 7 1085 #define CCU40_IN3_ERU0_IOUT3 10 1086 #define CCU40_IN3_ERU0_PDOUT2 3 1087 #define CCU40_IN3_ERU0_PDOUT3 9 1088 #define CCU40_IN3_P0_12 0 1089 #define CCU40_IN3_P0_3 2 1090 #define CCU40_IN3_P0_9 1 1091 #define CCU40_IN3_POSIF0_OUT3 4 1092 #define CCU40_IN3_POSIF0_OUT5 5 1093 #define CCU40_IN3_SCU_GSC40 8 1094 #define CCU40_IN3_VADC0_G0ARBCNT 6 1095 #endif 1096 1097 1098 #if (UC_DEVICE == XMC1302) && (UC_PACKAGE == TSSOP16) 1099 #define CCU40_IN0_CCU40_GP01 12 1100 #define CCU40_IN0_CCU40_ST1 13 1101 #define CCU40_IN0_CCU40_ST2 14 1102 #define CCU40_IN0_CCU40_ST3 15 1103 #define CCU40_IN0_CCU80_ST3 7 1104 #define CCU40_IN0_ERU0_IOUT0 10 1105 #define CCU40_IN0_ERU0_PDOUT0 9 1106 #define CCU40_IN0_ERU0_PDOUT1 3 1107 #define CCU40_IN0_P0_0 2 1108 #define CCU40_IN0_P0_6 1 1109 #define CCU40_IN0_POSIF0_OUT0 4 1110 #define CCU40_IN0_POSIF0_OUT1 5 1111 #define CCU40_IN0_POSIF0_OUT3 6 1112 #define CCU40_IN0_SCU_GSC40 8 1113 #define CCU40_IN0_U0C0_DX2INS 11 1114 #define CCU40_IN1_CCU40_GP02 12 1115 #define CCU40_IN1_CCU40_ST0 13 1116 #define CCU40_IN1_CCU40_ST2 14 1117 #define CCU40_IN1_CCU40_ST3 15 1118 #define CCU40_IN1_ERU0_IOUT1 10 1119 #define CCU40_IN1_ERU0_PDOUT0 3 1120 #define CCU40_IN1_ERU0_PDOUT1 9 1121 #define CCU40_IN1_P0_7 1 1122 #define CCU40_IN1_POSIF0_OUT0 4 1123 #define CCU40_IN1_POSIF0_OUT1 5 1124 #define CCU40_IN1_POSIF0_OUT3 6 1125 #define CCU40_IN1_POSIF0_OUT4 7 1126 #define CCU40_IN1_SCU_GSC40 8 1127 #define CCU40_IN1_U0C1_DX2INS 11 1128 #define CCU40_IN2_CCU40_GP03 12 1129 #define CCU40_IN2_CCU40_ST0 13 1130 #define CCU40_IN2_CCU40_ST1 14 1131 #define CCU40_IN2_CCU40_ST3 15 1132 #define CCU40_IN2_ERU0_IOUT2 10 1133 #define CCU40_IN2_ERU0_PDOUT2 9 1134 #define CCU40_IN2_ERU0_PDOUT3 3 1135 #define CCU40_IN2_P0_8 1 1136 #define CCU40_IN2_POSIF0_OUT1 4 1137 #define CCU40_IN2_POSIF0_OUT2 5 1138 #define CCU40_IN2_POSIF0_OUT3 6 1139 #define CCU40_IN2_POSIF0_OUT4 7 1140 #define CCU40_IN2_SCU_GSC40 8 1141 #define CCU40_IN3_CCU40_GP00 12 1142 #define CCU40_IN3_CCU40_ST0 13 1143 #define CCU40_IN3_CCU40_ST1 14 1144 #define CCU40_IN3_CCU40_ST2 15 1145 #define CCU40_IN3_CCU80_IGBTO 7 1146 #define CCU40_IN3_ERU0_IOUT3 10 1147 #define CCU40_IN3_ERU0_PDOUT2 3 1148 #define CCU40_IN3_ERU0_PDOUT3 9 1149 #define CCU40_IN3_P0_9 1 1150 #define CCU40_IN3_POSIF0_OUT3 4 1151 #define CCU40_IN3_POSIF0_OUT5 5 1152 #define CCU40_IN3_SCU_GSC40 8 1153 #define CCU40_IN3_VADC0_G0ARBCNT 6 1154 #endif 1155 1156 1157 #if (UC_DEVICE == XMC1302) && (UC_PACKAGE == TSSOP28) 1158 #define CCU40_IN0_CCU40_GP01 12 1159 #define CCU40_IN0_CCU40_ST1 13 1160 #define CCU40_IN0_CCU40_ST2 14 1161 #define CCU40_IN0_CCU40_ST3 15 1162 #define CCU40_IN0_CCU80_ST3 7 1163 #define CCU40_IN0_ERU0_IOUT0 10 1164 #define CCU40_IN0_ERU0_PDOUT0 9 1165 #define CCU40_IN0_ERU0_PDOUT1 3 1166 #define CCU40_IN0_P0_0 2 1167 #define CCU40_IN0_P0_12 0 1168 #define CCU40_IN0_P0_6 1 1169 #define CCU40_IN0_POSIF0_OUT0 4 1170 #define CCU40_IN0_POSIF0_OUT1 5 1171 #define CCU40_IN0_POSIF0_OUT3 6 1172 #define CCU40_IN0_SCU_GSC40 8 1173 #define CCU40_IN0_U0C0_DX2INS 11 1174 #define CCU40_IN1_CCU40_GP02 12 1175 #define CCU40_IN1_CCU40_ST0 13 1176 #define CCU40_IN1_CCU40_ST2 14 1177 #define CCU40_IN1_CCU40_ST3 15 1178 #define CCU40_IN1_ERU0_IOUT1 10 1179 #define CCU40_IN1_ERU0_PDOUT0 3 1180 #define CCU40_IN1_ERU0_PDOUT1 9 1181 #define CCU40_IN1_P0_12 0 1182 #define CCU40_IN1_P0_7 1 1183 #define CCU40_IN1_POSIF0_OUT0 4 1184 #define CCU40_IN1_POSIF0_OUT1 5 1185 #define CCU40_IN1_POSIF0_OUT3 6 1186 #define CCU40_IN1_POSIF0_OUT4 7 1187 #define CCU40_IN1_SCU_GSC40 8 1188 #define CCU40_IN1_U0C1_DX2INS 11 1189 #define CCU40_IN2_CCU40_GP03 12 1190 #define CCU40_IN2_CCU40_ST0 13 1191 #define CCU40_IN2_CCU40_ST1 14 1192 #define CCU40_IN2_CCU40_ST3 15 1193 #define CCU40_IN2_ERU0_IOUT2 10 1194 #define CCU40_IN2_ERU0_PDOUT2 9 1195 #define CCU40_IN2_ERU0_PDOUT3 3 1196 #define CCU40_IN2_P0_12 0 1197 #define CCU40_IN2_P0_8 1 1198 #define CCU40_IN2_POSIF0_OUT1 4 1199 #define CCU40_IN2_POSIF0_OUT2 5 1200 #define CCU40_IN2_POSIF0_OUT3 6 1201 #define CCU40_IN2_POSIF0_OUT4 7 1202 #define CCU40_IN2_SCU_GSC40 8 1203 #define CCU40_IN3_CCU40_GP00 12 1204 #define CCU40_IN3_CCU40_ST0 13 1205 #define CCU40_IN3_CCU40_ST1 14 1206 #define CCU40_IN3_CCU40_ST2 15 1207 #define CCU40_IN3_CCU80_IGBTO 7 1208 #define CCU40_IN3_ERU0_IOUT3 10 1209 #define CCU40_IN3_ERU0_PDOUT2 3 1210 #define CCU40_IN3_ERU0_PDOUT3 9 1211 #define CCU40_IN3_P0_12 0 1212 #define CCU40_IN3_P0_9 1 1213 #define CCU40_IN3_POSIF0_OUT3 4 1214 #define CCU40_IN3_POSIF0_OUT5 5 1215 #define CCU40_IN3_SCU_GSC40 8 1216 #define CCU40_IN3_VADC0_G0ARBCNT 6 1217 #endif 1218 1219 1220 #if (UC_DEVICE == XMC1302) && (UC_PACKAGE == TSSOP38) 1221 #define CCU40_IN0_CCU40_GP01 12 1222 #define CCU40_IN0_CCU40_ST1 13 1223 #define CCU40_IN0_CCU40_ST2 14 1224 #define CCU40_IN0_CCU40_ST3 15 1225 #define CCU40_IN0_CCU80_ST3 7 1226 #define CCU40_IN0_ERU0_IOUT0 10 1227 #define CCU40_IN0_ERU0_PDOUT0 9 1228 #define CCU40_IN0_ERU0_PDOUT1 3 1229 #define CCU40_IN0_P0_0 2 1230 #define CCU40_IN0_P0_12 0 1231 #define CCU40_IN0_P0_6 1 1232 #define CCU40_IN0_POSIF0_OUT0 4 1233 #define CCU40_IN0_POSIF0_OUT1 5 1234 #define CCU40_IN0_POSIF0_OUT3 6 1235 #define CCU40_IN0_SCU_GSC40 8 1236 #define CCU40_IN0_U0C0_DX2INS 11 1237 #define CCU40_IN1_CCU40_GP02 12 1238 #define CCU40_IN1_CCU40_ST0 13 1239 #define CCU40_IN1_CCU40_ST2 14 1240 #define CCU40_IN1_CCU40_ST3 15 1241 #define CCU40_IN1_ERU0_IOUT1 10 1242 #define CCU40_IN1_ERU0_PDOUT0 3 1243 #define CCU40_IN1_ERU0_PDOUT1 9 1244 #define CCU40_IN1_P0_1 2 1245 #define CCU40_IN1_P0_12 0 1246 #define CCU40_IN1_P0_7 1 1247 #define CCU40_IN1_POSIF0_OUT0 4 1248 #define CCU40_IN1_POSIF0_OUT1 5 1249 #define CCU40_IN1_POSIF0_OUT3 6 1250 #define CCU40_IN1_POSIF0_OUT4 7 1251 #define CCU40_IN1_SCU_GSC40 8 1252 #define CCU40_IN1_U0C1_DX2INS 11 1253 #define CCU40_IN2_CCU40_GP03 12 1254 #define CCU40_IN2_CCU40_ST0 13 1255 #define CCU40_IN2_CCU40_ST1 14 1256 #define CCU40_IN2_CCU40_ST3 15 1257 #define CCU40_IN2_ERU0_IOUT2 10 1258 #define CCU40_IN2_ERU0_PDOUT2 9 1259 #define CCU40_IN2_ERU0_PDOUT3 3 1260 #define CCU40_IN2_P0_12 0 1261 #define CCU40_IN2_P0_2 2 1262 #define CCU40_IN2_P0_8 1 1263 #define CCU40_IN2_POSIF0_OUT1 4 1264 #define CCU40_IN2_POSIF0_OUT2 5 1265 #define CCU40_IN2_POSIF0_OUT3 6 1266 #define CCU40_IN2_POSIF0_OUT4 7 1267 #define CCU40_IN2_SCU_GSC40 8 1268 #define CCU40_IN3_CCU40_GP00 12 1269 #define CCU40_IN3_CCU40_ST0 13 1270 #define CCU40_IN3_CCU40_ST1 14 1271 #define CCU40_IN3_CCU40_ST2 15 1272 #define CCU40_IN3_CCU80_IGBTO 7 1273 #define CCU40_IN3_ERU0_IOUT3 10 1274 #define CCU40_IN3_ERU0_PDOUT2 3 1275 #define CCU40_IN3_ERU0_PDOUT3 9 1276 #define CCU40_IN3_P0_12 0 1277 #define CCU40_IN3_P0_3 2 1278 #define CCU40_IN3_P0_9 1 1279 #define CCU40_IN3_POSIF0_OUT3 4 1280 #define CCU40_IN3_POSIF0_OUT5 5 1281 #define CCU40_IN3_SCU_GSC40 8 1282 #define CCU40_IN3_VADC0_G0ARBCNT 6 1283 #endif 1284 1285 1286 #if (UC_DEVICE == XMC1401) && (UC_PACKAGE == LQFP64) 1287 #define CCU40_IN0_CCU40_GP01 12 1288 #define CCU40_IN0_CCU40_SR0 27 1289 #define CCU40_IN0_CCU40_SR2 19 1290 #define CCU40_IN0_CCU40_ST0 20 1291 #define CCU40_IN0_CCU40_ST1 13 1292 #define CCU40_IN0_CCU40_ST2 14 1293 #define CCU40_IN0_CCU40_ST3 15 1294 #define CCU40_IN0_ERU0_IOUT0 10 1295 #define CCU40_IN0_ERU0_PDOUT0 9 1296 #define CCU40_IN0_ERU0_PDOUT1 3 1297 #define CCU40_IN0_ERU1_IOUT0 23 1298 #define CCU40_IN0_ERU1_PDOUT0 22 1299 #define CCU40_IN0_ERU1_PDOUT1 24 1300 #define CCU40_IN0_P0_0 2 1301 #define CCU40_IN0_P0_12 0 1302 #define CCU40_IN0_P0_6 1 1303 #define CCU40_IN0_P4_0 26 1304 #define CCU40_IN0_P4_8 21 1305 #define CCU40_IN0_SCU_GSC40 8 1306 #define CCU40_IN0_U0C0_DX2INS 11 1307 #define CCU40_IN1_CCU40_GP02 12 1308 #define CCU40_IN1_CCU40_SR1 27 1309 #define CCU40_IN1_CCU40_SR2 19 1310 #define CCU40_IN1_CCU40_ST0 13 1311 #define CCU40_IN1_CCU40_ST1 20 1312 #define CCU40_IN1_CCU40_ST2 14 1313 #define CCU40_IN1_CCU40_ST3 15 1314 #define CCU40_IN1_ERU0_IOUT1 10 1315 #define CCU40_IN1_ERU0_PDOUT0 3 1316 #define CCU40_IN1_ERU0_PDOUT1 9 1317 #define CCU40_IN1_ERU1_IOUT1 23 1318 #define CCU40_IN1_ERU1_PDOUT0 24 1319 #define CCU40_IN1_ERU1_PDOUT1 22 1320 #define CCU40_IN1_P0_1 2 1321 #define CCU40_IN1_P0_12 0 1322 #define CCU40_IN1_P0_7 1 1323 #define CCU40_IN1_P4_1 26 1324 #define CCU40_IN1_P4_9 21 1325 #define CCU40_IN1_SCU_GSC40 8 1326 #define CCU40_IN1_U0C1_DX2INS 11 1327 #define CCU40_IN2_CCU40_GP03 12 1328 #define CCU40_IN2_CCU40_SR1 19 1329 #define CCU40_IN2_CCU40_SR2 27 1330 #define CCU40_IN2_CCU40_ST0 13 1331 #define CCU40_IN2_CCU40_ST1 14 1332 #define CCU40_IN2_CCU40_ST2 20 1333 #define CCU40_IN2_CCU40_ST3 15 1334 #define CCU40_IN2_ERU0_IOUT2 10 1335 #define CCU40_IN2_ERU0_PDOUT2 9 1336 #define CCU40_IN2_ERU0_PDOUT3 3 1337 #define CCU40_IN2_ERU1_IOUT2 23 1338 #define CCU40_IN2_ERU1_PDOUT2 22 1339 #define CCU40_IN2_ERU1_PDOUT3 24 1340 #define CCU40_IN2_LEDTS0_SR 11 1341 #define CCU40_IN2_P0_12 0 1342 #define CCU40_IN2_P0_2 2 1343 #define CCU40_IN2_P0_8 1 1344 #define CCU40_IN2_P4_10 21 1345 #define CCU40_IN2_P4_2 26 1346 #define CCU40_IN2_SCU_GSC40 8 1347 #define CCU40_IN3_CCU40_GP00 12 1348 #define CCU40_IN3_CCU40_SR1 19 1349 #define CCU40_IN3_CCU40_SR3 27 1350 #define CCU40_IN3_CCU40_ST0 13 1351 #define CCU40_IN3_CCU40_ST1 14 1352 #define CCU40_IN3_CCU40_ST2 15 1353 #define CCU40_IN3_CCU40_ST3 20 1354 #define CCU40_IN3_ERU0_IOUT3 10 1355 #define CCU40_IN3_ERU0_PDOUT2 3 1356 #define CCU40_IN3_ERU0_PDOUT3 9 1357 #define CCU40_IN3_ERU1_IOUT3 23 1358 #define CCU40_IN3_ERU1_PDOUT2 24 1359 #define CCU40_IN3_ERU1_PDOUT3 22 1360 #define CCU40_IN3_LEDTS1_SR 11 1361 #define CCU40_IN3_P0_12 0 1362 #define CCU40_IN3_P0_3 2 1363 #define CCU40_IN3_P0_9 1 1364 #define CCU40_IN3_P4_11 21 1365 #define CCU40_IN3_P4_3 26 1366 #define CCU40_IN3_SCU_GSC40 8 1367 #define CCU40_IN3_VADC0_G0ARBCNT 6 1368 #define CCU41_IN0_CCU41_GP01 12 1369 #define CCU41_IN0_CCU41_SR0 27 1370 #define CCU41_IN0_CCU41_SR2 19 1371 #define CCU41_IN0_CCU41_ST0 20 1372 #define CCU41_IN0_CCU41_ST1 13 1373 #define CCU41_IN0_CCU41_ST2 14 1374 #define CCU41_IN0_CCU41_ST3 15 1375 #define CCU41_IN0_ERU0_IOUT0 10 1376 #define CCU41_IN0_ERU0_PDOUT0 9 1377 #define CCU41_IN0_ERU0_PDOUT1 3 1378 #define CCU41_IN0_ERU1_IOUT0 23 1379 #define CCU41_IN0_ERU1_PDOUT0 22 1380 #define CCU41_IN0_ERU1_PDOUT1 24 1381 #define CCU41_IN0_P0_4 1 1382 #define CCU41_IN0_P3_0 0 1383 #define CCU41_IN0_P4_0 2 1384 #define CCU41_IN0_P4_4 21 1385 #define CCU41_IN0_P4_8 26 1386 #define CCU41_IN0_SCU_GSC40 8 1387 #define CCU41_IN0_U1C0_DX2INS 28 1388 #define CCU41_IN1_CCU40_ST1 11 1389 #define CCU41_IN1_CCU41_GP02 12 1390 #define CCU41_IN1_CCU41_SR1 27 1391 #define CCU41_IN1_CCU41_SR2 19 1392 #define CCU41_IN1_CCU41_ST0 13 1393 #define CCU41_IN1_CCU41_ST1 20 1394 #define CCU41_IN1_CCU41_ST2 14 1395 #define CCU41_IN1_CCU41_ST3 15 1396 #define CCU41_IN1_ERU0_IOUT1 10 1397 #define CCU41_IN1_ERU0_PDOUT0 3 1398 #define CCU41_IN1_ERU0_PDOUT1 9 1399 #define CCU41_IN1_ERU1_IOUT1 23 1400 #define CCU41_IN1_ERU1_PDOUT0 24 1401 #define CCU41_IN1_ERU1_PDOUT1 22 1402 #define CCU41_IN1_P0_5 1 1403 #define CCU41_IN1_P3_0 0 1404 #define CCU41_IN1_P4_1 2 1405 #define CCU41_IN1_P4_5 21 1406 #define CCU41_IN1_P4_9 26 1407 #define CCU41_IN1_SCU_GSC40 8 1408 #define CCU41_IN1_U1C1_DX2INS 28 1409 #define CCU41_IN2_CCU40_ST2 11 1410 #define CCU41_IN2_CCU41_GP03 12 1411 #define CCU41_IN2_CCU41_SR1 19 1412 #define CCU41_IN2_CCU41_SR2 27 1413 #define CCU41_IN2_CCU41_ST0 13 1414 #define CCU41_IN2_CCU41_ST1 14 1415 #define CCU41_IN2_CCU41_ST2 20 1416 #define CCU41_IN2_CCU41_ST3 15 1417 #define CCU41_IN2_ERU0_IOUT2 10 1418 #define CCU41_IN2_ERU0_PDOUT2 9 1419 #define CCU41_IN2_ERU0_PDOUT3 3 1420 #define CCU41_IN2_ERU1_IOUT2 23 1421 #define CCU41_IN2_ERU1_PDOUT2 22 1422 #define CCU41_IN2_ERU1_PDOUT3 24 1423 #define CCU41_IN2_P0_6 1 1424 #define CCU41_IN2_P3_0 0 1425 #define CCU41_IN2_P4_10 26 1426 #define CCU41_IN2_P4_2 2 1427 #define CCU41_IN2_P4_6 21 1428 #define CCU41_IN2_SCU_GSC40 8 1429 #define CCU41_IN3_CCU40_ST3 11 1430 #define CCU41_IN3_CCU41_GP00 12 1431 #define CCU41_IN3_CCU41_SR1 19 1432 #define CCU41_IN3_CCU41_SR3 27 1433 #define CCU41_IN3_CCU41_ST0 13 1434 #define CCU41_IN3_CCU41_ST1 14 1435 #define CCU41_IN3_CCU41_ST2 15 1436 #define CCU41_IN3_CCU41_ST3 20 1437 #define CCU41_IN3_ERU0_IOUT3 10 1438 #define CCU41_IN3_ERU0_PDOUT2 3 1439 #define CCU41_IN3_ERU0_PDOUT3 9 1440 #define CCU41_IN3_ERU1_IOUT3 23 1441 #define CCU41_IN3_ERU1_PDOUT2 24 1442 #define CCU41_IN3_ERU1_PDOUT3 22 1443 #define CCU41_IN3_P0_7 1 1444 #define CCU41_IN3_P3_0 0 1445 #define CCU41_IN3_P4_11 26 1446 #define CCU41_IN3_P4_3 2 1447 #define CCU41_IN3_P4_7 21 1448 #define CCU41_IN3_SCU_GSC40 8 1449 #define CCU41_IN3_VADC0_G0ARBCNT 6 1450 #endif 1451 1452 1453 #if (UC_DEVICE == XMC1401) && (UC_PACKAGE == VQFN48) 1454 #define CCU40_IN0_CCU40_GP01 12 1455 #define CCU40_IN0_CCU40_SR0 27 1456 #define CCU40_IN0_CCU40_SR2 19 1457 #define CCU40_IN0_CCU40_ST0 20 1458 #define CCU40_IN0_CCU40_ST1 13 1459 #define CCU40_IN0_CCU40_ST2 14 1460 #define CCU40_IN0_CCU40_ST3 15 1461 #define CCU40_IN0_ERU0_IOUT0 10 1462 #define CCU40_IN0_ERU0_PDOUT0 9 1463 #define CCU40_IN0_ERU0_PDOUT1 3 1464 #define CCU40_IN0_ERU1_IOUT0 23 1465 #define CCU40_IN0_ERU1_PDOUT0 22 1466 #define CCU40_IN0_ERU1_PDOUT1 24 1467 #define CCU40_IN0_P0_0 2 1468 #define CCU40_IN0_P0_12 0 1469 #define CCU40_IN0_P0_6 1 1470 #define CCU40_IN0_P4_0 26 1471 #define CCU40_IN0_SCU_GSC40 8 1472 #define CCU40_IN0_U0C0_DX2INS 11 1473 #define CCU40_IN1_CCU40_GP02 12 1474 #define CCU40_IN1_CCU40_SR1 27 1475 #define CCU40_IN1_CCU40_SR2 19 1476 #define CCU40_IN1_CCU40_ST0 13 1477 #define CCU40_IN1_CCU40_ST1 20 1478 #define CCU40_IN1_CCU40_ST2 14 1479 #define CCU40_IN1_CCU40_ST3 15 1480 #define CCU40_IN1_ERU0_IOUT1 10 1481 #define CCU40_IN1_ERU0_PDOUT0 3 1482 #define CCU40_IN1_ERU0_PDOUT1 9 1483 #define CCU40_IN1_ERU1_IOUT1 23 1484 #define CCU40_IN1_ERU1_PDOUT0 24 1485 #define CCU40_IN1_ERU1_PDOUT1 22 1486 #define CCU40_IN1_P0_1 2 1487 #define CCU40_IN1_P0_12 0 1488 #define CCU40_IN1_P0_7 1 1489 #define CCU40_IN1_SCU_GSC40 8 1490 #define CCU40_IN1_U0C1_DX2INS 11 1491 #define CCU40_IN2_CCU40_GP03 12 1492 #define CCU40_IN2_CCU40_SR1 19 1493 #define CCU40_IN2_CCU40_SR2 27 1494 #define CCU40_IN2_CCU40_ST0 13 1495 #define CCU40_IN2_CCU40_ST1 14 1496 #define CCU40_IN2_CCU40_ST2 20 1497 #define CCU40_IN2_CCU40_ST3 15 1498 #define CCU40_IN2_ERU0_IOUT2 10 1499 #define CCU40_IN2_ERU0_PDOUT2 9 1500 #define CCU40_IN2_ERU0_PDOUT3 3 1501 #define CCU40_IN2_ERU1_IOUT2 23 1502 #define CCU40_IN2_ERU1_PDOUT2 22 1503 #define CCU40_IN2_ERU1_PDOUT3 24 1504 #define CCU40_IN2_LEDTS0_SR 11 1505 #define CCU40_IN2_P0_12 0 1506 #define CCU40_IN2_P0_2 2 1507 #define CCU40_IN2_P0_8 1 1508 #define CCU40_IN2_SCU_GSC40 8 1509 #define CCU40_IN3_CCU40_GP00 12 1510 #define CCU40_IN3_CCU40_SR1 19 1511 #define CCU40_IN3_CCU40_SR3 27 1512 #define CCU40_IN3_CCU40_ST0 13 1513 #define CCU40_IN3_CCU40_ST1 14 1514 #define CCU40_IN3_CCU40_ST2 15 1515 #define CCU40_IN3_CCU40_ST3 20 1516 #define CCU40_IN3_ERU0_IOUT3 10 1517 #define CCU40_IN3_ERU0_PDOUT2 3 1518 #define CCU40_IN3_ERU0_PDOUT3 9 1519 #define CCU40_IN3_ERU1_IOUT3 23 1520 #define CCU40_IN3_ERU1_PDOUT2 24 1521 #define CCU40_IN3_ERU1_PDOUT3 22 1522 #define CCU40_IN3_LEDTS1_SR 11 1523 #define CCU40_IN3_P0_12 0 1524 #define CCU40_IN3_P0_3 2 1525 #define CCU40_IN3_P0_9 1 1526 #define CCU40_IN3_SCU_GSC40 8 1527 #define CCU40_IN3_VADC0_G0ARBCNT 6 1528 #define CCU41_IN0_CCU41_GP01 12 1529 #define CCU41_IN0_CCU41_SR0 27 1530 #define CCU41_IN0_CCU41_SR2 19 1531 #define CCU41_IN0_CCU41_ST0 20 1532 #define CCU41_IN0_CCU41_ST1 13 1533 #define CCU41_IN0_CCU41_ST2 14 1534 #define CCU41_IN0_CCU41_ST3 15 1535 #define CCU41_IN0_ERU0_IOUT0 10 1536 #define CCU41_IN0_ERU0_PDOUT0 9 1537 #define CCU41_IN0_ERU0_PDOUT1 3 1538 #define CCU41_IN0_ERU1_IOUT0 23 1539 #define CCU41_IN0_ERU1_PDOUT0 22 1540 #define CCU41_IN0_ERU1_PDOUT1 24 1541 #define CCU41_IN0_P0_4 1 1542 #define CCU41_IN0_P3_0 0 1543 #define CCU41_IN0_P4_4 21 1544 #define CCU41_IN0_SCU_GSC40 8 1545 #define CCU41_IN0_U1C0_DX2INS 28 1546 #define CCU41_IN1_CCU40_ST1 11 1547 #define CCU41_IN1_CCU41_GP02 12 1548 #define CCU41_IN1_CCU41_SR1 27 1549 #define CCU41_IN1_CCU41_SR2 19 1550 #define CCU41_IN1_CCU41_ST0 13 1551 #define CCU41_IN1_CCU41_ST1 20 1552 #define CCU41_IN1_CCU41_ST2 14 1553 #define CCU41_IN1_CCU41_ST3 15 1554 #define CCU41_IN1_ERU0_IOUT1 10 1555 #define CCU41_IN1_ERU0_PDOUT0 3 1556 #define CCU41_IN1_ERU0_PDOUT1 9 1557 #define CCU41_IN1_ERU1_IOUT1 23 1558 #define CCU41_IN1_ERU1_PDOUT0 24 1559 #define CCU41_IN1_ERU1_PDOUT1 22 1560 #define CCU41_IN1_P0_5 1 1561 #define CCU41_IN1_P3_0 0 1562 #define CCU41_IN1_P4_5 21 1563 #define CCU41_IN1_SCU_GSC40 8 1564 #define CCU41_IN1_U1C1_DX2INS 28 1565 #define CCU41_IN2_CCU40_ST2 11 1566 #define CCU41_IN2_CCU41_GP03 12 1567 #define CCU41_IN2_CCU41_SR1 19 1568 #define CCU41_IN2_CCU41_SR2 27 1569 #define CCU41_IN2_CCU41_ST0 13 1570 #define CCU41_IN2_CCU41_ST1 14 1571 #define CCU41_IN2_CCU41_ST2 20 1572 #define CCU41_IN2_CCU41_ST3 15 1573 #define CCU41_IN2_ERU0_IOUT2 10 1574 #define CCU41_IN2_ERU0_PDOUT2 9 1575 #define CCU41_IN2_ERU0_PDOUT3 3 1576 #define CCU41_IN2_ERU1_IOUT2 23 1577 #define CCU41_IN2_ERU1_PDOUT2 22 1578 #define CCU41_IN2_ERU1_PDOUT3 24 1579 #define CCU41_IN2_P0_6 1 1580 #define CCU41_IN2_P3_0 0 1581 #define CCU41_IN2_P4_6 21 1582 #define CCU41_IN2_SCU_GSC40 8 1583 #define CCU41_IN3_CCU40_ST3 11 1584 #define CCU41_IN3_CCU41_GP00 12 1585 #define CCU41_IN3_CCU41_SR1 19 1586 #define CCU41_IN3_CCU41_SR3 27 1587 #define CCU41_IN3_CCU41_ST0 13 1588 #define CCU41_IN3_CCU41_ST1 14 1589 #define CCU41_IN3_CCU41_ST2 15 1590 #define CCU41_IN3_CCU41_ST3 20 1591 #define CCU41_IN3_ERU0_IOUT3 10 1592 #define CCU41_IN3_ERU0_PDOUT2 3 1593 #define CCU41_IN3_ERU0_PDOUT3 9 1594 #define CCU41_IN3_ERU1_IOUT3 23 1595 #define CCU41_IN3_ERU1_PDOUT2 24 1596 #define CCU41_IN3_ERU1_PDOUT3 22 1597 #define CCU41_IN3_P0_7 1 1598 #define CCU41_IN3_P3_0 0 1599 #define CCU41_IN3_P4_7 21 1600 #define CCU41_IN3_SCU_GSC40 8 1601 #define CCU41_IN3_VADC0_G0ARBCNT 6 1602 #endif 1603 1604 1605 #if (UC_DEVICE == XMC1402) && (UC_PACKAGE == LQFP64) 1606 #define CCU40_IN0_BCCU0_OUT0 16 1607 #define CCU40_IN0_BCCU0_OUT6 25 1608 #define CCU40_IN0_CCU40_GP01 12 1609 #define CCU40_IN0_CCU40_SR0 27 1610 #define CCU40_IN0_CCU40_SR2 19 1611 #define CCU40_IN0_CCU40_ST0 20 1612 #define CCU40_IN0_CCU40_ST1 13 1613 #define CCU40_IN0_CCU40_ST2 14 1614 #define CCU40_IN0_CCU40_ST3 15 1615 #define CCU40_IN0_CCU80_ST3 7 1616 #define CCU40_IN0_ERU0_IOUT0 10 1617 #define CCU40_IN0_ERU0_PDOUT0 9 1618 #define CCU40_IN0_ERU0_PDOUT1 3 1619 #define CCU40_IN0_ERU1_IOUT0 23 1620 #define CCU40_IN0_ERU1_PDOUT0 22 1621 #define CCU40_IN0_ERU1_PDOUT1 24 1622 #define CCU40_IN0_P0_0 2 1623 #define CCU40_IN0_P0_12 0 1624 #define CCU40_IN0_P0_6 1 1625 #define CCU40_IN0_P4_0 26 1626 #define CCU40_IN0_P4_8 21 1627 #define CCU40_IN0_POSIF0_OUT0 4 1628 #define CCU40_IN0_POSIF0_OUT1 5 1629 #define CCU40_IN0_POSIF0_OUT3 6 1630 #define CCU40_IN0_SCU_ACMP0_OUT 18 1631 #define CCU40_IN0_SCU_ACMP1_OUT 17 1632 #define CCU40_IN0_SCU_GSC40 8 1633 #define CCU40_IN0_U0C0_DX2INS 11 1634 #define CCU40_IN1_BCCU0_OUT3 25 1635 #define CCU40_IN1_BCCU0_OUT8 16 1636 #define CCU40_IN1_CCU40_GP02 12 1637 #define CCU40_IN1_CCU40_SR1 27 1638 #define CCU40_IN1_CCU40_SR2 19 1639 #define CCU40_IN1_CCU40_ST0 13 1640 #define CCU40_IN1_CCU40_ST1 20 1641 #define CCU40_IN1_CCU40_ST2 14 1642 #define CCU40_IN1_CCU40_ST3 15 1643 #define CCU40_IN1_ERU0_IOUT1 10 1644 #define CCU40_IN1_ERU0_PDOUT0 3 1645 #define CCU40_IN1_ERU0_PDOUT1 9 1646 #define CCU40_IN1_ERU1_IOUT1 23 1647 #define CCU40_IN1_ERU1_PDOUT0 24 1648 #define CCU40_IN1_ERU1_PDOUT1 22 1649 #define CCU40_IN1_P0_1 2 1650 #define CCU40_IN1_P0_12 0 1651 #define CCU40_IN1_P0_7 1 1652 #define CCU40_IN1_P4_1 26 1653 #define CCU40_IN1_P4_9 21 1654 #define CCU40_IN1_POSIF0_OUT0 4 1655 #define CCU40_IN1_POSIF0_OUT1 5 1656 #define CCU40_IN1_POSIF0_OUT3 6 1657 #define CCU40_IN1_POSIF0_OUT4 7 1658 #define CCU40_IN1_SCU_ACMP2_OUT 18 1659 #define CCU40_IN1_SCU_ACMP3_OUT 17 1660 #define CCU40_IN1_SCU_GSC40 8 1661 #define CCU40_IN1_U0C1_DX2INS 11 1662 #define CCU40_IN2_BCCU0_OUT4 16 1663 #define CCU40_IN2_BCCU0_OUT7 25 1664 #define CCU40_IN2_CCU40_GP03 12 1665 #define CCU40_IN2_CCU40_SR1 19 1666 #define CCU40_IN2_CCU40_SR2 27 1667 #define CCU40_IN2_CCU40_ST0 13 1668 #define CCU40_IN2_CCU40_ST1 14 1669 #define CCU40_IN2_CCU40_ST2 20 1670 #define CCU40_IN2_CCU40_ST3 15 1671 #define CCU40_IN2_ERU0_IOUT2 10 1672 #define CCU40_IN2_ERU0_PDOUT2 9 1673 #define CCU40_IN2_ERU0_PDOUT3 3 1674 #define CCU40_IN2_ERU1_IOUT2 23 1675 #define CCU40_IN2_ERU1_PDOUT2 22 1676 #define CCU40_IN2_ERU1_PDOUT3 24 1677 #define CCU40_IN2_P0_12 0 1678 #define CCU40_IN2_P0_2 2 1679 #define CCU40_IN2_P0_8 1 1680 #define CCU40_IN2_P4_10 21 1681 #define CCU40_IN2_P4_2 26 1682 #define CCU40_IN2_POSIF0_OUT0 28 1683 #define CCU40_IN2_POSIF0_OUT1 4 1684 #define CCU40_IN2_POSIF0_OUT2 5 1685 #define CCU40_IN2_POSIF0_OUT3 6 1686 #define CCU40_IN2_POSIF0_OUT4 7 1687 #define CCU40_IN2_SCU_ACMP1_OUT 18 1688 #define CCU40_IN2_SCU_ACMP2_OUT 17 1689 #define CCU40_IN2_SCU_GSC40 8 1690 #define CCU40_IN3_BCCU0_OUT1 25 1691 #define CCU40_IN3_BCCU0_OUT5 16 1692 #define CCU40_IN3_CCU40_GP00 12 1693 #define CCU40_IN3_CCU40_SR1 19 1694 #define CCU40_IN3_CCU40_SR3 27 1695 #define CCU40_IN3_CCU40_ST0 13 1696 #define CCU40_IN3_CCU40_ST1 14 1697 #define CCU40_IN3_CCU40_ST2 15 1698 #define CCU40_IN3_CCU40_ST3 20 1699 #define CCU40_IN3_CCU80_IGBTO 7 1700 #define CCU40_IN3_ERU0_IOUT3 10 1701 #define CCU40_IN3_ERU0_PDOUT2 3 1702 #define CCU40_IN3_ERU0_PDOUT3 9 1703 #define CCU40_IN3_ERU1_IOUT3 23 1704 #define CCU40_IN3_ERU1_PDOUT2 24 1705 #define CCU40_IN3_ERU1_PDOUT3 22 1706 #define CCU40_IN3_P0_12 0 1707 #define CCU40_IN3_P0_3 2 1708 #define CCU40_IN3_P0_9 1 1709 #define CCU40_IN3_P4_11 21 1710 #define CCU40_IN3_P4_3 26 1711 #define CCU40_IN3_POSIF0_OUT0 28 1712 #define CCU40_IN3_POSIF0_OUT1 29 1713 #define CCU40_IN3_POSIF0_OUT3 4 1714 #define CCU40_IN3_POSIF0_OUT5 5 1715 #define CCU40_IN3_SCU_ACMP0_OUT 17 1716 #define CCU40_IN3_SCU_ACMP3_OUT 18 1717 #define CCU40_IN3_SCU_GSC40 8 1718 #define CCU40_IN3_VADC0_G0ARBCNT 6 1719 #define CCU41_IN0_BCCU0_OUT0 16 1720 #define CCU41_IN0_BCCU0_OUT6 25 1721 #define CCU41_IN0_CCU41_GP01 12 1722 #define CCU41_IN0_CCU41_SR0 27 1723 #define CCU41_IN0_CCU41_SR2 19 1724 #define CCU41_IN0_CCU41_ST0 20 1725 #define CCU41_IN0_CCU41_ST1 13 1726 #define CCU41_IN0_CCU41_ST2 14 1727 #define CCU41_IN0_CCU41_ST3 15 1728 #define CCU41_IN0_CCU81_ST3 7 1729 #define CCU41_IN0_ERU0_IOUT0 10 1730 #define CCU41_IN0_ERU0_PDOUT0 9 1731 #define CCU41_IN0_ERU0_PDOUT1 3 1732 #define CCU41_IN0_ERU1_IOUT0 23 1733 #define CCU41_IN0_ERU1_PDOUT0 22 1734 #define CCU41_IN0_ERU1_PDOUT1 24 1735 #define CCU41_IN0_P0_4 1 1736 #define CCU41_IN0_P3_0 0 1737 #define CCU41_IN0_P4_0 2 1738 #define CCU41_IN0_P4_4 21 1739 #define CCU41_IN0_P4_8 26 1740 #define CCU41_IN0_POSIF1_OUT0 4 1741 #define CCU41_IN0_POSIF1_OUT1 5 1742 #define CCU41_IN0_POSIF1_OUT3 6 1743 #define CCU41_IN0_SCU_ACMP0_OUT 18 1744 #define CCU41_IN0_SCU_ACMP1_OUT 17 1745 #define CCU41_IN0_SCU_GSC40 8 1746 #define CCU41_IN0_U1C0_DX2INS 28 1747 #define CCU41_IN1_BCCU0_OUT1 16 1748 #define CCU41_IN1_BCCU0_OUT3 25 1749 #define CCU41_IN1_CCU40_ST1 11 1750 #define CCU41_IN1_CCU41_GP02 12 1751 #define CCU41_IN1_CCU41_SR1 27 1752 #define CCU41_IN1_CCU41_SR2 19 1753 #define CCU41_IN1_CCU41_ST0 13 1754 #define CCU41_IN1_CCU41_ST1 20 1755 #define CCU41_IN1_CCU41_ST2 14 1756 #define CCU41_IN1_CCU41_ST3 15 1757 #define CCU41_IN1_ERU0_IOUT1 10 1758 #define CCU41_IN1_ERU0_PDOUT0 3 1759 #define CCU41_IN1_ERU0_PDOUT1 9 1760 #define CCU41_IN1_ERU1_IOUT1 23 1761 #define CCU41_IN1_ERU1_PDOUT0 24 1762 #define CCU41_IN1_ERU1_PDOUT1 22 1763 #define CCU41_IN1_P0_5 1 1764 #define CCU41_IN1_P3_0 0 1765 #define CCU41_IN1_P4_1 2 1766 #define CCU41_IN1_P4_5 21 1767 #define CCU41_IN1_P4_9 26 1768 #define CCU41_IN1_POSIF1_OUT0 4 1769 #define CCU41_IN1_POSIF1_OUT1 5 1770 #define CCU41_IN1_POSIF1_OUT3 6 1771 #define CCU41_IN1_POSIF1_OUT4 7 1772 #define CCU41_IN1_SCU_ACMP2_OUT 18 1773 #define CCU41_IN1_SCU_ACMP3_OUT 17 1774 #define CCU41_IN1_SCU_GSC40 8 1775 #define CCU41_IN1_U1C1_DX2INS 28 1776 #define CCU41_IN2_BCCU0_OUT2 16 1777 #define CCU41_IN2_BCCU0_OUT7 25 1778 #define CCU41_IN2_CCU40_ST2 11 1779 #define CCU41_IN2_CCU41_GP03 12 1780 #define CCU41_IN2_CCU41_SR1 19 1781 #define CCU41_IN2_CCU41_SR2 27 1782 #define CCU41_IN2_CCU41_ST0 13 1783 #define CCU41_IN2_CCU41_ST1 14 1784 #define CCU41_IN2_CCU41_ST2 20 1785 #define CCU41_IN2_CCU41_ST3 15 1786 #define CCU41_IN2_ERU0_IOUT2 10 1787 #define CCU41_IN2_ERU0_PDOUT2 9 1788 #define CCU41_IN2_ERU0_PDOUT3 3 1789 #define CCU41_IN2_ERU1_IOUT2 23 1790 #define CCU41_IN2_ERU1_PDOUT2 22 1791 #define CCU41_IN2_ERU1_PDOUT3 24 1792 #define CCU41_IN2_P0_6 1 1793 #define CCU41_IN2_P3_0 0 1794 #define CCU41_IN2_P4_10 26 1795 #define CCU41_IN2_P4_2 2 1796 #define CCU41_IN2_P4_6 21 1797 #define CCU41_IN2_POSIF1_OUT0 28 1798 #define CCU41_IN2_POSIF1_OUT1 4 1799 #define CCU41_IN2_POSIF1_OUT2 5 1800 #define CCU41_IN2_POSIF1_OUT3 6 1801 #define CCU41_IN2_POSIF1_OUT4 7 1802 #define CCU41_IN2_SCU_ACMP1_OUT 18 1803 #define CCU41_IN2_SCU_ACMP2_OUT 17 1804 #define CCU41_IN2_SCU_GSC40 8 1805 #define CCU41_IN3_BCCU0_OUT5 16 1806 #define CCU41_IN3_BCCU0_OUT8 25 1807 #define CCU41_IN3_CCU40_ST3 11 1808 #define CCU41_IN3_CCU41_GP00 12 1809 #define CCU41_IN3_CCU41_SR1 19 1810 #define CCU41_IN3_CCU41_SR3 27 1811 #define CCU41_IN3_CCU41_ST0 13 1812 #define CCU41_IN3_CCU41_ST1 14 1813 #define CCU41_IN3_CCU41_ST2 15 1814 #define CCU41_IN3_CCU41_ST3 20 1815 #define CCU41_IN3_CCU81_IGBTO 7 1816 #define CCU41_IN3_ERU0_IOUT3 10 1817 #define CCU41_IN3_ERU0_PDOUT2 3 1818 #define CCU41_IN3_ERU0_PDOUT3 9 1819 #define CCU41_IN3_ERU1_IOUT3 23 1820 #define CCU41_IN3_ERU1_PDOUT2 24 1821 #define CCU41_IN3_ERU1_PDOUT3 22 1822 #define CCU41_IN3_P0_7 1 1823 #define CCU41_IN3_P3_0 0 1824 #define CCU41_IN3_P4_11 26 1825 #define CCU41_IN3_P4_3 2 1826 #define CCU41_IN3_P4_7 21 1827 #define CCU41_IN3_POSIF1_OUT0 28 1828 #define CCU41_IN3_POSIF1_OUT1 29 1829 #define CCU41_IN3_POSIF1_OUT3 4 1830 #define CCU41_IN3_POSIF1_OUT5 5 1831 #define CCU41_IN3_SCU_ACMP0_OUT 17 1832 #define CCU41_IN3_SCU_ACMP3_OUT 18 1833 #define CCU41_IN3_SCU_GSC40 8 1834 #define CCU41_IN3_VADC0_G0ARBCNT 6 1835 #endif 1836 1837 1838 #if (UC_DEVICE == XMC1402) && (UC_PACKAGE == VQFN40) 1839 #define CCU40_IN0_BCCU0_OUT0 16 1840 #define CCU40_IN0_BCCU0_OUT6 25 1841 #define CCU40_IN0_CCU40_GP01 12 1842 #define CCU40_IN0_CCU40_SR0 27 1843 #define CCU40_IN0_CCU40_SR2 19 1844 #define CCU40_IN0_CCU40_ST0 20 1845 #define CCU40_IN0_CCU40_ST1 13 1846 #define CCU40_IN0_CCU40_ST2 14 1847 #define CCU40_IN0_CCU40_ST3 15 1848 #define CCU40_IN0_CCU80_ST3 7 1849 #define CCU40_IN0_ERU0_IOUT0 10 1850 #define CCU40_IN0_ERU0_PDOUT0 9 1851 #define CCU40_IN0_ERU0_PDOUT1 3 1852 #define CCU40_IN0_ERU1_IOUT0 23 1853 #define CCU40_IN0_ERU1_PDOUT0 22 1854 #define CCU40_IN0_ERU1_PDOUT1 24 1855 #define CCU40_IN0_P0_0 2 1856 #define CCU40_IN0_P0_12 0 1857 #define CCU40_IN0_P0_6 1 1858 #define CCU40_IN0_POSIF0_OUT0 4 1859 #define CCU40_IN0_POSIF0_OUT1 5 1860 #define CCU40_IN0_POSIF0_OUT3 6 1861 #define CCU40_IN0_SCU_ACMP0_OUT 18 1862 #define CCU40_IN0_SCU_ACMP1_OUT 17 1863 #define CCU40_IN0_SCU_GSC40 8 1864 #define CCU40_IN0_U0C0_DX2INS 11 1865 #define CCU40_IN1_BCCU0_OUT3 25 1866 #define CCU40_IN1_BCCU0_OUT8 16 1867 #define CCU40_IN1_CCU40_GP02 12 1868 #define CCU40_IN1_CCU40_SR1 27 1869 #define CCU40_IN1_CCU40_SR2 19 1870 #define CCU40_IN1_CCU40_ST0 13 1871 #define CCU40_IN1_CCU40_ST1 20 1872 #define CCU40_IN1_CCU40_ST2 14 1873 #define CCU40_IN1_CCU40_ST3 15 1874 #define CCU40_IN1_ERU0_IOUT1 10 1875 #define CCU40_IN1_ERU0_PDOUT0 3 1876 #define CCU40_IN1_ERU0_PDOUT1 9 1877 #define CCU40_IN1_ERU1_IOUT1 23 1878 #define CCU40_IN1_ERU1_PDOUT0 24 1879 #define CCU40_IN1_ERU1_PDOUT1 22 1880 #define CCU40_IN1_P0_1 2 1881 #define CCU40_IN1_P0_12 0 1882 #define CCU40_IN1_P0_7 1 1883 #define CCU40_IN1_POSIF0_OUT0 4 1884 #define CCU40_IN1_POSIF0_OUT1 5 1885 #define CCU40_IN1_POSIF0_OUT3 6 1886 #define CCU40_IN1_POSIF0_OUT4 7 1887 #define CCU40_IN1_SCU_ACMP2_OUT 18 1888 #define CCU40_IN1_SCU_GSC40 8 1889 #define CCU40_IN1_U0C1_DX2INS 11 1890 #define CCU40_IN2_BCCU0_OUT4 16 1891 #define CCU40_IN2_BCCU0_OUT7 25 1892 #define CCU40_IN2_CCU40_GP03 12 1893 #define CCU40_IN2_CCU40_SR1 19 1894 #define CCU40_IN2_CCU40_SR2 27 1895 #define CCU40_IN2_CCU40_ST0 13 1896 #define CCU40_IN2_CCU40_ST1 14 1897 #define CCU40_IN2_CCU40_ST2 20 1898 #define CCU40_IN2_CCU40_ST3 15 1899 #define CCU40_IN2_ERU0_IOUT2 10 1900 #define CCU40_IN2_ERU0_PDOUT2 9 1901 #define CCU40_IN2_ERU0_PDOUT3 3 1902 #define CCU40_IN2_ERU1_IOUT2 23 1903 #define CCU40_IN2_ERU1_PDOUT2 22 1904 #define CCU40_IN2_ERU1_PDOUT3 24 1905 #define CCU40_IN2_P0_12 0 1906 #define CCU40_IN2_P0_2 2 1907 #define CCU40_IN2_P0_8 1 1908 #define CCU40_IN2_POSIF0_OUT0 28 1909 #define CCU40_IN2_POSIF0_OUT1 4 1910 #define CCU40_IN2_POSIF0_OUT2 5 1911 #define CCU40_IN2_POSIF0_OUT3 6 1912 #define CCU40_IN2_POSIF0_OUT4 7 1913 #define CCU40_IN2_SCU_ACMP1_OUT 18 1914 #define CCU40_IN2_SCU_ACMP2_OUT 17 1915 #define CCU40_IN2_SCU_GSC40 8 1916 #define CCU40_IN3_BCCU0_OUT1 25 1917 #define CCU40_IN3_BCCU0_OUT5 16 1918 #define CCU40_IN3_CCU40_GP00 12 1919 #define CCU40_IN3_CCU40_SR1 19 1920 #define CCU40_IN3_CCU40_SR3 27 1921 #define CCU40_IN3_CCU40_ST0 13 1922 #define CCU40_IN3_CCU40_ST1 14 1923 #define CCU40_IN3_CCU40_ST2 15 1924 #define CCU40_IN3_CCU40_ST3 20 1925 #define CCU40_IN3_CCU80_IGBTO 7 1926 #define CCU40_IN3_ERU0_IOUT3 10 1927 #define CCU40_IN3_ERU0_PDOUT2 3 1928 #define CCU40_IN3_ERU0_PDOUT3 9 1929 #define CCU40_IN3_ERU1_IOUT3 23 1930 #define CCU40_IN3_ERU1_PDOUT2 24 1931 #define CCU40_IN3_ERU1_PDOUT3 22 1932 #define CCU40_IN3_P0_12 0 1933 #define CCU40_IN3_P0_3 2 1934 #define CCU40_IN3_P0_9 1 1935 #define CCU40_IN3_POSIF0_OUT0 28 1936 #define CCU40_IN3_POSIF0_OUT1 29 1937 #define CCU40_IN3_POSIF0_OUT3 4 1938 #define CCU40_IN3_POSIF0_OUT5 5 1939 #define CCU40_IN3_SCU_ACMP0_OUT 17 1940 #define CCU40_IN3_SCU_GSC40 8 1941 #define CCU40_IN3_VADC0_G0ARBCNT 6 1942 #define CCU41_IN0_BCCU0_OUT0 16 1943 #define CCU41_IN0_BCCU0_OUT6 25 1944 #define CCU41_IN0_CCU41_GP01 12 1945 #define CCU41_IN0_CCU41_SR0 27 1946 #define CCU41_IN0_CCU41_SR2 19 1947 #define CCU41_IN0_CCU41_ST0 20 1948 #define CCU41_IN0_CCU41_ST1 13 1949 #define CCU41_IN0_CCU41_ST2 14 1950 #define CCU41_IN0_CCU41_ST3 15 1951 #define CCU41_IN0_CCU81_ST3 7 1952 #define CCU41_IN0_ERU0_IOUT0 10 1953 #define CCU41_IN0_ERU0_PDOUT0 9 1954 #define CCU41_IN0_ERU0_PDOUT1 3 1955 #define CCU41_IN0_ERU1_IOUT0 23 1956 #define CCU41_IN0_ERU1_PDOUT0 22 1957 #define CCU41_IN0_ERU1_PDOUT1 24 1958 #define CCU41_IN0_P0_4 1 1959 #define CCU41_IN0_SCU_ACMP0_OUT 18 1960 #define CCU41_IN0_SCU_ACMP1_OUT 17 1961 #define CCU41_IN0_SCU_GSC40 8 1962 #define CCU41_IN0_U1C0_DX2INS 28 1963 #define CCU41_IN1_BCCU0_OUT1 16 1964 #define CCU41_IN1_BCCU0_OUT3 25 1965 #define CCU41_IN1_CCU40_ST1 11 1966 #define CCU41_IN1_CCU41_GP02 12 1967 #define CCU41_IN1_CCU41_SR1 27 1968 #define CCU41_IN1_CCU41_SR2 19 1969 #define CCU41_IN1_CCU41_ST0 13 1970 #define CCU41_IN1_CCU41_ST1 20 1971 #define CCU41_IN1_CCU41_ST2 14 1972 #define CCU41_IN1_CCU41_ST3 15 1973 #define CCU41_IN1_ERU0_IOUT1 10 1974 #define CCU41_IN1_ERU0_PDOUT0 3 1975 #define CCU41_IN1_ERU0_PDOUT1 9 1976 #define CCU41_IN1_ERU1_IOUT1 23 1977 #define CCU41_IN1_ERU1_PDOUT0 24 1978 #define CCU41_IN1_ERU1_PDOUT1 22 1979 #define CCU41_IN1_P0_5 1 1980 #define CCU41_IN1_SCU_ACMP2_OUT 18 1981 #define CCU41_IN1_SCU_GSC40 8 1982 #define CCU41_IN1_U1C1_DX2INS 28 1983 #define CCU41_IN2_BCCU0_OUT2 16 1984 #define CCU41_IN2_BCCU0_OUT7 25 1985 #define CCU41_IN2_CCU40_ST2 11 1986 #define CCU41_IN2_CCU41_GP03 12 1987 #define CCU41_IN2_CCU41_SR1 19 1988 #define CCU41_IN2_CCU41_SR2 27 1989 #define CCU41_IN2_CCU41_ST0 13 1990 #define CCU41_IN2_CCU41_ST1 14 1991 #define CCU41_IN2_CCU41_ST2 20 1992 #define CCU41_IN2_CCU41_ST3 15 1993 #define CCU41_IN2_ERU0_IOUT2 10 1994 #define CCU41_IN2_ERU0_PDOUT2 9 1995 #define CCU41_IN2_ERU0_PDOUT3 3 1996 #define CCU41_IN2_ERU1_IOUT2 23 1997 #define CCU41_IN2_ERU1_PDOUT2 22 1998 #define CCU41_IN2_ERU1_PDOUT3 24 1999 #define CCU41_IN2_P0_6 1 2000 #define CCU41_IN2_SCU_ACMP1_OUT 18 2001 #define CCU41_IN2_SCU_ACMP2_OUT 17 2002 #define CCU41_IN2_SCU_GSC40 8 2003 #define CCU41_IN3_BCCU0_OUT5 16 2004 #define CCU41_IN3_BCCU0_OUT8 25 2005 #define CCU41_IN3_CCU40_ST3 11 2006 #define CCU41_IN3_CCU41_GP00 12 2007 #define CCU41_IN3_CCU41_SR1 19 2008 #define CCU41_IN3_CCU41_SR3 27 2009 #define CCU41_IN3_CCU41_ST0 13 2010 #define CCU41_IN3_CCU41_ST1 14 2011 #define CCU41_IN3_CCU41_ST2 15 2012 #define CCU41_IN3_CCU41_ST3 20 2013 #define CCU41_IN3_CCU81_IGBTO 7 2014 #define CCU41_IN3_ERU0_IOUT3 10 2015 #define CCU41_IN3_ERU0_PDOUT2 3 2016 #define CCU41_IN3_ERU0_PDOUT3 9 2017 #define CCU41_IN3_ERU1_IOUT3 23 2018 #define CCU41_IN3_ERU1_PDOUT2 24 2019 #define CCU41_IN3_ERU1_PDOUT3 22 2020 #define CCU41_IN3_P0_7 1 2021 #define CCU41_IN3_SCU_ACMP0_OUT 17 2022 #define CCU41_IN3_SCU_GSC40 8 2023 #define CCU41_IN3_VADC0_G0ARBCNT 6 2024 #endif 2025 2026 2027 #if (UC_DEVICE == XMC1402) && (UC_PACKAGE == VQFN48) 2028 #define CCU40_IN0_BCCU0_OUT0 16 2029 #define CCU40_IN0_BCCU0_OUT6 25 2030 #define CCU40_IN0_CCU40_GP01 12 2031 #define CCU40_IN0_CCU40_SR0 27 2032 #define CCU40_IN0_CCU40_SR2 19 2033 #define CCU40_IN0_CCU40_ST0 20 2034 #define CCU40_IN0_CCU40_ST1 13 2035 #define CCU40_IN0_CCU40_ST2 14 2036 #define CCU40_IN0_CCU40_ST3 15 2037 #define CCU40_IN0_CCU80_ST3 7 2038 #define CCU40_IN0_ERU0_IOUT0 10 2039 #define CCU40_IN0_ERU0_PDOUT0 9 2040 #define CCU40_IN0_ERU0_PDOUT1 3 2041 #define CCU40_IN0_ERU1_IOUT0 23 2042 #define CCU40_IN0_ERU1_PDOUT0 22 2043 #define CCU40_IN0_ERU1_PDOUT1 24 2044 #define CCU40_IN0_P0_0 2 2045 #define CCU40_IN0_P0_12 0 2046 #define CCU40_IN0_P0_6 1 2047 #define CCU40_IN0_POSIF0_OUT0 4 2048 #define CCU40_IN0_POSIF0_OUT1 5 2049 #define CCU40_IN0_POSIF0_OUT3 6 2050 #define CCU40_IN0_SCU_ACMP0_OUT 18 2051 #define CCU40_IN0_SCU_ACMP1_OUT 17 2052 #define CCU40_IN0_SCU_GSC40 8 2053 #define CCU40_IN0_U0C0_DX2INS 11 2054 #define CCU40_IN1_BCCU0_OUT3 25 2055 #define CCU40_IN1_BCCU0_OUT8 16 2056 #define CCU40_IN1_CCU40_GP02 12 2057 #define CCU40_IN1_CCU40_SR1 27 2058 #define CCU40_IN1_CCU40_SR2 19 2059 #define CCU40_IN1_CCU40_ST0 13 2060 #define CCU40_IN1_CCU40_ST1 20 2061 #define CCU40_IN1_CCU40_ST2 14 2062 #define CCU40_IN1_CCU40_ST3 15 2063 #define CCU40_IN1_ERU0_IOUT1 10 2064 #define CCU40_IN1_ERU0_PDOUT0 3 2065 #define CCU40_IN1_ERU0_PDOUT1 9 2066 #define CCU40_IN1_ERU1_IOUT1 23 2067 #define CCU40_IN1_ERU1_PDOUT0 24 2068 #define CCU40_IN1_ERU1_PDOUT1 22 2069 #define CCU40_IN1_P0_1 2 2070 #define CCU40_IN1_P0_12 0 2071 #define CCU40_IN1_P0_7 1 2072 #define CCU40_IN1_POSIF0_OUT0 4 2073 #define CCU40_IN1_POSIF0_OUT1 5 2074 #define CCU40_IN1_POSIF0_OUT3 6 2075 #define CCU40_IN1_POSIF0_OUT4 7 2076 #define CCU40_IN1_SCU_ACMP2_OUT 18 2077 #define CCU40_IN1_SCU_ACMP3_OUT 17 2078 #define CCU40_IN1_SCU_GSC40 8 2079 #define CCU40_IN1_U0C1_DX2INS 11 2080 #define CCU40_IN2_BCCU0_OUT4 16 2081 #define CCU40_IN2_BCCU0_OUT7 25 2082 #define CCU40_IN2_CCU40_GP03 12 2083 #define CCU40_IN2_CCU40_SR1 19 2084 #define CCU40_IN2_CCU40_SR2 27 2085 #define CCU40_IN2_CCU40_ST0 13 2086 #define CCU40_IN2_CCU40_ST1 14 2087 #define CCU40_IN2_CCU40_ST2 20 2088 #define CCU40_IN2_CCU40_ST3 15 2089 #define CCU40_IN2_ERU0_IOUT2 10 2090 #define CCU40_IN2_ERU0_PDOUT2 9 2091 #define CCU40_IN2_ERU0_PDOUT3 3 2092 #define CCU40_IN2_ERU1_IOUT2 23 2093 #define CCU40_IN2_ERU1_PDOUT2 22 2094 #define CCU40_IN2_ERU1_PDOUT3 24 2095 #define CCU40_IN2_P0_12 0 2096 #define CCU40_IN2_P0_2 2 2097 #define CCU40_IN2_P0_8 1 2098 #define CCU40_IN2_POSIF0_OUT0 28 2099 #define CCU40_IN2_POSIF0_OUT1 4 2100 #define CCU40_IN2_POSIF0_OUT2 5 2101 #define CCU40_IN2_POSIF0_OUT3 6 2102 #define CCU40_IN2_POSIF0_OUT4 7 2103 #define CCU40_IN2_SCU_ACMP1_OUT 18 2104 #define CCU40_IN2_SCU_ACMP2_OUT 17 2105 #define CCU40_IN2_SCU_GSC40 8 2106 #define CCU40_IN3_BCCU0_OUT1 25 2107 #define CCU40_IN3_BCCU0_OUT5 16 2108 #define CCU40_IN3_CCU40_GP00 12 2109 #define CCU40_IN3_CCU40_SR1 19 2110 #define CCU40_IN3_CCU40_SR3 27 2111 #define CCU40_IN3_CCU40_ST0 13 2112 #define CCU40_IN3_CCU40_ST1 14 2113 #define CCU40_IN3_CCU40_ST2 15 2114 #define CCU40_IN3_CCU40_ST3 20 2115 #define CCU40_IN3_CCU80_IGBTO 7 2116 #define CCU40_IN3_ERU0_IOUT3 10 2117 #define CCU40_IN3_ERU0_PDOUT2 3 2118 #define CCU40_IN3_ERU0_PDOUT3 9 2119 #define CCU40_IN3_ERU1_IOUT3 23 2120 #define CCU40_IN3_ERU1_PDOUT2 24 2121 #define CCU40_IN3_ERU1_PDOUT3 22 2122 #define CCU40_IN3_P0_12 0 2123 #define CCU40_IN3_P0_3 2 2124 #define CCU40_IN3_P0_9 1 2125 #define CCU40_IN3_POSIF0_OUT0 28 2126 #define CCU40_IN3_POSIF0_OUT1 29 2127 #define CCU40_IN3_POSIF0_OUT3 4 2128 #define CCU40_IN3_POSIF0_OUT5 5 2129 #define CCU40_IN3_SCU_ACMP0_OUT 17 2130 #define CCU40_IN3_SCU_ACMP3_OUT 18 2131 #define CCU40_IN3_SCU_GSC40 8 2132 #define CCU40_IN3_VADC0_G0ARBCNT 6 2133 #define CCU41_IN0_BCCU0_OUT0 16 2134 #define CCU41_IN0_BCCU0_OUT6 25 2135 #define CCU41_IN0_CCU41_GP01 12 2136 #define CCU41_IN0_CCU41_SR0 27 2137 #define CCU41_IN0_CCU41_SR2 19 2138 #define CCU41_IN0_CCU41_ST0 20 2139 #define CCU41_IN0_CCU41_ST1 13 2140 #define CCU41_IN0_CCU41_ST2 14 2141 #define CCU41_IN0_CCU41_ST3 15 2142 #define CCU41_IN0_CCU81_ST3 7 2143 #define CCU41_IN0_ERU0_IOUT0 10 2144 #define CCU41_IN0_ERU0_PDOUT0 9 2145 #define CCU41_IN0_ERU0_PDOUT1 3 2146 #define CCU41_IN0_ERU1_IOUT0 23 2147 #define CCU41_IN0_ERU1_PDOUT0 22 2148 #define CCU41_IN0_ERU1_PDOUT1 24 2149 #define CCU41_IN0_P0_4 1 2150 #define CCU41_IN0_P3_0 0 2151 #define CCU41_IN0_P4_4 21 2152 #define CCU41_IN0_POSIF1_OUT0 4 2153 #define CCU41_IN0_POSIF1_OUT1 5 2154 #define CCU41_IN0_POSIF1_OUT3 6 2155 #define CCU41_IN0_SCU_ACMP0_OUT 18 2156 #define CCU41_IN0_SCU_ACMP1_OUT 17 2157 #define CCU41_IN0_SCU_GSC40 8 2158 #define CCU41_IN0_U1C0_DX2INS 28 2159 #define CCU41_IN1_BCCU0_OUT1 16 2160 #define CCU41_IN1_BCCU0_OUT3 25 2161 #define CCU41_IN1_CCU40_ST1 11 2162 #define CCU41_IN1_CCU41_GP02 12 2163 #define CCU41_IN1_CCU41_SR1 27 2164 #define CCU41_IN1_CCU41_SR2 19 2165 #define CCU41_IN1_CCU41_ST0 13 2166 #define CCU41_IN1_CCU41_ST1 20 2167 #define CCU41_IN1_CCU41_ST2 14 2168 #define CCU41_IN1_CCU41_ST3 15 2169 #define CCU41_IN1_ERU0_IOUT1 10 2170 #define CCU41_IN1_ERU0_PDOUT0 3 2171 #define CCU41_IN1_ERU0_PDOUT1 9 2172 #define CCU41_IN1_ERU1_IOUT1 23 2173 #define CCU41_IN1_ERU1_PDOUT0 24 2174 #define CCU41_IN1_ERU1_PDOUT1 22 2175 #define CCU41_IN1_P0_5 1 2176 #define CCU41_IN1_P3_0 0 2177 #define CCU41_IN1_P4_5 21 2178 #define CCU41_IN1_POSIF1_OUT0 4 2179 #define CCU41_IN1_POSIF1_OUT1 5 2180 #define CCU41_IN1_POSIF1_OUT3 6 2181 #define CCU41_IN1_POSIF1_OUT4 7 2182 #define CCU41_IN1_SCU_ACMP2_OUT 18 2183 #define CCU41_IN1_SCU_ACMP3_OUT 17 2184 #define CCU41_IN1_SCU_GSC40 8 2185 #define CCU41_IN1_U1C1_DX2INS 28 2186 #define CCU41_IN2_BCCU0_OUT2 16 2187 #define CCU41_IN2_BCCU0_OUT7 25 2188 #define CCU41_IN2_CCU40_ST2 11 2189 #define CCU41_IN2_CCU41_GP03 12 2190 #define CCU41_IN2_CCU41_SR1 19 2191 #define CCU41_IN2_CCU41_SR2 27 2192 #define CCU41_IN2_CCU41_ST0 13 2193 #define CCU41_IN2_CCU41_ST1 14 2194 #define CCU41_IN2_CCU41_ST2 20 2195 #define CCU41_IN2_CCU41_ST3 15 2196 #define CCU41_IN2_ERU0_IOUT2 10 2197 #define CCU41_IN2_ERU0_PDOUT2 9 2198 #define CCU41_IN2_ERU0_PDOUT3 3 2199 #define CCU41_IN2_ERU1_IOUT2 23 2200 #define CCU41_IN2_ERU1_PDOUT2 22 2201 #define CCU41_IN2_ERU1_PDOUT3 24 2202 #define CCU41_IN2_P0_6 1 2203 #define CCU41_IN2_P3_0 0 2204 #define CCU41_IN2_P4_6 21 2205 #define CCU41_IN2_POSIF1_OUT0 28 2206 #define CCU41_IN2_POSIF1_OUT1 4 2207 #define CCU41_IN2_POSIF1_OUT2 5 2208 #define CCU41_IN2_POSIF1_OUT3 6 2209 #define CCU41_IN2_POSIF1_OUT4 7 2210 #define CCU41_IN2_SCU_ACMP1_OUT 18 2211 #define CCU41_IN2_SCU_ACMP2_OUT 17 2212 #define CCU41_IN2_SCU_GSC40 8 2213 #define CCU41_IN3_BCCU0_OUT5 16 2214 #define CCU41_IN3_BCCU0_OUT8 25 2215 #define CCU41_IN3_CCU40_ST3 11 2216 #define CCU41_IN3_CCU41_GP00 12 2217 #define CCU41_IN3_CCU41_SR1 19 2218 #define CCU41_IN3_CCU41_SR3 27 2219 #define CCU41_IN3_CCU41_ST0 13 2220 #define CCU41_IN3_CCU41_ST1 14 2221 #define CCU41_IN3_CCU41_ST2 15 2222 #define CCU41_IN3_CCU41_ST3 20 2223 #define CCU41_IN3_CCU81_IGBTO 7 2224 #define CCU41_IN3_ERU0_IOUT3 10 2225 #define CCU41_IN3_ERU0_PDOUT2 3 2226 #define CCU41_IN3_ERU0_PDOUT3 9 2227 #define CCU41_IN3_ERU1_IOUT3 23 2228 #define CCU41_IN3_ERU1_PDOUT2 24 2229 #define CCU41_IN3_ERU1_PDOUT3 22 2230 #define CCU41_IN3_P0_7 1 2231 #define CCU41_IN3_P3_0 0 2232 #define CCU41_IN3_P4_7 21 2233 #define CCU41_IN3_POSIF1_OUT0 28 2234 #define CCU41_IN3_POSIF1_OUT1 29 2235 #define CCU41_IN3_POSIF1_OUT3 4 2236 #define CCU41_IN3_POSIF1_OUT5 5 2237 #define CCU41_IN3_SCU_ACMP0_OUT 17 2238 #define CCU41_IN3_SCU_ACMP3_OUT 18 2239 #define CCU41_IN3_SCU_GSC40 8 2240 #define CCU41_IN3_VADC0_G0ARBCNT 6 2241 #endif 2242 2243 2244 #if (UC_DEVICE == XMC1402) && (UC_PACKAGE == VQFN64) 2245 #define CCU40_IN0_BCCU0_OUT0 16 2246 #define CCU40_IN0_BCCU0_OUT6 25 2247 #define CCU40_IN0_CCU40_GP01 12 2248 #define CCU40_IN0_CCU40_SR0 27 2249 #define CCU40_IN0_CCU40_SR2 19 2250 #define CCU40_IN0_CCU40_ST0 20 2251 #define CCU40_IN0_CCU40_ST1 13 2252 #define CCU40_IN0_CCU40_ST2 14 2253 #define CCU40_IN0_CCU40_ST3 15 2254 #define CCU40_IN0_CCU80_ST3 7 2255 #define CCU40_IN0_ERU0_IOUT0 10 2256 #define CCU40_IN0_ERU0_PDOUT0 9 2257 #define CCU40_IN0_ERU0_PDOUT1 3 2258 #define CCU40_IN0_ERU1_IOUT0 23 2259 #define CCU40_IN0_ERU1_PDOUT0 22 2260 #define CCU40_IN0_ERU1_PDOUT1 24 2261 #define CCU40_IN0_P0_0 2 2262 #define CCU40_IN0_P0_12 0 2263 #define CCU40_IN0_P0_6 1 2264 #define CCU40_IN0_P4_0 26 2265 #define CCU40_IN0_P4_8 21 2266 #define CCU40_IN0_POSIF0_OUT0 4 2267 #define CCU40_IN0_POSIF0_OUT1 5 2268 #define CCU40_IN0_POSIF0_OUT3 6 2269 #define CCU40_IN0_SCU_ACMP0_OUT 18 2270 #define CCU40_IN0_SCU_ACMP1_OUT 17 2271 #define CCU40_IN0_SCU_GSC40 8 2272 #define CCU40_IN0_U0C0_DX2INS 11 2273 #define CCU40_IN1_BCCU0_OUT3 25 2274 #define CCU40_IN1_BCCU0_OUT8 16 2275 #define CCU40_IN1_CCU40_GP02 12 2276 #define CCU40_IN1_CCU40_SR1 27 2277 #define CCU40_IN1_CCU40_SR2 19 2278 #define CCU40_IN1_CCU40_ST0 13 2279 #define CCU40_IN1_CCU40_ST1 20 2280 #define CCU40_IN1_CCU40_ST2 14 2281 #define CCU40_IN1_CCU40_ST3 15 2282 #define CCU40_IN1_ERU0_IOUT1 10 2283 #define CCU40_IN1_ERU0_PDOUT0 3 2284 #define CCU40_IN1_ERU0_PDOUT1 9 2285 #define CCU40_IN1_ERU1_IOUT1 23 2286 #define CCU40_IN1_ERU1_PDOUT0 24 2287 #define CCU40_IN1_ERU1_PDOUT1 22 2288 #define CCU40_IN1_P0_1 2 2289 #define CCU40_IN1_P0_12 0 2290 #define CCU40_IN1_P0_7 1 2291 #define CCU40_IN1_P4_1 26 2292 #define CCU40_IN1_P4_9 21 2293 #define CCU40_IN1_POSIF0_OUT0 4 2294 #define CCU40_IN1_POSIF0_OUT1 5 2295 #define CCU40_IN1_POSIF0_OUT3 6 2296 #define CCU40_IN1_POSIF0_OUT4 7 2297 #define CCU40_IN1_SCU_ACMP2_OUT 18 2298 #define CCU40_IN1_SCU_ACMP3_OUT 17 2299 #define CCU40_IN1_SCU_GSC40 8 2300 #define CCU40_IN1_U0C1_DX2INS 11 2301 #define CCU40_IN2_BCCU0_OUT4 16 2302 #define CCU40_IN2_BCCU0_OUT7 25 2303 #define CCU40_IN2_CCU40_GP03 12 2304 #define CCU40_IN2_CCU40_SR1 19 2305 #define CCU40_IN2_CCU40_SR2 27 2306 #define CCU40_IN2_CCU40_ST0 13 2307 #define CCU40_IN2_CCU40_ST1 14 2308 #define CCU40_IN2_CCU40_ST2 20 2309 #define CCU40_IN2_CCU40_ST3 15 2310 #define CCU40_IN2_ERU0_IOUT2 10 2311 #define CCU40_IN2_ERU0_PDOUT2 9 2312 #define CCU40_IN2_ERU0_PDOUT3 3 2313 #define CCU40_IN2_ERU1_IOUT2 23 2314 #define CCU40_IN2_ERU1_PDOUT2 22 2315 #define CCU40_IN2_ERU1_PDOUT3 24 2316 #define CCU40_IN2_P0_12 0 2317 #define CCU40_IN2_P0_2 2 2318 #define CCU40_IN2_P0_8 1 2319 #define CCU40_IN2_P4_10 21 2320 #define CCU40_IN2_P4_2 26 2321 #define CCU40_IN2_POSIF0_OUT0 28 2322 #define CCU40_IN2_POSIF0_OUT1 4 2323 #define CCU40_IN2_POSIF0_OUT2 5 2324 #define CCU40_IN2_POSIF0_OUT3 6 2325 #define CCU40_IN2_POSIF0_OUT4 7 2326 #define CCU40_IN2_SCU_ACMP1_OUT 18 2327 #define CCU40_IN2_SCU_ACMP2_OUT 17 2328 #define CCU40_IN2_SCU_GSC40 8 2329 #define CCU40_IN3_BCCU0_OUT1 25 2330 #define CCU40_IN3_BCCU0_OUT5 16 2331 #define CCU40_IN3_CCU40_GP00 12 2332 #define CCU40_IN3_CCU40_SR1 19 2333 #define CCU40_IN3_CCU40_SR3 27 2334 #define CCU40_IN3_CCU40_ST0 13 2335 #define CCU40_IN3_CCU40_ST1 14 2336 #define CCU40_IN3_CCU40_ST2 15 2337 #define CCU40_IN3_CCU40_ST3 20 2338 #define CCU40_IN3_CCU80_IGBTO 7 2339 #define CCU40_IN3_ERU0_IOUT3 10 2340 #define CCU40_IN3_ERU0_PDOUT2 3 2341 #define CCU40_IN3_ERU0_PDOUT3 9 2342 #define CCU40_IN3_ERU1_IOUT3 23 2343 #define CCU40_IN3_ERU1_PDOUT2 24 2344 #define CCU40_IN3_ERU1_PDOUT3 22 2345 #define CCU40_IN3_P0_12 0 2346 #define CCU40_IN3_P0_3 2 2347 #define CCU40_IN3_P0_9 1 2348 #define CCU40_IN3_P4_11 21 2349 #define CCU40_IN3_P4_3 26 2350 #define CCU40_IN3_POSIF0_OUT0 28 2351 #define CCU40_IN3_POSIF0_OUT1 29 2352 #define CCU40_IN3_POSIF0_OUT3 4 2353 #define CCU40_IN3_POSIF0_OUT5 5 2354 #define CCU40_IN3_SCU_ACMP0_OUT 17 2355 #define CCU40_IN3_SCU_ACMP3_OUT 18 2356 #define CCU40_IN3_SCU_GSC40 8 2357 #define CCU40_IN3_VADC0_G0ARBCNT 6 2358 #define CCU41_IN0_BCCU0_OUT0 16 2359 #define CCU41_IN0_BCCU0_OUT6 25 2360 #define CCU41_IN0_CCU41_GP01 12 2361 #define CCU41_IN0_CCU41_SR0 27 2362 #define CCU41_IN0_CCU41_SR2 19 2363 #define CCU41_IN0_CCU41_ST0 20 2364 #define CCU41_IN0_CCU41_ST1 13 2365 #define CCU41_IN0_CCU41_ST2 14 2366 #define CCU41_IN0_CCU41_ST3 15 2367 #define CCU41_IN0_CCU81_ST3 7 2368 #define CCU41_IN0_ERU0_IOUT0 10 2369 #define CCU41_IN0_ERU0_PDOUT0 9 2370 #define CCU41_IN0_ERU0_PDOUT1 3 2371 #define CCU41_IN0_ERU1_IOUT0 23 2372 #define CCU41_IN0_ERU1_PDOUT0 22 2373 #define CCU41_IN0_ERU1_PDOUT1 24 2374 #define CCU41_IN0_P0_4 1 2375 #define CCU41_IN0_P3_0 0 2376 #define CCU41_IN0_P4_0 2 2377 #define CCU41_IN0_P4_4 21 2378 #define CCU41_IN0_P4_8 26 2379 #define CCU41_IN0_POSIF1_OUT0 4 2380 #define CCU41_IN0_POSIF1_OUT1 5 2381 #define CCU41_IN0_POSIF1_OUT3 6 2382 #define CCU41_IN0_SCU_ACMP0_OUT 18 2383 #define CCU41_IN0_SCU_ACMP1_OUT 17 2384 #define CCU41_IN0_SCU_GSC40 8 2385 #define CCU41_IN0_U1C0_DX2INS 28 2386 #define CCU41_IN1_BCCU0_OUT1 16 2387 #define CCU41_IN1_BCCU0_OUT3 25 2388 #define CCU41_IN1_CCU40_ST1 11 2389 #define CCU41_IN1_CCU41_GP02 12 2390 #define CCU41_IN1_CCU41_SR1 27 2391 #define CCU41_IN1_CCU41_SR2 19 2392 #define CCU41_IN1_CCU41_ST0 13 2393 #define CCU41_IN1_CCU41_ST1 20 2394 #define CCU41_IN1_CCU41_ST2 14 2395 #define CCU41_IN1_CCU41_ST3 15 2396 #define CCU41_IN1_ERU0_IOUT1 10 2397 #define CCU41_IN1_ERU0_PDOUT0 3 2398 #define CCU41_IN1_ERU0_PDOUT1 9 2399 #define CCU41_IN1_ERU1_IOUT1 23 2400 #define CCU41_IN1_ERU1_PDOUT0 24 2401 #define CCU41_IN1_ERU1_PDOUT1 22 2402 #define CCU41_IN1_P0_5 1 2403 #define CCU41_IN1_P3_0 0 2404 #define CCU41_IN1_P4_1 2 2405 #define CCU41_IN1_P4_5 21 2406 #define CCU41_IN1_P4_9 26 2407 #define CCU41_IN1_POSIF1_OUT0 4 2408 #define CCU41_IN1_POSIF1_OUT1 5 2409 #define CCU41_IN1_POSIF1_OUT3 6 2410 #define CCU41_IN1_POSIF1_OUT4 7 2411 #define CCU41_IN1_SCU_ACMP2_OUT 18 2412 #define CCU41_IN1_SCU_ACMP3_OUT 17 2413 #define CCU41_IN1_SCU_GSC40 8 2414 #define CCU41_IN1_U1C1_DX2INS 28 2415 #define CCU41_IN2_BCCU0_OUT2 16 2416 #define CCU41_IN2_BCCU0_OUT7 25 2417 #define CCU41_IN2_CCU40_ST2 11 2418 #define CCU41_IN2_CCU41_GP03 12 2419 #define CCU41_IN2_CCU41_SR1 19 2420 #define CCU41_IN2_CCU41_SR2 27 2421 #define CCU41_IN2_CCU41_ST0 13 2422 #define CCU41_IN2_CCU41_ST1 14 2423 #define CCU41_IN2_CCU41_ST2 20 2424 #define CCU41_IN2_CCU41_ST3 15 2425 #define CCU41_IN2_ERU0_IOUT2 10 2426 #define CCU41_IN2_ERU0_PDOUT2 9 2427 #define CCU41_IN2_ERU0_PDOUT3 3 2428 #define CCU41_IN2_ERU1_IOUT2 23 2429 #define CCU41_IN2_ERU1_PDOUT2 22 2430 #define CCU41_IN2_ERU1_PDOUT3 24 2431 #define CCU41_IN2_P0_6 1 2432 #define CCU41_IN2_P3_0 0 2433 #define CCU41_IN2_P4_10 26 2434 #define CCU41_IN2_P4_2 2 2435 #define CCU41_IN2_P4_6 21 2436 #define CCU41_IN2_POSIF1_OUT0 28 2437 #define CCU41_IN2_POSIF1_OUT1 4 2438 #define CCU41_IN2_POSIF1_OUT2 5 2439 #define CCU41_IN2_POSIF1_OUT3 6 2440 #define CCU41_IN2_POSIF1_OUT4 7 2441 #define CCU41_IN2_SCU_ACMP1_OUT 18 2442 #define CCU41_IN2_SCU_ACMP2_OUT 17 2443 #define CCU41_IN2_SCU_GSC40 8 2444 #define CCU41_IN3_BCCU0_OUT5 16 2445 #define CCU41_IN3_BCCU0_OUT8 25 2446 #define CCU41_IN3_CCU40_ST3 11 2447 #define CCU41_IN3_CCU41_GP00 12 2448 #define CCU41_IN3_CCU41_SR1 19 2449 #define CCU41_IN3_CCU41_SR3 27 2450 #define CCU41_IN3_CCU41_ST0 13 2451 #define CCU41_IN3_CCU41_ST1 14 2452 #define CCU41_IN3_CCU41_ST2 15 2453 #define CCU41_IN3_CCU41_ST3 20 2454 #define CCU41_IN3_CCU81_IGBTO 7 2455 #define CCU41_IN3_ERU0_IOUT3 10 2456 #define CCU41_IN3_ERU0_PDOUT2 3 2457 #define CCU41_IN3_ERU0_PDOUT3 9 2458 #define CCU41_IN3_ERU1_IOUT3 23 2459 #define CCU41_IN3_ERU1_PDOUT2 24 2460 #define CCU41_IN3_ERU1_PDOUT3 22 2461 #define CCU41_IN3_P0_7 1 2462 #define CCU41_IN3_P3_0 0 2463 #define CCU41_IN3_P4_11 26 2464 #define CCU41_IN3_P4_3 2 2465 #define CCU41_IN3_P4_7 21 2466 #define CCU41_IN3_POSIF1_OUT0 28 2467 #define CCU41_IN3_POSIF1_OUT1 29 2468 #define CCU41_IN3_POSIF1_OUT3 4 2469 #define CCU41_IN3_POSIF1_OUT5 5 2470 #define CCU41_IN3_SCU_ACMP0_OUT 17 2471 #define CCU41_IN3_SCU_ACMP3_OUT 18 2472 #define CCU41_IN3_SCU_GSC40 8 2473 #define CCU41_IN3_VADC0_G0ARBCNT 6 2474 #endif 2475 2476 2477 #if (UC_DEVICE == XMC1402) && (UC_PACKAGE == TSSOP38) 2478 #define CCU40_IN0_BCCU0_OUT0 16 2479 #define CCU40_IN0_BCCU0_OUT6 25 2480 #define CCU40_IN0_CCU40_GP01 12 2481 #define CCU40_IN0_CCU40_SR0 27 2482 #define CCU40_IN0_CCU40_SR2 19 2483 #define CCU40_IN0_CCU40_ST0 20 2484 #define CCU40_IN0_CCU40_ST1 13 2485 #define CCU40_IN0_CCU40_ST2 14 2486 #define CCU40_IN0_CCU40_ST3 15 2487 #define CCU40_IN0_CCU80_ST3 7 2488 #define CCU40_IN0_ERU0_IOUT0 10 2489 #define CCU40_IN0_ERU0_PDOUT0 9 2490 #define CCU40_IN0_ERU0_PDOUT1 3 2491 #define CCU40_IN0_ERU1_IOUT0 23 2492 #define CCU40_IN0_ERU1_PDOUT0 22 2493 #define CCU40_IN0_ERU1_PDOUT1 24 2494 #define CCU40_IN0_P0_0 2 2495 #define CCU40_IN0_P0_12 0 2496 #define CCU40_IN0_P0_6 1 2497 #define CCU40_IN0_POSIF0_OUT0 4 2498 #define CCU40_IN0_POSIF0_OUT1 5 2499 #define CCU40_IN0_POSIF0_OUT3 6 2500 #define CCU40_IN0_SCU_ACMP0_OUT 18 2501 #define CCU40_IN0_SCU_ACMP1_OUT 17 2502 #define CCU40_IN0_SCU_GSC40 8 2503 #define CCU40_IN0_U0C0_DX2INS 11 2504 #define CCU40_IN1_BCCU0_OUT3 25 2505 #define CCU40_IN1_BCCU0_OUT8 16 2506 #define CCU40_IN1_CCU40_GP02 12 2507 #define CCU40_IN1_CCU40_SR1 27 2508 #define CCU40_IN1_CCU40_SR2 19 2509 #define CCU40_IN1_CCU40_ST0 13 2510 #define CCU40_IN1_CCU40_ST1 20 2511 #define CCU40_IN1_CCU40_ST2 14 2512 #define CCU40_IN1_CCU40_ST3 15 2513 #define CCU40_IN1_ERU0_IOUT1 10 2514 #define CCU40_IN1_ERU0_PDOUT0 3 2515 #define CCU40_IN1_ERU0_PDOUT1 9 2516 #define CCU40_IN1_ERU1_IOUT1 23 2517 #define CCU40_IN1_ERU1_PDOUT0 24 2518 #define CCU40_IN1_ERU1_PDOUT1 22 2519 #define CCU40_IN1_P0_1 2 2520 #define CCU40_IN1_P0_12 0 2521 #define CCU40_IN1_P0_7 1 2522 #define CCU40_IN1_POSIF0_OUT0 4 2523 #define CCU40_IN1_POSIF0_OUT1 5 2524 #define CCU40_IN1_POSIF0_OUT3 6 2525 #define CCU40_IN1_POSIF0_OUT4 7 2526 #define CCU40_IN1_SCU_ACMP2_OUT 18 2527 #define CCU40_IN1_SCU_GSC40 8 2528 #define CCU40_IN1_U0C1_DX2INS 11 2529 #define CCU40_IN2_BCCU0_OUT4 16 2530 #define CCU40_IN2_BCCU0_OUT7 25 2531 #define CCU40_IN2_CCU40_GP03 12 2532 #define CCU40_IN2_CCU40_SR1 19 2533 #define CCU40_IN2_CCU40_SR2 27 2534 #define CCU40_IN2_CCU40_ST0 13 2535 #define CCU40_IN2_CCU40_ST1 14 2536 #define CCU40_IN2_CCU40_ST2 20 2537 #define CCU40_IN2_CCU40_ST3 15 2538 #define CCU40_IN2_ERU0_IOUT2 10 2539 #define CCU40_IN2_ERU0_PDOUT2 9 2540 #define CCU40_IN2_ERU0_PDOUT3 3 2541 #define CCU40_IN2_ERU1_IOUT2 23 2542 #define CCU40_IN2_ERU1_PDOUT2 22 2543 #define CCU40_IN2_ERU1_PDOUT3 24 2544 #define CCU40_IN2_P0_12 0 2545 #define CCU40_IN2_P0_2 2 2546 #define CCU40_IN2_P0_8 1 2547 #define CCU40_IN2_POSIF0_OUT0 28 2548 #define CCU40_IN2_POSIF0_OUT1 4 2549 #define CCU40_IN2_POSIF0_OUT2 5 2550 #define CCU40_IN2_POSIF0_OUT3 6 2551 #define CCU40_IN2_POSIF0_OUT4 7 2552 #define CCU40_IN2_SCU_ACMP1_OUT 18 2553 #define CCU40_IN2_SCU_ACMP2_OUT 17 2554 #define CCU40_IN2_SCU_GSC40 8 2555 #define CCU40_IN3_BCCU0_OUT1 25 2556 #define CCU40_IN3_BCCU0_OUT5 16 2557 #define CCU40_IN3_CCU40_GP00 12 2558 #define CCU40_IN3_CCU40_SR1 19 2559 #define CCU40_IN3_CCU40_SR3 27 2560 #define CCU40_IN3_CCU40_ST0 13 2561 #define CCU40_IN3_CCU40_ST1 14 2562 #define CCU40_IN3_CCU40_ST2 15 2563 #define CCU40_IN3_CCU40_ST3 20 2564 #define CCU40_IN3_CCU80_IGBTO 7 2565 #define CCU40_IN3_ERU0_IOUT3 10 2566 #define CCU40_IN3_ERU0_PDOUT2 3 2567 #define CCU40_IN3_ERU0_PDOUT3 9 2568 #define CCU40_IN3_ERU1_IOUT3 23 2569 #define CCU40_IN3_ERU1_PDOUT2 24 2570 #define CCU40_IN3_ERU1_PDOUT3 22 2571 #define CCU40_IN3_P0_12 0 2572 #define CCU40_IN3_P0_3 2 2573 #define CCU40_IN3_P0_9 1 2574 #define CCU40_IN3_POSIF0_OUT0 28 2575 #define CCU40_IN3_POSIF0_OUT1 29 2576 #define CCU40_IN3_POSIF0_OUT3 4 2577 #define CCU40_IN3_POSIF0_OUT5 5 2578 #define CCU40_IN3_SCU_ACMP0_OUT 17 2579 #define CCU40_IN3_SCU_GSC40 8 2580 #define CCU40_IN3_VADC0_G0ARBCNT 6 2581 #define CCU41_IN0_BCCU0_OUT0 16 2582 #define CCU41_IN0_BCCU0_OUT6 25 2583 #define CCU41_IN0_CCU41_GP01 12 2584 #define CCU41_IN0_CCU41_SR0 27 2585 #define CCU41_IN0_CCU41_SR2 19 2586 #define CCU41_IN0_CCU41_ST0 20 2587 #define CCU41_IN0_CCU41_ST1 13 2588 #define CCU41_IN0_CCU41_ST2 14 2589 #define CCU41_IN0_CCU41_ST3 15 2590 #define CCU41_IN0_CCU81_ST3 7 2591 #define CCU41_IN0_ERU0_IOUT0 10 2592 #define CCU41_IN0_ERU0_PDOUT0 9 2593 #define CCU41_IN0_ERU0_PDOUT1 3 2594 #define CCU41_IN0_ERU1_IOUT0 23 2595 #define CCU41_IN0_ERU1_PDOUT0 22 2596 #define CCU41_IN0_ERU1_PDOUT1 24 2597 #define CCU41_IN0_P0_4 1 2598 #define CCU41_IN0_SCU_ACMP0_OUT 18 2599 #define CCU41_IN0_SCU_ACMP1_OUT 17 2600 #define CCU41_IN0_SCU_GSC40 8 2601 #define CCU41_IN0_U1C0_DX2INS 28 2602 #define CCU41_IN1_BCCU0_OUT1 16 2603 #define CCU41_IN1_BCCU0_OUT3 25 2604 #define CCU41_IN1_CCU40_ST1 11 2605 #define CCU41_IN1_CCU41_GP02 12 2606 #define CCU41_IN1_CCU41_SR1 27 2607 #define CCU41_IN1_CCU41_SR2 19 2608 #define CCU41_IN1_CCU41_ST0 13 2609 #define CCU41_IN1_CCU41_ST1 20 2610 #define CCU41_IN1_CCU41_ST2 14 2611 #define CCU41_IN1_CCU41_ST3 15 2612 #define CCU41_IN1_ERU0_IOUT1 10 2613 #define CCU41_IN1_ERU0_PDOUT0 3 2614 #define CCU41_IN1_ERU0_PDOUT1 9 2615 #define CCU41_IN1_ERU1_IOUT1 23 2616 #define CCU41_IN1_ERU1_PDOUT0 24 2617 #define CCU41_IN1_ERU1_PDOUT1 22 2618 #define CCU41_IN1_P0_5 1 2619 #define CCU41_IN1_SCU_ACMP2_OUT 18 2620 #define CCU41_IN1_SCU_GSC40 8 2621 #define CCU41_IN1_U1C1_DX2INS 28 2622 #define CCU41_IN2_BCCU0_OUT2 16 2623 #define CCU41_IN2_BCCU0_OUT7 25 2624 #define CCU41_IN2_CCU40_ST2 11 2625 #define CCU41_IN2_CCU41_GP03 12 2626 #define CCU41_IN2_CCU41_SR1 19 2627 #define CCU41_IN2_CCU41_SR2 27 2628 #define CCU41_IN2_CCU41_ST0 13 2629 #define CCU41_IN2_CCU41_ST1 14 2630 #define CCU41_IN2_CCU41_ST2 20 2631 #define CCU41_IN2_CCU41_ST3 15 2632 #define CCU41_IN2_ERU0_IOUT2 10 2633 #define CCU41_IN2_ERU0_PDOUT2 9 2634 #define CCU41_IN2_ERU0_PDOUT3 3 2635 #define CCU41_IN2_ERU1_IOUT2 23 2636 #define CCU41_IN2_ERU1_PDOUT2 22 2637 #define CCU41_IN2_ERU1_PDOUT3 24 2638 #define CCU41_IN2_P0_6 1 2639 #define CCU41_IN2_SCU_ACMP1_OUT 18 2640 #define CCU41_IN2_SCU_ACMP2_OUT 17 2641 #define CCU41_IN2_SCU_GSC40 8 2642 #define CCU41_IN3_BCCU0_OUT5 16 2643 #define CCU41_IN3_BCCU0_OUT8 25 2644 #define CCU41_IN3_CCU40_ST3 11 2645 #define CCU41_IN3_CCU41_GP00 12 2646 #define CCU41_IN3_CCU41_SR1 19 2647 #define CCU41_IN3_CCU41_SR3 27 2648 #define CCU41_IN3_CCU41_ST0 13 2649 #define CCU41_IN3_CCU41_ST1 14 2650 #define CCU41_IN3_CCU41_ST2 15 2651 #define CCU41_IN3_CCU41_ST3 20 2652 #define CCU41_IN3_CCU81_IGBTO 7 2653 #define CCU41_IN3_ERU0_IOUT3 10 2654 #define CCU41_IN3_ERU0_PDOUT2 3 2655 #define CCU41_IN3_ERU0_PDOUT3 9 2656 #define CCU41_IN3_ERU1_IOUT3 23 2657 #define CCU41_IN3_ERU1_PDOUT2 24 2658 #define CCU41_IN3_ERU1_PDOUT3 22 2659 #define CCU41_IN3_P0_7 1 2660 #define CCU41_IN3_SCU_ACMP0_OUT 17 2661 #define CCU41_IN3_SCU_GSC40 8 2662 #define CCU41_IN3_VADC0_G0ARBCNT 6 2663 #endif 2664 2665 2666 #if (UC_DEVICE == XMC1403) && (UC_PACKAGE == VQFN40) 2667 #define CCU40_IN0_CCU40_GP01 12 2668 #define CCU40_IN0_CCU40_SR0 27 2669 #define CCU40_IN0_CCU40_SR2 19 2670 #define CCU40_IN0_CCU40_ST0 20 2671 #define CCU40_IN0_CCU40_ST1 13 2672 #define CCU40_IN0_CCU40_ST2 14 2673 #define CCU40_IN0_CCU40_ST3 15 2674 #define CCU40_IN0_ERU0_IOUT0 10 2675 #define CCU40_IN0_ERU0_PDOUT0 9 2676 #define CCU40_IN0_ERU0_PDOUT1 3 2677 #define CCU40_IN0_ERU1_IOUT0 23 2678 #define CCU40_IN0_ERU1_PDOUT0 22 2679 #define CCU40_IN0_ERU1_PDOUT1 24 2680 #define CCU40_IN0_P0_0 2 2681 #define CCU40_IN0_P0_12 0 2682 #define CCU40_IN0_P0_6 1 2683 #define CCU40_IN0_SCU_GSC40 8 2684 #define CCU40_IN0_U0C0_DX2INS 11 2685 #define CCU40_IN1_CCU40_GP02 12 2686 #define CCU40_IN1_CCU40_SR1 27 2687 #define CCU40_IN1_CCU40_SR2 19 2688 #define CCU40_IN1_CCU40_ST0 13 2689 #define CCU40_IN1_CCU40_ST1 20 2690 #define CCU40_IN1_CCU40_ST2 14 2691 #define CCU40_IN1_CCU40_ST3 15 2692 #define CCU40_IN1_ERU0_IOUT1 10 2693 #define CCU40_IN1_ERU0_PDOUT0 3 2694 #define CCU40_IN1_ERU0_PDOUT1 9 2695 #define CCU40_IN1_ERU1_IOUT1 23 2696 #define CCU40_IN1_ERU1_PDOUT0 24 2697 #define CCU40_IN1_ERU1_PDOUT1 22 2698 #define CCU40_IN1_P0_1 2 2699 #define CCU40_IN1_P0_12 0 2700 #define CCU40_IN1_P0_7 1 2701 #define CCU40_IN1_SCU_GSC40 8 2702 #define CCU40_IN1_U0C1_DX2INS 11 2703 #define CCU40_IN2_CCU40_GP03 12 2704 #define CCU40_IN2_CCU40_SR1 19 2705 #define CCU40_IN2_CCU40_SR2 27 2706 #define CCU40_IN2_CCU40_ST0 13 2707 #define CCU40_IN2_CCU40_ST1 14 2708 #define CCU40_IN2_CCU40_ST2 20 2709 #define CCU40_IN2_CCU40_ST3 15 2710 #define CCU40_IN2_ERU0_IOUT2 10 2711 #define CCU40_IN2_ERU0_PDOUT2 9 2712 #define CCU40_IN2_ERU0_PDOUT3 3 2713 #define CCU40_IN2_ERU1_IOUT2 23 2714 #define CCU40_IN2_ERU1_PDOUT2 22 2715 #define CCU40_IN2_ERU1_PDOUT3 24 2716 #define CCU40_IN2_P0_12 0 2717 #define CCU40_IN2_P0_2 2 2718 #define CCU40_IN2_P0_8 1 2719 #define CCU40_IN2_SCU_GSC40 8 2720 #define CCU40_IN3_CCU40_GP00 12 2721 #define CCU40_IN3_CCU40_SR1 19 2722 #define CCU40_IN3_CCU40_SR3 27 2723 #define CCU40_IN3_CCU40_ST0 13 2724 #define CCU40_IN3_CCU40_ST1 14 2725 #define CCU40_IN3_CCU40_ST2 15 2726 #define CCU40_IN3_CCU40_ST3 20 2727 #define CCU40_IN3_ERU0_IOUT3 10 2728 #define CCU40_IN3_ERU0_PDOUT2 3 2729 #define CCU40_IN3_ERU0_PDOUT3 9 2730 #define CCU40_IN3_ERU1_IOUT3 23 2731 #define CCU40_IN3_ERU1_PDOUT2 24 2732 #define CCU40_IN3_ERU1_PDOUT3 22 2733 #define CCU40_IN3_P0_12 0 2734 #define CCU40_IN3_P0_3 2 2735 #define CCU40_IN3_P0_9 1 2736 #define CCU40_IN3_SCU_GSC40 8 2737 #define CCU40_IN3_VADC0_G0ARBCNT 6 2738 #define CCU41_IN0_CCU41_GP01 12 2739 #define CCU41_IN0_CCU41_SR0 27 2740 #define CCU41_IN0_CCU41_SR2 19 2741 #define CCU41_IN0_CCU41_ST0 20 2742 #define CCU41_IN0_CCU41_ST1 13 2743 #define CCU41_IN0_CCU41_ST2 14 2744 #define CCU41_IN0_CCU41_ST3 15 2745 #define CCU41_IN0_ERU0_IOUT0 10 2746 #define CCU41_IN0_ERU0_PDOUT0 9 2747 #define CCU41_IN0_ERU0_PDOUT1 3 2748 #define CCU41_IN0_ERU1_IOUT0 23 2749 #define CCU41_IN0_ERU1_PDOUT0 22 2750 #define CCU41_IN0_ERU1_PDOUT1 24 2751 #define CCU41_IN0_P0_4 1 2752 #define CCU41_IN0_SCU_GSC40 8 2753 #define CCU41_IN0_U1C0_DX2INS 28 2754 #define CCU41_IN1_CCU40_ST1 11 2755 #define CCU41_IN1_CCU41_GP02 12 2756 #define CCU41_IN1_CCU41_SR1 27 2757 #define CCU41_IN1_CCU41_SR2 19 2758 #define CCU41_IN1_CCU41_ST0 13 2759 #define CCU41_IN1_CCU41_ST1 20 2760 #define CCU41_IN1_CCU41_ST2 14 2761 #define CCU41_IN1_CCU41_ST3 15 2762 #define CCU41_IN1_ERU0_IOUT1 10 2763 #define CCU41_IN1_ERU0_PDOUT0 3 2764 #define CCU41_IN1_ERU0_PDOUT1 9 2765 #define CCU41_IN1_ERU1_IOUT1 23 2766 #define CCU41_IN1_ERU1_PDOUT0 24 2767 #define CCU41_IN1_ERU1_PDOUT1 22 2768 #define CCU41_IN1_P0_5 1 2769 #define CCU41_IN1_SCU_GSC40 8 2770 #define CCU41_IN1_U1C1_DX2INS 28 2771 #define CCU41_IN2_CCU40_ST2 11 2772 #define CCU41_IN2_CCU41_GP03 12 2773 #define CCU41_IN2_CCU41_SR1 19 2774 #define CCU41_IN2_CCU41_SR2 27 2775 #define CCU41_IN2_CCU41_ST0 13 2776 #define CCU41_IN2_CCU41_ST1 14 2777 #define CCU41_IN2_CCU41_ST2 20 2778 #define CCU41_IN2_CCU41_ST3 15 2779 #define CCU41_IN2_ERU0_IOUT2 10 2780 #define CCU41_IN2_ERU0_PDOUT2 9 2781 #define CCU41_IN2_ERU0_PDOUT3 3 2782 #define CCU41_IN2_ERU1_IOUT2 23 2783 #define CCU41_IN2_ERU1_PDOUT2 22 2784 #define CCU41_IN2_ERU1_PDOUT3 24 2785 #define CCU41_IN2_P0_6 1 2786 #define CCU41_IN2_SCU_GSC40 8 2787 #define CCU41_IN3_CCU40_ST3 11 2788 #define CCU41_IN3_CCU41_GP00 12 2789 #define CCU41_IN3_CCU41_SR1 19 2790 #define CCU41_IN3_CCU41_SR3 27 2791 #define CCU41_IN3_CCU41_ST0 13 2792 #define CCU41_IN3_CCU41_ST1 14 2793 #define CCU41_IN3_CCU41_ST2 15 2794 #define CCU41_IN3_CCU41_ST3 20 2795 #define CCU41_IN3_ERU0_IOUT3 10 2796 #define CCU41_IN3_ERU0_PDOUT2 3 2797 #define CCU41_IN3_ERU0_PDOUT3 9 2798 #define CCU41_IN3_ERU1_IOUT3 23 2799 #define CCU41_IN3_ERU1_PDOUT2 24 2800 #define CCU41_IN3_ERU1_PDOUT3 22 2801 #define CCU41_IN3_P0_7 1 2802 #define CCU41_IN3_SCU_GSC40 8 2803 #define CCU41_IN3_VADC0_G0ARBCNT 6 2804 #endif 2805 2806 2807 #if (UC_DEVICE == XMC1403) && (UC_PACKAGE == VQFN48) 2808 #define CCU40_IN0_CCU40_GP01 12 2809 #define CCU40_IN0_CCU40_SR0 27 2810 #define CCU40_IN0_CCU40_SR2 19 2811 #define CCU40_IN0_CCU40_ST0 20 2812 #define CCU40_IN0_CCU40_ST1 13 2813 #define CCU40_IN0_CCU40_ST2 14 2814 #define CCU40_IN0_CCU40_ST3 15 2815 #define CCU40_IN0_ERU0_IOUT0 10 2816 #define CCU40_IN0_ERU0_PDOUT0 9 2817 #define CCU40_IN0_ERU0_PDOUT1 3 2818 #define CCU40_IN0_ERU1_IOUT0 23 2819 #define CCU40_IN0_ERU1_PDOUT0 22 2820 #define CCU40_IN0_ERU1_PDOUT1 24 2821 #define CCU40_IN0_P0_0 2 2822 #define CCU40_IN0_P0_12 0 2823 #define CCU40_IN0_P0_6 1 2824 #define CCU40_IN0_P4_0 26 2825 #define CCU40_IN0_SCU_GSC40 8 2826 #define CCU40_IN0_U0C0_DX2INS 11 2827 #define CCU40_IN1_CCU40_GP02 12 2828 #define CCU40_IN1_CCU40_SR1 27 2829 #define CCU40_IN1_CCU40_SR2 19 2830 #define CCU40_IN1_CCU40_ST0 13 2831 #define CCU40_IN1_CCU40_ST1 20 2832 #define CCU40_IN1_CCU40_ST2 14 2833 #define CCU40_IN1_CCU40_ST3 15 2834 #define CCU40_IN1_ERU0_IOUT1 10 2835 #define CCU40_IN1_ERU0_PDOUT0 3 2836 #define CCU40_IN1_ERU0_PDOUT1 9 2837 #define CCU40_IN1_ERU1_IOUT1 23 2838 #define CCU40_IN1_ERU1_PDOUT0 24 2839 #define CCU40_IN1_ERU1_PDOUT1 22 2840 #define CCU40_IN1_P0_1 2 2841 #define CCU40_IN1_P0_12 0 2842 #define CCU40_IN1_P0_7 1 2843 #define CCU40_IN1_SCU_GSC40 8 2844 #define CCU40_IN1_U0C1_DX2INS 11 2845 #define CCU40_IN2_CCU40_GP03 12 2846 #define CCU40_IN2_CCU40_SR1 19 2847 #define CCU40_IN2_CCU40_SR2 27 2848 #define CCU40_IN2_CCU40_ST0 13 2849 #define CCU40_IN2_CCU40_ST1 14 2850 #define CCU40_IN2_CCU40_ST2 20 2851 #define CCU40_IN2_CCU40_ST3 15 2852 #define CCU40_IN2_ERU0_IOUT2 10 2853 #define CCU40_IN2_ERU0_PDOUT2 9 2854 #define CCU40_IN2_ERU0_PDOUT3 3 2855 #define CCU40_IN2_ERU1_IOUT2 23 2856 #define CCU40_IN2_ERU1_PDOUT2 22 2857 #define CCU40_IN2_ERU1_PDOUT3 24 2858 #define CCU40_IN2_P0_12 0 2859 #define CCU40_IN2_P0_2 2 2860 #define CCU40_IN2_P0_8 1 2861 #define CCU40_IN2_SCU_GSC40 8 2862 #define CCU40_IN3_CCU40_GP00 12 2863 #define CCU40_IN3_CCU40_SR1 19 2864 #define CCU40_IN3_CCU40_SR3 27 2865 #define CCU40_IN3_CCU40_ST0 13 2866 #define CCU40_IN3_CCU40_ST1 14 2867 #define CCU40_IN3_CCU40_ST2 15 2868 #define CCU40_IN3_CCU40_ST3 20 2869 #define CCU40_IN3_ERU0_IOUT3 10 2870 #define CCU40_IN3_ERU0_PDOUT2 3 2871 #define CCU40_IN3_ERU0_PDOUT3 9 2872 #define CCU40_IN3_ERU1_IOUT3 23 2873 #define CCU40_IN3_ERU1_PDOUT2 24 2874 #define CCU40_IN3_ERU1_PDOUT3 22 2875 #define CCU40_IN3_P0_12 0 2876 #define CCU40_IN3_P0_3 2 2877 #define CCU40_IN3_P0_9 1 2878 #define CCU40_IN3_SCU_GSC40 8 2879 #define CCU40_IN3_VADC0_G0ARBCNT 6 2880 #define CCU41_IN0_CCU41_GP01 12 2881 #define CCU41_IN0_CCU41_SR0 27 2882 #define CCU41_IN0_CCU41_SR2 19 2883 #define CCU41_IN0_CCU41_ST0 20 2884 #define CCU41_IN0_CCU41_ST1 13 2885 #define CCU41_IN0_CCU41_ST2 14 2886 #define CCU41_IN0_CCU41_ST3 15 2887 #define CCU41_IN0_ERU0_IOUT0 10 2888 #define CCU41_IN0_ERU0_PDOUT0 9 2889 #define CCU41_IN0_ERU0_PDOUT1 3 2890 #define CCU41_IN0_ERU1_IOUT0 23 2891 #define CCU41_IN0_ERU1_PDOUT0 22 2892 #define CCU41_IN0_ERU1_PDOUT1 24 2893 #define CCU41_IN0_P0_4 1 2894 #define CCU41_IN0_P3_0 0 2895 #define CCU41_IN0_P4_4 21 2896 #define CCU41_IN0_SCU_GSC40 8 2897 #define CCU41_IN0_U1C0_DX2INS 28 2898 #define CCU41_IN1_CCU40_ST1 11 2899 #define CCU41_IN1_CCU41_GP02 12 2900 #define CCU41_IN1_CCU41_SR1 27 2901 #define CCU41_IN1_CCU41_SR2 19 2902 #define CCU41_IN1_CCU41_ST0 13 2903 #define CCU41_IN1_CCU41_ST1 20 2904 #define CCU41_IN1_CCU41_ST2 14 2905 #define CCU41_IN1_CCU41_ST3 15 2906 #define CCU41_IN1_ERU0_IOUT1 10 2907 #define CCU41_IN1_ERU0_PDOUT0 3 2908 #define CCU41_IN1_ERU0_PDOUT1 9 2909 #define CCU41_IN1_ERU1_IOUT1 23 2910 #define CCU41_IN1_ERU1_PDOUT0 24 2911 #define CCU41_IN1_ERU1_PDOUT1 22 2912 #define CCU41_IN1_P0_5 1 2913 #define CCU41_IN1_P3_0 0 2914 #define CCU41_IN1_P4_5 21 2915 #define CCU41_IN1_SCU_GSC40 8 2916 #define CCU41_IN1_U1C1_DX2INS 28 2917 #define CCU41_IN2_CCU40_ST2 11 2918 #define CCU41_IN2_CCU41_GP03 12 2919 #define CCU41_IN2_CCU41_SR1 19 2920 #define CCU41_IN2_CCU41_SR2 27 2921 #define CCU41_IN2_CCU41_ST0 13 2922 #define CCU41_IN2_CCU41_ST1 14 2923 #define CCU41_IN2_CCU41_ST2 20 2924 #define CCU41_IN2_CCU41_ST3 15 2925 #define CCU41_IN2_ERU0_IOUT2 10 2926 #define CCU41_IN2_ERU0_PDOUT2 9 2927 #define CCU41_IN2_ERU0_PDOUT3 3 2928 #define CCU41_IN2_ERU1_IOUT2 23 2929 #define CCU41_IN2_ERU1_PDOUT2 22 2930 #define CCU41_IN2_ERU1_PDOUT3 24 2931 #define CCU41_IN2_P0_6 1 2932 #define CCU41_IN2_P3_0 0 2933 #define CCU41_IN2_P4_6 21 2934 #define CCU41_IN2_SCU_GSC40 8 2935 #define CCU41_IN3_CCU40_ST3 11 2936 #define CCU41_IN3_CCU41_GP00 12 2937 #define CCU41_IN3_CCU41_SR1 19 2938 #define CCU41_IN3_CCU41_SR3 27 2939 #define CCU41_IN3_CCU41_ST0 13 2940 #define CCU41_IN3_CCU41_ST1 14 2941 #define CCU41_IN3_CCU41_ST2 15 2942 #define CCU41_IN3_CCU41_ST3 20 2943 #define CCU41_IN3_ERU0_IOUT3 10 2944 #define CCU41_IN3_ERU0_PDOUT2 3 2945 #define CCU41_IN3_ERU0_PDOUT3 9 2946 #define CCU41_IN3_ERU1_IOUT3 23 2947 #define CCU41_IN3_ERU1_PDOUT2 24 2948 #define CCU41_IN3_ERU1_PDOUT3 22 2949 #define CCU41_IN3_P0_7 1 2950 #define CCU41_IN3_P3_0 0 2951 #define CCU41_IN3_P4_7 21 2952 #define CCU41_IN3_SCU_GSC40 8 2953 #define CCU41_IN3_VADC0_G0ARBCNT 6 2954 #endif 2955 2956 2957 #if (UC_DEVICE == XMC1403) && (UC_PACKAGE == VQFN64) 2958 #define CCU40_IN0_CCU40_GP01 12 2959 #define CCU40_IN0_CCU40_SR0 27 2960 #define CCU40_IN0_CCU40_SR2 19 2961 #define CCU40_IN0_CCU40_ST0 20 2962 #define CCU40_IN0_CCU40_ST1 13 2963 #define CCU40_IN0_CCU40_ST2 14 2964 #define CCU40_IN0_CCU40_ST3 15 2965 #define CCU40_IN0_ERU0_IOUT0 10 2966 #define CCU40_IN0_ERU0_PDOUT0 9 2967 #define CCU40_IN0_ERU0_PDOUT1 3 2968 #define CCU40_IN0_ERU1_IOUT0 23 2969 #define CCU40_IN0_ERU1_PDOUT0 22 2970 #define CCU40_IN0_ERU1_PDOUT1 24 2971 #define CCU40_IN0_P0_0 2 2972 #define CCU40_IN0_P0_12 0 2973 #define CCU40_IN0_P0_6 1 2974 #define CCU40_IN0_P4_0 26 2975 #define CCU40_IN0_P4_8 21 2976 #define CCU40_IN0_SCU_GSC40 8 2977 #define CCU40_IN0_U0C0_DX2INS 11 2978 #define CCU40_IN1_CCU40_GP02 12 2979 #define CCU40_IN1_CCU40_SR1 27 2980 #define CCU40_IN1_CCU40_SR2 19 2981 #define CCU40_IN1_CCU40_ST0 13 2982 #define CCU40_IN1_CCU40_ST1 20 2983 #define CCU40_IN1_CCU40_ST2 14 2984 #define CCU40_IN1_CCU40_ST3 15 2985 #define CCU40_IN1_ERU0_IOUT1 10 2986 #define CCU40_IN1_ERU0_PDOUT0 3 2987 #define CCU40_IN1_ERU0_PDOUT1 9 2988 #define CCU40_IN1_ERU1_IOUT1 23 2989 #define CCU40_IN1_ERU1_PDOUT0 24 2990 #define CCU40_IN1_ERU1_PDOUT1 22 2991 #define CCU40_IN1_P0_1 2 2992 #define CCU40_IN1_P0_12 0 2993 #define CCU40_IN1_P0_7 1 2994 #define CCU40_IN1_P4_1 26 2995 #define CCU40_IN1_P4_9 21 2996 #define CCU40_IN1_SCU_GSC40 8 2997 #define CCU40_IN1_U0C1_DX2INS 11 2998 #define CCU40_IN2_CCU40_GP03 12 2999 #define CCU40_IN2_CCU40_SR1 19 3000 #define CCU40_IN2_CCU40_SR2 27 3001 #define CCU40_IN2_CCU40_ST0 13 3002 #define CCU40_IN2_CCU40_ST1 14 3003 #define CCU40_IN2_CCU40_ST2 20 3004 #define CCU40_IN2_CCU40_ST3 15 3005 #define CCU40_IN2_ERU0_IOUT2 10 3006 #define CCU40_IN2_ERU0_PDOUT2 9 3007 #define CCU40_IN2_ERU0_PDOUT3 3 3008 #define CCU40_IN2_ERU1_IOUT2 23 3009 #define CCU40_IN2_ERU1_PDOUT2 22 3010 #define CCU40_IN2_ERU1_PDOUT3 24 3011 #define CCU40_IN2_P0_12 0 3012 #define CCU40_IN2_P0_2 2 3013 #define CCU40_IN2_P0_8 1 3014 #define CCU40_IN2_P4_10 21 3015 #define CCU40_IN2_P4_2 26 3016 #define CCU40_IN2_SCU_GSC40 8 3017 #define CCU40_IN3_CCU40_GP00 12 3018 #define CCU40_IN3_CCU40_SR1 19 3019 #define CCU40_IN3_CCU40_SR3 27 3020 #define CCU40_IN3_CCU40_ST0 13 3021 #define CCU40_IN3_CCU40_ST1 14 3022 #define CCU40_IN3_CCU40_ST2 15 3023 #define CCU40_IN3_CCU40_ST3 20 3024 #define CCU40_IN3_ERU0_IOUT3 10 3025 #define CCU40_IN3_ERU0_PDOUT2 3 3026 #define CCU40_IN3_ERU0_PDOUT3 9 3027 #define CCU40_IN3_ERU1_IOUT3 23 3028 #define CCU40_IN3_ERU1_PDOUT2 24 3029 #define CCU40_IN3_ERU1_PDOUT3 22 3030 #define CCU40_IN3_P0_12 0 3031 #define CCU40_IN3_P0_3 2 3032 #define CCU40_IN3_P0_9 1 3033 #define CCU40_IN3_P4_11 21 3034 #define CCU40_IN3_P4_3 26 3035 #define CCU40_IN3_SCU_GSC40 8 3036 #define CCU40_IN3_VADC0_G0ARBCNT 6 3037 #define CCU41_IN0_CCU41_GP01 12 3038 #define CCU41_IN0_CCU41_SR0 27 3039 #define CCU41_IN0_CCU41_SR2 19 3040 #define CCU41_IN0_CCU41_ST0 20 3041 #define CCU41_IN0_CCU41_ST1 13 3042 #define CCU41_IN0_CCU41_ST2 14 3043 #define CCU41_IN0_CCU41_ST3 15 3044 #define CCU41_IN0_ERU0_IOUT0 10 3045 #define CCU41_IN0_ERU0_PDOUT0 9 3046 #define CCU41_IN0_ERU0_PDOUT1 3 3047 #define CCU41_IN0_ERU1_IOUT0 23 3048 #define CCU41_IN0_ERU1_PDOUT0 22 3049 #define CCU41_IN0_ERU1_PDOUT1 24 3050 #define CCU41_IN0_P0_4 1 3051 #define CCU41_IN0_P3_0 0 3052 #define CCU41_IN0_P4_0 2 3053 #define CCU41_IN0_P4_4 21 3054 #define CCU41_IN0_P4_8 26 3055 #define CCU41_IN0_SCU_GSC40 8 3056 #define CCU41_IN0_U1C0_DX2INS 28 3057 #define CCU41_IN1_CCU40_ST1 11 3058 #define CCU41_IN1_CCU41_GP02 12 3059 #define CCU41_IN1_CCU41_SR1 27 3060 #define CCU41_IN1_CCU41_SR2 19 3061 #define CCU41_IN1_CCU41_ST0 13 3062 #define CCU41_IN1_CCU41_ST1 20 3063 #define CCU41_IN1_CCU41_ST2 14 3064 #define CCU41_IN1_CCU41_ST3 15 3065 #define CCU41_IN1_ERU0_IOUT1 10 3066 #define CCU41_IN1_ERU0_PDOUT0 3 3067 #define CCU41_IN1_ERU0_PDOUT1 9 3068 #define CCU41_IN1_ERU1_IOUT1 23 3069 #define CCU41_IN1_ERU1_PDOUT0 24 3070 #define CCU41_IN1_ERU1_PDOUT1 22 3071 #define CCU41_IN1_P0_5 1 3072 #define CCU41_IN1_P3_0 0 3073 #define CCU41_IN1_P4_1 2 3074 #define CCU41_IN1_P4_5 21 3075 #define CCU41_IN1_P4_9 26 3076 #define CCU41_IN1_SCU_GSC40 8 3077 #define CCU41_IN1_U1C1_DX2INS 28 3078 #define CCU41_IN2_CCU40_ST2 11 3079 #define CCU41_IN2_CCU41_GP03 12 3080 #define CCU41_IN2_CCU41_SR1 19 3081 #define CCU41_IN2_CCU41_SR2 27 3082 #define CCU41_IN2_CCU41_ST0 13 3083 #define CCU41_IN2_CCU41_ST1 14 3084 #define CCU41_IN2_CCU41_ST2 20 3085 #define CCU41_IN2_CCU41_ST3 15 3086 #define CCU41_IN2_ERU0_IOUT2 10 3087 #define CCU41_IN2_ERU0_PDOUT2 9 3088 #define CCU41_IN2_ERU0_PDOUT3 3 3089 #define CCU41_IN2_ERU1_IOUT2 23 3090 #define CCU41_IN2_ERU1_PDOUT2 22 3091 #define CCU41_IN2_ERU1_PDOUT3 24 3092 #define CCU41_IN2_P0_6 1 3093 #define CCU41_IN2_P3_0 0 3094 #define CCU41_IN2_P4_10 26 3095 #define CCU41_IN2_P4_2 2 3096 #define CCU41_IN2_P4_6 21 3097 #define CCU41_IN2_SCU_GSC40 8 3098 #define CCU41_IN3_CCU40_ST3 11 3099 #define CCU41_IN3_CCU41_GP00 12 3100 #define CCU41_IN3_CCU41_SR1 19 3101 #define CCU41_IN3_CCU41_SR3 27 3102 #define CCU41_IN3_CCU41_ST0 13 3103 #define CCU41_IN3_CCU41_ST1 14 3104 #define CCU41_IN3_CCU41_ST2 15 3105 #define CCU41_IN3_CCU41_ST3 20 3106 #define CCU41_IN3_ERU0_IOUT3 10 3107 #define CCU41_IN3_ERU0_PDOUT2 3 3108 #define CCU41_IN3_ERU0_PDOUT3 9 3109 #define CCU41_IN3_ERU1_IOUT3 23 3110 #define CCU41_IN3_ERU1_PDOUT2 24 3111 #define CCU41_IN3_ERU1_PDOUT3 22 3112 #define CCU41_IN3_P0_7 1 3113 #define CCU41_IN3_P3_0 0 3114 #define CCU41_IN3_P4_11 26 3115 #define CCU41_IN3_P4_3 2 3116 #define CCU41_IN3_P4_7 21 3117 #define CCU41_IN3_SCU_GSC40 8 3118 #define CCU41_IN3_VADC0_G0ARBCNT 6 3119 #endif 3120 3121 3122 #if (UC_DEVICE == XMC1404) && (UC_PACKAGE == LQFP64) 3123 #define CCU40_IN0_BCCU0_OUT0 16 3124 #define CCU40_IN0_BCCU0_OUT6 25 3125 #define CCU40_IN0_CCU40_GP01 12 3126 #define CCU40_IN0_CCU40_SR0 27 3127 #define CCU40_IN0_CCU40_SR2 19 3128 #define CCU40_IN0_CCU40_ST0 20 3129 #define CCU40_IN0_CCU40_ST1 13 3130 #define CCU40_IN0_CCU40_ST2 14 3131 #define CCU40_IN0_CCU40_ST3 15 3132 #define CCU40_IN0_CCU80_ST3 7 3133 #define CCU40_IN0_ERU0_IOUT0 10 3134 #define CCU40_IN0_ERU0_PDOUT0 9 3135 #define CCU40_IN0_ERU0_PDOUT1 3 3136 #define CCU40_IN0_ERU1_IOUT0 23 3137 #define CCU40_IN0_ERU1_PDOUT0 22 3138 #define CCU40_IN0_ERU1_PDOUT1 24 3139 #define CCU40_IN0_P0_0 2 3140 #define CCU40_IN0_P0_12 0 3141 #define CCU40_IN0_P0_6 1 3142 #define CCU40_IN0_P4_0 26 3143 #define CCU40_IN0_P4_8 21 3144 #define CCU40_IN0_POSIF0_OUT0 4 3145 #define CCU40_IN0_POSIF0_OUT1 5 3146 #define CCU40_IN0_POSIF0_OUT3 6 3147 #define CCU40_IN0_SCU_ACMP0_OUT 18 3148 #define CCU40_IN0_SCU_ACMP1_OUT 17 3149 #define CCU40_IN0_SCU_GSC40 8 3150 #define CCU40_IN0_U0C0_DX2INS 11 3151 #define CCU40_IN1_BCCU0_OUT3 25 3152 #define CCU40_IN1_BCCU0_OUT8 16 3153 #define CCU40_IN1_CCU40_GP02 12 3154 #define CCU40_IN1_CCU40_SR1 27 3155 #define CCU40_IN1_CCU40_SR2 19 3156 #define CCU40_IN1_CCU40_ST0 13 3157 #define CCU40_IN1_CCU40_ST1 20 3158 #define CCU40_IN1_CCU40_ST2 14 3159 #define CCU40_IN1_CCU40_ST3 15 3160 #define CCU40_IN1_ERU0_IOUT1 10 3161 #define CCU40_IN1_ERU0_PDOUT0 3 3162 #define CCU40_IN1_ERU0_PDOUT1 9 3163 #define CCU40_IN1_ERU1_IOUT1 23 3164 #define CCU40_IN1_ERU1_PDOUT0 24 3165 #define CCU40_IN1_ERU1_PDOUT1 22 3166 #define CCU40_IN1_P0_1 2 3167 #define CCU40_IN1_P0_12 0 3168 #define CCU40_IN1_P0_7 1 3169 #define CCU40_IN1_P4_1 26 3170 #define CCU40_IN1_P4_9 21 3171 #define CCU40_IN1_POSIF0_OUT0 4 3172 #define CCU40_IN1_POSIF0_OUT1 5 3173 #define CCU40_IN1_POSIF0_OUT3 6 3174 #define CCU40_IN1_POSIF0_OUT4 7 3175 #define CCU40_IN1_SCU_ACMP2_OUT 18 3176 #define CCU40_IN1_SCU_ACMP3_OUT 17 3177 #define CCU40_IN1_SCU_GSC40 8 3178 #define CCU40_IN1_U0C1_DX2INS 11 3179 #define CCU40_IN2_BCCU0_OUT4 16 3180 #define CCU40_IN2_BCCU0_OUT7 25 3181 #define CCU40_IN2_CCU40_GP03 12 3182 #define CCU40_IN2_CCU40_SR1 19 3183 #define CCU40_IN2_CCU40_SR2 27 3184 #define CCU40_IN2_CCU40_ST0 13 3185 #define CCU40_IN2_CCU40_ST1 14 3186 #define CCU40_IN2_CCU40_ST2 20 3187 #define CCU40_IN2_CCU40_ST3 15 3188 #define CCU40_IN2_ERU0_IOUT2 10 3189 #define CCU40_IN2_ERU0_PDOUT2 9 3190 #define CCU40_IN2_ERU0_PDOUT3 3 3191 #define CCU40_IN2_ERU1_IOUT2 23 3192 #define CCU40_IN2_ERU1_PDOUT2 22 3193 #define CCU40_IN2_ERU1_PDOUT3 24 3194 #define CCU40_IN2_LEDTS0_SR 11 3195 #define CCU40_IN2_P0_12 0 3196 #define CCU40_IN2_P0_2 2 3197 #define CCU40_IN2_P0_8 1 3198 #define CCU40_IN2_P4_10 21 3199 #define CCU40_IN2_P4_2 26 3200 #define CCU40_IN2_POSIF0_OUT0 28 3201 #define CCU40_IN2_POSIF0_OUT1 4 3202 #define CCU40_IN2_POSIF0_OUT2 5 3203 #define CCU40_IN2_POSIF0_OUT3 6 3204 #define CCU40_IN2_POSIF0_OUT4 7 3205 #define CCU40_IN2_SCU_ACMP1_OUT 18 3206 #define CCU40_IN2_SCU_ACMP2_OUT 17 3207 #define CCU40_IN2_SCU_GSC40 8 3208 #define CCU40_IN3_BCCU0_OUT1 25 3209 #define CCU40_IN3_BCCU0_OUT5 16 3210 #define CCU40_IN3_CCU40_GP00 12 3211 #define CCU40_IN3_CCU40_SR1 19 3212 #define CCU40_IN3_CCU40_SR3 27 3213 #define CCU40_IN3_CCU40_ST0 13 3214 #define CCU40_IN3_CCU40_ST1 14 3215 #define CCU40_IN3_CCU40_ST2 15 3216 #define CCU40_IN3_CCU40_ST3 20 3217 #define CCU40_IN3_CCU80_IGBTO 7 3218 #define CCU40_IN3_ERU0_IOUT3 10 3219 #define CCU40_IN3_ERU0_PDOUT2 3 3220 #define CCU40_IN3_ERU0_PDOUT3 9 3221 #define CCU40_IN3_ERU1_IOUT3 23 3222 #define CCU40_IN3_ERU1_PDOUT2 24 3223 #define CCU40_IN3_ERU1_PDOUT3 22 3224 #define CCU40_IN3_LEDTS1_SR 11 3225 #define CCU40_IN3_P0_12 0 3226 #define CCU40_IN3_P0_3 2 3227 #define CCU40_IN3_P0_9 1 3228 #define CCU40_IN3_P4_11 21 3229 #define CCU40_IN3_P4_3 26 3230 #define CCU40_IN3_POSIF0_OUT0 28 3231 #define CCU40_IN3_POSIF0_OUT1 29 3232 #define CCU40_IN3_POSIF0_OUT3 4 3233 #define CCU40_IN3_POSIF0_OUT5 5 3234 #define CCU40_IN3_SCU_ACMP0_OUT 17 3235 #define CCU40_IN3_SCU_ACMP3_OUT 18 3236 #define CCU40_IN3_SCU_GSC40 8 3237 #define CCU40_IN3_VADC0_G0ARBCNT 6 3238 #define CCU41_IN0_BCCU0_OUT0 16 3239 #define CCU41_IN0_BCCU0_OUT6 25 3240 #define CCU41_IN0_CCU41_GP01 12 3241 #define CCU41_IN0_CCU41_SR0 27 3242 #define CCU41_IN0_CCU41_SR2 19 3243 #define CCU41_IN0_CCU41_ST0 20 3244 #define CCU41_IN0_CCU41_ST1 13 3245 #define CCU41_IN0_CCU41_ST2 14 3246 #define CCU41_IN0_CCU41_ST3 15 3247 #define CCU41_IN0_CCU81_ST3 7 3248 #define CCU41_IN0_ERU0_IOUT0 10 3249 #define CCU41_IN0_ERU0_PDOUT0 9 3250 #define CCU41_IN0_ERU0_PDOUT1 3 3251 #define CCU41_IN0_ERU1_IOUT0 23 3252 #define CCU41_IN0_ERU1_PDOUT0 22 3253 #define CCU41_IN0_ERU1_PDOUT1 24 3254 #define CCU41_IN0_P0_4 1 3255 #define CCU41_IN0_P3_0 0 3256 #define CCU41_IN0_P4_0 2 3257 #define CCU41_IN0_P4_4 21 3258 #define CCU41_IN0_P4_8 26 3259 #define CCU41_IN0_POSIF1_OUT0 4 3260 #define CCU41_IN0_POSIF1_OUT1 5 3261 #define CCU41_IN0_POSIF1_OUT3 6 3262 #define CCU41_IN0_SCU_ACMP0_OUT 18 3263 #define CCU41_IN0_SCU_ACMP1_OUT 17 3264 #define CCU41_IN0_SCU_GSC40 8 3265 #define CCU41_IN0_U1C0_DX2INS 28 3266 #define CCU41_IN1_BCCU0_OUT1 16 3267 #define CCU41_IN1_BCCU0_OUT3 25 3268 #define CCU41_IN1_CCU40_ST1 11 3269 #define CCU41_IN1_CCU41_GP02 12 3270 #define CCU41_IN1_CCU41_SR1 27 3271 #define CCU41_IN1_CCU41_SR2 19 3272 #define CCU41_IN1_CCU41_ST0 13 3273 #define CCU41_IN1_CCU41_ST1 20 3274 #define CCU41_IN1_CCU41_ST2 14 3275 #define CCU41_IN1_CCU41_ST3 15 3276 #define CCU41_IN1_ERU0_IOUT1 10 3277 #define CCU41_IN1_ERU0_PDOUT0 3 3278 #define CCU41_IN1_ERU0_PDOUT1 9 3279 #define CCU41_IN1_ERU1_IOUT1 23 3280 #define CCU41_IN1_ERU1_PDOUT0 24 3281 #define CCU41_IN1_ERU1_PDOUT1 22 3282 #define CCU41_IN1_P0_5 1 3283 #define CCU41_IN1_P3_0 0 3284 #define CCU41_IN1_P4_1 2 3285 #define CCU41_IN1_P4_5 21 3286 #define CCU41_IN1_P4_9 26 3287 #define CCU41_IN1_POSIF1_OUT0 4 3288 #define CCU41_IN1_POSIF1_OUT1 5 3289 #define CCU41_IN1_POSIF1_OUT3 6 3290 #define CCU41_IN1_POSIF1_OUT4 7 3291 #define CCU41_IN1_SCU_ACMP2_OUT 18 3292 #define CCU41_IN1_SCU_ACMP3_OUT 17 3293 #define CCU41_IN1_SCU_GSC40 8 3294 #define CCU41_IN1_U1C1_DX2INS 28 3295 #define CCU41_IN2_BCCU0_OUT2 16 3296 #define CCU41_IN2_BCCU0_OUT7 25 3297 #define CCU41_IN2_CCU40_ST2 11 3298 #define CCU41_IN2_CCU41_GP03 12 3299 #define CCU41_IN2_CCU41_SR1 19 3300 #define CCU41_IN2_CCU41_SR2 27 3301 #define CCU41_IN2_CCU41_ST0 13 3302 #define CCU41_IN2_CCU41_ST1 14 3303 #define CCU41_IN2_CCU41_ST2 20 3304 #define CCU41_IN2_CCU41_ST3 15 3305 #define CCU41_IN2_ERU0_IOUT2 10 3306 #define CCU41_IN2_ERU0_PDOUT2 9 3307 #define CCU41_IN2_ERU0_PDOUT3 3 3308 #define CCU41_IN2_ERU1_IOUT2 23 3309 #define CCU41_IN2_ERU1_PDOUT2 22 3310 #define CCU41_IN2_ERU1_PDOUT3 24 3311 #define CCU41_IN2_P0_6 1 3312 #define CCU41_IN2_P3_0 0 3313 #define CCU41_IN2_P4_10 26 3314 #define CCU41_IN2_P4_2 2 3315 #define CCU41_IN2_P4_6 21 3316 #define CCU41_IN2_POSIF1_OUT0 28 3317 #define CCU41_IN2_POSIF1_OUT1 4 3318 #define CCU41_IN2_POSIF1_OUT2 5 3319 #define CCU41_IN2_POSIF1_OUT3 6 3320 #define CCU41_IN2_POSIF1_OUT4 7 3321 #define CCU41_IN2_SCU_ACMP1_OUT 18 3322 #define CCU41_IN2_SCU_ACMP2_OUT 17 3323 #define CCU41_IN2_SCU_GSC40 8 3324 #define CCU41_IN3_BCCU0_OUT5 16 3325 #define CCU41_IN3_BCCU0_OUT8 25 3326 #define CCU41_IN3_CCU40_ST3 11 3327 #define CCU41_IN3_CCU41_GP00 12 3328 #define CCU41_IN3_CCU41_SR1 19 3329 #define CCU41_IN3_CCU41_SR3 27 3330 #define CCU41_IN3_CCU41_ST0 13 3331 #define CCU41_IN3_CCU41_ST1 14 3332 #define CCU41_IN3_CCU41_ST2 15 3333 #define CCU41_IN3_CCU41_ST3 20 3334 #define CCU41_IN3_CCU81_IGBTO 7 3335 #define CCU41_IN3_ERU0_IOUT3 10 3336 #define CCU41_IN3_ERU0_PDOUT2 3 3337 #define CCU41_IN3_ERU0_PDOUT3 9 3338 #define CCU41_IN3_ERU1_IOUT3 23 3339 #define CCU41_IN3_ERU1_PDOUT2 24 3340 #define CCU41_IN3_ERU1_PDOUT3 22 3341 #define CCU41_IN3_P0_7 1 3342 #define CCU41_IN3_P3_0 0 3343 #define CCU41_IN3_P4_11 26 3344 #define CCU41_IN3_P4_3 2 3345 #define CCU41_IN3_P4_7 21 3346 #define CCU41_IN3_POSIF1_OUT0 28 3347 #define CCU41_IN3_POSIF1_OUT1 29 3348 #define CCU41_IN3_POSIF1_OUT3 4 3349 #define CCU41_IN3_POSIF1_OUT5 5 3350 #define CCU41_IN3_SCU_ACMP0_OUT 17 3351 #define CCU41_IN3_SCU_ACMP3_OUT 18 3352 #define CCU41_IN3_SCU_GSC40 8 3353 #define CCU41_IN3_VADC0_G0ARBCNT 6 3354 #endif 3355 3356 #if (UC_DEVICE == XMC1404) && (UC_PACKAGE == VQFN40) 3357 #define CCU40_IN0_BCCU0_OUT0 16 3358 #define CCU40_IN0_BCCU0_OUT6 25 3359 #define CCU40_IN0_CCU40_GP01 12 3360 #define CCU40_IN0_CCU40_SR0 27 3361 #define CCU40_IN0_CCU40_SR2 19 3362 #define CCU40_IN0_CCU40_ST0 20 3363 #define CCU40_IN0_CCU40_ST1 13 3364 #define CCU40_IN0_CCU40_ST2 14 3365 #define CCU40_IN0_CCU40_ST3 15 3366 #define CCU40_IN0_CCU80_ST3 7 3367 #define CCU40_IN0_ERU0_IOUT0 10 3368 #define CCU40_IN0_ERU0_PDOUT0 9 3369 #define CCU40_IN0_ERU0_PDOUT1 3 3370 #define CCU40_IN0_ERU1_IOUT0 23 3371 #define CCU40_IN0_ERU1_PDOUT0 22 3372 #define CCU40_IN0_ERU1_PDOUT1 24 3373 #define CCU40_IN0_P0_0 2 3374 #define CCU40_IN0_P0_12 0 3375 #define CCU40_IN0_P0_6 1 3376 #define CCU40_IN0_POSIF0_OUT0 4 3377 #define CCU40_IN0_POSIF0_OUT1 5 3378 #define CCU40_IN0_POSIF0_OUT3 6 3379 #define CCU40_IN0_SCU_ACMP0_OUT 18 3380 #define CCU40_IN0_SCU_ACMP1_OUT 17 3381 #define CCU40_IN0_SCU_GSC40 8 3382 #define CCU40_IN0_U0C0_DX2INS 11 3383 #define CCU40_IN1_BCCU0_OUT3 25 3384 #define CCU40_IN1_BCCU0_OUT8 16 3385 #define CCU40_IN1_CCU40_GP02 12 3386 #define CCU40_IN1_CCU40_SR1 27 3387 #define CCU40_IN1_CCU40_SR2 19 3388 #define CCU40_IN1_CCU40_ST0 13 3389 #define CCU40_IN1_CCU40_ST1 20 3390 #define CCU40_IN1_CCU40_ST2 14 3391 #define CCU40_IN1_CCU40_ST3 15 3392 #define CCU40_IN1_ERU0_IOUT1 10 3393 #define CCU40_IN1_ERU0_PDOUT0 3 3394 #define CCU40_IN1_ERU0_PDOUT1 9 3395 #define CCU40_IN1_ERU1_IOUT1 23 3396 #define CCU40_IN1_ERU1_PDOUT0 24 3397 #define CCU40_IN1_ERU1_PDOUT1 22 3398 #define CCU40_IN1_P0_1 2 3399 #define CCU40_IN1_P0_12 0 3400 #define CCU40_IN1_P0_7 1 3401 #define CCU40_IN1_POSIF0_OUT0 4 3402 #define CCU40_IN1_POSIF0_OUT1 5 3403 #define CCU40_IN1_POSIF0_OUT3 6 3404 #define CCU40_IN1_POSIF0_OUT4 7 3405 #define CCU40_IN1_SCU_ACMP2_OUT 18 3406 #define CCU40_IN1_SCU_GSC40 8 3407 #define CCU40_IN1_U0C1_DX2INS 11 3408 #define CCU40_IN2_BCCU0_OUT4 16 3409 #define CCU40_IN2_BCCU0_OUT7 25 3410 #define CCU40_IN2_CCU40_GP03 12 3411 #define CCU40_IN2_CCU40_SR1 19 3412 #define CCU40_IN2_CCU40_SR2 27 3413 #define CCU40_IN2_CCU40_ST0 13 3414 #define CCU40_IN2_CCU40_ST1 14 3415 #define CCU40_IN2_CCU40_ST2 20 3416 #define CCU40_IN2_CCU40_ST3 15 3417 #define CCU40_IN2_ERU0_IOUT2 10 3418 #define CCU40_IN2_ERU0_PDOUT2 9 3419 #define CCU40_IN2_ERU0_PDOUT3 3 3420 #define CCU40_IN2_ERU1_IOUT2 23 3421 #define CCU40_IN2_ERU1_PDOUT2 22 3422 #define CCU40_IN2_ERU1_PDOUT3 24 3423 #define CCU40_IN2_P0_12 0 3424 #define CCU40_IN2_P0_2 2 3425 #define CCU40_IN2_P0_8 1 3426 #define CCU40_IN2_POSIF0_OUT0 28 3427 #define CCU40_IN2_POSIF0_OUT1 4 3428 #define CCU40_IN2_POSIF0_OUT2 5 3429 #define CCU40_IN2_POSIF0_OUT3 6 3430 #define CCU40_IN2_POSIF0_OUT4 7 3431 #define CCU40_IN2_SCU_ACMP1_OUT 18 3432 #define CCU40_IN2_SCU_ACMP2_OUT 17 3433 #define CCU40_IN2_SCU_GSC40 8 3434 #define CCU40_IN3_BCCU0_OUT1 25 3435 #define CCU40_IN3_BCCU0_OUT5 16 3436 #define CCU40_IN3_CCU40_GP00 12 3437 #define CCU40_IN3_CCU40_SR1 19 3438 #define CCU40_IN3_CCU40_SR3 27 3439 #define CCU40_IN3_CCU40_ST0 13 3440 #define CCU40_IN3_CCU40_ST1 14 3441 #define CCU40_IN3_CCU40_ST2 15 3442 #define CCU40_IN3_CCU40_ST3 20 3443 #define CCU40_IN3_CCU80_IGBTO 7 3444 #define CCU40_IN3_ERU0_IOUT3 10 3445 #define CCU40_IN3_ERU0_PDOUT2 3 3446 #define CCU40_IN3_ERU0_PDOUT3 9 3447 #define CCU40_IN3_ERU1_IOUT3 23 3448 #define CCU40_IN3_ERU1_PDOUT2 24 3449 #define CCU40_IN3_ERU1_PDOUT3 22 3450 #define CCU40_IN3_P0_12 0 3451 #define CCU40_IN3_P0_3 2 3452 #define CCU40_IN3_P0_9 1 3453 #define CCU40_IN3_POSIF0_OUT0 28 3454 #define CCU40_IN3_POSIF0_OUT1 29 3455 #define CCU40_IN3_POSIF0_OUT3 4 3456 #define CCU40_IN3_POSIF0_OUT5 5 3457 #define CCU40_IN3_SCU_ACMP0_OUT 17 3458 #define CCU40_IN3_SCU_GSC40 8 3459 #define CCU40_IN3_VADC0_G0ARBCNT 6 3460 #define CCU41_IN0_BCCU0_OUT0 16 3461 #define CCU41_IN0_BCCU0_OUT6 25 3462 #define CCU41_IN0_CCU41_GP01 12 3463 #define CCU41_IN0_CCU41_SR0 27 3464 #define CCU41_IN0_CCU41_SR2 19 3465 #define CCU41_IN0_CCU41_ST0 20 3466 #define CCU41_IN0_CCU41_ST1 13 3467 #define CCU41_IN0_CCU41_ST2 14 3468 #define CCU41_IN0_CCU41_ST3 15 3469 #define CCU41_IN0_CCU81_ST3 7 3470 #define CCU41_IN0_ERU0_IOUT0 10 3471 #define CCU41_IN0_ERU0_PDOUT0 9 3472 #define CCU41_IN0_ERU0_PDOUT1 3 3473 #define CCU41_IN0_ERU1_IOUT0 23 3474 #define CCU41_IN0_ERU1_PDOUT0 22 3475 #define CCU41_IN0_ERU1_PDOUT1 24 3476 #define CCU41_IN0_P0_4 1 3477 #define CCU41_IN0_SCU_ACMP0_OUT 18 3478 #define CCU41_IN0_SCU_ACMP1_OUT 17 3479 #define CCU41_IN0_SCU_GSC40 8 3480 #define CCU41_IN0_U1C0_DX2INS 28 3481 #define CCU41_IN1_BCCU0_OUT1 16 3482 #define CCU41_IN1_BCCU0_OUT3 25 3483 #define CCU41_IN1_CCU40_ST1 11 3484 #define CCU41_IN1_CCU41_GP02 12 3485 #define CCU41_IN1_CCU41_SR1 27 3486 #define CCU41_IN1_CCU41_SR2 19 3487 #define CCU41_IN1_CCU41_ST0 13 3488 #define CCU41_IN1_CCU41_ST1 20 3489 #define CCU41_IN1_CCU41_ST2 14 3490 #define CCU41_IN1_CCU41_ST3 15 3491 #define CCU41_IN1_ERU0_IOUT1 10 3492 #define CCU41_IN1_ERU0_PDOUT0 3 3493 #define CCU41_IN1_ERU0_PDOUT1 9 3494 #define CCU41_IN1_ERU1_IOUT1 23 3495 #define CCU41_IN1_ERU1_PDOUT0 24 3496 #define CCU41_IN1_ERU1_PDOUT1 22 3497 #define CCU41_IN1_P0_5 1 3498 #define CCU41_IN1_SCU_ACMP2_OUT 18 3499 #define CCU41_IN1_SCU_GSC40 8 3500 #define CCU41_IN1_U1C1_DX2INS 28 3501 #define CCU41_IN2_BCCU0_OUT2 16 3502 #define CCU41_IN2_BCCU0_OUT7 25 3503 #define CCU41_IN2_CCU40_ST2 11 3504 #define CCU41_IN2_CCU41_GP03 12 3505 #define CCU41_IN2_CCU41_SR1 19 3506 #define CCU41_IN2_CCU41_SR2 27 3507 #define CCU41_IN2_CCU41_ST0 13 3508 #define CCU41_IN2_CCU41_ST1 14 3509 #define CCU41_IN2_CCU41_ST2 20 3510 #define CCU41_IN2_CCU41_ST3 15 3511 #define CCU41_IN2_ERU0_IOUT2 10 3512 #define CCU41_IN2_ERU0_PDOUT2 9 3513 #define CCU41_IN2_ERU0_PDOUT3 3 3514 #define CCU41_IN2_ERU1_IOUT2 23 3515 #define CCU41_IN2_ERU1_PDOUT2 22 3516 #define CCU41_IN2_ERU1_PDOUT3 24 3517 #define CCU41_IN2_P0_6 1 3518 #define CCU41_IN2_SCU_ACMP1_OUT 18 3519 #define CCU41_IN2_SCU_ACMP2_OUT 17 3520 #define CCU41_IN2_SCU_GSC40 8 3521 #define CCU41_IN3_BCCU0_OUT5 16 3522 #define CCU41_IN3_BCCU0_OUT8 25 3523 #define CCU41_IN3_CCU40_ST3 11 3524 #define CCU41_IN3_CCU41_GP00 12 3525 #define CCU41_IN3_CCU41_SR1 19 3526 #define CCU41_IN3_CCU41_SR3 27 3527 #define CCU41_IN3_CCU41_ST0 13 3528 #define CCU41_IN3_CCU41_ST1 14 3529 #define CCU41_IN3_CCU41_ST2 15 3530 #define CCU41_IN3_CCU41_ST3 20 3531 #define CCU41_IN3_CCU81_IGBTO 7 3532 #define CCU41_IN3_ERU0_IOUT3 10 3533 #define CCU41_IN3_ERU0_PDOUT2 3 3534 #define CCU41_IN3_ERU0_PDOUT3 9 3535 #define CCU41_IN3_ERU1_IOUT3 23 3536 #define CCU41_IN3_ERU1_PDOUT2 24 3537 #define CCU41_IN3_ERU1_PDOUT3 22 3538 #define CCU41_IN3_P0_7 1 3539 #define CCU41_IN3_SCU_ACMP0_OUT 17 3540 #define CCU41_IN3_SCU_GSC40 8 3541 #define CCU41_IN3_VADC0_G0ARBCNT 6 3542 #endif 3543 3544 #if (UC_DEVICE == XMC1404) && (UC_PACKAGE == VQFN48) 3545 #define CCU40_IN0_BCCU0_OUT0 16 3546 #define CCU40_IN0_BCCU0_OUT6 25 3547 #define CCU40_IN0_CCU40_GP01 12 3548 #define CCU40_IN0_CCU40_SR0 27 3549 #define CCU40_IN0_CCU40_SR2 19 3550 #define CCU40_IN0_CCU40_ST0 20 3551 #define CCU40_IN0_CCU40_ST1 13 3552 #define CCU40_IN0_CCU40_ST2 14 3553 #define CCU40_IN0_CCU40_ST3 15 3554 #define CCU40_IN0_CCU80_ST3 7 3555 #define CCU40_IN0_ERU0_IOUT0 10 3556 #define CCU40_IN0_ERU0_PDOUT0 9 3557 #define CCU40_IN0_ERU0_PDOUT1 3 3558 #define CCU40_IN0_ERU1_IOUT0 23 3559 #define CCU40_IN0_ERU1_PDOUT0 22 3560 #define CCU40_IN0_ERU1_PDOUT1 24 3561 #define CCU40_IN0_P0_0 2 3562 #define CCU40_IN0_P0_12 0 3563 #define CCU40_IN0_P0_6 1 3564 #define CCU40_IN0_POSIF0_OUT0 4 3565 #define CCU40_IN0_POSIF0_OUT1 5 3566 #define CCU40_IN0_POSIF0_OUT3 6 3567 #define CCU40_IN0_SCU_ACMP0_OUT 18 3568 #define CCU40_IN0_SCU_ACMP1_OUT 17 3569 #define CCU40_IN0_SCU_GSC40 8 3570 #define CCU40_IN0_U0C0_DX2INS 11 3571 #define CCU40_IN1_BCCU0_OUT3 25 3572 #define CCU40_IN1_BCCU0_OUT8 16 3573 #define CCU40_IN1_CCU40_GP02 12 3574 #define CCU40_IN1_CCU40_SR1 27 3575 #define CCU40_IN1_CCU40_SR2 19 3576 #define CCU40_IN1_CCU40_ST0 13 3577 #define CCU40_IN1_CCU40_ST1 20 3578 #define CCU40_IN1_CCU40_ST2 14 3579 #define CCU40_IN1_CCU40_ST3 15 3580 #define CCU40_IN1_ERU0_IOUT1 10 3581 #define CCU40_IN1_ERU0_PDOUT0 3 3582 #define CCU40_IN1_ERU0_PDOUT1 9 3583 #define CCU40_IN1_ERU1_IOUT1 23 3584 #define CCU40_IN1_ERU1_PDOUT0 24 3585 #define CCU40_IN1_ERU1_PDOUT1 22 3586 #define CCU40_IN1_P0_1 2 3587 #define CCU40_IN1_P0_12 0 3588 #define CCU40_IN1_P0_7 1 3589 #define CCU40_IN1_POSIF0_OUT0 4 3590 #define CCU40_IN1_POSIF0_OUT1 5 3591 #define CCU40_IN1_POSIF0_OUT3 6 3592 #define CCU40_IN1_POSIF0_OUT4 7 3593 #define CCU40_IN1_SCU_ACMP2_OUT 18 3594 #define CCU40_IN1_SCU_ACMP3_OUT 17 3595 #define CCU40_IN1_SCU_GSC40 8 3596 #define CCU40_IN1_U0C1_DX2INS 11 3597 #define CCU40_IN2_BCCU0_OUT4 16 3598 #define CCU40_IN2_BCCU0_OUT7 25 3599 #define CCU40_IN2_CCU40_GP03 12 3600 #define CCU40_IN2_CCU40_SR1 19 3601 #define CCU40_IN2_CCU40_SR2 27 3602 #define CCU40_IN2_CCU40_ST0 13 3603 #define CCU40_IN2_CCU40_ST1 14 3604 #define CCU40_IN2_CCU40_ST2 20 3605 #define CCU40_IN2_CCU40_ST3 15 3606 #define CCU40_IN2_ERU0_IOUT2 10 3607 #define CCU40_IN2_ERU0_PDOUT2 9 3608 #define CCU40_IN2_ERU0_PDOUT3 3 3609 #define CCU40_IN2_ERU1_IOUT2 23 3610 #define CCU40_IN2_ERU1_PDOUT2 22 3611 #define CCU40_IN2_ERU1_PDOUT3 24 3612 #define CCU40_IN2_LEDTS0_SR 11 3613 #define CCU40_IN2_P0_12 0 3614 #define CCU40_IN2_P0_2 2 3615 #define CCU40_IN2_P0_8 1 3616 #define CCU40_IN2_POSIF0_OUT0 28 3617 #define CCU40_IN2_POSIF0_OUT1 4 3618 #define CCU40_IN2_POSIF0_OUT2 5 3619 #define CCU40_IN2_POSIF0_OUT3 6 3620 #define CCU40_IN2_POSIF0_OUT4 7 3621 #define CCU40_IN2_SCU_ACMP1_OUT 18 3622 #define CCU40_IN2_SCU_ACMP2_OUT 17 3623 #define CCU40_IN2_SCU_GSC40 8 3624 #define CCU40_IN3_BCCU0_OUT1 25 3625 #define CCU40_IN3_BCCU0_OUT5 16 3626 #define CCU40_IN3_CCU40_GP00 12 3627 #define CCU40_IN3_CCU40_SR1 19 3628 #define CCU40_IN3_CCU40_SR3 27 3629 #define CCU40_IN3_CCU40_ST0 13 3630 #define CCU40_IN3_CCU40_ST1 14 3631 #define CCU40_IN3_CCU40_ST2 15 3632 #define CCU40_IN3_CCU40_ST3 20 3633 #define CCU40_IN3_CCU80_IGBTO 7 3634 #define CCU40_IN3_ERU0_IOUT3 10 3635 #define CCU40_IN3_ERU0_PDOUT2 3 3636 #define CCU40_IN3_ERU0_PDOUT3 9 3637 #define CCU40_IN3_ERU1_IOUT3 23 3638 #define CCU40_IN3_ERU1_PDOUT2 24 3639 #define CCU40_IN3_ERU1_PDOUT3 22 3640 #define CCU40_IN3_LEDTS1_SR 11 3641 #define CCU40_IN3_P0_12 0 3642 #define CCU40_IN3_P0_3 2 3643 #define CCU40_IN3_P0_9 1 3644 #define CCU40_IN3_POSIF0_OUT0 28 3645 #define CCU40_IN3_POSIF0_OUT1 29 3646 #define CCU40_IN3_POSIF0_OUT3 4 3647 #define CCU40_IN3_POSIF0_OUT5 5 3648 #define CCU40_IN3_SCU_ACMP0_OUT 17 3649 #define CCU40_IN3_SCU_ACMP3_OUT 18 3650 #define CCU40_IN3_SCU_GSC40 8 3651 #define CCU40_IN3_VADC0_G0ARBCNT 6 3652 #define CCU41_IN0_BCCU0_OUT0 16 3653 #define CCU41_IN0_BCCU0_OUT6 25 3654 #define CCU41_IN0_CCU41_GP01 12 3655 #define CCU41_IN0_CCU41_SR0 27 3656 #define CCU41_IN0_CCU41_SR2 19 3657 #define CCU41_IN0_CCU41_ST0 20 3658 #define CCU41_IN0_CCU41_ST1 13 3659 #define CCU41_IN0_CCU41_ST2 14 3660 #define CCU41_IN0_CCU41_ST3 15 3661 #define CCU41_IN0_CCU81_ST3 7 3662 #define CCU41_IN0_ERU0_IOUT0 10 3663 #define CCU41_IN0_ERU0_PDOUT0 9 3664 #define CCU41_IN0_ERU0_PDOUT1 3 3665 #define CCU41_IN0_ERU1_IOUT0 23 3666 #define CCU41_IN0_ERU1_PDOUT0 22 3667 #define CCU41_IN0_ERU1_PDOUT1 24 3668 #define CCU41_IN0_P0_4 1 3669 #define CCU41_IN0_P3_0 0 3670 #define CCU41_IN0_P4_4 21 3671 #define CCU41_IN0_POSIF1_OUT0 4 3672 #define CCU41_IN0_POSIF1_OUT1 5 3673 #define CCU41_IN0_POSIF1_OUT3 6 3674 #define CCU41_IN0_SCU_ACMP0_OUT 18 3675 #define CCU41_IN0_SCU_ACMP1_OUT 17 3676 #define CCU41_IN0_SCU_GSC40 8 3677 #define CCU41_IN0_U1C0_DX2INS 28 3678 #define CCU41_IN1_BCCU0_OUT1 16 3679 #define CCU41_IN1_BCCU0_OUT3 25 3680 #define CCU41_IN1_CCU40_ST1 11 3681 #define CCU41_IN1_CCU41_GP02 12 3682 #define CCU41_IN1_CCU41_SR1 27 3683 #define CCU41_IN1_CCU41_SR2 19 3684 #define CCU41_IN1_CCU41_ST0 13 3685 #define CCU41_IN1_CCU41_ST1 20 3686 #define CCU41_IN1_CCU41_ST2 14 3687 #define CCU41_IN1_CCU41_ST3 15 3688 #define CCU41_IN1_ERU0_IOUT1 10 3689 #define CCU41_IN1_ERU0_PDOUT0 3 3690 #define CCU41_IN1_ERU0_PDOUT1 9 3691 #define CCU41_IN1_ERU1_IOUT1 23 3692 #define CCU41_IN1_ERU1_PDOUT0 24 3693 #define CCU41_IN1_ERU1_PDOUT1 22 3694 #define CCU41_IN1_P0_5 1 3695 #define CCU41_IN1_P3_0 0 3696 #define CCU41_IN1_P4_5 21 3697 #define CCU41_IN1_POSIF1_OUT0 4 3698 #define CCU41_IN1_POSIF1_OUT1 5 3699 #define CCU41_IN1_POSIF1_OUT3 6 3700 #define CCU41_IN1_POSIF1_OUT4 7 3701 #define CCU41_IN1_SCU_ACMP2_OUT 18 3702 #define CCU41_IN1_SCU_ACMP3_OUT 17 3703 #define CCU41_IN1_SCU_GSC40 8 3704 #define CCU41_IN1_U1C1_DX2INS 28 3705 #define CCU41_IN2_BCCU0_OUT2 16 3706 #define CCU41_IN2_BCCU0_OUT7 25 3707 #define CCU41_IN2_CCU40_ST2 11 3708 #define CCU41_IN2_CCU41_GP03 12 3709 #define CCU41_IN2_CCU41_SR1 19 3710 #define CCU41_IN2_CCU41_SR2 27 3711 #define CCU41_IN2_CCU41_ST0 13 3712 #define CCU41_IN2_CCU41_ST1 14 3713 #define CCU41_IN2_CCU41_ST2 20 3714 #define CCU41_IN2_CCU41_ST3 15 3715 #define CCU41_IN2_ERU0_IOUT2 10 3716 #define CCU41_IN2_ERU0_PDOUT2 9 3717 #define CCU41_IN2_ERU0_PDOUT3 3 3718 #define CCU41_IN2_ERU1_IOUT2 23 3719 #define CCU41_IN2_ERU1_PDOUT2 22 3720 #define CCU41_IN2_ERU1_PDOUT3 24 3721 #define CCU41_IN2_P0_6 1 3722 #define CCU41_IN2_P3_0 0 3723 #define CCU41_IN2_P4_6 21 3724 #define CCU41_IN2_POSIF1_OUT0 28 3725 #define CCU41_IN2_POSIF1_OUT1 4 3726 #define CCU41_IN2_POSIF1_OUT2 5 3727 #define CCU41_IN2_POSIF1_OUT3 6 3728 #define CCU41_IN2_POSIF1_OUT4 7 3729 #define CCU41_IN2_SCU_ACMP1_OUT 18 3730 #define CCU41_IN2_SCU_ACMP2_OUT 17 3731 #define CCU41_IN2_SCU_GSC40 8 3732 #define CCU41_IN3_BCCU0_OUT5 16 3733 #define CCU41_IN3_BCCU0_OUT8 25 3734 #define CCU41_IN3_CCU40_ST3 11 3735 #define CCU41_IN3_CCU41_GP00 12 3736 #define CCU41_IN3_CCU41_SR1 19 3737 #define CCU41_IN3_CCU41_SR3 27 3738 #define CCU41_IN3_CCU41_ST0 13 3739 #define CCU41_IN3_CCU41_ST1 14 3740 #define CCU41_IN3_CCU41_ST2 15 3741 #define CCU41_IN3_CCU41_ST3 20 3742 #define CCU41_IN3_CCU81_IGBTO 7 3743 #define CCU41_IN3_ERU0_IOUT3 10 3744 #define CCU41_IN3_ERU0_PDOUT2 3 3745 #define CCU41_IN3_ERU0_PDOUT3 9 3746 #define CCU41_IN3_ERU1_IOUT3 23 3747 #define CCU41_IN3_ERU1_PDOUT2 24 3748 #define CCU41_IN3_ERU1_PDOUT3 22 3749 #define CCU41_IN3_P0_7 1 3750 #define CCU41_IN3_P3_0 0 3751 #define CCU41_IN3_P4_7 21 3752 #define CCU41_IN3_POSIF1_OUT0 28 3753 #define CCU41_IN3_POSIF1_OUT1 29 3754 #define CCU41_IN3_POSIF1_OUT3 4 3755 #define CCU41_IN3_POSIF1_OUT5 5 3756 #define CCU41_IN3_SCU_ACMP0_OUT 17 3757 #define CCU41_IN3_SCU_ACMP3_OUT 18 3758 #define CCU41_IN3_SCU_GSC40 8 3759 #define CCU41_IN3_VADC0_G0ARBCNT 6 3760 #endif 3761 3762 3763 #if (UC_DEVICE == XMC1404) && (UC_PACKAGE == VQFN64) 3764 #define CCU40_IN0_BCCU0_OUT0 16 3765 #define CCU40_IN0_BCCU0_OUT6 25 3766 #define CCU40_IN0_CCU40_GP01 12 3767 #define CCU40_IN0_CCU40_SR0 27 3768 #define CCU40_IN0_CCU40_SR2 19 3769 #define CCU40_IN0_CCU40_ST0 20 3770 #define CCU40_IN0_CCU40_ST1 13 3771 #define CCU40_IN0_CCU40_ST2 14 3772 #define CCU40_IN0_CCU40_ST3 15 3773 #define CCU40_IN0_CCU80_ST3 7 3774 #define CCU40_IN0_ERU0_IOUT0 10 3775 #define CCU40_IN0_ERU0_PDOUT0 9 3776 #define CCU40_IN0_ERU0_PDOUT1 3 3777 #define CCU40_IN0_ERU1_IOUT0 23 3778 #define CCU40_IN0_ERU1_PDOUT0 22 3779 #define CCU40_IN0_ERU1_PDOUT1 24 3780 #define CCU40_IN0_P0_0 2 3781 #define CCU40_IN0_P0_12 0 3782 #define CCU40_IN0_P0_6 1 3783 #define CCU40_IN0_P4_0 26 3784 #define CCU40_IN0_P4_8 21 3785 #define CCU40_IN0_POSIF0_OUT0 4 3786 #define CCU40_IN0_POSIF0_OUT1 5 3787 #define CCU40_IN0_POSIF0_OUT3 6 3788 #define CCU40_IN0_SCU_ACMP0_OUT 18 3789 #define CCU40_IN0_SCU_ACMP1_OUT 17 3790 #define CCU40_IN0_SCU_GSC40 8 3791 #define CCU40_IN0_U0C0_DX2INS 11 3792 #define CCU40_IN1_BCCU0_OUT3 25 3793 #define CCU40_IN1_BCCU0_OUT8 16 3794 #define CCU40_IN1_CCU40_GP02 12 3795 #define CCU40_IN1_CCU40_SR1 27 3796 #define CCU40_IN1_CCU40_SR2 19 3797 #define CCU40_IN1_CCU40_ST0 13 3798 #define CCU40_IN1_CCU40_ST1 20 3799 #define CCU40_IN1_CCU40_ST2 14 3800 #define CCU40_IN1_CCU40_ST3 15 3801 #define CCU40_IN1_ERU0_IOUT1 10 3802 #define CCU40_IN1_ERU0_PDOUT0 3 3803 #define CCU40_IN1_ERU0_PDOUT1 9 3804 #define CCU40_IN1_ERU1_IOUT1 23 3805 #define CCU40_IN1_ERU1_PDOUT0 24 3806 #define CCU40_IN1_ERU1_PDOUT1 22 3807 #define CCU40_IN1_P0_1 2 3808 #define CCU40_IN1_P0_12 0 3809 #define CCU40_IN1_P0_7 1 3810 #define CCU40_IN1_P4_1 26 3811 #define CCU40_IN1_P4_9 21 3812 #define CCU40_IN1_POSIF0_OUT0 4 3813 #define CCU40_IN1_POSIF0_OUT1 5 3814 #define CCU40_IN1_POSIF0_OUT3 6 3815 #define CCU40_IN1_POSIF0_OUT4 7 3816 #define CCU40_IN1_SCU_ACMP2_OUT 18 3817 #define CCU40_IN1_SCU_ACMP3_OUT 17 3818 #define CCU40_IN1_SCU_GSC40 8 3819 #define CCU40_IN1_U0C1_DX2INS 11 3820 #define CCU40_IN2_BCCU0_OUT4 16 3821 #define CCU40_IN2_BCCU0_OUT7 25 3822 #define CCU40_IN2_CCU40_GP03 12 3823 #define CCU40_IN2_CCU40_SR1 19 3824 #define CCU40_IN2_CCU40_SR2 27 3825 #define CCU40_IN2_CCU40_ST0 13 3826 #define CCU40_IN2_CCU40_ST1 14 3827 #define CCU40_IN2_CCU40_ST2 20 3828 #define CCU40_IN2_CCU40_ST3 15 3829 #define CCU40_IN2_ERU0_IOUT2 10 3830 #define CCU40_IN2_ERU0_PDOUT2 9 3831 #define CCU40_IN2_ERU0_PDOUT3 3 3832 #define CCU40_IN2_ERU1_IOUT2 23 3833 #define CCU40_IN2_ERU1_PDOUT2 22 3834 #define CCU40_IN2_ERU1_PDOUT3 24 3835 #define CCU40_IN2_LEDTS0_SR 11 3836 #define CCU40_IN2_P0_12 0 3837 #define CCU40_IN2_P0_2 2 3838 #define CCU40_IN2_P0_8 1 3839 #define CCU40_IN2_P4_10 21 3840 #define CCU40_IN2_P4_2 26 3841 #define CCU40_IN2_POSIF0_OUT0 28 3842 #define CCU40_IN2_POSIF0_OUT1 4 3843 #define CCU40_IN2_POSIF0_OUT2 5 3844 #define CCU40_IN2_POSIF0_OUT3 6 3845 #define CCU40_IN2_POSIF0_OUT4 7 3846 #define CCU40_IN2_SCU_ACMP1_OUT 18 3847 #define CCU40_IN2_SCU_ACMP2_OUT 17 3848 #define CCU40_IN2_SCU_GSC40 8 3849 #define CCU40_IN3_BCCU0_OUT1 25 3850 #define CCU40_IN3_BCCU0_OUT5 16 3851 #define CCU40_IN3_CCU40_GP00 12 3852 #define CCU40_IN3_CCU40_SR1 19 3853 #define CCU40_IN3_CCU40_SR3 27 3854 #define CCU40_IN3_CCU40_ST0 13 3855 #define CCU40_IN3_CCU40_ST1 14 3856 #define CCU40_IN3_CCU40_ST2 15 3857 #define CCU40_IN3_CCU40_ST3 20 3858 #define CCU40_IN3_CCU80_IGBTO 7 3859 #define CCU40_IN3_ERU0_IOUT3 10 3860 #define CCU40_IN3_ERU0_PDOUT2 3 3861 #define CCU40_IN3_ERU0_PDOUT3 9 3862 #define CCU40_IN3_ERU1_IOUT3 23 3863 #define CCU40_IN3_ERU1_PDOUT2 24 3864 #define CCU40_IN3_ERU1_PDOUT3 22 3865 #define CCU40_IN3_LEDTS1_SR 11 3866 #define CCU40_IN3_P0_12 0 3867 #define CCU40_IN3_P0_3 2 3868 #define CCU40_IN3_P0_9 1 3869 #define CCU40_IN3_P4_11 21 3870 #define CCU40_IN3_P4_3 26 3871 #define CCU40_IN3_POSIF0_OUT0 28 3872 #define CCU40_IN3_POSIF0_OUT1 29 3873 #define CCU40_IN3_POSIF0_OUT3 4 3874 #define CCU40_IN3_POSIF0_OUT5 5 3875 #define CCU40_IN3_SCU_ACMP0_OUT 17 3876 #define CCU40_IN3_SCU_ACMP3_OUT 18 3877 #define CCU40_IN3_SCU_GSC40 8 3878 #define CCU40_IN3_VADC0_G0ARBCNT 6 3879 #define CCU41_IN0_BCCU0_OUT0 16 3880 #define CCU41_IN0_BCCU0_OUT6 25 3881 #define CCU41_IN0_CCU41_GP01 12 3882 #define CCU41_IN0_CCU41_SR0 27 3883 #define CCU41_IN0_CCU41_SR2 19 3884 #define CCU41_IN0_CCU41_ST0 20 3885 #define CCU41_IN0_CCU41_ST1 13 3886 #define CCU41_IN0_CCU41_ST2 14 3887 #define CCU41_IN0_CCU41_ST3 15 3888 #define CCU41_IN0_CCU81_ST3 7 3889 #define CCU41_IN0_ERU0_IOUT0 10 3890 #define CCU41_IN0_ERU0_PDOUT0 9 3891 #define CCU41_IN0_ERU0_PDOUT1 3 3892 #define CCU41_IN0_ERU1_IOUT0 23 3893 #define CCU41_IN0_ERU1_PDOUT0 22 3894 #define CCU41_IN0_ERU1_PDOUT1 24 3895 #define CCU41_IN0_P0_4 1 3896 #define CCU41_IN0_P3_0 0 3897 #define CCU41_IN0_P4_0 2 3898 #define CCU41_IN0_P4_4 21 3899 #define CCU41_IN0_P4_8 26 3900 #define CCU41_IN0_POSIF1_OUT0 4 3901 #define CCU41_IN0_POSIF1_OUT1 5 3902 #define CCU41_IN0_POSIF1_OUT3 6 3903 #define CCU41_IN0_SCU_ACMP0_OUT 18 3904 #define CCU41_IN0_SCU_ACMP1_OUT 17 3905 #define CCU41_IN0_SCU_GSC40 8 3906 #define CCU41_IN0_U1C0_DX2INS 28 3907 #define CCU41_IN1_BCCU0_OUT1 16 3908 #define CCU41_IN1_BCCU0_OUT3 25 3909 #define CCU41_IN1_CCU40_ST1 11 3910 #define CCU41_IN1_CCU41_GP02 12 3911 #define CCU41_IN1_CCU41_SR1 27 3912 #define CCU41_IN1_CCU41_SR2 19 3913 #define CCU41_IN1_CCU41_ST0 13 3914 #define CCU41_IN1_CCU41_ST1 20 3915 #define CCU41_IN1_CCU41_ST2 14 3916 #define CCU41_IN1_CCU41_ST3 15 3917 #define CCU41_IN1_ERU0_IOUT1 10 3918 #define CCU41_IN1_ERU0_PDOUT0 3 3919 #define CCU41_IN1_ERU0_PDOUT1 9 3920 #define CCU41_IN1_ERU1_IOUT1 23 3921 #define CCU41_IN1_ERU1_PDOUT0 24 3922 #define CCU41_IN1_ERU1_PDOUT1 22 3923 #define CCU41_IN1_P0_5 1 3924 #define CCU41_IN1_P3_0 0 3925 #define CCU41_IN1_P4_1 2 3926 #define CCU41_IN1_P4_5 21 3927 #define CCU41_IN1_P4_9 26 3928 #define CCU41_IN1_POSIF1_OUT0 4 3929 #define CCU41_IN1_POSIF1_OUT1 5 3930 #define CCU41_IN1_POSIF1_OUT3 6 3931 #define CCU41_IN1_POSIF1_OUT4 7 3932 #define CCU41_IN1_SCU_ACMP2_OUT 18 3933 #define CCU41_IN1_SCU_ACMP3_OUT 17 3934 #define CCU41_IN1_SCU_GSC40 8 3935 #define CCU41_IN1_U1C1_DX2INS 28 3936 #define CCU41_IN2_BCCU0_OUT2 16 3937 #define CCU41_IN2_BCCU0_OUT7 25 3938 #define CCU41_IN2_CCU40_ST2 11 3939 #define CCU41_IN2_CCU41_GP03 12 3940 #define CCU41_IN2_CCU41_SR1 19 3941 #define CCU41_IN2_CCU41_SR2 27 3942 #define CCU41_IN2_CCU41_ST0 13 3943 #define CCU41_IN2_CCU41_ST1 14 3944 #define CCU41_IN2_CCU41_ST2 20 3945 #define CCU41_IN2_CCU41_ST3 15 3946 #define CCU41_IN2_ERU0_IOUT2 10 3947 #define CCU41_IN2_ERU0_PDOUT2 9 3948 #define CCU41_IN2_ERU0_PDOUT3 3 3949 #define CCU41_IN2_ERU1_IOUT2 23 3950 #define CCU41_IN2_ERU1_PDOUT2 22 3951 #define CCU41_IN2_ERU1_PDOUT3 24 3952 #define CCU41_IN2_P0_6 1 3953 #define CCU41_IN2_P3_0 0 3954 #define CCU41_IN2_P4_10 26 3955 #define CCU41_IN2_P4_2 2 3956 #define CCU41_IN2_P4_6 21 3957 #define CCU41_IN2_POSIF1_OUT0 28 3958 #define CCU41_IN2_POSIF1_OUT1 4 3959 #define CCU41_IN2_POSIF1_OUT2 5 3960 #define CCU41_IN2_POSIF1_OUT3 6 3961 #define CCU41_IN2_POSIF1_OUT4 7 3962 #define CCU41_IN2_SCU_ACMP1_OUT 18 3963 #define CCU41_IN2_SCU_ACMP2_OUT 17 3964 #define CCU41_IN2_SCU_GSC40 8 3965 #define CCU41_IN3_BCCU0_OUT5 16 3966 #define CCU41_IN3_BCCU0_OUT8 25 3967 #define CCU41_IN3_CCU40_ST3 11 3968 #define CCU41_IN3_CCU41_SR1 19 3969 #define CCU41_IN3_CCU41_SR3 27 3970 #define CCU41_IN3_CCU41_ST0 13 3971 #define CCU41_IN3_CCU41_ST1 14 3972 #define CCU41_IN3_CCU41_ST2 15 3973 #define CCU41_IN3_CCU41_ST3 20 3974 #define CCU41_IN3_CCU81_IGBTO 7 3975 #define CCU41_IN3_ERU0_IOUT3 10 3976 #define CCU41_IN3_ERU0_PDOUT2 3 3977 #define CCU41_IN3_ERU0_PDOUT3 9 3978 #define CCU41_IN3_ERU1_IOUT3 23 3979 #define CCU41_IN3_ERU1_PDOUT2 24 3980 #define CCU41_IN3_ERU1_PDOUT3 22 3981 #define CCU41_IN3_P0_7 1 3982 #define CCU41_IN3_P3_0 0 3983 #define CCU41_IN3_P4_11 26 3984 #define CCU41_IN3_P4_3 2 3985 #define CCU41_IN3_P4_7 21 3986 #define CCU41_IN3_POSIF1_OUT0 28 3987 #define CCU41_IN3_POSIF1_OUT1 29 3988 #define CCU41_IN3_POSIF1_OUT3 4 3989 #define CCU41_IN3_POSIF1_OUT5 5 3990 #define CCU41_IN3_SCU_ACMP0_OUT 17 3991 #define CCU41_IN3_SCU_ACMP3_OUT 18 3992 #define CCU41_IN3_SCU_GSC40 8 3993 #define CCU41_IN3_VADC0_G0ARBCNT 6 3994 #endif 3995 3996 #endif /* XMC1_CCU4_MAP_H */ 3997
