1 /*
2  * Copyright (c) 2019 Stephanos Ioannidis <root@stephanos.io>
3  * Copyright (c) 2018 Xilinx, Inc.
4  *
5  * SPDX-License-Identifier: Apache-2.0
6  */
7 
8 #ifndef ZEPHYR_DRIVERS_TIMER_XLNX_PSTTC_TIMER_PRIV_H_
9 #define ZEPHYR_DRIVERS_TIMER_XLNX_PSTTC_TIMER_PRIV_H_
10 
11 /*
12  * Refer to the "Zynq UltraScale+ Device Technical Reference Manual" document
13  * from Xilinx for more information on this peripheral.
14  */
15 
16 /*
17  * Triple-timer Counter (TTC) Register Offsets
18  */
19 
20 /* Clock Control Register */
21 #define XTTCPS_CLK_CNTRL_OFFSET     0x00000000U
22 /* Counter Control Register*/
23 #define XTTCPS_CNT_CNTRL_OFFSET     0x0000000CU
24 /* Current Counter Value */
25 #define XTTCPS_COUNT_VALUE_OFFSET   0x00000018U
26 /* Interval Count Value */
27 #define XTTCPS_INTERVAL_VAL_OFFSET  0x00000024U
28 /* Match 1 value */
29 #define XTTCPS_MATCH_0_OFFSET       0x00000030U
30 /* Match 2 value */
31 #define XTTCPS_MATCH_1_OFFSET       0x0000003CU
32 /* Match 3 value */
33 #define XTTCPS_MATCH_2_OFFSET       0x00000048U
34 /* Interrupt Status Register */
35 #define XTTCPS_ISR_OFFSET           0x00000054U
36 /* Interrupt Enable Register */
37 #define XTTCPS_IER_OFFSET           0x00000060U
38 
39 /*
40  * Clock Control Register Definitions
41  */
42 
43 /* Prescale enable */
44 #define XTTCPS_CLK_CNTRL_PS_EN_MASK     0x00000001U
45 /* Prescale value */
46 #define XTTCPS_CLK_CNTRL_PS_VAL_MASK    0x0000001EU
47 /* Prescale shift */
48 #define XTTCPS_CLK_CNTRL_PS_VAL_SHIFT   1U
49 /* Prescale disable */
50 #define XTTCPS_CLK_CNTRL_PS_DISABLE     16U
51 /* Clock source */
52 #define XTTCPS_CLK_CNTRL_SRC_MASK       0x00000020U
53 /* External Clock edge */
54 #define XTTCPS_CLK_CNTRL_EXT_EDGE_MASK  0x00000040U
55 
56 /*
57  * Counter Control Register Definitions
58  */
59 
60 /* Disable the counter */
61 #define XTTCPS_CNT_CNTRL_DIS_MASK       0x00000001U
62 /* Interval mode */
63 #define XTTCPS_CNT_CNTRL_INT_MASK       0x00000002U
64 /* Decrement mode */
65 #define XTTCPS_CNT_CNTRL_DECR_MASK      0x00000004U
66 /* Match mode */
67 #define XTTCPS_CNT_CNTRL_MATCH_MASK     0x00000008U
68 /* Reset counter */
69 #define XTTCPS_CNT_CNTRL_RST_MASK       0x00000010U
70 /* Enable waveform */
71 #define XTTCPS_CNT_CNTRL_EN_WAVE_MASK   0x00000020U
72 /* Waveform polarity */
73 #define XTTCPS_CNT_CNTRL_POL_WAVE_MASK  0x00000040U
74 /* Reset value */
75 #define XTTCPS_CNT_CNTRL_RESET_VALUE    0x00000021U
76 
77 /*
78  * Interrupt Register Definitions
79  */
80 
81 /* Interval Interrupt */
82 #define XTTCPS_IXR_INTERVAL_MASK    0x00000001U
83 /* Match 1 Interrupt */
84 #define XTTCPS_IXR_MATCH_0_MASK     0x00000002U
85 /* Match 2 Interrupt */
86 #define XTTCPS_IXR_MATCH_1_MASK     0x00000004U
87 /* Match 3 Interrupt */
88 #define XTTCPS_IXR_MATCH_2_MASK     0x00000008U
89 /* Counter Overflow */
90 #define XTTCPS_IXR_CNT_OVR_MASK     0x00000010U
91 /* All valid Interrupts */
92 #define XTTCPS_IXR_ALL_MASK         0x0000001FU
93 
94 /*
95  * Constants
96  */
97 
98 /* Maximum value of interval counter */
99 #define XTTC_MAX_INTERVAL_COUNT 0xFFFFFFFFU
100 
101 #endif /* ZEPHYR_DRIVERS_TIMER_XLNX_PSTTC_TIMER_PRIV_H_ */
102