1 /*
2 * Copyright (c) 2020 Stephanos Ioannidis <root@stephanos.io>
3 * Copyright (c) 2018 Xilinx, Inc.
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8 #define DT_DRV_COMPAT xlnx_ttcps
9
10 #include <zephyr/arch/cpu.h>
11 #include <zephyr/init.h>
12 #include <zephyr/irq.h>
13 #include <zephyr/sys_clock.h>
14 #include <soc.h>
15 #include <zephyr/drivers/timer/system_timer.h>
16 #include "xlnx_psttc_timer_priv.h"
17
18 #define TIMER_INDEX CONFIG_XLNX_PSTTC_TIMER_INDEX
19
20 #define TIMER_IRQ DT_INST_IRQN(0)
21 #define TIMER_BASE_ADDR DT_INST_REG_ADDR(0)
22 #define TIMER_CLOCK_FREQUECY DT_INST_PROP(0, clock_frequency)
23
24 #define TICKS_PER_SEC CONFIG_SYS_CLOCK_TICKS_PER_SEC
25 #define CYCLES_PER_SEC TIMER_CLOCK_FREQUECY
26 #define CYCLES_PER_TICK (CYCLES_PER_SEC / TICKS_PER_SEC)
27
28 #if defined(CONFIG_TEST)
29 const int32_t z_sys_timer_irq_for_test = DT_IRQN(DT_INST(0, xlnx_ttcps));
30 #endif
31 /*
32 * CYCLES_NEXT_MIN must be large enough to ensure that the timer does not miss
33 * interrupts. This value was conservatively set using the trial and error
34 * method, and there is room for improvement.
35 */
36 #define CYCLES_NEXT_MIN (10000)
37 #define CYCLES_NEXT_MAX (XTTC_MAX_INTERVAL_COUNT)
38
39 BUILD_ASSERT(TIMER_CLOCK_FREQUECY ==
40 CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC,
41 "Configured system timer frequency does not match the TTC "
42 "clock frequency in the device tree");
43
44 BUILD_ASSERT(CYCLES_PER_SEC >= TICKS_PER_SEC,
45 "Timer clock frequency must be greater than the system tick "
46 "frequency");
47
48 BUILD_ASSERT((CYCLES_PER_SEC % TICKS_PER_SEC) == 0,
49 "Timer clock frequency is not divisible by the system tick "
50 "frequency");
51
52 #ifdef CONFIG_TICKLESS_KERNEL
53 static uint32_t last_cycles;
54 #endif
55
read_count(void)56 static uint32_t read_count(void)
57 {
58 /* Read current counter value */
59 return sys_read32(TIMER_BASE_ADDR + XTTCPS_COUNT_VALUE_OFFSET);
60 }
61
update_match(uint32_t cycles,uint32_t match)62 static void update_match(uint32_t cycles, uint32_t match)
63 {
64 uint32_t delta = match - cycles;
65
66 /* Ensure that the match value meets the minimum timing requirements */
67 if (delta < CYCLES_NEXT_MIN) {
68 match += CYCLES_NEXT_MIN - delta;
69 }
70
71 /* Write counter match value for interrupt generation */
72 sys_write32(match, TIMER_BASE_ADDR + XTTCPS_MATCH_0_OFFSET);
73 }
74
ttc_isr(const void * arg)75 static void ttc_isr(const void *arg)
76 {
77 uint32_t cycles;
78 uint32_t ticks;
79
80 ARG_UNUSED(arg);
81
82 /* Acknowledge interrupt */
83 sys_read32(TIMER_BASE_ADDR + XTTCPS_ISR_OFFSET);
84
85 /* Read counter value */
86 cycles = read_count();
87
88 #ifdef CONFIG_TICKLESS_KERNEL
89 /* Calculate the number of ticks since last announcement */
90 ticks = (cycles - last_cycles) / CYCLES_PER_TICK;
91
92 /* Update last cycles count */
93 last_cycles = cycles;
94 #else
95 /* Update counter match value for the next interrupt */
96 update_match(cycles, cycles + CYCLES_PER_TICK);
97
98 /* Advance tick count by 1 */
99 ticks = 1;
100 #endif
101
102 /* Announce to the kernel*/
103 sys_clock_announce(ticks);
104 }
105
sys_clock_set_timeout(int32_t ticks,bool idle)106 void sys_clock_set_timeout(int32_t ticks, bool idle)
107 {
108 #ifdef CONFIG_TICKLESS_KERNEL
109 uint32_t cycles;
110 uint32_t next_cycles;
111
112 /* Read counter value */
113 cycles = read_count();
114
115 /* Calculate timeout counter value */
116 if (ticks == K_TICKS_FOREVER) {
117 next_cycles = cycles + CYCLES_NEXT_MAX;
118 } else {
119 next_cycles = cycles + ((uint32_t)ticks * CYCLES_PER_TICK);
120 }
121
122 /* Set match value for the next interrupt */
123 update_match(cycles, next_cycles);
124 #endif
125 }
126
sys_clock_elapsed(void)127 uint32_t sys_clock_elapsed(void)
128 {
129 #ifdef CONFIG_TICKLESS_KERNEL
130 uint32_t cycles;
131
132 /* Read counter value */
133 cycles = read_count();
134
135 /* Return the number of ticks since last announcement */
136 return (cycles - last_cycles) / CYCLES_PER_TICK;
137 #else
138 /* Always return 0 for tickful operation */
139 return 0;
140 #endif
141 }
142
sys_clock_cycle_get_32(void)143 uint32_t sys_clock_cycle_get_32(void)
144 {
145 /* Return the current counter value */
146 return read_count();
147 }
148
sys_clock_driver_init(void)149 static int sys_clock_driver_init(void)
150 {
151 uint32_t reg_val;
152
153 /* Stop timer */
154 sys_write32(XTTCPS_CNT_CNTRL_DIS_MASK,
155 TIMER_BASE_ADDR + XTTCPS_CNT_CNTRL_OFFSET);
156
157 #ifdef CONFIG_TICKLESS_KERNEL
158 /* Initialise internal states */
159 last_cycles = 0;
160 #endif
161
162 /* Initialise timer registers */
163 sys_write32(XTTCPS_CNT_CNTRL_RESET_VALUE,
164 TIMER_BASE_ADDR + XTTCPS_CNT_CNTRL_OFFSET);
165 sys_write32(0, TIMER_BASE_ADDR + XTTCPS_CLK_CNTRL_OFFSET);
166 sys_write32(0, TIMER_BASE_ADDR + XTTCPS_INTERVAL_VAL_OFFSET);
167 sys_write32(0, TIMER_BASE_ADDR + XTTCPS_MATCH_0_OFFSET);
168 sys_write32(0, TIMER_BASE_ADDR + XTTCPS_MATCH_1_OFFSET);
169 sys_write32(0, TIMER_BASE_ADDR + XTTCPS_MATCH_2_OFFSET);
170 sys_write32(0, TIMER_BASE_ADDR + XTTCPS_IER_OFFSET);
171 sys_write32(XTTCPS_IXR_ALL_MASK, TIMER_BASE_ADDR + XTTCPS_ISR_OFFSET);
172
173 /* Reset counter value */
174 reg_val = sys_read32(TIMER_BASE_ADDR + XTTCPS_CNT_CNTRL_OFFSET);
175 reg_val |= XTTCPS_CNT_CNTRL_RST_MASK;
176 sys_write32(reg_val, TIMER_BASE_ADDR + XTTCPS_CNT_CNTRL_OFFSET);
177
178 /* Set match mode */
179 reg_val = sys_read32(TIMER_BASE_ADDR + XTTCPS_CNT_CNTRL_OFFSET);
180 reg_val |= XTTCPS_CNT_CNTRL_MATCH_MASK;
181 sys_write32(reg_val, TIMER_BASE_ADDR + XTTCPS_CNT_CNTRL_OFFSET);
182
183 /* Set initial timeout */
184 reg_val = IS_ENABLED(CONFIG_TICKLESS_KERNEL) ?
185 CYCLES_NEXT_MAX : CYCLES_PER_TICK;
186 sys_write32(reg_val, TIMER_BASE_ADDR + XTTCPS_MATCH_0_OFFSET);
187
188 /* Connect timer interrupt */
189 IRQ_CONNECT(TIMER_IRQ, 0, ttc_isr, 0, 0);
190 irq_enable(TIMER_IRQ);
191
192 /* Enable timer interrupt */
193 reg_val = sys_read32(TIMER_BASE_ADDR + XTTCPS_IER_OFFSET);
194 reg_val |= XTTCPS_IXR_MATCH_0_MASK;
195 sys_write32(reg_val, TIMER_BASE_ADDR + XTTCPS_IER_OFFSET);
196
197 /* Start timer */
198 reg_val = sys_read32(TIMER_BASE_ADDR + XTTCPS_CNT_CNTRL_OFFSET);
199 reg_val &= (~XTTCPS_CNT_CNTRL_DIS_MASK);
200 sys_write32(reg_val, TIMER_BASE_ADDR + XTTCPS_CNT_CNTRL_OFFSET);
201
202 return 0;
203 }
204
205 SYS_INIT(sys_clock_driver_init, PRE_KERNEL_2,
206 CONFIG_SYSTEM_CLOCK_INIT_PRIORITY);
207
