1 /*
2 * Copyright (c) 2019 Centaur Analytics, Inc
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT st_stm32_window_watchdog
8
9 #include <zephyr/drivers/watchdog.h>
10 #include <soc.h>
11 #include <stm32_ll_bus.h>
12 #include <stm32_ll_wwdg.h>
13 #include <stm32_ll_system.h>
14 #include <errno.h>
15 #include <zephyr/sys/__assert.h>
16 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
17 #include <zephyr/drivers/clock_control.h>
18 #include <zephyr/irq.h>
19 #include <zephyr/sys_clock.h>
20
21 #include "wdt_wwdg_stm32.h"
22
23 #define LOG_LEVEL CONFIG_WDT_LOG_LEVEL
24 #include <zephyr/logging/log.h>
25 LOG_MODULE_REGISTER(wdt_wwdg_stm32);
26
27 #define WWDG_INTERNAL_DIVIDER 4096U
28 #define WWDG_RESET_LIMIT WWDG_COUNTER_MIN
29 #define WWDG_COUNTER_MIN 0x40
30 #define WWDG_COUNTER_MAX 0x7f
31
32 #if defined WWDG_CFR_WDGTB_Pos
33 #define WWDG_PRESCALER_POS WWDG_CFR_WDGTB_Pos
34 #define WWDG_PRESCALER_MASK WWDG_CFR_WDGTB_Msk
35 #else
36 #error "WWDG CFR WDGTB position not defined for soc"
37 #endif
38
39 /*
40 * additionally to the internal divider, the clock is divided by a
41 * programmable prescaler.
42 */
43 #if defined(LL_WWDG_PRESCALER_128)
44 #define WWDG_PRESCALER_EXPONENT_MAX 7 /* 2^7 = 128 */
45 #elif defined(LL_WWDG_PRESCALER_8)
46 #define WWDG_PRESCALER_EXPONENT_MAX 3 /* 2^3 = 8 */
47 #endif
48
49 /* The timeout of the WWDG in milliseconds is calculated by the below formula:
50 *
51 * t_WWDG = 1000 * ((counter & 0x3F) + 1) / f_WWDG (ms)
52 *
53 * where:
54 * - t_WWDG: WWDG timeout
55 * - counter: a value in [0x40, 0x7F] representing the cycles before timeout.
56 * Giving the counter a value below 0x40, will result in an
57 * immediate system reset. A reset is produced when the counter
58 * rolls over from 0x40 to 0x3F.
59 * - f_WWDG: the frequency of the WWDG clock. This can be calculated by the
60 * below formula:
61 * f_WWDG = f_PCLK / (4096 * prescaler) (Hz)
62 * where:
63 * - f_PCLK: the clock frequency of the system
64 * - 4096: the constant internal divider
65 * - prescaler: the programmable divider with valid values of 1, 2, 4 or 8,
66 * and for some series additionally 16, 32, 64 and 128
67 *
68 * The minimum timeout is calculated with:
69 * - counter = 0x40
70 * - prescaler = 1
71 * The maximum timeout is calculated with:
72 * - counter = 0x7F
73 * - prescaler = 8
74 *
75 * E.g. for f_PCLK = 2MHz
76 * t_WWDG_min = 1000 * ((0x40 & 0x3F) + 1) / (2000000 / (4096 * 1))
77 * = 2.048 ms
78 * t_WWDG_max = 1000 * ((0x7F & 0x3F) + 1) / (2000000 / (4096 * 8))
79 * = 1048.576 ms
80 */
81
82 #define ABS_DIFF_UINT(a, b) ((a) > (b) ? (a) - (b) : (b) - (a))
83 #define WWDG_TIMEOUT_ERROR_MARGIN(__TIMEOUT__) (__TIMEOUT__ / 10)
84 #define IS_WWDG_TIMEOUT(__TIMEOUT_GOLDEN__, __TIMEOUT__) \
85 (__TIMEOUT__ - __TIMEOUT_GOLDEN__) < \
86 WWDG_TIMEOUT_ERROR_MARGIN(__TIMEOUT_GOLDEN__)
87
88 static void wwdg_stm32_irq_config(const struct device *dev);
89
wwdg_stm32_get_pclk(const struct device * dev)90 static uint32_t wwdg_stm32_get_pclk(const struct device *dev)
91 {
92 const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
93 const struct wwdg_stm32_config *cfg = WWDG_STM32_CFG(dev);
94 uint32_t pclk_rate;
95
96 if (clock_control_get_rate(clk, (clock_control_subsys_t) &cfg->pclken,
97 &pclk_rate) < 0) {
98 LOG_ERR("Failed call clock_control_get_rate");
99 return -EIO;
100 }
101
102 return pclk_rate;
103 }
104
105 /**
106 * @brief Calculates the timeout in microseconds.
107 *
108 * @param dev Pointer to device structure.
109 * @param prescaler_exp The prescaler exponent value(Base 2).
110 * @param counter The counter value.
111 * @return The timeout calculated in microseconds.
112 */
wwdg_stm32_get_timeout(const struct device * dev,uint32_t prescaler_exp,uint32_t counter)113 static uint32_t wwdg_stm32_get_timeout(const struct device *dev,
114 uint32_t prescaler_exp,
115 uint32_t counter)
116 {
117 uint32_t divider = WWDG_INTERNAL_DIVIDER * (1 << prescaler_exp);
118 float f_wwdg = (float)wwdg_stm32_get_pclk(dev) / divider;
119
120 return USEC_PER_SEC * (((counter & 0x3F) + 1) / f_wwdg);
121 }
122
123 /**
124 * @brief Calculates prescaler & counter values.
125 *
126 * @param dev Pointer to device structure.
127 * @param timeout Timeout value in microseconds.
128 * @param prescaler_exp Pointer to prescaler exponent value(Base 2).
129 * @param counter Pointer to counter value.
130 */
wwdg_stm32_convert_timeout(const struct device * dev,uint32_t timeout,uint32_t * prescaler_exp,uint32_t * counter)131 static void wwdg_stm32_convert_timeout(const struct device *dev,
132 uint32_t timeout,
133 uint32_t *prescaler_exp,
134 uint32_t *counter)
135 {
136 uint32_t clock_freq = wwdg_stm32_get_pclk(dev);
137
138 /* Convert timeout to seconds. */
139 float timeout_s = (float)timeout / USEC_PER_SEC;
140 float wwdg_freq;
141
142 *prescaler_exp = 0U;
143 *counter = 0;
144
145 for (*prescaler_exp = 0; *prescaler_exp <= WWDG_PRESCALER_EXPONENT_MAX;
146 (*prescaler_exp)++) {
147 wwdg_freq = ((float)clock_freq) / WWDG_INTERNAL_DIVIDER
148 / (1 << *prescaler_exp);
149 /* +1 to ceil the result, which may lose from truncation */
150 *counter = (uint32_t)(timeout_s * wwdg_freq + 1) - 1;
151 *counter += WWDG_RESET_LIMIT;
152
153 if (*counter <= WWDG_COUNTER_MAX) {
154 return;
155 }
156 }
157
158 /* timeout longer than wwdg can provide, set to max possible value */
159 *counter = WWDG_COUNTER_MAX;
160 *prescaler_exp = WWDG_PRESCALER_EXPONENT_MAX;
161 }
162
wwdg_stm32_setup(const struct device * dev,uint8_t options)163 static int wwdg_stm32_setup(const struct device *dev, uint8_t options)
164 {
165 WWDG_TypeDef *wwdg = WWDG_STM32_STRUCT(dev);
166
167 /* Deactivate running when debugger is attached. */
168 if (options & WDT_OPT_PAUSE_HALTED_BY_DBG) {
169 #if defined(CONFIG_SOC_SERIES_STM32F0X)
170 LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_DBGMCU);
171 #elif defined(CONFIG_SOC_SERIES_STM32L0X)
172 LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_DBGMCU);
173 #elif defined(CONFIG_SOC_SERIES_STM32C0X) || defined(CONFIG_SOC_SERIES_STM32G0X)
174 LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_DBGMCU);
175 #endif
176 #if defined(CONFIG_SOC_SERIES_STM32H7X)
177 LL_DBGMCU_APB3_GRP1_FreezePeriph(LL_DBGMCU_APB3_GRP1_WWDG1_STOP);
178 #elif defined(CONFIG_SOC_SERIES_STM32MP1X)
179 LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_WWDG1_STOP);
180 #else
181 LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_WWDG_STOP);
182 #endif /* CONFIG_SOC_SERIES_STM32H7X */
183 }
184
185 if (options & WDT_OPT_PAUSE_IN_SLEEP) {
186 return -ENOTSUP;
187 }
188
189 /* Ensure that Early Wakeup Interrupt Flag is cleared */
190 LL_WWDG_ClearFlag_EWKUP(wwdg);
191
192 /* Enable the WWDG */
193 LL_WWDG_Enable(wwdg);
194
195 return 0;
196 }
197
wwdg_stm32_disable(const struct device * dev)198 static int wwdg_stm32_disable(const struct device *dev)
199 {
200 /* watchdog cannot be stopped once started unless SOC gets a reset */
201 ARG_UNUSED(dev);
202
203 return -EPERM;
204 }
205
wwdg_stm32_install_timeout(const struct device * dev,const struct wdt_timeout_cfg * config)206 static int wwdg_stm32_install_timeout(const struct device *dev,
207 const struct wdt_timeout_cfg *config)
208 {
209 struct wwdg_stm32_data *data = WWDG_STM32_DATA(dev);
210 WWDG_TypeDef *wwdg = WWDG_STM32_STRUCT(dev);
211 uint32_t timeout = config->window.max * USEC_PER_MSEC;
212 uint32_t calculated_timeout;
213 uint32_t prescaler_exp = 0U;
214 uint32_t counter = 0U;
215
216 if (config->callback != NULL) {
217 data->callback = config->callback;
218 }
219
220 wwdg_stm32_convert_timeout(dev, timeout, &prescaler_exp, &counter);
221 calculated_timeout = wwdg_stm32_get_timeout(dev, prescaler_exp, counter);
222
223 LOG_DBG("prescaler: %d", (1 << prescaler_exp));
224 LOG_DBG("Desired WDT: %d us", timeout);
225 LOG_DBG("Set WDT: %d us", calculated_timeout);
226
227 if (!(IS_WWDG_COUNTER(counter) &&
228 IS_WWDG_TIMEOUT(timeout, calculated_timeout))) {
229 /* One of the parameters provided is invalid */
230 return -EINVAL;
231 }
232
233 data->counter = counter;
234
235 /* Configure WWDG */
236 /* Set the programmable prescaler */
237 LL_WWDG_SetPrescaler(wwdg,
238 (prescaler_exp << WWDG_PRESCALER_POS) & WWDG_PRESCALER_MASK);
239
240 /* Set window the same as the counter to be able to feed the WWDG almost
241 * immediately
242 */
243 LL_WWDG_SetWindow(wwdg, counter);
244 LL_WWDG_SetCounter(wwdg, counter);
245
246 return 0;
247 }
248
wwdg_stm32_feed(const struct device * dev,int channel_id)249 static int wwdg_stm32_feed(const struct device *dev, int channel_id)
250 {
251 WWDG_TypeDef *wwdg = WWDG_STM32_STRUCT(dev);
252 struct wwdg_stm32_data *data = WWDG_STM32_DATA(dev);
253
254 ARG_UNUSED(channel_id);
255 LL_WWDG_SetCounter(wwdg, data->counter);
256
257 return 0;
258 }
259
wwdg_stm32_isr(const struct device * dev)260 void wwdg_stm32_isr(const struct device *dev)
261 {
262 struct wwdg_stm32_data *data = WWDG_STM32_DATA(dev);
263 WWDG_TypeDef *wwdg = WWDG_STM32_STRUCT(dev);
264
265 if (LL_WWDG_IsEnabledIT_EWKUP(wwdg)) {
266 if (LL_WWDG_IsActiveFlag_EWKUP(wwdg)) {
267 LL_WWDG_ClearFlag_EWKUP(wwdg);
268 data->callback(dev, 0);
269 }
270 }
271 }
272
273 static DEVICE_API(wdt, wwdg_stm32_api) = {
274 .setup = wwdg_stm32_setup,
275 .disable = wwdg_stm32_disable,
276 .install_timeout = wwdg_stm32_install_timeout,
277 .feed = wwdg_stm32_feed,
278 };
279
wwdg_stm32_init(const struct device * dev)280 static int wwdg_stm32_init(const struct device *dev)
281 {
282 const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
283 const struct wwdg_stm32_config *cfg = WWDG_STM32_CFG(dev);
284
285 if (!device_is_ready(clk)) {
286 LOG_ERR("clock control device not ready");
287 return -ENODEV;
288 }
289
290 if (clock_control_on(clk, (clock_control_subsys_t)&cfg->pclken) != 0) {
291 LOG_ERR("clock control on failed");
292 return -EIO;
293 }
294
295 /* Enable IRQ, especially EWKUP, once the peripheral is clocked */
296 wwdg_stm32_irq_config(dev);
297
298 return 0;
299 }
300
301 static struct wwdg_stm32_data wwdg_stm32_dev_data = {
302 .counter = WWDG_RESET_LIMIT,
303 .callback = NULL
304 };
305
306 static struct wwdg_stm32_config wwdg_stm32_dev_config = {
307 .pclken = {
308 .enr = DT_INST_CLOCKS_CELL(0, bits),
309 .bus = DT_INST_CLOCKS_CELL(0, bus)
310 },
311 .Instance = (WWDG_TypeDef *)DT_INST_REG_ADDR(0),
312 };
313
314 DEVICE_DT_INST_DEFINE(0, wwdg_stm32_init, NULL,
315 &wwdg_stm32_dev_data, &wwdg_stm32_dev_config,
316 POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
317 &wwdg_stm32_api);
318
wwdg_stm32_irq_config(const struct device * dev)319 static void wwdg_stm32_irq_config(const struct device *dev)
320 {
321 WWDG_TypeDef *wwdg = WWDG_STM32_STRUCT(dev);
322
323 IRQ_CONNECT(DT_INST_IRQN(0),
324 DT_INST_IRQ(0, priority),
325 wwdg_stm32_isr, DEVICE_DT_INST_GET(0), 0);
326 irq_enable(DT_INST_IRQN(0));
327
328 LL_WWDG_ClearFlag_EWKUP(wwdg);
329 LL_WWDG_EnableIT_EWKUP(wwdg);
330 }
331
