1/*
2 * Copyright (c) 2024 Michael Hope
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <freq.h>
8#include <mem.h>
9#include <zephyr/dt-bindings/gpio/gpio.h>
10#include <zephyr/dt-bindings/i2c/i2c.h>
11#include <zephyr/dt-bindings/clock/ch32v00x-clocks.h>
12
13/ {
14	#address-cells = <1>;
15	#size-cells = <1>;
16
17	cpus {
18		#address-cells = <1>;
19		#size-cells = <0>;
20
21		cpu0: cpu@0 {
22			device_type = "cpu";
23			compatible = "wch,qingke-v2";
24			reg = <0>;
25			clock-frequency = <DT_FREQ_M(48)>;
26		};
27	};
28
29	clocks {
30		clk_hse: clk-hse {
31			#clock-cells = <0>;
32			compatible = "wch,ch32v00x-hse-clock";
33			status = "disabled";
34		};
35
36		clk_hsi: clk-hsi {
37			#clock-cells = <0>;
38			compatible = "wch,ch32v00x-hsi-clock";
39			clock-frequency = <DT_FREQ_M(24)>;
40			status = "disabled";
41		};
42
43		clk_lsi: clk-lsi {
44			#clock-cells = <0>;
45			compatible = "fixed-clock";
46			clock-frequency = <DT_FREQ_K(128)>;
47			status = "disabled";
48		};
49
50		pll: pll {
51			#clock-cells = <0>;
52			compatible = "wch,ch32v00x-pll-clock";
53			status = "disabled";
54		};
55	};
56
57	soc {
58		#address-cells = <1>;
59		#size-cells = <1>;
60		compatible = "simple-bus";
61		ranges;
62
63		sram0: memory@20000000 {
64			compatible = "mmio-sram";
65			reg = <0x20000000 0x800>;
66		};
67
68		flash: flash-controller@40022000 {
69			compatible = "wch,ch32v00x-flash-controller";
70			reg = <0x40022000 0x400>;
71
72			#address-cells = <1>;
73			#size-cells = <1>;
74
75			flash0: flash@0 {
76				compatible = "soc-nv-flash";
77				reg = <0 0x4000>;
78			};
79		};
80
81		pfic: interrupt-controller@e000e000 {
82			compatible = "wch,pfic";
83			#address-cells = <0>;
84			#interrupt-cells = <1>;
85			interrupt-controller;
86			reg = <0xe000e000 16>;
87			status = "okay";
88		};
89
90		systick: systimer@e000f000 {
91			compatible = "wch,systick";
92			reg = <0xe000f000 16>;
93			status = "okay";
94			interrupt-parent = <&pfic>;
95			interrupts = <12>;
96		};
97
98		pwr: pwr@40007000 {
99			compatible = "wch,pwr";
100			reg = <0x40007000 16>;
101		};
102
103		pinctrl: pin-controller@40010000 {
104			compatible = "wch,afio";
105			reg = <0x40010000 16>;
106			#address-cells = <1>;
107			#size-cells = <1>;
108			status = "okay";
109
110			gpioa: gpio@40010800 {
111				compatible = "wch,gpio";
112				reg = <0x40010800 32>;
113				gpio-controller;
114				#gpio-cells = <2>;
115				ngpios = <8>;
116				clocks = <&rcc CH32V00X_CLOCK_IOPA>;
117			};
118
119			gpioc: gpio@40011000 {
120				compatible = "wch,gpio";
121				reg = <0x40011000 32>;
122				gpio-controller;
123				#gpio-cells = <2>;
124				ngpios = <8>;
125				clocks = <&rcc CH32V00X_CLOCK_IOPC>;
126			};
127
128			gpiod: gpio@40011400 {
129				compatible = "wch,gpio";
130				reg = <0x40011400 32>;
131				gpio-controller;
132				#gpio-cells = <2>;
133				ngpios = <8>;
134				clocks = <&rcc CH32V00X_CLOCK_IOPD>;
135			};
136		};
137
138		usart1: uart@40013800 {
139			compatible = "wch,usart";
140			reg = <0x40013800 16>;
141			clocks = <&rcc CH32V00X_CLOCK_USART1>;
142			interrupt-parent = <&pfic>;
143			interrupts = <32>;
144		};
145
146		rcc: rcc@40021000 {
147			compatible = "wch,rcc";
148			reg = <0x40021000 16>;
149			#clock-cells = <1>;
150			status = "okay";
151		};
152	};
153};
154