1 /*
2 * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
3 * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved.
4 * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #include <common/debug.h>
10 #include <common/interrupt_props.h>
11 #include <drivers/arm/gicv3.h>
12 #include <lib/utils.h>
13 #include <plat/common/platform.h>
14
15 #include <plat_private.h>
16 #include <platform_def.h>
17
18 /******************************************************************************
19 * The following functions are defined as weak to allow a platform to override
20 * the way the GICv3 driver is initialised and used.
21 *****************************************************************************/
22 #pragma weak plat_versal_net_gic_driver_init
23 #pragma weak plat_versal_net_gic_init
24 #pragma weak plat_versal_net_gic_cpuif_enable
25 #pragma weak plat_versal_net_gic_cpuif_disable
26 #pragma weak plat_versal_net_gic_pcpu_init
27 #pragma weak plat_versal_net_gic_redistif_on
28 #pragma weak plat_versal_net_gic_redistif_off
29
30 /* The GICv3 driver only needs to be initialized in EL3 */
31 static uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
32
33 static const interrupt_prop_t versal_net_interrupt_props[] = {
34 PLAT_VERSAL_NET_G1S_IRQ_PROPS(INTR_GROUP1S),
35 PLAT_VERSAL_NET_G0_IRQ_PROPS(INTR_GROUP0)
36 };
37
38 /*
39 * We save and restore the GICv3 context on system suspend. Allocate the
40 * data in the designated EL3 Secure carve-out memory.
41 */
42 static gicv3_redist_ctx_t rdist_ctx __section(".versal_net_el3_tzc_dram");
43 static gicv3_dist_ctx_t dist_ctx __section(".versal_net_el3_tzc_dram");
44
45 /*
46 * MPIDR hashing function for translating MPIDRs read from GICR_TYPER register
47 * to core position.
48 *
49 * Calculating core position is dependent on MPIDR_EL1.MT bit. However, affinity
50 * values read from GICR_TYPER don't have an MT field. To reuse the same
51 * translation used for CPUs, we insert MT bit read from the PE's MPIDR into
52 * that read from GICR_TYPER.
53 *
54 * Assumptions:
55 *
56 * - All CPUs implemented in the system have MPIDR_EL1.MT bit set;
57 * - No CPUs implemented in the system use affinity level 3.
58 */
versal_net_gicv3_mpidr_hash(u_register_t mpidr)59 static uint32_t versal_net_gicv3_mpidr_hash(u_register_t mpidr)
60 {
61 mpidr |= (read_mpidr_el1() & MPIDR_MT_MASK);
62 return plat_core_pos_by_mpidr(mpidr);
63 }
64
65 static const gicv3_driver_data_t versal_net_gic_data __unused = {
66 .gicd_base = PLAT_GICD_BASE_VALUE,
67 .gicr_base = PLAT_GICR_BASE_VALUE,
68 .interrupt_props = versal_net_interrupt_props,
69 .interrupt_props_num = ARRAY_SIZE(versal_net_interrupt_props),
70 .rdistif_num = PLATFORM_CORE_COUNT,
71 .rdistif_base_addrs = rdistif_base_addrs,
72 .mpidr_to_core_pos = versal_net_gicv3_mpidr_hash
73 };
74
plat_versal_net_gic_driver_init(void)75 void __init plat_versal_net_gic_driver_init(void)
76 {
77 /*
78 * The GICv3 driver is initialized in EL3 and does not need
79 * to be initialized again in SEL1. This is because the S-EL1
80 * can use GIC system registers to manage interrupts and does
81 * not need GIC interface base addresses to be configured.
82 */
83 #if IMAGE_BL31
84 gicv3_driver_init(&versal_net_gic_data);
85 #endif
86 }
87
88 /******************************************************************************
89 * Versal NET common helper to initialize the GIC. Only invoked by BL31
90 *****************************************************************************/
plat_versal_net_gic_init(void)91 void __init plat_versal_net_gic_init(void)
92 {
93 gicv3_distif_init();
94 gicv3_rdistif_init(plat_my_core_pos());
95 gicv3_cpuif_enable(plat_my_core_pos());
96 }
97
98 /******************************************************************************
99 * Versal NET common helper to enable the GIC CPU interface
100 *****************************************************************************/
plat_versal_net_gic_cpuif_enable(void)101 void plat_versal_net_gic_cpuif_enable(void)
102 {
103 gicv3_cpuif_enable(plat_my_core_pos());
104 }
105
106 /******************************************************************************
107 * Versal NET common helper to disable the GIC CPU interface
108 *****************************************************************************/
plat_versal_net_gic_cpuif_disable(void)109 void plat_versal_net_gic_cpuif_disable(void)
110 {
111 gicv3_cpuif_disable(plat_my_core_pos());
112 }
113
114 /******************************************************************************
115 * Versal NET common helper to initialize the per-cpu redistributor interface in
116 * GICv3
117 *****************************************************************************/
plat_versal_net_gic_pcpu_init(void)118 void plat_versal_net_gic_pcpu_init(void)
119 {
120 gicv3_rdistif_init(plat_my_core_pos());
121 }
122
123 /******************************************************************************
124 * Versal NET common helpers to power GIC redistributor interface
125 *****************************************************************************/
plat_versal_net_gic_redistif_on(void)126 void plat_versal_net_gic_redistif_on(void)
127 {
128 gicv3_rdistif_on(plat_my_core_pos());
129 }
130
plat_versal_net_gic_redistif_off(void)131 void plat_versal_net_gic_redistif_off(void)
132 {
133 gicv3_rdistif_off(plat_my_core_pos());
134 }
135
136 /******************************************************************************
137 * Versal NET common helper to save & restore the GICv3 on resume from system
138 * suspend
139 *****************************************************************************/
plat_versal_net_gic_save(void)140 void plat_versal_net_gic_save(void)
141 {
142 /*
143 * If an ITS is available, save its context before
144 * the Redistributor using:
145 * gicv3_its_save_disable(gits_base, &its_ctx[i])
146 * Additionnaly, an implementation-defined sequence may
147 * be required to save the whole ITS state.
148 */
149
150 /*
151 * Save the GIC Redistributors and ITS contexts before the
152 * Distributor context. As we only handle SYSTEM SUSPEND API,
153 * we only need to save the context of the CPU that is issuing
154 * the SYSTEM SUSPEND call, i.e. the current CPU.
155 */
156 gicv3_rdistif_save(plat_my_core_pos(), &rdist_ctx);
157
158 /* Save the GIC Distributor context */
159 gicv3_distif_save(&dist_ctx);
160
161 /*
162 * From here, all the components of the GIC can be safely powered down
163 * as long as there is an alternate way to handle wakeup interrupt
164 * sources.
165 */
166 }
167
plat_versal_net_gic_resume(void)168 void plat_versal_net_gic_resume(void)
169 {
170 /* Restore the GIC Distributor context */
171 gicv3_distif_init_restore(&dist_ctx);
172
173 /*
174 * Restore the GIC Redistributor and ITS contexts after the
175 * Distributor context. As we only handle SYSTEM SUSPEND API,
176 * we only need to restore the context of the CPU that issued
177 * the SYSTEM SUSPEND call.
178 */
179 gicv3_rdistif_init_restore(plat_my_core_pos(), &rdist_ctx);
180
181 /*
182 * If an ITS is available, restore its context after
183 * the Redistributor using:
184 * gicv3_its_restore(gits_base, &its_ctx[i])
185 * An implementation-defined sequence may be required to
186 * restore the whole ITS state. The ITS must also be
187 * re-enabled after this sequence has been executed.
188 */
189 }
190
