1 /* 2 * Copyright (c) 2015 Intel Corporation. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_INCLUDE_ARCH_ARC_V2_SYS_IO_H_ 8 #define ZEPHYR_INCLUDE_ARCH_ARC_V2_SYS_IO_H_ 9 10 #ifndef _ASMLANGUAGE 11 12 #include <zephyr/toolchain.h> 13 #include <zephyr/sys/sys_io.h> 14 #include <zephyr/arch/arc/v2/aux_regs.h> 15 16 #include <zephyr/types.h> 17 #include <stddef.h> 18 19 #ifdef __cplusplus 20 extern "C" { 21 #endif 22 23 /* Implementation of sys_io.h's documented functions */ 24 25 static ALWAYS_INLINE sys_out8(uint8_t data,io_port_t port)26 void sys_out8(uint8_t data, io_port_t port) 27 { 28 z_arc_v2_aux_reg_write(port, data); 29 } 30 31 static ALWAYS_INLINE sys_in8(io_port_t port)32 uint8_t sys_in8(io_port_t port) 33 { 34 return (uint8_t)(z_arc_v2_aux_reg_read(port) & 0x000000ff); 35 } 36 37 static ALWAYS_INLINE sys_out16(uint16_t data,io_port_t port)38 void sys_out16(uint16_t data, io_port_t port) 39 { 40 z_arc_v2_aux_reg_write(port, data); 41 } 42 43 static ALWAYS_INLINE sys_in16(io_port_t port)44 uint16_t sys_in16(io_port_t port) 45 { 46 return (uint16_t)(z_arc_v2_aux_reg_read(port) & 0x0000ffff); 47 } 48 49 static ALWAYS_INLINE sys_out32(uint32_t data,io_port_t port)50 void sys_out32(uint32_t data, io_port_t port) 51 { 52 z_arc_v2_aux_reg_write(port, data); 53 } 54 55 static ALWAYS_INLINE sys_in32(io_port_t port)56 uint32_t sys_in32(io_port_t port) 57 { 58 return z_arc_v2_aux_reg_read(port); 59 } 60 61 static ALWAYS_INLINE sys_io_set_bit(io_port_t port,unsigned int bit)62 void sys_io_set_bit(io_port_t port, unsigned int bit) 63 { 64 uint32_t reg = 0; 65 66 __asm__ volatile("lr %1, [%0]\n" 67 "bset %1, %1, %2\n" 68 "sr %1, [%0];\n\t" 69 : 70 : "ir" (port), 71 "r" (reg), "ir" (bit) 72 : "memory", "cc"); 73 } 74 75 static ALWAYS_INLINE sys_io_clear_bit(io_port_t port,unsigned int bit)76 void sys_io_clear_bit(io_port_t port, unsigned int bit) 77 { 78 uint32_t reg = 0; 79 80 __asm__ volatile("lr %1, [%0]\n" 81 "bclr %1, %1, %2\n" 82 "sr %1, [%0];\n\t" 83 : 84 : "ir" (port), 85 "r" (reg), "ir" (bit) 86 : "memory", "cc"); 87 } 88 89 static ALWAYS_INLINE sys_io_test_bit(io_port_t port,unsigned int bit)90 int sys_io_test_bit(io_port_t port, unsigned int bit) 91 { 92 uint32_t status = _ARC_V2_STATUS32; 93 uint32_t reg = 0; 94 uint32_t ret; 95 96 __asm__ volatile("lr %2, [%1]\n" 97 "btst %2, %3\n" 98 "lr %0, [%4];\n\t" 99 : "=r" (ret) 100 : "ir" (port), 101 "r" (reg), "ir" (bit), "i" (status) 102 : "memory", "cc"); 103 104 return !(ret & _ARC_V2_STATUS32_Z); 105 } 106 107 static ALWAYS_INLINE sys_io_test_and_set_bit(io_port_t port,unsigned int bit)108 int sys_io_test_and_set_bit(io_port_t port, unsigned int bit) 109 { 110 int ret; 111 112 ret = sys_io_test_bit(port, bit); 113 sys_io_set_bit(port, bit); 114 115 return ret; 116 } 117 118 static ALWAYS_INLINE sys_io_test_and_clear_bit(io_port_t port,unsigned int bit)119 int sys_io_test_and_clear_bit(io_port_t port, unsigned int bit) 120 { 121 int ret; 122 123 ret = sys_io_test_bit(port, bit); 124 sys_io_clear_bit(port, bit); 125 126 return ret; 127 } 128 129 #ifdef __cplusplus 130 } 131 #endif 132 133 #endif /* _ASMLANGUAGE */ 134 135 #endif /* ZEPHYR_INCLUDE_ARCH_ARC_V2_SYS_IO_H_ */ 136
