1 /**************************************************************************//** 2 * @file uspi_reg.h 3 * @version V1.00 4 * @brief USPI register definition header file 5 * 6 * @copyright SPDX-License-Identifier: Apache-2.0 7 * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __USPI_REG_H__ 10 #define __USPI_REG_H__ 11 12 /** @addtogroup REGISTER Control Register 13 14 @{ 15 16 */ 17 18 /*---------------------- SPI Mode of USCI Controller -------------------------*/ 19 /** 20 @addtogroup USPI SPI Mode of USCI Controller(USPI) 21 Memory Mapped Structure for USPI Controller 22 @{ 23 */ 24 25 typedef struct 26 { 27 28 29 /** 30 * @var USPI_T::CTL 31 * Offset: 0x00 USCI Control Register 32 * --------------------------------------------------------------------------------------------------- 33 * |Bits |Field |Descriptions 34 * | :----: | :----: | :---- | 35 * |[2:0] |FUNMODE |Function Mode 36 * | | |This bit field selects the protocol for this USCI controller 37 * | | |Selecting a protocol that is not available or a reserved combination disables the USCI 38 * | | |When switching between two protocols, the USCI has to be disabled before selecting a new protocol 39 * | | |Simultaneously, the USCI will be reset when user write 000 to FUNMODE. 40 * | | |000 = The USCI is disabled. All protocol related state machines are set to idle state. 41 * | | |001 = The SPI protocol is selected. 42 * | | |010 = The UART protocol is selected. 43 * | | |100 = The I2C protocol is selected. 44 * | | |Note: Other bit combinations are reserved. 45 * @var USPI_T::INTEN 46 * Offset: 0x04 USCI Interrupt Enable Register 47 * --------------------------------------------------------------------------------------------------- 48 * |Bits |Field |Descriptions 49 * | :----: | :----: | :---- | 50 * |[1] |TXSTIEN |Transmit Start Interrupt Enable Bit 51 * | | |This bit enables the interrupt generation in case of a transmit start event. 52 * | | |0 = The transmit start interrupt is disabled. 53 * | | |1 = The transmit start interrupt is enabled. 54 * |[2] |TXENDIEN |Transmit End Interrupt Enable Bit 55 * | | |This bit enables the interrupt generation in case of a transmit finish event. 56 * | | |0 = The transmit finish interrupt is disabled. 57 * | | |1 = The transmit finish interrupt is enabled. 58 * |[3] |RXSTIEN |Receive Start Interrupt Enable Bit 59 * | | |This bit enables the interrupt generation in case of a receive start event. 60 * | | |0 = The receive start interrupt is disabled. 61 * | | |1 = The receive start interrupt is enabled. 62 * |[4] |RXENDIEN |Receive End Interrupt Enable Bit 63 * | | |This bit enables the interrupt generation in case of a receive finish event. 64 * | | |0 = The receive end interrupt is disabled. 65 * | | |1 = The receive end interrupt is enabled. 66 * @var USPI_T::BRGEN 67 * Offset: 0x08 USCI Baud Rate Generator Register 68 * --------------------------------------------------------------------------------------------------- 69 * |Bits |Field |Descriptions 70 * | :----: | :----: | :---- | 71 * |[0] |RCLKSEL |Reference Clock Source Selection 72 * | | |This bit selects the source of reference clock (fREF_CLK). 73 * | | |0 = Peripheral device clock fPCLK. 74 * | | |1 = Reserved. 75 * |[1] |PTCLKSEL |Protocol Clock Source Selection 76 * | | |This bit selects the source of protocol clock (fPROT_CLK). 77 * | | |0 = Reference clock fREF_CLK. 78 * | | |1 = fREF_CLK2 (its frequency is half of fREF_CLK). 79 * |[3:2] |SPCLKSEL |Sample Clock Source Selection 80 * | | |This bit field used for the clock source selection of sample clock (fSAMP_CLK) for the protocol processor. 81 * | | |00 = fDIV_CLK. 82 * | | |01 = fPROT_CLK. 83 * | | |10 = fSCLK. 84 * | | |11 = fREF_CLK. 85 * |[4] |TMCNTEN |Time Measurement Counter Enable Bit 86 * | | |This bit enables the 10-bit timing measurement counter. 87 * | | |0 = Time measurement counter is Disabled. 88 * | | |1 = Time measurement counter is Enabled. 89 * |[5] |TMCNTSRC |Time Measurement Counter Clock Source Selection 90 * | | |0 = Time measurement counter with fPROT_CLK. 91 * | | |1 = Time measurement counter with fDIV_CLK. 92 * |[25:16] |CLKDIV |Clock Divider 93 * | | |This bit field defines the ratio between the protocol clock frequency fPROT_CLK and the clock divider frequency fDIV_CLK (fDIV_CLK = fPROT_CLK / (CLKDIV+1) ). 94 * | | |Note: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(USPI_PROTCTL[6])) is enabled 95 * | | |The revised value is the average bit time between bit 5 and bit 6 96 * | | |The user can use revised CLKDIV and new BRDETITV (USPI_PROTCTL[24:16]) to calculate the precise baud rate. 97 * @var USPI_T::DATIN0 98 * Offset: 0x10 USCI Input Data Signal Configuration Register 0 99 * --------------------------------------------------------------------------------------------------- 100 * |Bits |Field |Descriptions 101 * | :----: | :----: | :---- | 102 * |[0] |SYNCSEL |Input Signal Synchronization Selection 103 * | | |This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. 104 * | | |0 = The un-synchronized signal can be taken as input for the data shift unit. 105 * | | |1 = The synchronized signal can be taken as input for the data shift unit. 106 * | | |Note: In SPI protocol, it is suggested this bit should be set as 0. 107 * |[2] |ININV |Input Signal Inverse Selection 108 * | | |This bit defines the inverter enable of the input asynchronous signal. 109 * | | |0 = The un-synchronized input signal will not be inverted. 110 * | | |1 = The un-synchronized input signal will be inverted. 111 * | | |Note: In SPI protocol, it is suggested this bit should be set as 0. 112 * @var USPI_T::CTLIN0 113 * Offset: 0x20 USCI Input Control Signal Configuration Register 0 114 * --------------------------------------------------------------------------------------------------- 115 * |Bits |Field |Descriptions 116 * | :----: | :----: | :---- | 117 * |[0] |SYNCSEL |Input Synchronization Signal Selection 118 * | | |This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. 119 * | | |0 = The un-synchronized signal can be taken as input for the data shift unit. 120 * | | |1 = The synchronized signal can be taken as input for the data shift unit. 121 * | | |Note: In SPI protocol, it is suggested this bit should be set as 0. 122 * |[2] |ININV |Input Signal Inverse Selection 123 * | | |This bit defines the inverter enable of the input asynchronous signal. 124 * | | |0 = The un-synchronized input signal will not be inverted. 125 * | | |1 = The un-synchronized input signal will be inverted. 126 * @var USPI_T::CLKIN 127 * Offset: 0x28 USCI Input Clock Signal Configuration Register 128 * --------------------------------------------------------------------------------------------------- 129 * |Bits |Field |Descriptions 130 * | :----: | :----: | :---- | 131 * |[0] |SYNCSEL |Input Synchronization Signal Selection 132 * | | |This bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. 133 * | | |0 = The un-synchronized signal can be taken as input for the data shift unit. 134 * | | |1 = The synchronized signal can be taken as input for the data shift unit. 135 * | | |Note: In SPI protocol, it is suggested this bit should be set as 0. 136 * @var USPI_T::LINECTL 137 * Offset: 0x2C USCI Line Control Register 138 * --------------------------------------------------------------------------------------------------- 139 * |Bits |Field |Descriptions 140 * | :----: | :----: | :---- | 141 * |[0] |LSB |LSB First Transmission Selection 142 * | | |0 = The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first. 143 * | | |1 = The LSB, the bit 0 of data buffer, will be transmitted/received first. 144 * |[5] |DATOINV |Data Output Inverse Selection 145 * | | |This bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT0/1 pin. 146 * | | |0 = Data output level is not inverted. 147 * | | |1 = Data output level is inverted. 148 * |[7] |CTLOINV |Control Signal Output Inverse Selection 149 * | | |This bit defines the relation between the internal control signal and the output control signal. 150 * | | |0 = No effect. 151 * | | |1 = The control signal will be inverted before its output. 152 * | | |Note: The control signal has different definitions in different protocol 153 * | | |In SPI protocol, the control signal means slave select signal 154 * |[11:8] |DWIDTH |Word Length of Transmission 155 * | | |This bit field defines the data word length (amount of bits) for reception and transmission 156 * | | |The data word is always right-aligned in the data buffer 157 * | | |USCI support word length from 4 to 16 bits. 158 * | | |0x0: The data word contains 16 bits located at bit positions [15:0]. 159 * | | |0x1: Reserved. 160 * | | |0x2: Reserved. 161 * | | |0x3: Reserved. 162 * | | |0x4: The data word contains 4 bits located at bit positions [3:0]. 163 * | | |0x5: The data word contains 5 bits located at bit positions [4:0]. 164 * | | |... 165 * | | |0xF: The data word contains 15 bits located at bit positions [14:0]. 166 * @var USPI_T::TXDAT 167 * Offset: 0x30 USCI Transmit Data Register 168 * --------------------------------------------------------------------------------------------------- 169 * |Bits |Field |Descriptions 170 * | :----: | :----: | :---- | 171 * |[15:0] |TXDAT |Transmit Data 172 * | | |Software can use this bit field to write 16-bit transmit data for transmission 173 * | | |In order to avoid overwriting the transmit data, user have to check TXEMPTY (USPI_BUFSTS[8]) status before writing transmit data into this bit field. 174 * |[16] |PORTDIR |Port Direction Control 175 * | | |This bit field is only available while USCI operates in SPI protocol (FUNMODE = 0x1) with half-duplex transfer 176 * | | |It is used to define the direction of the data port pin 177 * | | |When software writes USPI_TXDAT register, the transmit data and its port direction are settled simultaneously. 178 * | | |0 = The data pin is configured as output mode. 179 * | | |1 = The data pin is configured as input mode. 180 * @var USPI_T::RXDAT 181 * Offset: 0x34 USCI Receive Data Register 182 * --------------------------------------------------------------------------------------------------- 183 * |Bits |Field |Descriptions 184 * | :----: | :----: | :---- | 185 * |[15:0] |RXDAT |Received Data 186 * | | |This bit field monitors the received data which stored in receive data buffer. 187 * @var USPI_T::BUFCTL 188 * Offset: 0x38 USCI Transmit/Receive Buffer Control Register 189 * --------------------------------------------------------------------------------------------------- 190 * |Bits |Field |Descriptions 191 * | :----: | :----: | :---- | 192 * |[6] |TXUDRIEN |Slave Transmit Under-run Interrupt Enable Bit 193 * | | |0 = Transmit under-run interrupt Disabled. 194 * | | |1 = Transmit under-run interrupt Enabled. 195 * |[7] |TXCLR |Clear Transmit Buffer 196 * | | |0 = No effect. 197 * | | |1 = The transmit buffer is cleared 198 * | | |Should only be used while the buffer is not taking part in data traffic. 199 * | | |Note: It is cleared automatically after one PCLK cycle. 200 * |[14] |RXOVIEN |Receive Buffer Overrun Interrupt Enable Bit 201 * | | |0 = Receive overrun interrupt Disabled. 202 * | | |1 = Receive overrun interrupt Enabled. 203 * |[15] |RXCLR |Clear Receive Buffer 204 * | | |0 = No effect. 205 * | | |1 = The receive buffer is cleared 206 * | | |Should only be used while the buffer is not taking part in data traffic. 207 * | | |Note: It is cleared automatically after one PCLK cycle. 208 * |[16] |TXRST |Transmit Reset 209 * | | |0 = No effect. 210 * | | |1 = Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer. 211 * | | |Note 1: It is cleared automatically after one PCLK cycle. 212 * | | |Note 2: Write 1 to this bit will set the output data pin to zero if USPI_PROTCTL[28]=0. 213 * |[17] |RXRST |Receive Reset 214 * | | |0 = No effect. 215 * | | |1 = Reset the receive-related counters, state machine, and the content of receive shift register and data buffer. 216 * | | |Note: It is cleared automatically after one PCLK cycle. 217 * @var USPI_T::BUFSTS 218 * Offset: 0x3C USCI Transmit/Receive Buffer Status Register 219 * --------------------------------------------------------------------------------------------------- 220 * |Bits |Field |Descriptions 221 * | :----: | :----: | :---- | 222 * |[0] |RXEMPTY |Receive Buffer Empty Indicator (Read Only) 223 * | | |0 = Receive buffer is not empty. 224 * | | |1 = Receive buffer is empty. 225 * |[1] |RXFULL |Receive Buffer Full Indicator (Read Only) 226 * | | |0 = Receive buffer is not full. 227 * | | |1 = Receive buffer is full. 228 * |[3] |RXOVIF |Receive Buffer Overrun Interrupt Status 229 * | | |This bit indicates that a receive buffer overrun event has been detected 230 * | | |If RXOVIEN (USPI_BUFCTL[14]) is enabled, the corresponding interrupt request is activated 231 * | | |It is cleared by software writes 1 to this bit. 232 * | | |0 = A receive buffer overrun event has not been detected. 233 * | | |1 = A receive buffer overrun event has been detected. 234 * |[8] |TXEMPTY |Transmit Buffer Empty Indicator (Read Only) 235 * | | |0 = Transmit buffer is not empty. 236 * | | |1 = Transmit buffer is empty and available for the next transmission datum. 237 * |[9] |TXFULL |Transmit Buffer Full Indicator (Read Only) 238 * | | |0 = Transmit buffer is not full. 239 * | | |1 = Transmit buffer is full. 240 * |[11] |TXUDRIF |Transmit Buffer Under-run Interrupt Status 241 * | | |This bit indicates that a transmit buffer under-run event has been detected 242 * | | |If enabled by TXUDRIEN (USPI_BUFCTL[6]), the corresponding interrupt request is activated 243 * | | |It is cleared by software writes 1 to this bit 244 * | | |0 = A transmit buffer under-run event has not been detected. 245 * | | |1 = A transmit buffer under-run event has been detected. 246 * @var USPI_T::PDMACTL 247 * Offset: 0x40 USCI PDMA Control Register 248 * --------------------------------------------------------------------------------------------------- 249 * |Bits |Field |Descriptions 250 * | :----: | :----: | :---- | 251 * |[0] |PDMARST |PDMA Reset 252 * | | |0 = No effect. 253 * | | |1 = Reset the USCI's PDMA control logic. This bit will be cleared to 0 automatically. 254 * |[1] |TXPDMAEN |PDMA Transmit Channel Available 255 * | | |0 = Transmit PDMA function Disabled. 256 * | | |1 = Transmit PDMA function Enabled. 257 * |[2] |RXPDMAEN |PDMA Receive Channel Available 258 * | | |0 = Receive PDMA function Disabled. 259 * | | |1 = Receive PDMA function Enabled. 260 * |[3] |PDMAEN |PDMA Mode Enable Bit 261 * | | |0 = PDMA function Disabled. 262 * | | |1 = PDMA function Enabled. 263 * | | |Note: The I2C is not supporting PDMA function. 264 * @var USPI_T::WKCTL 265 * Offset: 0x54 USCI Wake-up Control Register 266 * --------------------------------------------------------------------------------------------------- 267 * |Bits |Field |Descriptions 268 * | :----: | :----: | :---- | 269 * |[0] |WKEN |Wake-up Enable Bit 270 * | | |0 = Wake-up function Disabled. 271 * | | |1 = Wake-up function Enabled. 272 * |[1] |WKADDREN |Wake-up Address Match Enable Bit 273 * | | |0 = The chip is woken up according data toggle. 274 * | | |1 = The chip is woken up according address match. 275 * |[2] |PDBOPT |Power Down Blocking Option 276 * | | |0 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately. 277 * | | |1 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately. 278 * @var USPI_T::WKSTS 279 * Offset: 0x58 USCI Wake-up Status Register 280 * --------------------------------------------------------------------------------------------------- 281 * |Bits |Field |Descriptions 282 * | :----: | :----: | :---- | 283 * |[0] |WKF |Wake-up Flag 284 * | | |When chip is woken up from Power-down mode, this bit is set to 1 285 * | | |Software can write 1 to clear this bit. 286 * @var USPI_T::PROTCTL 287 * Offset: 0x5C USCI Protocol Control Register 288 * --------------------------------------------------------------------------------------------------- 289 * |Bits |Field |Descriptions 290 * | :----: | :----: | :---- | 291 * |[0] |SLAVE |Slave Mode Selection 292 * | | |0 = Master mode. 293 * | | |1 = Slave mode. 294 * |[1] |SLV3WIRE |Slave 3-wire Mode Selection (Slave Only) 295 * | | |The SPI protocol can work with 3-wire interface (without slave select signal) in Slave mode. 296 * | | |0 = 4-wire bi-direction interface. 297 * | | |1 = 3-wire bi-direction interface. 298 * |[2] |SS |Slave Select Control (Master Only) 299 * | | |If AUTOSS bit is cleared, setting this bit to 1 will set the slave select signal to active state, and setting this bit to 0 will set the slave select signal back to inactive state. 300 * | | |If the AUTOSS function is enabled (AUTOSS = 1), the setting value of this bit will not affect the current state of slave select signal. 301 * | | |Note: In SPI protocol, the internal slave select signal is active high. 302 * |[3] |AUTOSS |Automatic Slave Select Function Enable (Master Only) 303 * | | |0 = Slave select signal will be controlled by the setting value of SS (USPI_PROTCTL[2]) bit. 304 * | | |1 = Slave select signal will be generated automatically 305 * | | |The slave select signal will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished. 306 * |[7:6] |SCLKMODE |Serial Bus Clock Mode 307 * | | |This bit field defines the SCLK idle status, data transmit, and data receive edge. 308 * | | |00 = MODE0. The idle state of SPI clock is low level. 309 * | | |Data is transmitted with falling edge and received with rising edge. 310 * | | |01 = MODE1. The idle state of SPI clock is low level. 311 * | | |Data is transmitted with rising edge and received with falling edge. 312 * | | |10 = MODE2. The idle state of SPI clock is high level. 313 * | | |Data is transmitted with rising edge and received with falling edge. 314 * | | |11 = MODE3. The idle state of SPI clock is high level. 315 * | | |Data is transmitted with falling edge and received with rising edge. 316 * |[11:8] |SUSPITV |Suspend Interval (Master Only) 317 * | | |This bit field provides the configurable suspend interval between two successive transmit/receive transaction in a transfer 318 * | | |The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word 319 * | | |The default value is 0x3 320 * | | |The period of the suspend interval is obtained according to the following equation. 321 * | | |(SUSPITV[3:0] + 0.5) * period of SPI_CLK clock cycle 322 * | | |Example: 323 * | | |SUSPITV = 0x0 ... 0.5 SPI_CLK clock cycle. 324 * | | |SUSPITV = 0x1 ... 1.5 SPI_CLK clock cycle. 325 * | | |..... 326 * | | |SUSPITV = 0xE ... 14.5 SPI_CLK clock cycle. 327 * | | |SUSPITV = 0xF ... 15.5 SPI_CLK clock cycle. 328 * |[14:12] |TSMSEL |Transmit Data Mode Selection 329 * | | |This bit field describes how receive and transmit data is shifted in and out. 330 * | | |TSMSEL = 000b: Full-duplex SPI. 331 * | | |TSMSEL = 100b: Half-duplex SPI. 332 * | | |Others = Reserved. 333 * | | |Note: Changing the value of this bit field will produce the TXRST and RXRST to clear the TX/RX data buffer automatically. 334 * |[25:16] |SLVTOCNT |Slave Mode Time-out Period (Slave Only) 335 * | | |In Slave mode, this bit field is used for Slave time-out period 336 * | | |This bit field indicates how many clock periods (selected by TMCNTSRC, USPI_BRGEN[5]) between the two edges of input SCLK will assert the Slave time-out event 337 * | | |Writing 0x0 into this bit field will disable the Slave time-out function. 338 * | | |Example: Assume SLVTOCNT is 0x0A and TMCNTSRC (USPI_BRGEN[5]) is 1, it means the time-out event will occur if the state of SPI bus clock pin is not changed more than (10+1) periods of fDIV_CLK. 339 * |[28] |TXUDRPOL |Transmit Under-run Data Polarity (Slave Only) 340 * | | |This bit defines the transmitting data level when no data is available for transferring. 341 * | | |0 = The output data level is 0 if TX under-run event occurs. 342 * | | |1 = The output data level is 1 if TX under-run event occurs. 343 * |[31] |PROTEN |SPI Protocol Enable Bit 344 * | | |0 = SPI Protocol Disabled. 345 * | | |1 = SPI Protocol Enabled. 346 * @var USPI_T::PROTIEN 347 * Offset: 0x60 USCI Protocol Interrupt Enable Register 348 * --------------------------------------------------------------------------------------------------- 349 * |Bits |Field |Descriptions 350 * | :----: | :----: | :---- | 351 * |[0] |SSINAIEN |Slave Select Inactive Interrupt Enable Bit 352 * | | |This bit enables/disables the generation of a slave select interrupt if the slave select changes to inactive. 353 * | | |0 = Slave select inactive interrupt generation Disabled. 354 * | | |1 = Slave select inactive interrupt generation Enabled. 355 * |[1] |SSACTIEN |Slave Select Active Interrupt Enable Bit 356 * | | |This bit enables/disables the generation of a slave select interrupt if the slave select changes to active. 357 * | | |0 = Slave select active interrupt generation Disabled. 358 * | | |1 = Slave select active interrupt generation Enabled. 359 * |[2] |SLVTOIEN |Slave Time-out Interrupt Enable Bit 360 * | | |In SPI protocol, this bit enables the interrupt generation in case of a Slave time-out event. 361 * | | |0 = The Slave time-out interrupt Disabled. 362 * | | |1 = The Slave time-out interrupt Enabled. 363 * |[3] |SLVBEIEN |Slave Mode Bit Count Error Interrupt Enable Bit 364 * | | |If data transfer is terminated by slave time-out or slave select inactive event in Slave mode, so that the transmit/receive data bit count does not match the setting of DWIDTH (USPI_LINECTL[11:8]) 365 * | | |Bit count error event occurs. 366 * | | |0 = The Slave mode bit count error interrupt Disabled. 367 * | | |1 = The Slave mode bit count error interrupt Enabled. 368 * @var USPI_T::PROTSTS 369 * Offset: 0x64 USCI Protocol Status Register 370 * --------------------------------------------------------------------------------------------------- 371 * |Bits |Field |Descriptions 372 * | :----: | :----: | :---- | 373 * |[1] |TXSTIF |Transmit Start Interrupt Flag 374 * | | |0 = Transmit start event did not occur. 375 * | | |1 = Transmit start event occurred. 376 * | | |Note: It is cleared by software write 1 to this bit 377 * |[2] |TXENDIF |Transmit End Interrupt Flag 378 * | | |0 = Transmit end event did not occur. 379 * | | |1 = Transmit end event occurred. 380 * | | |Note: It is cleared by software write 1 to this bit 381 * |[3] |RXSTIF |Receive Start Interrupt Flag 382 * | | |0 = Receive start event did not occur. 383 * | | |1 = Receive start event occurred. 384 * | | |Note: It is cleared by software write 1 to this bit 385 * |[4] |RXENDIF |Receive End Interrupt Flag 386 * | | |0 = Receive end event did not occur. 387 * | | |1 = Receive end event occurred. 388 * | | |Note: It is cleared by software write 1 to this bit 389 * |[5] |SLVTOIF |Slave Time-out Interrupt Flag (Slave Only) 390 * | | |0 = Slave time-out event did not occur. 391 * | | |1 = Slave time-out event occurred. 392 * | | |Note: It is cleared by software write 1 to this bit 393 * |[6] |SLVBEIF |Slave Bit Count Error Interrupt Flag (Slave Only) 394 * | | |0 = Slave bit count error event did not occur. 395 * | | |1 = Slave bit count error event occurred. 396 * | | |Note: It is cleared by software write 1 to this bit. 397 * |[8] |SSINAIF |Slave Select Inactive Interrupt Flag (Slave Only) 398 * | | |This bit indicates that the internal slave select signal has changed to inactive 399 * | | |It is cleared by software writes 1 to this bit 400 * | | |0 = The slave select signal has not changed to inactive. 401 * | | |1 = The slave select signal has changed to inactive. 402 * | | |Note: The internal slave select signal is active high. 403 * |[9] |SSACTIF |Slave Select Active Interrupt Flag (Slave Only) 404 * | | |This bit indicates that the internal slave select signal has changed to active 405 * | | |It is cleared by software writes one to this bit 406 * | | |0 = The slave select signal has not changed to active. 407 * | | |1 = The slave select signal has changed to active. 408 * | | |Note: The internal slave select signal is active high. 409 * |[16] |SSLINE |Slave Select Line Bus Status (Read Only) 410 * | | |This bit is only available in Slave mode 411 * | | |It used to monitor the current status of the input slave select signal on the bus. 412 * | | |0 = The slave select line status is 0. 413 * | | |1 = The slave select line status is 1. 414 * |[17] |BUSY |Busy Status (Read Only) 415 * | | |0 = SPI is in idle state. 416 * | | |1 = SPI is in busy state. 417 * | | |The following listing are the bus busy conditions: 418 * | | |a. USPI_PROTCTL[31] = 1 and the TXEMPTY = 0. 419 * | | |b. For SPI Master mode, the TXEMPTY = 1 but the current transaction is not finished yet. 420 * | | |c. For SPI Slave mode, the USPI_PROTCTL[31] = 1 and there is serial clock input into the SPI core logic when slave select is active. 421 * | | |d. For SPI Slave mode, the USPI_PROTCTL[31] = 1 and the transmit buffer or transmit shift register is not empty even if the slave select is inactive. 422 * |[18] |SLVUDR |Slave Mode Transmit Under-run Status (Read Only) 423 * | | |In Slave mode, if there is no available transmit data in buffer while transmit data shift out caused by input serial bus clock, this status flag will be set to 1 424 * | | |This bit indicates whether the current shift-out data of word transmission is switched to TXUDRPOL (USPI_PROTCTL[28]) or not. 425 * | | |0 = Slave transmit under-run event did not occur. 426 * | | |1 = Slave transmit under-run event occurred. 427 */ 428 __IO uint32_t CTL; /*!< [0x0000] USCI Control Register */ 429 __IO uint32_t INTEN; /*!< [0x0004] USCI Interrupt Enable Register */ 430 __IO uint32_t BRGEN; /*!< [0x0008] USCI Baud Rate Generator Register */ 431 __I uint32_t RESERVE0[1]; 432 __IO uint32_t DATIN0; /*!< [0x0010] USCI Input Data Signal Configuration Register 0 */ 433 __I uint32_t RESERVE1[3]; 434 __IO uint32_t CTLIN0; /*!< [0x0020] USCI Input Control Signal Configuration Register 0 */ 435 __I uint32_t RESERVE2[1]; 436 __IO uint32_t CLKIN; /*!< [0x0028] USCI Input Clock Signal Configuration Register */ 437 __IO uint32_t LINECTL; /*!< [0x002c] USCI Line Control Register */ 438 __O uint32_t TXDAT; /*!< [0x0030] USCI Transmit Data Register */ 439 __I uint32_t RXDAT; /*!< [0x0034] USCI Receive Data Register */ 440 __IO uint32_t BUFCTL; /*!< [0x0038] USCI Transmit/Receive Buffer Control Register */ 441 __IO uint32_t BUFSTS; /*!< [0x003c] USCI Transmit/Receive Buffer Status Register */ 442 __IO uint32_t PDMACTL; /*!< [0x0040] USCI PDMA Control Register */ 443 __I uint32_t RESERVE3[4]; 444 __IO uint32_t WKCTL; /*!< [0x0054] USCI Wake-up Control Register */ 445 __IO uint32_t WKSTS; /*!< [0x0058] USCI Wake-up Status Register */ 446 __IO uint32_t PROTCTL; /*!< [0x005c] USCI Protocol Control Register */ 447 __IO uint32_t PROTIEN; /*!< [0x0060] USCI Protocol Interrupt Enable Register */ 448 __IO uint32_t PROTSTS; /*!< [0x0064] USCI Protocol Status Register */ 449 450 } USPI_T; 451 452 /** 453 @addtogroup USPI_CONST USPI Bit Field Definition 454 Constant Definitions for USPI Controller 455 @{ 456 */ 457 458 #define USPI_CTL_FUNMODE_Pos (0) /*!< USPI_T::CTL: FUNMODE Position */ 459 #define USPI_CTL_FUNMODE_Msk (0x7ul << USPI_CTL_FUNMODE_Pos) /*!< USPI_T::CTL: FUNMODE Mask */ 460 461 #define USPI_INTEN_TXSTIEN_Pos (1) /*!< USPI_T::INTEN: TXSTIEN Position */ 462 #define USPI_INTEN_TXSTIEN_Msk (0x1ul << USPI_INTEN_TXSTIEN_Pos) /*!< USPI_T::INTEN: TXSTIEN Mask */ 463 464 #define USPI_INTEN_TXENDIEN_Pos (2) /*!< USPI_T::INTEN: TXENDIEN Position */ 465 #define USPI_INTEN_TXENDIEN_Msk (0x1ul << USPI_INTEN_TXENDIEN_Pos) /*!< USPI_T::INTEN: TXENDIEN Mask */ 466 467 #define USPI_INTEN_RXSTIEN_Pos (3) /*!< USPI_T::INTEN: RXSTIEN Position */ 468 #define USPI_INTEN_RXSTIEN_Msk (0x1ul << USPI_INTEN_RXSTIEN_Pos) /*!< USPI_T::INTEN: RXSTIEN Mask */ 469 470 #define USPI_INTEN_RXENDIEN_Pos (4) /*!< USPI_T::INTEN: RXENDIEN Position */ 471 #define USPI_INTEN_RXENDIEN_Msk (0x1ul << USPI_INTEN_RXENDIEN_Pos) /*!< USPI_T::INTEN: RXENDIEN Mask */ 472 473 #define USPI_BRGEN_RCLKSEL_Pos (0) /*!< USPI_T::BRGEN: RCLKSEL Position */ 474 #define USPI_BRGEN_RCLKSEL_Msk (0x1ul << USPI_BRGEN_RCLKSEL_Pos) /*!< USPI_T::BRGEN: RCLKSEL Mask */ 475 476 #define USPI_BRGEN_PTCLKSEL_Pos (1) /*!< USPI_T::BRGEN: PTCLKSEL Position */ 477 #define USPI_BRGEN_PTCLKSEL_Msk (0x1ul << USPI_BRGEN_PTCLKSEL_Pos) /*!< USPI_T::BRGEN: PTCLKSEL Mask */ 478 479 #define USPI_BRGEN_SPCLKSEL_Pos (2) /*!< USPI_T::BRGEN: SPCLKSEL Position */ 480 #define USPI_BRGEN_SPCLKSEL_Msk (0x3ul << USPI_BRGEN_SPCLKSEL_Pos) /*!< USPI_T::BRGEN: SPCLKSEL Mask */ 481 482 #define USPI_BRGEN_TMCNTEN_Pos (4) /*!< USPI_T::BRGEN: TMCNTEN Position */ 483 #define USPI_BRGEN_TMCNTEN_Msk (0x1ul << USPI_BRGEN_TMCNTEN_Pos) /*!< USPI_T::BRGEN: TMCNTEN Mask */ 484 485 #define USPI_BRGEN_TMCNTSRC_Pos (5) /*!< USPI_T::BRGEN: TMCNTSRC Position */ 486 #define USPI_BRGEN_TMCNTSRC_Msk (0x1ul << USPI_BRGEN_TMCNTSRC_Pos) /*!< USPI_T::BRGEN: TMCNTSRC Mask */ 487 488 #define USPI_BRGEN_CLKDIV_Pos (16) /*!< USPI_T::BRGEN: CLKDIV Position */ 489 #define USPI_BRGEN_CLKDIV_Msk (0x3fful << USPI_BRGEN_CLKDIV_Pos) /*!< USPI_T::BRGEN: CLKDIV Mask */ 490 491 #define USPI_DATIN0_SYNCSEL_Pos (0) /*!< USPI_T::DATIN0: SYNCSEL Position */ 492 #define USPI_DATIN0_SYNCSEL_Msk (0x1ul << USPI_DATIN0_SYNCSEL_Pos) /*!< USPI_T::DATIN0: SYNCSEL Mask */ 493 494 #define USPI_DATIN0_ININV_Pos (2) /*!< USPI_T::DATIN0: ININV Position */ 495 #define USPI_DATIN0_ININV_Msk (0x1ul << USPI_DATIN0_ININV_Pos) /*!< USPI_T::DATIN0: ININV Mask */ 496 497 #define USPI_CTLIN0_SYNCSEL_Pos (0) /*!< USPI_T::CTLIN0: SYNCSEL Position */ 498 #define USPI_CTLIN0_SYNCSEL_Msk (0x1ul << USPI_CTLIN0_SYNCSEL_Pos) /*!< USPI_T::CTLIN0: SYNCSEL Mask */ 499 500 #define USPI_CTLIN0_ININV_Pos (2) /*!< USPI_T::CTLIN0: ININV Position */ 501 #define USPI_CTLIN0_ININV_Msk (0x1ul << USPI_CTLIN0_ININV_Pos) /*!< USPI_T::CTLIN0: ININV Mask */ 502 503 #define USPI_CLKIN_SYNCSEL_Pos (0) /*!< USPI_T::CLKIN: SYNCSEL Position */ 504 #define USPI_CLKIN_SYNCSEL_Msk (0x1ul << USPI_CLKIN_SYNCSEL_Pos) /*!< USPI_T::CLKIN: SYNCSEL Mask */ 505 506 #define USPI_LINECTL_LSB_Pos (0) /*!< USPI_T::LINECTL: LSB Position */ 507 #define USPI_LINECTL_LSB_Msk (0x1ul << USPI_LINECTL_LSB_Pos) /*!< USPI_T::LINECTL: LSB Mask */ 508 509 #define USPI_LINECTL_DATOINV_Pos (5) /*!< USPI_T::LINECTL: DATOINV Position */ 510 #define USPI_LINECTL_DATOINV_Msk (0x1ul << USPI_LINECTL_DATOINV_Pos) /*!< USPI_T::LINECTL: DATOINV Mask */ 511 512 #define USPI_LINECTL_CTLOINV_Pos (7) /*!< USPI_T::LINECTL: CTLOINV Position */ 513 #define USPI_LINECTL_CTLOINV_Msk (0x1ul << USPI_LINECTL_CTLOINV_Pos) /*!< USPI_T::LINECTL: CTLOINV Mask */ 514 515 #define USPI_LINECTL_DWIDTH_Pos (8) /*!< USPI_T::LINECTL: DWIDTH Position */ 516 #define USPI_LINECTL_DWIDTH_Msk (0xful << USPI_LINECTL_DWIDTH_Pos) /*!< USPI_T::LINECTL: DWIDTH Mask */ 517 518 #define USPI_TXDAT_TXDAT_Pos (0) /*!< USPI_T::TXDAT: TXDAT Position */ 519 #define USPI_TXDAT_TXDAT_Msk (0xfffful << USPI_TXDAT_TXDAT_Pos) /*!< USPI_T::TXDAT: TXDAT Mask */ 520 521 #define USPI_TXDAT_PORTDIR_Pos (16) /*!< USPI_T::TXDAT: PORTDIR Position */ 522 #define USPI_TXDAT_PORTDIR_Msk (0x1ul << USPI_TXDAT_PORTDIR_Pos) /*!< USPI_T::TXDAT: PORTDIR Mask */ 523 524 #define USPI_RXDAT_RXDAT_Pos (0) /*!< USPI_T::RXDAT: RXDAT Position */ 525 #define USPI_RXDAT_RXDAT_Msk (0xfffful << USPI_RXDAT_RXDAT_Pos) /*!< USPI_T::RXDAT: RXDAT Mask */ 526 527 #define USPI_BUFCTL_TXUDRIEN_Pos (6) /*!< USPI_T::BUFCTL: TXUDRIEN Position */ 528 #define USPI_BUFCTL_TXUDRIEN_Msk (0x1ul << USPI_BUFCTL_TXUDRIEN_Pos) /*!< USPI_T::BUFCTL: TXUDRIEN Mask */ 529 530 #define USPI_BUFCTL_TXCLR_Pos (7) /*!< USPI_T::BUFCTL: TXCLR Position */ 531 #define USPI_BUFCTL_TXCLR_Msk (0x1ul << USPI_BUFCTL_TXCLR_Pos) /*!< USPI_T::BUFCTL: TXCLR Mask */ 532 533 #define USPI_BUFCTL_RXOVIEN_Pos (14) /*!< USPI_T::BUFCTL: RXOVIEN Position */ 534 #define USPI_BUFCTL_RXOVIEN_Msk (0x1ul << USPI_BUFCTL_RXOVIEN_Pos) /*!< USPI_T::BUFCTL: RXOVIEN Mask */ 535 536 #define USPI_BUFCTL_RXCLR_Pos (15) /*!< USPI_T::BUFCTL: RXCLR Position */ 537 #define USPI_BUFCTL_RXCLR_Msk (0x1ul << USPI_BUFCTL_RXCLR_Pos) /*!< USPI_T::BUFCTL: RXCLR Mask */ 538 539 #define USPI_BUFCTL_TXRST_Pos (16) /*!< USPI_T::BUFCTL: TXRST Position */ 540 #define USPI_BUFCTL_TXRST_Msk (0x1ul << USPI_BUFCTL_TXRST_Pos) /*!< USPI_T::BUFCTL: TXRST Mask */ 541 542 #define USPI_BUFCTL_RXRST_Pos (17) /*!< USPI_T::BUFCTL: RXRST Position */ 543 #define USPI_BUFCTL_RXRST_Msk (0x1ul << USPI_BUFCTL_RXRST_Pos) /*!< USPI_T::BUFCTL: RXRST Mask */ 544 545 #define USPI_BUFSTS_RXEMPTY_Pos (0) /*!< USPI_T::BUFSTS: RXEMPTY Position */ 546 #define USPI_BUFSTS_RXEMPTY_Msk (0x1ul << USPI_BUFSTS_RXEMPTY_Pos) /*!< USPI_T::BUFSTS: RXEMPTY Mask */ 547 548 #define USPI_BUFSTS_RXFULL_Pos (1) /*!< USPI_T::BUFSTS: RXFULL Position */ 549 #define USPI_BUFSTS_RXFULL_Msk (0x1ul << USPI_BUFSTS_RXFULL_Pos) /*!< USPI_T::BUFSTS: RXFULL Mask */ 550 551 #define USPI_BUFSTS_RXOVIF_Pos (3) /*!< USPI_T::BUFSTS: RXOVIF Position */ 552 #define USPI_BUFSTS_RXOVIF_Msk (0x1ul << USPI_BUFSTS_RXOVIF_Pos) /*!< USPI_T::BUFSTS: RXOVIF Mask */ 553 554 #define USPI_BUFSTS_TXEMPTY_Pos (8) /*!< USPI_T::BUFSTS: TXEMPTY Position */ 555 #define USPI_BUFSTS_TXEMPTY_Msk (0x1ul << USPI_BUFSTS_TXEMPTY_Pos) /*!< USPI_T::BUFSTS: TXEMPTY Mask */ 556 557 #define USPI_BUFSTS_TXFULL_Pos (9) /*!< USPI_T::BUFSTS: TXFULL Position */ 558 #define USPI_BUFSTS_TXFULL_Msk (0x1ul << USPI_BUFSTS_TXFULL_Pos) /*!< USPI_T::BUFSTS: TXFULL Mask */ 559 560 #define USPI_BUFSTS_TXUDRIF_Pos (11) /*!< USPI_T::BUFSTS: TXUDRIF Position */ 561 #define USPI_BUFSTS_TXUDRIF_Msk (0x1ul << USPI_BUFSTS_TXUDRIF_Pos) /*!< USPI_T::BUFSTS: TXUDRIF Mask */ 562 563 #define USPI_PDMACTL_PDMARST_Pos (0) /*!< USPI_T::PDMACTL: PDMARST Position */ 564 #define USPI_PDMACTL_PDMARST_Msk (0x1ul << USPI_PDMACTL_PDMARST_Pos) /*!< USPI_T::PDMACTL: PDMARST Mask */ 565 566 #define USPI_PDMACTL_TXPDMAEN_Pos (1) /*!< USPI_T::PDMACTL: TXPDMAEN Position */ 567 #define USPI_PDMACTL_TXPDMAEN_Msk (0x1ul << USPI_PDMACTL_TXPDMAEN_Pos) /*!< USPI_T::PDMACTL: TXPDMAEN Mask */ 568 569 #define USPI_PDMACTL_RXPDMAEN_Pos (2) /*!< USPI_T::PDMACTL: RXPDMAEN Position */ 570 #define USPI_PDMACTL_RXPDMAEN_Msk (0x1ul << USPI_PDMACTL_RXPDMAEN_Pos) /*!< USPI_T::PDMACTL: RXPDMAEN Mask */ 571 572 #define USPI_PDMACTL_PDMAEN_Pos (3) /*!< USPI_T::PDMACTL: PDMAEN Position */ 573 #define USPI_PDMACTL_PDMAEN_Msk (0x1ul << USPI_PDMACTL_PDMAEN_Pos) /*!< USPI_T::PDMACTL: PDMAEN Mask */ 574 575 #define USPI_WKCTL_WKEN_Pos (0) /*!< USPI_T::WKCTL: WKEN Position */ 576 #define USPI_WKCTL_WKEN_Msk (0x1ul << USPI_WKCTL_WKEN_Pos) /*!< USPI_T::WKCTL: WKEN Mask */ 577 578 #define USPI_WKCTL_WKADDREN_Pos (1) /*!< USPI_T::WKCTL: WKADDREN Position */ 579 #define USPI_WKCTL_WKADDREN_Msk (0x1ul << USPI_WKCTL_WKADDREN_Pos) /*!< USPI_T::WKCTL: WKADDREN Mask */ 580 581 #define USPI_WKCTL_PDBOPT_Pos (2) /*!< USPI_T::WKCTL: PDBOPT Position */ 582 #define USPI_WKCTL_PDBOPT_Msk (0x1ul << USPI_WKCTL_PDBOPT_Pos) /*!< USPI_T::WKCTL: PDBOPT Mask */ 583 584 #define USPI_WKSTS_WKF_Pos (0) /*!< USPI_T::WKSTS: WKF Position */ 585 #define USPI_WKSTS_WKF_Msk (0x1ul << USPI_WKSTS_WKF_Pos) /*!< USPI_T::WKSTS: WKF Mask */ 586 587 #define USPI_PROTCTL_SLAVE_Pos (0) /*!< USPI_T::PROTCTL: SLAVE Position */ 588 #define USPI_PROTCTL_SLAVE_Msk (0x1ul << USPI_PROTCTL_SLAVE_Pos) /*!< USPI_T::PROTCTL: SLAVE Mask */ 589 590 #define USPI_PROTCTL_SLV3WIRE_Pos (1) /*!< USPI_T::PROTCTL: SLV3WIRE Position */ 591 #define USPI_PROTCTL_SLV3WIRE_Msk (0x1ul << USPI_PROTCTL_SLV3WIRE_Pos) /*!< USPI_T::PROTCTL: SLV3WIRE Mask */ 592 593 #define USPI_PROTCTL_SS_Pos (2) /*!< USPI_T::PROTCTL: SS Position */ 594 #define USPI_PROTCTL_SS_Msk (0x1ul << USPI_PROTCTL_SS_Pos) /*!< USPI_T::PROTCTL: SS Mask */ 595 596 #define USPI_PROTCTL_AUTOSS_Pos (3) /*!< USPI_T::PROTCTL: AUTOSS Position */ 597 #define USPI_PROTCTL_AUTOSS_Msk (0x1ul << USPI_PROTCTL_AUTOSS_Pos) /*!< USPI_T::PROTCTL: AUTOSS Mask */ 598 599 #define USPI_PROTCTL_SCLKMODE_Pos (6) /*!< USPI_T::PROTCTL: SCLKMODE Position */ 600 #define USPI_PROTCTL_SCLKMODE_Msk (0x3ul << USPI_PROTCTL_SCLKMODE_Pos) /*!< USPI_T::PROTCTL: SCLKMODE Mask */ 601 602 #define USPI_PROTCTL_SUSPITV_Pos (8) /*!< USPI_T::PROTCTL: SUSPITV Position */ 603 #define USPI_PROTCTL_SUSPITV_Msk (0xful << USPI_PROTCTL_SUSPITV_Pos) /*!< USPI_T::PROTCTL: SUSPITV Mask */ 604 605 #define USPI_PROTCTL_TSMSEL_Pos (12) /*!< USPI_T::PROTCTL: TSMSEL Position */ 606 #define USPI_PROTCTL_TSMSEL_Msk (0x7ul << USPI_PROTCTL_TSMSEL_Pos) /*!< USPI_T::PROTCTL: TSMSEL Mask */ 607 608 #define USPI_PROTCTL_SLVTOCNT_Pos (16) /*!< USPI_T::PROTCTL: SLVTOCNT Position */ 609 #define USPI_PROTCTL_SLVTOCNT_Msk (0x3fful << USPI_PROTCTL_SLVTOCNT_Pos) /*!< USPI_T::PROTCTL: SLVTOCNT Mask */ 610 611 #define USPI_PROTCTL_TXUDRPOL_Pos (28) /*!< USPI_T::PROTCTL: TXUDRPOL Position */ 612 #define USPI_PROTCTL_TXUDRPOL_Msk (0x1ul << USPI_PROTCTL_TXUDRPOL_Pos) /*!< USPI_T::PROTCTL: TXUDRPOL Mask */ 613 614 #define USPI_PROTCTL_PROTEN_Pos (31) /*!< USPI_T::PROTCTL: PROTEN Position */ 615 #define USPI_PROTCTL_PROTEN_Msk (0x1ul << USPI_PROTCTL_PROTEN_Pos) /*!< USPI_T::PROTCTL: PROTEN Mask */ 616 617 #define USPI_PROTIEN_SSINAIEN_Pos (0) /*!< USPI_T::PROTIEN: SSINAIEN Position */ 618 #define USPI_PROTIEN_SSINAIEN_Msk (0x1ul << USPI_PROTIEN_SSINAIEN_Pos) /*!< USPI_T::PROTIEN: SSINAIEN Mask */ 619 620 #define USPI_PROTIEN_SSACTIEN_Pos (1) /*!< USPI_T::PROTIEN: SSACTIEN Position */ 621 #define USPI_PROTIEN_SSACTIEN_Msk (0x1ul << USPI_PROTIEN_SSACTIEN_Pos) /*!< USPI_T::PROTIEN: SSACTIEN Mask */ 622 623 #define USPI_PROTIEN_SLVTOIEN_Pos (2) /*!< USPI_T::PROTIEN: SLVTOIEN Position */ 624 #define USPI_PROTIEN_SLVTOIEN_Msk (0x1ul << USPI_PROTIEN_SLVTOIEN_Pos) /*!< USPI_T::PROTIEN: SLVTOIEN Mask */ 625 626 #define USPI_PROTIEN_SLVBEIEN_Pos (3) /*!< USPI_T::PROTIEN: SLVBEIEN Position */ 627 #define USPI_PROTIEN_SLVBEIEN_Msk (0x1ul << USPI_PROTIEN_SLVBEIEN_Pos) /*!< USPI_T::PROTIEN: SLVBEIEN Mask */ 628 629 #define USPI_PROTSTS_TXSTIF_Pos (1) /*!< USPI_T::PROTSTS: TXSTIF Position */ 630 #define USPI_PROTSTS_TXSTIF_Msk (0x1ul << USPI_PROTSTS_TXSTIF_Pos) /*!< USPI_T::PROTSTS: TXSTIF Mask */ 631 632 #define USPI_PROTSTS_TXENDIF_Pos (2) /*!< USPI_T::PROTSTS: TXENDIF Position */ 633 #define USPI_PROTSTS_TXENDIF_Msk (0x1ul << USPI_PROTSTS_TXENDIF_Pos) /*!< USPI_T::PROTSTS: TXENDIF Mask */ 634 635 #define USPI_PROTSTS_RXSTIF_Pos (3) /*!< USPI_T::PROTSTS: RXSTIF Position */ 636 #define USPI_PROTSTS_RXSTIF_Msk (0x1ul << USPI_PROTSTS_RXSTIF_Pos) /*!< USPI_T::PROTSTS: RXSTIF Mask */ 637 638 #define USPI_PROTSTS_RXENDIF_Pos (4) /*!< USPI_T::PROTSTS: RXENDIF Position */ 639 #define USPI_PROTSTS_RXENDIF_Msk (0x1ul << USPI_PROTSTS_RXENDIF_Pos) /*!< USPI_T::PROTSTS: RXENDIF Mask */ 640 641 #define USPI_PROTSTS_SLVTOIF_Pos (5) /*!< USPI_T::PROTSTS: SLVTOIF Position */ 642 #define USPI_PROTSTS_SLVTOIF_Msk (0x1ul << USPI_PROTSTS_SLVTOIF_Pos) /*!< USPI_T::PROTSTS: SLVTOIF Mask */ 643 644 #define USPI_PROTSTS_SLVBEIF_Pos (6) /*!< USPI_T::PROTSTS: SLVBEIF Position */ 645 #define USPI_PROTSTS_SLVBEIF_Msk (0x1ul << USPI_PROTSTS_SLVBEIF_Pos) /*!< USPI_T::PROTSTS: SLVBEIF Mask */ 646 647 #define USPI_PROTSTS_SSINAIF_Pos (8) /*!< USPI_T::PROTSTS: SSINAIF Position */ 648 #define USPI_PROTSTS_SSINAIF_Msk (0x1ul << USPI_PROTSTS_SSINAIF_Pos) /*!< USPI_T::PROTSTS: SSINAIF Mask */ 649 650 #define USPI_PROTSTS_SSACTIF_Pos (9) /*!< USPI_T::PROTSTS: SSACTIF Position */ 651 #define USPI_PROTSTS_SSACTIF_Msk (0x1ul << USPI_PROTSTS_SSACTIF_Pos) /*!< USPI_T::PROTSTS: SSACTIF Mask */ 652 653 #define USPI_PROTSTS_SSLINE_Pos (16) /*!< USPI_T::PROTSTS: SSLINE Position */ 654 #define USPI_PROTSTS_SSLINE_Msk (0x1ul << USPI_PROTSTS_SSLINE_Pos) /*!< USPI_T::PROTSTS: SSLINE Mask */ 655 656 #define USPI_PROTSTS_BUSY_Pos (17) /*!< USPI_T::PROTSTS: BUSY Position */ 657 #define USPI_PROTSTS_BUSY_Msk (0x1ul << USPI_PROTSTS_BUSY_Pos) /*!< USPI_T::PROTSTS: BUSY Mask */ 658 659 #define USPI_PROTSTS_SLVUDR_Pos (18) /*!< USPI_T::PROTSTS: SLVUDR Position */ 660 #define USPI_PROTSTS_SLVUDR_Msk (0x1ul << USPI_PROTSTS_SLVUDR_Pos) /*!< USPI_T::PROTSTS: SLVUDR Mask */ 661 662 /**@}*/ /* USPI_CONST */ 663 /**@}*/ /* end of USPI register group */ 664 /**@}*/ /* end of REGISTER group */ 665 666 #endif /* __USPI_REG_H__ */ 667
