1 /**************************************************************************//** 2 * @file usbh_reg.h 3 * @version V1.00 4 * @brief USBH register definition header file 5 * 6 * @copyright SPDX-License-Identifier: Apache-2.0 7 * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __USBH_REG_H__ 10 #define __USBH_REG_H__ 11 12 /** @addtogroup REGISTER Control Register 13 14 @{ 15 16 */ 17 18 /*---------------------- USB Host Controller -------------------------*/ 19 /** 20 @addtogroup USBH USB Host Controller(USBH) 21 Memory Mapped Structure for USBH Controller 22 @{ 23 */ 24 25 typedef struct 26 { 27 28 29 /** 30 * @var USBH_T::HcRevision 31 * Offset: 0x00 Host Controller Revision Register 32 * --------------------------------------------------------------------------------------------------- 33 * |Bits |Field |Descriptions 34 * | :----: | :----: | :---- | 35 * |[7:0] |REV |Revision Number 36 * | | |Indicates the Open HCI Specification revision number implemented by the Hardware 37 * | | |Host Controller supports 1.1 specification. 38 * | | |(X.Y = XYh). 39 * @var USBH_T::HcControl 40 * Offset: 0x04 Host Controller Control Register 41 * --------------------------------------------------------------------------------------------------- 42 * |Bits |Field |Descriptions 43 * | :----: | :----: | :---- | 44 * |[1:0] |CBSR |Control Bulk Service Ratio 45 * | | |This specifies the service ratio between Control and Bulk EDs 46 * | | |Before processing any of the non-periodic lists, HC must compare the ratio specified with its internal count on how many nonempty Control EDs have been processed, in determining whether to continue serving another Control ED or switching to Bulk EDs 47 * | | |The internal count will be retained when crossing the frame boundary 48 * | | |In case of reset, HCD is responsible for restoring this value. 49 * | | |00 = Number of Control EDs over Bulk EDs served is 1:1. 50 * | | |01 = Number of Control EDs over Bulk EDs served is 2:1. 51 * | | |10 = Number of Control EDs over Bulk EDs served is 3:1. 52 * | | |11 = Number of Control EDs over Bulk EDs served is 4:1. 53 * |[2] |PLE |Periodic List Enable Bit 54 * | | |When set, this bit enables processing of the Periodic (interrupt and isochronous) list 55 * | | |The Host Controller checks this bit prior to attempting any periodic transfers in a frame. 56 * | | |0 = Processing of the Periodic (Interrupt and Isochronous) list after next SOF (Start-Of-Frame) Disabled. 57 * | | |1 = Processing of the Periodic (Interrupt and Isochronous) list in the next frame Enabled. 58 * | | |Note: To enable the processing of the Isochronous list, user has to set both PLE and IE (HcControl[3]) high. 59 * |[3] |IE |Isochronous List Enable Bit 60 * | | |Both IE and PLE (HcControl[2]) high enables Host Controller to process the Isochronous list 61 * | | |Either IE or PLE (HcControl[2]) is low disables Host Controller to process the Isochronous list. 62 * | | |0 = Processing of the Isochronous list after next SOF (Start-Of-Frame) Disabled. 63 * | | |1 = Processing of the Isochronous list in the next frame Enabled, if the PLE (HcControl[2]) is high, too. 64 * |[4] |CLE |Control List Enable Bit 65 * | | |0 = Processing of the Control list after next SOF (Start-Of-Frame) Disabled. 66 * | | |1 = Processing of the Control list in the next frame Enabled. 67 * |[5] |BLE |Bulk List Enable Bit 68 * | | |0 = Processing of the Bulk list after next SOF (Start-Of-Frame) Disabled. 69 * | | |1 = Processing of the Bulk list in the next frame Enabled. 70 * |[7:6] |HCFS |Host Controller Functional State 71 * | | |This field sets the Host Controller state 72 * | | |The Controller may force a state change from USBSUSPEND to USBRESUME after detecting resume signaling from a downstream port 73 * | | |States are: 74 * | | |00 = USBRESET. 75 * | | |01 = USBRESUME. 76 * | | |10 = USBOPERATIONAL. 77 * | | |11 = USBSUSPEND. 78 * @var USBH_T::HcCommandStatus 79 * Offset: 0x08 Host Controller Command Status Register 80 * --------------------------------------------------------------------------------------------------- 81 * |Bits |Field |Descriptions 82 * | :----: | :----: | :---- | 83 * |[0] |HCR |Host Controller Reset 84 * | | |This bit is set to initiate the software reset of Host Controller 85 * | | |This bit is cleared by the Host Controller, upon completed of the reset operation. 86 * | | |This bit, when set, didn't reset the Root Hub and no subsequent reset signaling be asserted to its downstream ports. 87 * | | |0 = Host Controller is not in software reset state. 88 * | | |1 = Host Controller is in software reset state. 89 * |[1] |CLF |Control List Filled 90 * | | |Set high to indicate there is an active TD on the Control List 91 * | | |It may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Control List. 92 * | | |0 = No active TD found or Host Controller begins to process the head of the Control list. 93 * | | |1 = An active TD added or found on the Control list. 94 * |[2] |BLF |Bulk List Filled 95 * | | |Set high to indicate there is an active TD on the Bulk list 96 * | | |This bit may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Bulk list. 97 * | | |0 = No active TD found or Host Controller begins to process the head of the Bulk list. 98 * | | |1 = An active TD added or found on the Bulk list. 99 * |[17:16] |SOC |Schedule Overrun Count (Read-Only) 100 * | | |These bits are incremented on each scheduling overrun error 101 * | | |It is initialized to 00b and wraps around at 11b 102 * | | |This will be incremented when a scheduling overrun is detected even if SO (HcInterruptStatus[0]) has already been set. 103 * @var USBH_T::HcInterruptStatus 104 * Offset: 0x0C Host Controller Interrupt Status Register 105 * --------------------------------------------------------------------------------------------------- 106 * |Bits |Field |Descriptions 107 * | :----: | :----: | :---- | 108 * |[0] |SO |Scheduling Overrun 109 * | | |Set when the List Processor determines a Schedule Overrun has occurred. 110 * | | |0 = Schedule Overrun didn't occur. 111 * | | |1 = Schedule Overrun has occurred. 112 * | | |Note: This bit is cleared by writing 1 to it. 113 * |[1] |WDH |Write Back Done Head 114 * | | |Set after the Host Controller has written HcDoneHead to HccaDoneHead 115 * | | |Further updates of the HccaDoneHead will not occur until this bit has been cleared. 116 * | | |0 = Host Controller didn't update HccaDoneHead. 117 * | | |1 = Host Controller has written HcDoneHead to HccaDoneHead. 118 * | | |Note: This bit is cleared by writing 1 to it. 119 * |[2] |SF |Start of Frame 120 * | | |Set when the Frame Management functional block signals a u2018Start of Frame' event 121 * | | |Host Control generates a SOF token at the same time. 122 * | | |0 = Not the start of a frame. 123 * | | |1 = Indicate the start of a frame and Host Controller generates a SOF token. 124 * | | |Note: This bit is cleared by writing 1 to it. 125 * |[3] |RD |Resume Detected 126 * | | |Set when Host Controller detects resume signaling on a downstream port. 127 * | | |0 = No resume signaling detected on a downstream port. 128 * | | |1 = Resume signaling detected on a downstream port. 129 * | | |Note: This bit is cleared by writing 1 to it. 130 * |[5] |FNO |Frame Number Overflow 131 * | | |This bit is set when bit 15 of Frame Number changes from 1 to 0 or from 0 to 1. 132 * | | |0 = The bit 15 of Frame Number didn't change. 133 * | | |1 = The bit 15 of Frame Number changes from 1 to 0 or from 0 to 1. 134 * | | |Note: This bit is cleared by writing 1 to it. 135 * |[6] |RHSC |Root Hub Status Change 136 * | | |This bit is set when the content of HcRhStatus or the content of HcRhPortStatus register has changed. 137 * | | |0 = The content of HcRhStatus and the content of HcRhPortStatus register didn't change. 138 * | | |1 = The content of HcRhStatus or the content of HcRhPortStatus register has changed. 139 * | | |Note: This bit is cleared by writing ‘1Fh’ to HcRhPortStatus1[20:16]. 140 * @var USBH_T::HcInterruptEnable 141 * Offset: 0x10 Host Controller Interrupt Enable Register 142 * --------------------------------------------------------------------------------------------------- 143 * |Bits |Field |Descriptions 144 * | :----: | :----: | :---- | 145 * |[0] |SO |Scheduling Overrun Enable Bit 146 * | | |Write Operation: 147 * | | |0 = No effect. 148 * | | |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Enabled. 149 * | | |Read Operation: 150 * | | |0 = Interrupt generation due to SO (HcInterruptStatus[0]) Disabled. 151 * | | |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Enabled. 152 * |[1] |WDH |Write Back Done Head Enable Bit 153 * | | |Write Operation: 154 * | | |0 = No effect. 155 * | | |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Enabled. 156 * | | |Read Operation: 157 * | | |0 = Interrupt generation due to WDH (HcInterruptStatus[1]) Disabled. 158 * | | |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Enabled. 159 * |[2] |SF |Start of Frame Enable Bit 160 * | | |Write Operation: 161 * | | |0 = No effect. 162 * | | |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Enabled. 163 * | | |Read Operation: 164 * | | |0 = Interrupt generation due to SF (HcInterruptStatus[2]) Disabled. 165 * | | |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Enabled. 166 * |[3] |RD |Resume Detected Enable Bit 167 * | | |Write Operation: 168 * | | |0 = No effect. 169 * | | |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Enabled. 170 * | | |Read Operation: 171 * | | |0 = Interrupt generation due to RD (HcInterruptStatus[3]) Disabled. 172 * | | |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Enabled. 173 * |[5] |FNO |Frame Number Overflow Enable Bit 174 * | | |Write Operation: 175 * | | |0 = No effect. 176 * | | |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Enabled. 177 * | | |Read Operation: 178 * | | |0 = Interrupt generation due to FNO (HcInterruptStatus[5]) Disabled. 179 * | | |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Enabled. 180 * |[6] |RHSC |Root Hub Status Change Enable Bit 181 * | | |Write Operation: 182 * | | |0 = No effect. 183 * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Enabled. 184 * | | |Read Operation: 185 * | | |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Disabled. 186 * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Enabled. 187 * |[31] |MIE |Master Interrupt Enable Bit 188 * | | |This bit is a global interrupt enable 189 * | | |A write of u20181' allows interrupts to be enabled via the specific enable bits listed above. 190 * | | |Write Operation: 191 * | | |0 = No effect. 192 * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Enabled if the corresponding bit in HcInterruptEnable is high. 193 * | | |Read Operation: 194 * | | |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled even if the corresponding bit in HcInterruptEnable is high. 195 * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Enabled if the corresponding bit in HcInterruptEnable is high. 196 * @var USBH_T::HcInterruptDisable 197 * Offset: 0x14 Host Controller Interrupt Disable Register 198 * --------------------------------------------------------------------------------------------------- 199 * |Bits |Field |Descriptions 200 * | :----: | :----: | :---- | 201 * |[0] |SO |Scheduling Overrun Disable Bit 202 * | | |Write Operation: 203 * | | |0 = No effect. 204 * | | |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Disabled. 205 * | | |Read Operation: 206 * | | |0 = Interrupt generation due to SO (HcInterruptStatus[0]) Disabled. 207 * | | |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Enabled. 208 * |[1] |WDH |Write Back Done Head Disable Bit 209 * | | |Write Operation: 210 * | | |0 = No effect. 211 * | | |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Disabled. 212 * | | |Read Operation: 213 * | | |0 = Interrupt generation due to WDH (HcInterruptStatus[1]) Disabled. 214 * | | |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Enabled. 215 * |[2] |SF |Start of Frame Disable Bit 216 * | | |Write Operation: 217 * | | |0 = No effect. 218 * | | |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Disabled. 219 * | | |Read Operation: 220 * | | |0 = Interrupt generation due to SF (HcInterruptStatus[2]) Disabled. 221 * | | |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Enabled. 222 * |[3] |RD |Resume Detected Disable Bit 223 * | | |Write Operation: 224 * | | |0 = No effect. 225 * | | |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Disabled. 226 * | | |Read Operation: 227 * | | |0 = Interrupt generation due to RD (HcInterruptStatus[3]) Disabled. 228 * | | |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Enabled. 229 * |[5] |FNO |Frame Number Overflow Disable Bit 230 * | | |Write Operation: 231 * | | |0 = No effect. 232 * | | |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Disabled. 233 * | | |Read Operation: 234 * | | |0 = Interrupt generation due to FNO (HcInterruptStatus[5]) Disabled. 235 * | | |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Enabled. 236 * |[6] |RHSC |Root Hub Status Change Disable Bit 237 * | | |Write Operation: 238 * | | |0 = No effect. 239 * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Disabled. 240 * | | |Read Operation: 241 * | | |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Disabled. 242 * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Enabled. 243 * |[31] |MIE |Master Interrupt Disable Bit 244 * | | |Global interrupt disable. Writing u20181' to disable all interrupts. 245 * | | |Write Operation: 246 * | | |0 = No effect. 247 * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled if the corresponding bit in HcInterruptEnable is high. 248 * | | |Read Operation: 249 * | | |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled even if the corresponding bit in HcInterruptEnable is high. 250 * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Enabled if the corresponding bit in HcInterruptEnable is high. 251 * @var USBH_T::HcHCCA 252 * Offset: 0x18 Host Controller Communication Area Register 253 * --------------------------------------------------------------------------------------------------- 254 * |Bits |Field |Descriptions 255 * | :----: | :----: | :---- | 256 * |[31:8] |HCCA |Host Controller Communication Area 257 * | | |Pointer to indicate the base address of the Host Controller Communication Area (HCCA). 258 * @var USBH_T::HcPeriodCurrentED 259 * Offset: 0x1C Host Controller Period Current ED Register 260 * --------------------------------------------------------------------------------------------------- 261 * |Bits |Field |Descriptions 262 * | :----: | :----: | :---- | 263 * |[31:4] |PCED |Periodic Current ED 264 * | | |Pointer to indicate the physical address of the current Isochronous or Interrupt Endpoint Descriptor. 265 * @var USBH_T::HcControlHeadED 266 * Offset: 0x20 Host Controller Control ED Register 267 * --------------------------------------------------------------------------------------------------- 268 * |Bits |Field |Descriptions 269 * | :----: | :----: | :---- | 270 * |[31:4] |CHED |Control Head ED 271 * | | |Pointer to indicate the physical address of the first Endpoint Descriptor of the Control list. 272 * @var USBH_T::HcControlCurrentED 273 * Offset: 0x24 Host Controller Control Current ED Register 274 * --------------------------------------------------------------------------------------------------- 275 * |Bits |Field |Descriptions 276 * | :----: | :----: | :---- | 277 * |[31:4] |CCED |Control Current Head ED 278 * | | |Pointer to indicate the physical address of the current Endpoint Descriptor of the Control list. 279 * @var USBH_T::HcBulkHeadED 280 * Offset: 0x28 Host Controller Bulk Head ED Register 281 * --------------------------------------------------------------------------------------------------- 282 * |Bits |Field |Descriptions 283 * | :----: | :----: | :---- | 284 * |[31:4] |BHED |Bulk Head ED 285 * | | |Pointer to indicate the physical address of the first Endpoint Descriptor of the Bulk list. 286 * @var USBH_T::HcBulkCurrentED 287 * Offset: 0x2C Host Controller Bulk Current ED Register 288 * --------------------------------------------------------------------------------------------------- 289 * |Bits |Field |Descriptions 290 * | :----: | :----: | :---- | 291 * |[31:4] |BCED |Bulk Current Head ED 292 * | | |Pointer to indicate the physical address of the current endpoint of the Bulk list. 293 * @var USBH_T::HcDoneHead 294 * Offset: 0x30 Host Controller Done Head Register 295 * --------------------------------------------------------------------------------------------------- 296 * |Bits |Field |Descriptions 297 * | :----: | :----: | :---- | 298 * |[31:4] |DH |Done Head 299 * | | |Pointer to indicate the physical address of the last completed Transfer Descriptor that was added to the Done queue. 300 * @var USBH_T::HcFmInterval 301 * Offset: 0x34 Host Controller Frame Interval Register 302 * --------------------------------------------------------------------------------------------------- 303 * |Bits |Field |Descriptions 304 * | :----: | :----: | :---- | 305 * |[13:0] |FI |Frame Interval 306 * | | |This field specifies the length of a frame as (bit times - 1) 307 * | | |For 12,000 bit times in a frame, a value of 11,999 is stored here. 308 * |[29:16] |FSMPS |FS Largest Data Packet 309 * | | |This field specifies a value that is loaded into the Largest Data Packet Counter at the beginning of each frame. 310 * |[31] |FIT |Frame Interval Toggle 311 * | | |This bit is toggled by Host Controller Driver when it loads a new value into FI (HcFmInterval[13:0]). 312 * | | |0 = Host Controller Driver didn't load new value into FI (HcFmInterval[13:0]). 313 * | | |1 = Host Controller Driver loads a new value into FI (HcFmInterval[13:0]). 314 * @var USBH_T::HcFmRemaining 315 * Offset: 0x38 Host Controller Frame Remaining Register 316 * --------------------------------------------------------------------------------------------------- 317 * |Bits |Field |Descriptions 318 * | :----: | :----: | :---- | 319 * |[13:0] |FR |Frame Remaining 320 * | | |When the Host Controller is in the USBOPERATIONAL state, this 14-bit field decrements each 12 MHz clock period 321 * | | |When the count reaches 0, (end of frame) the counter reloads with Frame Interval 322 * | | |In addition, the counter loads when the Host Controller transitions into USBOPERATIONAL. 323 * |[31] |FRT |Frame Remaining Toggle 324 * | | |This bit is loaded from the FIT (HcFmInterval[31]) whenever FR (HcFmRemaining[13:0]) reaches 0. 325 * @var USBH_T::HcFmNumber 326 * Offset: 0x3C Host Controller Frame Number Register 327 * --------------------------------------------------------------------------------------------------- 328 * |Bits |Field |Descriptions 329 * | :----: | :----: | :---- | 330 * |[15:0] |FN |Frame Number 331 * | | |This 16-bit incrementing counter field is incremented coincident with the re-load of FR (HcFmRemaining[13:0]) 332 * | | |The count rolls over from u2018FFFFh' to u20180h.' 333 * @var USBH_T::HcPeriodicStart 334 * Offset: 0x40 Host Controller Periodic Start Register 335 * --------------------------------------------------------------------------------------------------- 336 * |Bits |Field |Descriptions 337 * | :----: | :----: | :---- | 338 * |[13:0] |PS |Periodic Start 339 * | | |This field contains a value used by the List Processor to determine where in a frame the Periodic List processing must begin. 340 * @var USBH_T::HcLSThreshold 341 * Offset: 0x44 Host Controller Low-speed Threshold Register 342 * --------------------------------------------------------------------------------------------------- 343 * |Bits |Field |Descriptions 344 * | :----: | :----: | :---- | 345 * |[11:0] |LST |Low-speed Threshold 346 * | | |This field contains a value which is compared to the FR (HcFmRemaining[13:0]) field prior to initiating a Low-speed transaction 347 * | | |The transaction is started only if FR (HcFmRemaining[13:0]) >= this field 348 * | | |The value is calculated by Host Controller Driver with the consideration of transmission and setup overhead. 349 * @var USBH_T::HcRhDescriptorA 350 * Offset: 0x48 Host Controller Root Hub Descriptor A Register 351 * --------------------------------------------------------------------------------------------------- 352 * |Bits |Field |Descriptions 353 * | :----: | :----: | :---- | 354 * |[7:0] |NDP |Number Downstream Ports 355 * | | |USB host control supports two downstream ports and only one port is available in this series of chip. 356 * | | |Note: NDP = 1 in this series of chip. 357 * |[8] |PSM |Power Switching Mode 358 * | | |This bit is used to specify how the power switching of the Root Hub ports is controlled. 359 * | | |0 = Global switching. 360 * | | |1 = Individual switching. 361 * |[11] |OCPM |Over Current Protection Mode 362 * | | |This bit describes how the over current status for the Root Hub ports reported 363 * | | |This bit is only valid when NOCP (HcRhDescriptorA[12]) is cleared. 364 * | | |0 = Global over current. 365 * | | |1 = Individual over current. 366 * |[12] |NOCP |No Over Current Protection 367 * | | |This bit describes how the over current status for the Root Hub ports reported. 368 * | | |0 = Over current status is reported. 369 * | | |1 = Over current status is not reported. 370 * @var USBH_T::HcRhDescriptorB 371 * Offset: 0x4C Host Controller Root Hub Descriptor B Register 372 * --------------------------------------------------------------------------------------------------- 373 * |Bits |Field |Descriptions 374 * | :----: | :----: | :---- | 375 * |[31:16] |PPCM |Port Power Control Mask 376 * | | |Global power switching 377 * | | |This field is only valid if Power Switching Mode is set (individual port switching) 378 * | | |When set, the port only responds to individual port power switching commands (Set/Clear Port Power) 379 * | | |When cleared, the port only responds to global power switching commands (Set/Clear Global Power). 380 * | | |0 = Port power controlled by global power switching. 381 * | | |1 = Port power controlled by port power switching. 382 * | | |Note: PPCM[15:2] and PPCM[0] are reserved. 383 * @var USBH_T::HcRhStatus 384 * Offset: 0x50 Host Controller Root Hub Status Register 385 * --------------------------------------------------------------------------------------------------- 386 * |Bits |Field |Descriptions 387 * | :----: | :----: | :---- | 388 * |[0] |LPS |Clear Global Power 389 * | | |In global power mode (PSM (HcRhDescriptorA[8]) = 0), this bit is written to one to clear all ports' power. 390 * | | |This bit always read as zero. 391 * | | |Write Operation: 392 * | | |0 = No effect. 393 * | | |1 = Clear global power. 394 * |[1] |OCI |Over Current Indicator (Read-Only) 395 * | | |This bit reflects the state of the over current status pin 396 * | | |This field is only valid if NOCP (HcRhDescriptorA[12]) and OCPM (HcRhDescriptorA[11]) are cleared. 397 * | | |0 = No over current condition. 398 * | | |1 = Over current condition. 399 * |[15] |DRWE |Device Remote Wakeup Enable Bit 400 * | | |This bit controls if port's Connect Status Change as a remote wake-up event. 401 * | | |Write Operation: 402 * | | |0 = No effect. 403 * | | |1 = Connect Status Change as a remote wake-up event Enabled. 404 * | | |Read Operation: 405 * | | |0 = Connect Status Change as a remote wake-up event Disabled. 406 * | | |1 = Connect Status Change as a remote wake-up event Enabled. 407 * |[16] |LPSC |Set Global Power 408 * | | |In global power mode (PSM (HcRhDescriptorA[8]) = 0), this bit is written to one to enable power to all ports. 409 * | | |This bit always read as zero. 410 * | | |Write Operation: 411 * | | |0 = No effect. 412 * | | |1 = Set global power. 413 * |[17] |OCIC |Over Current Indicator Change 414 * | | |This bit is set by hardware when a change has occurred in OCI (HcRhStatus[1]). 415 * | | |Write 1 to clear this bit to zero. 416 * | | |0 = OCI (HcRhStatus[1]) didn't change. 417 * | | |1 = OCI (HcRhStatus[1]) change. 418 * |[31] |CRWE |Clear Remote Wake-up Enable Bit 419 * | | |This bit is use to clear DRWE (HcRhStatus[15]). 420 * | | |This bit always read as zero. 421 * | | |Write Operation: 422 * | | |0 = No effect. 423 * | | |1 = Clear DRWE (HcRhStatus[15]). 424 * @var USBH_T::HcRhPortStatus[2] 425 * Offset: 0x54 Host Controller Root Hub Port Status 426 * --------------------------------------------------------------------------------------------------- 427 * |Bits |Field |Descriptions 428 * | :----: | :----: | :---- | 429 * |[0] |CCS |Current Connect Status (Read) or Clear Port Enable (Write) 430 * | | |Write Operation: 431 * | | |0 = No effect. 432 * | | |1 = Clear port enable. 433 * | | |Read Operation: 434 * | | |0 = No device connected. 435 * | | |1 = Device connected. 436 * |[1] |PES |Port Enable Status (Read) or Set Port Enable (Write) 437 * | | |Write Operation: 438 * | | |0 = No effect. 439 * | | |1 = Set port enable. 440 * | | |Read Operation: 441 * | | |0 = Port Disabled. 442 * | | |1 = Port Enabled. 443 * |[2] |PSS |Port Suspend Status (Read) or Set Port Suspend (Write) 444 * | | |This bit indicates the port is suspended 445 * | | |Write Operation: 446 * | | |0 = No effect. 447 * | | |1 = Set port suspend. 448 * | | |Read Operation: 449 * | | |0 = Port is not suspended. 450 * | | |1 = Port is selectively suspended. 451 * |[3] |POCI |Port Over Current Indicator (Read) or Clear Port Suspend (Write) 452 * | | |This bit reflects the state of the over current status pin dedicated to this port 453 * | | |This field is only valid if NOCP (HcRhDescriptorA[12]) is cleared and OCPM (HcRhDescriptorA[11]) is set. 454 * | | |This bit is also used to initiate the selective result sequence for the port. 455 * | | |Write Operation: 456 * | | |0 = No effect. 457 * | | |1 = Clear port suspend. 458 * | | |Read Operation: 459 * | | |0 = No over current condition. 460 * | | |1 = Over current condition. 461 * |[4] |PRS |Port Reset Status (Read) or Set Port Reset (Write) 462 * | | |This bit reflects the reset state of the port. 463 * | | |Write Operation: 464 * | | |0 = No effect. 465 * | | |1 = Set port reset. 466 * | | |Read Operation 467 * | | |0 = Port reset signal is not active. 468 * | | |1 = Port reset signal is active. 469 * |[8] |PPS |Port Power Status (Read) or Set Port Power (Write) 470 * | | |This bit reflects the power state of the port regardless of the power switching mode. 471 * | | |Write Operation: 472 * | | |0 = No effect. 473 * | | |1 = Port Power Enabled. 474 * | | |Read Operation: 475 * | | |0 = Port power is Disabled. 476 * | | |1 = Port power is Enabled. 477 * |[9] |LSDA |Low Speed Device Attached (Read) or Clear Port Power (Write) 478 * | | |This bit defines the speed (and bus idle) of the attached device 479 * | | |It is only valid when CCS (HcRhPortStatus[0]) is set. 480 * | | |This bit is also used to clear port power. 481 * | | |Write Operation: 482 * | | |0 = No effect. 483 * | | |1 = Clear PPS (HcRhPortStatus[8]). 484 * | | |Read Operation: 485 * | | |0 = Full Speed device. 486 * | | |1 = Low-speed device. 487 * |[16] |CSC |Connect Status Change 488 * | | |This bit indicates connect or disconnect event has been detected (CCS (HcRhPortStatus[0]) changed). 489 * | | |Write 1 to clear this bit to zero. 490 * | | |0 = No connect/disconnect event (CCS (HcRhPortStatus[0]) didn't change). 491 * | | |1 = Hardware detection of connect/disconnect event (CCS (HcRhPortStatus[0]) changed). 492 * |[17] |PESC |Port Enable Status Change 493 * | | |This bit indicates that the port has been disabled (PES (HcRhPortStatus[1]) cleared) due to a hardware event. 494 * | | |Write 1 to clear this bit to zero. 495 * | | |0 = PES (HcRhPortStatus[1]) didn't change. 496 * | | |1 = PES (HcRhPortStatus[1]) changed. 497 * |[18] |PSSC |Port Suspend Status Change 498 * | | |This bit indicates the completion of the selective resume sequence for the port. 499 * | | |Write 1 to clear this bit to zero. 500 * | | |0 = Port resume is not complete. 501 * | | |1 = Port resume complete. 502 * |[19] |OCIC |Port Over Current Indicator Change 503 * | | |This bit is set when POCI (HcRhPortStatus[3]) changes. 504 * | | |Write 1 to clear this bit to zero. 505 * | | |0 = POCI (HcRhPortStatus[3]) didn't change. 506 * | | |1 = POCI (HcRhPortStatus[3]) changes. 507 * |[20] |PRSC |Port Reset Status Change 508 * | | |This bit indicates that the port reset signal has completed. 509 * | | |Write 1 to clear this bit to zero. 510 * | | |0 = Port reset is not complete. 511 * | | |1 = Port reset is complete. 512 * @var USBH_T::HcPhyControl 513 * Offset: 0x200 Host Controller PHY Control Register 514 * --------------------------------------------------------------------------------------------------- 515 * |Bits |Field |Descriptions 516 * | :----: | :----: | :---- | 517 * |[27] |STBYEN |USB Transceiver Standby Enable Bit 518 * | | |This bit controls if USB transceiver could enter the standby mode to reduce power consumption. 519 * | | |0 = The USB transceiver would never enter the standby mode. 520 * | | |1 = The USB transceiver will enter standby mode while port is in power off state (port power is inactive). 521 * @var USBH_T::HcMiscControl 522 * Offset: 0x204 Host Controller Miscellaneous Control Register 523 * --------------------------------------------------------------------------------------------------- 524 * |Bits |Field |Descriptions 525 * | :----: | :----: | :---- | 526 * |[1] |ABORT |AHB Bus Error Response 527 * | | |This bit indicates there is an Error response received in AHB bus. 528 * | | |0 = No Error response received. 529 * | | |1 = Error response received. 530 * | | |Note: This bit is cleared by writing 1 to it. 531 * |[3] |OCAL |over Current Active Low 532 * | | |This bit controls the polarity of over current flag from external power IC. 533 * | | |0 = Over current flag is high active. 534 * | | |1 = Over current flag is low active. 535 * |[16] |DPRT1 |Disable Port 1 536 * | | |This bit controls if the connection between USB host controller and transceiver of port 1 is disabled 537 * | | |If the connection is disabled, the USB host controller will not recognize any event of USB bus. 538 * | | |Set this bit high, the transceiver of port 1 will also be forced into the standby mode no matter what USB host controller operation is. 539 * | | |0 = The connection between USB host controller and transceiver of port 1 Enabled. 540 * | | |1 = The connection between USB host controller and transceiver of port 1 Disabled and the transceiver of port 1 will also be forced into the standby mode. 541 */ 542 __I uint32_t HcRevision; /*!< [0x0000] Host Controller Revision Register */ 543 __IO uint32_t HcControl; /*!< [0x0004] Host Controller Control Register */ 544 __IO uint32_t HcCommandStatus; /*!< [0x0008] Host Controller Command Status Register */ 545 __IO uint32_t HcInterruptStatus; /*!< [0x000c] Host Controller Interrupt Status Register */ 546 __IO uint32_t HcInterruptEnable; /*!< [0x0010] Host Controller Interrupt Enable Register */ 547 __IO uint32_t HcInterruptDisable; /*!< [0x0014] Host Controller Interrupt Disable Register */ 548 __IO uint32_t HcHCCA; /*!< [0x0018] Host Controller Communication Area Register */ 549 __IO uint32_t HcPeriodCurrentED; /*!< [0x001c] Host Controller Period Current ED Register */ 550 __IO uint32_t HcControlHeadED; /*!< [0x0020] Host Controller Control Head ED Register */ 551 __IO uint32_t HcControlCurrentED; /*!< [0x0024] Host Controller Control Current ED Register */ 552 __IO uint32_t HcBulkHeadED; /*!< [0x0028] Host Controller Bulk Head ED Register */ 553 __IO uint32_t HcBulkCurrentED; /*!< [0x002c] Host Controller Bulk Current ED Register */ 554 __IO uint32_t HcDoneHead; /*!< [0x0030] Host Controller Done Head Register */ 555 __IO uint32_t HcFmInterval; /*!< [0x0034] Host Controller Frame Interval Register */ 556 __I uint32_t HcFmRemaining; /*!< [0x0038] Host Controller Frame Remaining Register */ 557 __I uint32_t HcFmNumber; /*!< [0x003c] Host Controller Frame Number Register */ 558 __IO uint32_t HcPeriodicStart; /*!< [0x0040] Host Controller Periodic Start Register */ 559 __IO uint32_t HcLSThreshold; /*!< [0x0044] Host Controller Low-speed Threshold Register */ 560 __IO uint32_t HcRhDescriptorA; /*!< [0x0048] Host Controller Root Hub Descriptor A Register */ 561 __IO uint32_t HcRhDescriptorB; /*!< [0x004c] Host Controller Root Hub Descriptor B Register */ 562 __IO uint32_t HcRhStatus; /*!< [0x0050] Host Controller Root Hub Status Register */ 563 __IO uint32_t HcRhPortStatus[2]; /*!< [0x0054] Host Controller Root Hub Port Status */ 564 __I uint32_t RESERVE0[105]; 565 __IO uint32_t HcPhyControl; /*!< [0x0200] Host Controller PHY Control Register */ 566 __IO uint32_t HcMiscControl; /*!< [0x0204] Host Controller Miscellaneous Control Register */ 567 568 } USBH_T; 569 570 /** 571 @addtogroup USBH_CONST USBH Bit Field Definition 572 Constant Definitions for USBH Controller 573 @{ 574 */ 575 576 #define USBH_HcRevision_REV_Pos (0) /*!< USBH_T::HcRevision: REV Position */ 577 #define USBH_HcRevision_REV_Msk (0xfful << USBH_HcRevision_REV_Pos) /*!< USBH_T::HcRevision: REV Mask */ 578 579 #define USBH_HcControl_CBSR_Pos (0) /*!< USBH_T::HcControl: CBSR Position */ 580 #define USBH_HcControl_CBSR_Msk (0x3ul << USBH_HcControl_CBSR_Pos) /*!< USBH_T::HcControl: CBSR Mask */ 581 582 #define USBH_HcControl_PLE_Pos (2) /*!< USBH_T::HcControl: PLE Position */ 583 #define USBH_HcControl_PLE_Msk (0x1ul << USBH_HcControl_PLE_Pos) /*!< USBH_T::HcControl: PLE Mask */ 584 585 #define USBH_HcControl_IE_Pos (3) /*!< USBH_T::HcControl: IE Position */ 586 #define USBH_HcControl_IE_Msk (0x1ul << USBH_HcControl_IE_Pos) /*!< USBH_T::HcControl: IE Mask */ 587 588 #define USBH_HcControl_CLE_Pos (4) /*!< USBH_T::HcControl: CLE Position */ 589 #define USBH_HcControl_CLE_Msk (0x1ul << USBH_HcControl_CLE_Pos) /*!< USBH_T::HcControl: CLE Mask */ 590 591 #define USBH_HcControl_BLE_Pos (5) /*!< USBH_T::HcControl: BLE Position */ 592 #define USBH_HcControl_BLE_Msk (0x1ul << USBH_HcControl_BLE_Pos) /*!< USBH_T::HcControl: BLE Mask */ 593 594 #define USBH_HcControl_HCFS_Pos (6) /*!< USBH_T::HcControl: HCFS Position */ 595 #define USBH_HcControl_HCFS_Msk (0x3ul << USBH_HcControl_HCFS_Pos) /*!< USBH_T::HcControl: HCFS Mask */ 596 597 #define USBH_HcCommandStatus_HCR_Pos (0) /*!< USBH_T::HcCommandStatus: HCR Position */ 598 #define USBH_HcCommandStatus_HCR_Msk (0x1ul << USBH_HcCommandStatus_HCR_Pos) /*!< USBH_T::HcCommandStatus: HCR Mask */ 599 600 #define USBH_HcCommandStatus_CLF_Pos (1) /*!< USBH_T::HcCommandStatus: CLF Position */ 601 #define USBH_HcCommandStatus_CLF_Msk (0x1ul << USBH_HcCommandStatus_CLF_Pos) /*!< USBH_T::HcCommandStatus: CLF Mask */ 602 603 #define USBH_HcCommandStatus_BLF_Pos (2) /*!< USBH_T::HcCommandStatus: BLF Position */ 604 #define USBH_HcCommandStatus_BLF_Msk (0x1ul << USBH_HcCommandStatus_BLF_Pos) /*!< USBH_T::HcCommandStatus: BLF Mask */ 605 606 #define USBH_HcCommandStatus_SOC_Pos (16) /*!< USBH_T::HcCommandStatus: SOC Position */ 607 #define USBH_HcCommandStatus_SOC_Msk (0x3ul << USBH_HcCommandStatus_SOC_Pos) /*!< USBH_T::HcCommandStatus: SOC Mask */ 608 609 #define USBH_HcInterruptStatus_SO_Pos (0) /*!< USBH_T::HcInterruptStatus: SO Position */ 610 #define USBH_HcInterruptStatus_SO_Msk (0x1ul << USBH_HcInterruptStatus_SO_Pos) /*!< USBH_T::HcInterruptStatus: SO Mask */ 611 612 #define USBH_HcInterruptStatus_WDH_Pos (1) /*!< USBH_T::HcInterruptStatus: WDH Position*/ 613 #define USBH_HcInterruptStatus_WDH_Msk (0x1ul << USBH_HcInterruptStatus_WDH_Pos) /*!< USBH_T::HcInterruptStatus: WDH Mask */ 614 615 #define USBH_HcInterruptStatus_SF_Pos (2) /*!< USBH_T::HcInterruptStatus: SF Position */ 616 #define USBH_HcInterruptStatus_SF_Msk (0x1ul << USBH_HcInterruptStatus_SF_Pos) /*!< USBH_T::HcInterruptStatus: SF Mask */ 617 618 #define USBH_HcInterruptStatus_RD_Pos (3) /*!< USBH_T::HcInterruptStatus: RD Position */ 619 #define USBH_HcInterruptStatus_RD_Msk (0x1ul << USBH_HcInterruptStatus_RD_Pos) /*!< USBH_T::HcInterruptStatus: RD Mask */ 620 621 #define USBH_HcInterruptStatus_FNO_Pos (5) /*!< USBH_T::HcInterruptStatus: FNO Position*/ 622 #define USBH_HcInterruptStatus_FNO_Msk (0x1ul << USBH_HcInterruptStatus_FNO_Pos) /*!< USBH_T::HcInterruptStatus: FNO Mask */ 623 624 #define USBH_HcInterruptStatus_RHSC_Pos (6) /*!< USBH_T::HcInterruptStatus: RHSC Position*/ 625 #define USBH_HcInterruptStatus_RHSC_Msk (0x1ul << USBH_HcInterruptStatus_RHSC_Pos) /*!< USBH_T::HcInterruptStatus: RHSC Mask */ 626 627 #define USBH_HcInterruptEnable_SO_Pos (0) /*!< USBH_T::HcInterruptEnable: SO Position */ 628 #define USBH_HcInterruptEnable_SO_Msk (0x1ul << USBH_HcInterruptEnable_SO_Pos) /*!< USBH_T::HcInterruptEnable: SO Mask */ 629 630 #define USBH_HcInterruptEnable_WDH_Pos (1) /*!< USBH_T::HcInterruptEnable: WDH Position*/ 631 #define USBH_HcInterruptEnable_WDH_Msk (0x1ul << USBH_HcInterruptEnable_WDH_Pos) /*!< USBH_T::HcInterruptEnable: WDH Mask */ 632 633 #define USBH_HcInterruptEnable_SF_Pos (2) /*!< USBH_T::HcInterruptEnable: SF Position */ 634 #define USBH_HcInterruptEnable_SF_Msk (0x1ul << USBH_HcInterruptEnable_SF_Pos) /*!< USBH_T::HcInterruptEnable: SF Mask */ 635 636 #define USBH_HcInterruptEnable_RD_Pos (3) /*!< USBH_T::HcInterruptEnable: RD Position */ 637 #define USBH_HcInterruptEnable_RD_Msk (0x1ul << USBH_HcInterruptEnable_RD_Pos) /*!< USBH_T::HcInterruptEnable: RD Mask */ 638 639 #define USBH_HcInterruptEnable_FNO_Pos (5) /*!< USBH_T::HcInterruptEnable: FNO Position*/ 640 #define USBH_HcInterruptEnable_FNO_Msk (0x1ul << USBH_HcInterruptEnable_FNO_Pos) /*!< USBH_T::HcInterruptEnable: FNO Mask */ 641 642 #define USBH_HcInterruptEnable_RHSC_Pos (6) /*!< USBH_T::HcInterruptEnable: RHSC Position*/ 643 #define USBH_HcInterruptEnable_RHSC_Msk (0x1ul << USBH_HcInterruptEnable_RHSC_Pos) /*!< USBH_T::HcInterruptEnable: RHSC Mask */ 644 645 #define USBH_HcInterruptEnable_MIE_Pos (31) /*!< USBH_T::HcInterruptEnable: MIE Position*/ 646 #define USBH_HcInterruptEnable_MIE_Msk (0x1ul << USBH_HcInterruptEnable_MIE_Pos) /*!< USBH_T::HcInterruptEnable: MIE Mask */ 647 648 #define USBH_HcInterruptDisable_SO_Pos (0) /*!< USBH_T::HcInterruptDisable: SO Position*/ 649 #define USBH_HcInterruptDisable_SO_Msk (0x1ul << USBH_HcInterruptDisable_SO_Pos) /*!< USBH_T::HcInterruptDisable: SO Mask */ 650 651 #define USBH_HcInterruptDisable_WDH_Pos (1) /*!< USBH_T::HcInterruptDisable: WDH Position*/ 652 #define USBH_HcInterruptDisable_WDH_Msk (0x1ul << USBH_HcInterruptDisable_WDH_Pos) /*!< USBH_T::HcInterruptDisable: WDH Mask */ 653 654 #define USBH_HcInterruptDisable_SF_Pos (2) /*!< USBH_T::HcInterruptDisable: SF Position*/ 655 #define USBH_HcInterruptDisable_SF_Msk (0x1ul << USBH_HcInterruptDisable_SF_Pos) /*!< USBH_T::HcInterruptDisable: SF Mask */ 656 657 #define USBH_HcInterruptDisable_RD_Pos (3) /*!< USBH_T::HcInterruptDisable: RD Position*/ 658 #define USBH_HcInterruptDisable_RD_Msk (0x1ul << USBH_HcInterruptDisable_RD_Pos) /*!< USBH_T::HcInterruptDisable: RD Mask */ 659 660 #define USBH_HcInterruptDisable_FNO_Pos (5) /*!< USBH_T::HcInterruptDisable: FNO Position*/ 661 #define USBH_HcInterruptDisable_FNO_Msk (0x1ul << USBH_HcInterruptDisable_FNO_Pos) /*!< USBH_T::HcInterruptDisable: FNO Mask */ 662 663 #define USBH_HcInterruptDisable_RHSC_Pos (6) /*!< USBH_T::HcInterruptDisable: RHSC Position*/ 664 #define USBH_HcInterruptDisable_RHSC_Msk (0x1ul << USBH_HcInterruptDisable_RHSC_Pos) /*!< USBH_T::HcInterruptDisable: RHSC Mask */ 665 666 #define USBH_HcInterruptDisable_MIE_Pos (31) /*!< USBH_T::HcInterruptDisable: MIE Position*/ 667 #define USBH_HcInterruptDisable_MIE_Msk (0x1ul << USBH_HcInterruptDisable_MIE_Pos) /*!< USBH_T::HcInterruptDisable: MIE Mask */ 668 669 #define USBH_HcHCCA_HCCA_Pos (8) /*!< USBH_T::HcHCCA: HCCA Position */ 670 #define USBH_HcHCCA_HCCA_Msk (0xfffffful << USBH_HcHCCA_HCCA_Pos) /*!< USBH_T::HcHCCA: HCCA Mask */ 671 672 #define USBH_HcPeriodCurrentED_PCED_Pos (4) /*!< USBH_T::HcPeriodCurrentED: PCED Position*/ 673 #define USBH_HcPeriodCurrentED_PCED_Msk (0xffffffful << USBH_HcPeriodCurrentED_PCED_Pos) /*!< USBH_T::HcPeriodCurrentED: PCED Mask */ 674 675 #define USBH_HcControlHeadED_CHED_Pos (4) /*!< USBH_T::HcControlHeadED: CHED Position */ 676 #define USBH_HcControlHeadED_CHED_Msk (0xffffffful << USBH_HcControlHeadED_CHED_Pos) /*!< USBH_T::HcControlHeadED: CHED Mask */ 677 678 #define USBH_HcControlCurrentED_CCED_Pos (4) /*!< USBH_T::HcControlCurrentED: CCED Position*/ 679 #define USBH_HcControlCurrentED_CCED_Msk (0xffffffful << USBH_HcControlCurrentED_CCED_Pos) /*!< USBH_T::HcControlCurrentED: CCED Mask */ 680 681 #define USBH_HcBulkHeadED_BHED_Pos (4) /*!< USBH_T::HcBulkHeadED: BHED Position */ 682 #define USBH_HcBulkHeadED_BHED_Msk (0xffffffful << USBH_HcBulkHeadED_BHED_Pos) /*!< USBH_T::HcBulkHeadED: BHED Mask */ 683 684 #define USBH_HcBulkCurrentED_BCED_Pos (4) /*!< USBH_T::HcBulkCurrentED: BCED Position */ 685 #define USBH_HcBulkCurrentED_BCED_Msk (0xffffffful << USBH_HcBulkCurrentED_BCED_Pos) /*!< USBH_T::HcBulkCurrentED: BCED Mask */ 686 687 #define USBH_HcDoneHead_DH_Pos (4) /*!< USBH_T::HcDoneHead: DH Position */ 688 #define USBH_HcDoneHead_DH_Msk (0xffffffful << USBH_HcDoneHead_DH_Pos) /*!< USBH_T::HcDoneHead: DH Mask */ 689 690 #define USBH_HcFmInterval_FI_Pos (0) /*!< USBH_T::HcFmInterval: FI Position */ 691 #define USBH_HcFmInterval_FI_Msk (0x3ffful << USBH_HcFmInterval_FI_Pos) /*!< USBH_T::HcFmInterval: FI Mask */ 692 693 #define USBH_HcFmInterval_FSMPS_Pos (16) /*!< USBH_T::HcFmInterval: FSMPS Position */ 694 #define USBH_HcFmInterval_FSMPS_Msk (0x3ffful << USBH_HcFmInterval_FSMPS_Pos) /*!< USBH_T::HcFmInterval: FSMPS Mask */ 695 696 #define USBH_HcFmInterval_FIT_Pos (31) /*!< USBH_T::HcFmInterval: FIT Position */ 697 #define USBH_HcFmInterval_FIT_Msk (0x1ul << USBH_HcFmInterval_FIT_Pos) /*!< USBH_T::HcFmInterval: FIT Mask */ 698 699 #define USBH_HcFmRemaining_FR_Pos (0) /*!< USBH_T::HcFmRemaining: FR Position */ 700 #define USBH_HcFmRemaining_FR_Msk (0x3ffful << USBH_HcFmRemaining_FR_Pos) /*!< USBH_T::HcFmRemaining: FR Mask */ 701 702 #define USBH_HcFmRemaining_FRT_Pos (31) /*!< USBH_T::HcFmRemaining: FRT Position */ 703 #define USBH_HcFmRemaining_FRT_Msk (0x1ul << USBH_HcFmRemaining_FRT_Pos) /*!< USBH_T::HcFmRemaining: FRT Mask */ 704 705 #define USBH_HcFmNumber_FN_Pos (0) /*!< USBH_T::HcFmNumber: FN Position */ 706 #define USBH_HcFmNumber_FN_Msk (0xfffful << USBH_HcFmNumber_FN_Pos) /*!< USBH_T::HcFmNumber: FN Mask */ 707 708 #define USBH_HcPeriodicStart_PS_Pos (0) /*!< USBH_T::HcPeriodicStart: PS Position */ 709 #define USBH_HcPeriodicStart_PS_Msk (0x3ffful << USBH_HcPeriodicStart_PS_Pos) /*!< USBH_T::HcPeriodicStart: PS Mask */ 710 711 #define USBH_HcLSThreshold_LST_Pos (0) /*!< USBH_T::HcLSThreshold: LST Position */ 712 #define USBH_HcLSThreshold_LST_Msk (0xffful << USBH_HcLSThreshold_LST_Pos) /*!< USBH_T::HcLSThreshold: LST Mask */ 713 714 #define USBH_HcRhDescriptorA_NDP_Pos (0) /*!< USBH_T::HcRhDescriptorA: NDP Position */ 715 #define USBH_HcRhDescriptorA_NDP_Msk (0xfful << USBH_HcRhDescriptorA_NDP_Pos) /*!< USBH_T::HcRhDescriptorA: NDP Mask */ 716 717 #define USBH_HcRhDescriptorA_PSM_Pos (8) /*!< USBH_T::HcRhDescriptorA: PSM Position */ 718 #define USBH_HcRhDescriptorA_PSM_Msk (0x1ul << USBH_HcRhDescriptorA_PSM_Pos) /*!< USBH_T::HcRhDescriptorA: PSM Mask */ 719 720 #define USBH_HcRhDescriptorA_OCPM_Pos (11) /*!< USBH_T::HcRhDescriptorA: OCPM Position */ 721 #define USBH_HcRhDescriptorA_OCPM_Msk (0x1ul << USBH_HcRhDescriptorA_OCPM_Pos) /*!< USBH_T::HcRhDescriptorA: OCPM Mask */ 722 723 #define USBH_HcRhDescriptorA_NOCP_Pos (12) /*!< USBH_T::HcRhDescriptorA: NOCP Position */ 724 #define USBH_HcRhDescriptorA_NOCP_Msk (0x1ul << USBH_HcRhDescriptorA_NOCP_Pos) /*!< USBH_T::HcRhDescriptorA: NOCP Mask */ 725 726 #define USBH_HcRhDescriptorB_PPCM_Pos (16) /*!< USBH_T::HcRhDescriptorB: PPCM Position */ 727 #define USBH_HcRhDescriptorB_PPCM_Msk (0xfffful << USBH_HcRhDescriptorB_PPCM_Pos) /*!< USBH_T::HcRhDescriptorB: PPCM Mask */ 728 729 #define USBH_HcRhStatus_LPS_Pos (0) /*!< USBH_T::HcRhStatus: LPS Position */ 730 #define USBH_HcRhStatus_LPS_Msk (0x1ul << USBH_HcRhStatus_LPS_Pos) /*!< USBH_T::HcRhStatus: LPS Mask */ 731 732 #define USBH_HcRhStatus_OCI_Pos (1) /*!< USBH_T::HcRhStatus: OCI Position */ 733 #define USBH_HcRhStatus_OCI_Msk (0x1ul << USBH_HcRhStatus_OCI_Pos) /*!< USBH_T::HcRhStatus: OCI Mask */ 734 735 #define USBH_HcRhStatus_DRWE_Pos (15) /*!< USBH_T::HcRhStatus: DRWE Position */ 736 #define USBH_HcRhStatus_DRWE_Msk (0x1ul << USBH_HcRhStatus_DRWE_Pos) /*!< USBH_T::HcRhStatus: DRWE Mask */ 737 738 #define USBH_HcRhStatus_LPSC_Pos (16) /*!< USBH_T::HcRhStatus: LPSC Position */ 739 #define USBH_HcRhStatus_LPSC_Msk (0x1ul << USBH_HcRhStatus_LPSC_Pos) /*!< USBH_T::HcRhStatus: LPSC Mask */ 740 741 #define USBH_HcRhStatus_OCIC_Pos (17) /*!< USBH_T::HcRhStatus: OCIC Position */ 742 #define USBH_HcRhStatus_OCIC_Msk (0x1ul << USBH_HcRhStatus_OCIC_Pos) /*!< USBH_T::HcRhStatus: OCIC Mask */ 743 744 #define USBH_HcRhStatus_CRWE_Pos (31) /*!< USBH_T::HcRhStatus: CRWE Position */ 745 #define USBH_HcRhStatus_CRWE_Msk (0x1ul << USBH_HcRhStatus_CRWE_Pos) /*!< USBH_T::HcRhStatus: CRWE Mask */ 746 747 #define USBH_HcRhPortStatus_CCS_Pos (0) /*!< USBH_T::HcRhPortStatus: CCS Position */ 748 #define USBH_HcRhPortStatus_CCS_Msk (0x1ul << USBH_HcRhPortStatus_CCS_Pos) /*!< USBH_T::HcRhPortStatus: CCS Mask */ 749 750 #define USBH_HcRhPortStatus_PES_Pos (1) /*!< USBH_T::HcRhPortStatus: PES Position */ 751 #define USBH_HcRhPortStatus_PES_Msk (0x1ul << USBH_HcRhPortStatus_PES_Pos) /*!< USBH_T::HcRhPortStatus: PES Mask */ 752 753 #define USBH_HcRhPortStatus_PSS_Pos (2) /*!< USBH_T::HcRhPortStatus: PSS Position */ 754 #define USBH_HcRhPortStatus_PSS_Msk (0x1ul << USBH_HcRhPortStatus_PSS_Pos) /*!< USBH_T::HcRhPortStatus: PSS Mask */ 755 756 #define USBH_HcRhPortStatus_POCI_Pos (3) /*!< USBH_T::HcRhPortStatus: POCI Position */ 757 #define USBH_HcRhPortStatus_POCI_Msk (0x1ul << USBH_HcRhPortStatus_POCI_Pos) /*!< USBH_T::HcRhPortStatus: POCI Mask */ 758 759 #define USBH_HcRhPortStatus_PRS_Pos (4) /*!< USBH_T::HcRhPortStatus: PRS Position */ 760 #define USBH_HcRhPortStatus_PRS_Msk (0x1ul << USBH_HcRhPortStatus_PRS_Pos) /*!< USBH_T::HcRhPortStatus: PRS Mask */ 761 762 #define USBH_HcRhPortStatus_PPS_Pos (8) /*!< USBH_T::HcRhPortStatus: PPS Position */ 763 #define USBH_HcRhPortStatus_PPS_Msk (0x1ul << USBH_HcRhPortStatus_PPS_Pos) /*!< USBH_T::HcRhPortStatus: PPS Mask */ 764 765 #define USBH_HcRhPortStatus_LSDA_Pos (9) /*!< USBH_T::HcRhPortStatus: LSDA Position */ 766 #define USBH_HcRhPortStatus_LSDA_Msk (0x1ul << USBH_HcRhPortStatus_LSDA_Pos) /*!< USBH_T::HcRhPortStatus: LSDA Mask */ 767 768 #define USBH_HcRhPortStatus_CSC_Pos (16) /*!< USBH_T::HcRhPortStatus: CSC Position */ 769 #define USBH_HcRhPortStatus_CSC_Msk (0x1ul << USBH_HcRhPortStatus_CSC_Pos) /*!< USBH_T::HcRhPortStatus: CSC Mask */ 770 771 #define USBH_HcRhPortStatus_PESC_Pos (17) /*!< USBH_T::HcRhPortStatus: PESC Position */ 772 #define USBH_HcRhPortStatus_PESC_Msk (0x1ul << USBH_HcRhPortStatus_PESC_Pos) /*!< USBH_T::HcRhPortStatus: PESC Mask */ 773 774 #define USBH_HcRhPortStatus_PSSC_Pos (18) /*!< USBH_T::HcRhPortStatus: PSSC Position */ 775 #define USBH_HcRhPortStatus_PSSC_Msk (0x1ul << USBH_HcRhPortStatus_PSSC_Pos) /*!< USBH_T::HcRhPortStatus: PSSC Mask */ 776 777 #define USBH_HcRhPortStatus_OCIC_Pos (19) /*!< USBH_T::HcRhPortStatus: OCIC Position */ 778 #define USBH_HcRhPortStatus_OCIC_Msk (0x1ul << USBH_HcRhPortStatus_OCIC_Pos) /*!< USBH_T::HcRhPortStatus: OCIC Mask */ 779 780 #define USBH_HcRhPortStatus_PRSC_Pos (20) /*!< USBH_T::HcRhPortStatus: PRSC Position */ 781 #define USBH_HcRhPortStatus_PRSC_Msk (0x1ul << USBH_HcRhPortStatus_PRSC_Pos) /*!< USBH_T::HcRhPortStatus: PRSC Mask */ 782 783 #define USBH_HcPhyControl_STBYEN_Pos (27) /*!< USBH_T::HcPhyControl: STBYEN Position */ 784 #define USBH_HcPhyControl_STBYEN_Msk (0x1ul << USBH_HcPhyControl_STBYEN_Pos) /*!< USBH_T::HcPhyControl: STBYEN Mask */ 785 786 #define USBH_HcMiscControl_ABORT_Pos (1) /*!< USBH_T::HcMiscControl: ABORT Position */ 787 #define USBH_HcMiscControl_ABORT_Msk (0x1ul << USBH_HcMiscControl_ABORT_Pos) /*!< USBH_T::HcMiscControl: ABORT Mask */ 788 789 #define USBH_HcMiscControl_OCAL_Pos (3) /*!< USBH_T::HcMiscControl: OCAL Position */ 790 #define USBH_HcMiscControl_OCAL_Msk (0x1ul << USBH_HcMiscControl_OCAL_Pos) /*!< USBH_T::HcMiscControl: OCAL Mask */ 791 792 #define USBH_HcMiscControl_DPRT1_Pos (16) /*!< USBH_T::HcMiscControl: DPRT1 Position */ 793 #define USBH_HcMiscControl_DPRT1_Msk (0x1ul << USBH_HcMiscControl_DPRT1_Pos) /*!< USBH_T::HcMiscControl: DPRT1 Mask */ 794 795 /**@}*/ /* USBH_CONST */ 796 /**@}*/ /* end of USBH register group */ 797 /**@}*/ /* end of REGISTER group */ 798 799 #endif /* __USBH_REG_H__ */ 800
