1/*
2 * Copyright 2023 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <nxp/s32/S32K146_LQFP64-pinctrl.h>
8
9&pinctrl {
10	lpuart0_default: lpuart0_default {
11		group0 {
12			pinmux = <LPUART0_RX_PTB0>, <LPUART0_TX_PTB1>;
13			drive-strength = "low";
14		};
15	};
16
17	lpuart1_default: lpuart1_default {
18		group0 {
19			pinmux = <LPUART1_RX_PTC6>, <LPUART1_TX_PTC7>;
20			drive-strength = "low";
21		};
22	};
23
24	lpi2c0_default: lpi2c0_default {
25		group1 {
26			pinmux = <LPI2C0_SDA_PTA2>, <LPI2C0_SCL_PTA3>;
27			drive-strength = "low";
28		};
29	};
30
31	lpspi0_default: lpspi0_default {
32		group0 {
33			pinmux = <LPSPI0_SCK_PTB2>,
34				<LPSPI0_SIN_PTB3>,
35				<LPSPI0_SOUT_PTB4>,
36				<LPSPI0_PCS0_PTB5>;
37			drive-strength = "low";
38		};
39	};
40
41	ftm0_default: ftm0_default {
42		group0 {
43			pinmux = <FTM0_CH0_PTD15>,
44				<FTM0_CH1_PTD16>,
45				<FTM0_CH2_PTD0>;
46			drive-strength = "low";
47		};
48	};
49
50	ftm1_default: ftm1_default {
51		group0 {
52			pinmux = <FTM1_CH1_PTA1>;
53			drive-strength = "low";
54		};
55	};
56
57	ftm2_default: ftm2_default {
58		group0 {
59			pinmux = <FTM2_CH1_PTA0>;
60			drive-strength = "low";
61		};
62	};
63
64	flexcan0_default: flexcan0_default {
65		group0 {
66			pinmux = <CAN0_RX_PTE4>, <CAN0_TX_PTE5>;
67			drive-strength = "low";
68		};
69	};
70
71	flexcan1_default: flexcan1_default {
72		group0 {
73			pinmux = <CAN1_RX_PTA12>, <CAN1_TX_PTA13>;
74			drive-strength = "low";
75		};
76	};
77};
78