1 /*
2 * Copyright (c) 2023 Antmicro <www.antmicro.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include "uart_rzt2m.h"
8 #include "zephyr/spinlock.h"
9 #include "zephyr/sys/printk.h"
10 #include <zephyr/drivers/uart.h>
11 #include <zephyr/drivers/pinctrl.h>
12 #include <zephyr/sys/util.h>
13 #include <zephyr/irq.h>
14 #include <stdint.h>
15 #include <zephyr/logging/log.h>
16 #include <soc.h>
17
18 #define DT_DRV_COMPAT renesas_rzt2m_uart
19
20 LOG_MODULE_REGISTER(uart_renesas_rzt2m, CONFIG_UART_LOG_LEVEL);
21
22 struct rzt2m_device_config {
23 mm_reg_t base;
24 const struct pinctrl_dev_config *pin_config;
25 uart_irq_config_func_t irq_config_func;
26 };
27
28 struct rzt2m_device_data {
29 struct uart_config uart_cfg;
30 struct k_spinlock lock;
31 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
32 uart_irq_callback_user_data_t callback;
33 void *callback_data;
34 #endif
35 };
36
rzt2m_poll_in(const struct device * dev,unsigned char * c)37 static int rzt2m_poll_in(const struct device *dev, unsigned char *c)
38 {
39 if (!dev || !dev->config || !dev->data) {
40 return -ENODEV;
41 }
42
43 const struct rzt2m_device_config *config = dev->config;
44 struct rzt2m_device_data *data = dev->data;
45
46 k_spinlock_key_t key = k_spin_lock(&data->lock);
47
48 if (FRSR_R(*FRSR(config->base)) == 0) {
49 k_spin_unlock(&data->lock, key);
50 return -1;
51 }
52 *c = *RDR(config->base) & RDR_MASK_RDAT;
53 *CFCLR(config->base) |= CFCLR_MASK_RDRFC;
54
55 if (FRSR_R(*FRSR(config->base)) == 0) {
56 *FFCLR(config->base) |= FFCLR_MASK_DRC;
57 }
58
59 k_spin_unlock(&data->lock, key);
60 return 0;
61 }
62
rzt2m_poll_out(const struct device * dev,unsigned char c)63 static void rzt2m_poll_out(const struct device *dev, unsigned char c)
64 {
65 if (!dev || !dev->config || !dev->data) {
66 return;
67 }
68
69 const struct rzt2m_device_config *config = dev->config;
70 struct rzt2m_device_data *data = dev->data;
71
72 k_spinlock_key_t key = k_spin_lock(&data->lock);
73
74 int fifo_count = FTSR_T(*FTSR(config->base));
75
76 while (fifo_count == MAX_FIFO_DEPTH) {
77 fifo_count = FTSR_T(*FTSR(config->base));
78 }
79
80 *TDR(config->base) = c;
81
82 /* Clear `Transmit data empty flag`. */
83 *CFCLR(config->base) |= CFCLR_MASK_TDREC;
84
85 k_spin_unlock(&data->lock, key);
86 }
87
rzt2m_err_check(const struct device * dev)88 static int rzt2m_err_check(const struct device *dev)
89 {
90 const struct rzt2m_device_config *config = dev->config;
91
92 uint32_t status = *CSR(config->base);
93 uint32_t retval = 0;
94
95 if (status & CSR_MASK_ORER) {
96 retval |= UART_ERROR_OVERRUN;
97 }
98 if (status & CSR_MASK_FER) {
99 retval |= UART_ERROR_FRAMING;
100 }
101 if (status & CSR_MASK_PER) {
102 retval |= UART_ERROR_PARITY;
103 }
104
105 return retval;
106 }
107
108 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
109 static int uart_rzt2m_irq_tx_ready(const struct device *dev);
110
rzt2m_fifo_fill(const struct device * dev,const uint8_t * tx_data,int size)111 static int rzt2m_fifo_fill(const struct device *dev, const uint8_t *tx_data, int size)
112 {
113 struct rzt2m_device_data *data = dev->data;
114 const struct rzt2m_device_config *config = dev->config;
115 int num_tx = 0;
116 k_spinlock_key_t key = k_spin_lock(&data->lock);
117
118 while ((size - num_tx > 0) && uart_rzt2m_irq_tx_ready(dev)) {
119 *TDR(config->base) = (uint8_t)tx_data[num_tx++];
120 }
121
122 k_spin_unlock(&data->lock, key);
123 return num_tx;
124 }
125
rzt2m_fifo_read(const struct device * dev,uint8_t * rx_data,const int size)126 static int rzt2m_fifo_read(const struct device *dev, uint8_t *rx_data, const int size)
127 {
128 struct rzt2m_device_data *data = dev->data;
129 const struct rzt2m_device_config *config = dev->config;
130 int num_rx = 0;
131 k_spinlock_key_t key = k_spin_lock(&data->lock);
132
133 while (num_rx < size && (FRSR_R(*FRSR(config->base)))) {
134 rx_data[num_rx++] = *RDR(config->base);
135 }
136 *CFCLR(config->base) = CFCLR_MASK_RDRFC;
137 *FFCLR(config->base) = FFCLR_MASK_DRC;
138 k_spin_unlock(&data->lock, key);
139 return num_rx;
140 }
141
uart_rzt2m_irq_rx_enable(const struct device * dev)142 static void uart_rzt2m_irq_rx_enable(const struct device *dev)
143 {
144 const struct rzt2m_device_config *config = dev->config;
145 *CCR0(config->base) |= CCR0_MASK_RIE | CCR0_MASK_RE;
146 }
147
uart_rzt2m_irq_rx_disable(const struct device * dev)148 static void uart_rzt2m_irq_rx_disable(const struct device *dev)
149 {
150 const struct rzt2m_device_config *config = dev->config;
151 *CCR0(config->base) &= ~CCR0_MASK_RIE;
152 }
153
uart_rzt2m_irq_tx_enable(const struct device * dev)154 static void uart_rzt2m_irq_tx_enable(const struct device *dev)
155 {
156 const struct rzt2m_device_config *config = dev->config;
157 /* These bits must be set simultaneously. */
158 *CCR0(config->base) |= CCR0_MASK_TE | CCR0_MASK_TIE | CCR0_MASK_TEIE;
159 }
160
uart_rzt2m_irq_tx_disable(const struct device * dev)161 static void uart_rzt2m_irq_tx_disable(const struct device *dev)
162 {
163 const struct rzt2m_device_config *config = dev->config;
164 *CCR0(config->base) &= ~(CCR0_MASK_TIE | CCR0_MASK_TEIE);
165 }
166
uart_rzt2m_irq_tx_ready(const struct device * dev)167 static int uart_rzt2m_irq_tx_ready(const struct device *dev)
168 {
169 const struct rzt2m_device_config *config = dev->config;
170
171 if (FTSR_T(*FTSR(config->base)) == MAX_FIFO_DEPTH ||
172 ((*CCR0(config->base) & CCR0_MASK_TIE) == 0)) {
173 return 0;
174 }
175
176 return 1;
177 }
178
uart_rzt2m_irq_rx_ready(const struct device * dev)179 static int uart_rzt2m_irq_rx_ready(const struct device *dev)
180 {
181 const struct rzt2m_device_config *config = dev->config;
182
183 if (FRSR_R(*FRSR(config->base))) {
184 return 1;
185 }
186
187 return 0;
188 }
189
uart_rzt2m_irq_is_pending(const struct device * dev)190 static int uart_rzt2m_irq_is_pending(const struct device *dev)
191 {
192 const struct rzt2m_device_config *config = dev->config;
193
194 if ((*CSR(config->base) & (CSR_MASK_RDRF)) || (*FRSR(config->base) & FRSR_MASK_DR)) {
195 return 1;
196 }
197 return 0;
198 }
199
uart_rzt2m_irq_callback_set(const struct device * dev,uart_irq_callback_user_data_t cb,void * cb_data)200 static void uart_rzt2m_irq_callback_set(const struct device *dev, uart_irq_callback_user_data_t cb,
201 void *cb_data)
202 {
203 struct rzt2m_device_data *data = dev->data;
204
205 data->callback = cb;
206 data->callback_data = cb_data;
207 }
208
uart_rzt2m_irq_update(const struct device * dev)209 static int uart_rzt2m_irq_update(const struct device *dev)
210 {
211 const struct rzt2m_device_config *config = dev->config;
212
213 *CFCLR(config->base) = CFCLR_MASK_RDRFC;
214 *FFCLR(config->base) = FFCLR_MASK_DRC;
215 return 1;
216 }
217 #endif /* CONFIG_UART_INTERRUPT_DRIVEN */
218
219 static DEVICE_API(uart, rzt2m_uart_api) = {
220 .poll_in = rzt2m_poll_in,
221 .poll_out = rzt2m_poll_out,
222 .err_check = rzt2m_err_check,
223 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
224 .fifo_fill = rzt2m_fifo_fill,
225 .fifo_read = rzt2m_fifo_read,
226 .irq_rx_enable = uart_rzt2m_irq_rx_enable,
227 .irq_rx_disable = uart_rzt2m_irq_rx_disable,
228 .irq_tx_enable = uart_rzt2m_irq_tx_enable,
229 .irq_tx_disable = uart_rzt2m_irq_tx_disable,
230 .irq_tx_ready = uart_rzt2m_irq_tx_ready,
231 .irq_rx_ready = uart_rzt2m_irq_rx_ready,
232 .irq_is_pending = uart_rzt2m_irq_is_pending,
233 .irq_callback_set = uart_rzt2m_irq_callback_set,
234 .irq_update = uart_rzt2m_irq_update,
235 #endif /* CONFIG_UART_INTERRUPT_DRIVEN */
236 };
237
rzt2m_module_start(const struct device * dev)238 static int rzt2m_module_start(const struct device *dev)
239 {
240 if (!dev || !dev->config || !dev->data) {
241 return -ENODEV;
242 }
243
244 const struct rzt2m_device_config *config = dev->config;
245 struct rzt2m_device_data *data = dev->data;
246 int interface_id = BASE_TO_IFACE_ID(config->base);
247 unsigned int irqkey = irq_lock();
248 volatile uint32_t dummy;
249
250 k_spinlock_key_t key = k_spin_lock(&data->lock);
251
252 if (interface_id < 5) {
253 /* Dummy-read at least one time as stated in 8.3.1 of the User's Manual: Hardware */
254 *MSTPCRA &= ~(MSTPCRA_MASK_SCIx(interface_id));
255 dummy = *MSTPCRA;
256 } else {
257 LOG_ERR("SCI modules in the secure domain on RZT2M are not supported.");
258 return -ENOTSUP;
259 }
260
261 /* Dummy-read at least five times as stated in 8.3.1 of the User's Manual: Hardware */
262 dummy = *RDR(config->base);
263 dummy = *RDR(config->base);
264 dummy = *RDR(config->base);
265 dummy = *RDR(config->base);
266 dummy = *RDR(config->base);
267
268 k_spin_unlock(&data->lock, key);
269 irq_unlock(irqkey);
270 return 0;
271 }
272
rzt2m_uart_init(const struct device * dev)273 static int rzt2m_uart_init(const struct device *dev)
274 {
275 const struct rzt2m_device_config *config = dev->config;
276 struct rzt2m_device_data *data = dev->data;
277 uint32_t baud_setting = 0;
278 uint32_t baud_settings[] = {CCR2_BAUD_SETTING_9600, CCR2_BAUD_SETTING_115200};
279
280 rzt2m_unlock_prcrs(PRCRS_GPIO);
281 rzt2m_unlock_prcrn(PRCRN_PRC1 | PRCRN_PRC2);
282
283 /* The module needs to be started
284 * to allow any operation on the registers of Serial Communications Interface.
285 */
286 int ret = rzt2m_module_start(dev);
287
288 if (ret) {
289 return ret;
290 }
291
292 /* Disable transmitter, receiver, interrupts. */
293 *CCR0(config->base) = CCR0_DEFAULT_VALUE;
294 while (*CCR0(config->base) & (CCR0_MASK_RE | CCR0_MASK_TE)) {
295 }
296
297 *CCR1(config->base) = CCR1_DEFAULT_VALUE;
298 *CCR2(config->base) = CCR2_DEFAULT_VALUE;
299 *CCR3(config->base) = CCR3_DEFAULT_VALUE;
300 *CCR4(config->base) = CCR4_DEFAULT_VALUE;
301
302 /* Configure pinmuxes */
303 ret = pinctrl_apply_state(config->pin_config, PINCTRL_STATE_DEFAULT);
304 if (ret) {
305 return ret;
306 }
307
308 *CFCLR(config->base) = CFCLR_ALL_FLAG_CLEAR;
309 *FFCLR(config->base) = FFCLR_MASK_DRC;
310
311 /* Use FIFO mode. */
312 *CCR3(config->base) |= (CCR3_MASK_FM);
313
314 switch (data->uart_cfg.stop_bits) {
315 case UART_CFG_STOP_BITS_1:
316 /* Default value, already set. */
317 break;
318 case UART_CFG_STOP_BITS_2:
319 *CCR3(config->base) |= CCR3_MASK_STP;
320 break;
321 default:
322 LOG_ERR("Selected bit stop length is not supported: %u.", data->uart_cfg.stop_bits);
323 return -ENOTSUP;
324 }
325
326 switch (data->uart_cfg.data_bits) {
327 case UART_CFG_DATA_BITS_7:
328 *CCR3(config->base) |= CCR3_CHR_7BIT;
329 break;
330 case UART_CFG_DATA_BITS_8:
331 *CCR3(config->base) |= CCR3_CHR_8BIT;
332 break;
333 default:
334 LOG_ERR("Selected number of data bits is not supported: %u.",
335 data->uart_cfg.data_bits);
336 return -ENOTSUP;
337 }
338
339 if (data->uart_cfg.baudrate > ARRAY_SIZE(baud_settings)) {
340 LOG_ERR("Selected baudrate variant is not supported: %u.", data->uart_cfg.baudrate);
341 return -ENOTSUP;
342 }
343 baud_setting = baud_settings[data->uart_cfg.baudrate];
344
345 *CCR2(config->base) &= ~(CCR2_MASK_BAUD_SETTING);
346 *CCR2(config->base) |= (baud_setting & CCR2_MASK_BAUD_SETTING);
347
348 *CCR1(config->base) |= (CCR1_MASK_NFEN | CCR1_MASK_SPB2DT | CCR1_MASK_SPB2IO);
349
350 switch (data->uart_cfg.parity) {
351 case UART_CFG_PARITY_NONE:
352 /* Default value, already set. */
353 break;
354 case UART_CFG_PARITY_EVEN:
355 *CCR1(config->base) |= CCR1_MASK_PE;
356 break;
357 case UART_CFG_PARITY_ODD:
358 *CCR1(config->base) |= (CCR1_MASK_PE | CCR1_MASK_PM);
359 break;
360 default:
361 LOG_ERR("Unsupported parity: %u", data->uart_cfg.parity);
362 }
363
364 /* Specify trigger thresholds and clear FIFOs. */
365 *FCR(config->base) = FCR_MASK_TFRST | FCR_MASK_RFRST | FCR_TTRG_15 | FCR_RTRG_15;
366
367 /* Enable the clock. */
368 *CCR3(config->base) &= ~CCR3_MASK_CKE;
369 *CCR3(config->base) |= CCR3_CKE_ENABLE;
370
371 /* Clear status flags. */
372 *CFCLR(config->base) = CFCLR_ALL_FLAG_CLEAR;
373 *FFCLR(config->base) = FFCLR_MASK_DRC;
374
375 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
376 config->irq_config_func(dev);
377 #endif /* CONFIG_UART_INTERRUPT_DRIVEN */
378
379 /* Start transmitter and receiver. */
380 *CCR0(config->base) |= (CCR0_MASK_TE | CCR0_MASK_RE);
381 while (!(*CCR0(config->base) & CCR0_MASK_RE)) {
382 }
383 while (!(*CCR0(config->base) & CCR0_MASK_TE)) {
384 }
385
386 rzt2m_lock_prcrs(PRCRS_GPIO);
387 rzt2m_lock_prcrn(PRCRN_PRC1 | PRCRN_PRC2);
388
389 return 0;
390 }
391
uart_rzt2m_isr(const struct device * dev)392 static void uart_rzt2m_isr(const struct device *dev)
393 {
394 const struct rzt2m_device_config *config = dev->config;
395 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
396 struct rzt2m_device_data *data = dev->data;
397
398 if (data->callback) {
399 data->callback(dev, data->callback_data);
400 }
401 #endif /* CONFIG_UART_INTERRUPT_DRIVEN */
402
403 *CFCLR(config->base) = CFCLR_MASK_RDRFC;
404 *FFCLR(config->base) = FFCLR_MASK_DRC;
405 }
406
407 #define UART_RZT2M_IRQ_CONNECT(n, irq_name) \
408 do { \
409 IRQ_CONNECT(DT_INST_IRQ_BY_NAME(n, irq_name, irq), \
410 DT_INST_IRQ_BY_NAME(n, irq_name, priority), uart_rzt2m_isr, \
411 DEVICE_DT_INST_GET(n), DT_INST_IRQ_BY_NAME(n, irq_name, flags)); \
412 irq_enable(DT_INST_IRQ_BY_NAME(n, irq_name, irq)); \
413 } while (false)
414
415 #define UART_RZT2M_CONFIG_FUNC(n) \
416 static void uart##n##_rzt2m_irq_config(const struct device *port) \
417 { \
418 UART_RZT2M_IRQ_CONNECT(n, rx_err); \
419 UART_RZT2M_IRQ_CONNECT(n, rx); \
420 UART_RZT2M_IRQ_CONNECT(n, tx); \
421 UART_RZT2M_IRQ_CONNECT(n, tx_end); \
422 }
423
424 #define UART_RZT2M_INIT(n) \
425 PINCTRL_DT_INST_DEFINE(n); \
426 static struct rzt2m_device_data rzt2m_uart_##n##data = { \
427 .uart_cfg = \
428 { \
429 .baudrate = DT_INST_ENUM_IDX(n, current_speed), \
430 .parity = DT_INST_ENUM_IDX_OR(n, parity, UART_CFG_PARITY_NONE), \
431 .stop_bits = \
432 DT_INST_ENUM_IDX_OR(n, stop_bits, UART_CFG_STOP_BITS_1), \
433 .data_bits = \
434 DT_INST_ENUM_IDX_OR(n, data_bits, UART_CFG_DATA_BITS_8), \
435 }, \
436 }; \
437 UART_RZT2M_CONFIG_FUNC(n); \
438 static const struct rzt2m_device_config rzt2m_uart_##n##_config = { \
439 .base = DT_INST_REG_ADDR(n), \
440 .irq_config_func = uart##n##_rzt2m_irq_config, \
441 .pin_config = PINCTRL_DT_INST_DEV_CONFIG_GET(n)}; \
442 DEVICE_DT_INST_DEFINE(n, rzt2m_uart_init, NULL, &rzt2m_uart_##n##data, \
443 &rzt2m_uart_##n##_config, PRE_KERNEL_1, CONFIG_SERIAL_INIT_PRIORITY, \
444 &rzt2m_uart_api);
445
446 DT_INST_FOREACH_STATUS_OKAY(UART_RZT2M_INIT)
447
