1 /***************************************************************************//** 2 * \file tviibe1m_config.h 3 * 4 * \brief 5 * TVIIBE1M device configuration header 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _TVIIBE1M_CONFIG_H_ 28 #define _TVIIBE1M_CONFIG_H_ 29 30 /* Clock Connections */ 31 typedef enum 32 { 33 PCLK_CPUSS_CLOCK_TRACE_IN = 0x0000u, /* cpuss.clock_trace_in */ 34 PCLK_SMARTIO12_CLOCK = 0x0001u, /* smartio[12].clock */ 35 PCLK_SMARTIO13_CLOCK = 0x0002u, /* smartio[13].clock */ 36 PCLK_SMARTIO14_CLOCK = 0x0003u, /* smartio[14].clock */ 37 PCLK_SMARTIO15_CLOCK = 0x0004u, /* smartio[15].clock */ 38 PCLK_SMARTIO17_CLOCK = 0x0005u, /* smartio[17].clock */ 39 PCLK_CANFD0_CLOCK_CAN0 = 0x0006u, /* canfd[0].clock_can[0] */ 40 PCLK_CANFD0_CLOCK_CAN1 = 0x0007u, /* canfd[0].clock_can[1] */ 41 PCLK_CANFD0_CLOCK_CAN2 = 0x0008u, /* canfd[0].clock_can[2] */ 42 PCLK_CANFD1_CLOCK_CAN0 = 0x0009u, /* canfd[1].clock_can[0] */ 43 PCLK_CANFD1_CLOCK_CAN1 = 0x000Au, /* canfd[1].clock_can[1] */ 44 PCLK_CANFD1_CLOCK_CAN2 = 0x000Bu, /* canfd[1].clock_can[2] */ 45 PCLK_LIN0_CLOCK_CH_EN0 = 0x000Cu, /* lin[0].clock_ch_en[0] */ 46 PCLK_LIN0_CLOCK_CH_EN1 = 0x000Du, /* lin[0].clock_ch_en[1] */ 47 PCLK_LIN0_CLOCK_CH_EN2 = 0x000Eu, /* lin[0].clock_ch_en[2] */ 48 PCLK_LIN0_CLOCK_CH_EN3 = 0x000Fu, /* lin[0].clock_ch_en[3] */ 49 PCLK_LIN0_CLOCK_CH_EN4 = 0x0010u, /* lin[0].clock_ch_en[4] */ 50 PCLK_LIN0_CLOCK_CH_EN5 = 0x0011u, /* lin[0].clock_ch_en[5] */ 51 PCLK_LIN0_CLOCK_CH_EN6 = 0x0012u, /* lin[0].clock_ch_en[6] */ 52 PCLK_LIN0_CLOCK_CH_EN7 = 0x0013u, /* lin[0].clock_ch_en[7] */ 53 PCLK_SCB0_CLOCK = 0x0014u, /* scb[0].clock */ 54 PCLK_SCB1_CLOCK = 0x0015u, /* scb[1].clock */ 55 PCLK_SCB2_CLOCK = 0x0016u, /* scb[2].clock */ 56 PCLK_SCB3_CLOCK = 0x0017u, /* scb[3].clock */ 57 PCLK_SCB4_CLOCK = 0x0018u, /* scb[4].clock */ 58 PCLK_SCB5_CLOCK = 0x0019u, /* scb[5].clock */ 59 PCLK_SCB6_CLOCK = 0x001Au, /* scb[6].clock */ 60 PCLK_SCB7_CLOCK = 0x001Bu, /* scb[7].clock */ 61 PCLK_PASS0_CLOCK_SAR0 = 0x001Cu, /* pass[0].clock_sar[0] */ 62 PCLK_PASS0_CLOCK_SAR1 = 0x001Du, /* pass[0].clock_sar[1] */ 63 PCLK_PASS0_CLOCK_SAR2 = 0x001Eu, /* pass[0].clock_sar[2] */ 64 PCLK_TCPWM0_CLOCKS0 = 0x001Fu, /* tcpwm[0].clocks[0] */ 65 PCLK_TCPWM0_CLOCKS1 = 0x0020u, /* tcpwm[0].clocks[1] */ 66 PCLK_TCPWM0_CLOCKS2 = 0x0021u, /* tcpwm[0].clocks[2] */ 67 PCLK_TCPWM0_CLOCKS3 = 0x0022u, /* tcpwm[0].clocks[3] */ 68 PCLK_TCPWM0_CLOCKS4 = 0x0023u, /* tcpwm[0].clocks[4] */ 69 PCLK_TCPWM0_CLOCKS5 = 0x0024u, /* tcpwm[0].clocks[5] */ 70 PCLK_TCPWM0_CLOCKS6 = 0x0025u, /* tcpwm[0].clocks[6] */ 71 PCLK_TCPWM0_CLOCKS7 = 0x0026u, /* tcpwm[0].clocks[7] */ 72 PCLK_TCPWM0_CLOCKS8 = 0x0027u, /* tcpwm[0].clocks[8] */ 73 PCLK_TCPWM0_CLOCKS9 = 0x0028u, /* tcpwm[0].clocks[9] */ 74 PCLK_TCPWM0_CLOCKS10 = 0x0029u, /* tcpwm[0].clocks[10] */ 75 PCLK_TCPWM0_CLOCKS11 = 0x002Au, /* tcpwm[0].clocks[11] */ 76 PCLK_TCPWM0_CLOCKS12 = 0x002Bu, /* tcpwm[0].clocks[12] */ 77 PCLK_TCPWM0_CLOCKS13 = 0x002Cu, /* tcpwm[0].clocks[13] */ 78 PCLK_TCPWM0_CLOCKS14 = 0x002Du, /* tcpwm[0].clocks[14] */ 79 PCLK_TCPWM0_CLOCKS15 = 0x002Eu, /* tcpwm[0].clocks[15] */ 80 PCLK_TCPWM0_CLOCKS16 = 0x002Fu, /* tcpwm[0].clocks[16] */ 81 PCLK_TCPWM0_CLOCKS17 = 0x0030u, /* tcpwm[0].clocks[17] */ 82 PCLK_TCPWM0_CLOCKS18 = 0x0031u, /* tcpwm[0].clocks[18] */ 83 PCLK_TCPWM0_CLOCKS19 = 0x0032u, /* tcpwm[0].clocks[19] */ 84 PCLK_TCPWM0_CLOCKS20 = 0x0033u, /* tcpwm[0].clocks[20] */ 85 PCLK_TCPWM0_CLOCKS21 = 0x0034u, /* tcpwm[0].clocks[21] */ 86 PCLK_TCPWM0_CLOCKS22 = 0x0035u, /* tcpwm[0].clocks[22] */ 87 PCLK_TCPWM0_CLOCKS23 = 0x0036u, /* tcpwm[0].clocks[23] */ 88 PCLK_TCPWM0_CLOCKS24 = 0x0037u, /* tcpwm[0].clocks[24] */ 89 PCLK_TCPWM0_CLOCKS25 = 0x0038u, /* tcpwm[0].clocks[25] */ 90 PCLK_TCPWM0_CLOCKS26 = 0x0039u, /* tcpwm[0].clocks[26] */ 91 PCLK_TCPWM0_CLOCKS27 = 0x003Au, /* tcpwm[0].clocks[27] */ 92 PCLK_TCPWM0_CLOCKS28 = 0x003Bu, /* tcpwm[0].clocks[28] */ 93 PCLK_TCPWM0_CLOCKS29 = 0x003Cu, /* tcpwm[0].clocks[29] */ 94 PCLK_TCPWM0_CLOCKS30 = 0x003Du, /* tcpwm[0].clocks[30] */ 95 PCLK_TCPWM0_CLOCKS31 = 0x003Eu, /* tcpwm[0].clocks[31] */ 96 PCLK_TCPWM0_CLOCKS32 = 0x003Fu, /* tcpwm[0].clocks[32] */ 97 PCLK_TCPWM0_CLOCKS33 = 0x0040u, /* tcpwm[0].clocks[33] */ 98 PCLK_TCPWM0_CLOCKS34 = 0x0041u, /* tcpwm[0].clocks[34] */ 99 PCLK_TCPWM0_CLOCKS35 = 0x0042u, /* tcpwm[0].clocks[35] */ 100 PCLK_TCPWM0_CLOCKS36 = 0x0043u, /* tcpwm[0].clocks[36] */ 101 PCLK_TCPWM0_CLOCKS37 = 0x0044u, /* tcpwm[0].clocks[37] */ 102 PCLK_TCPWM0_CLOCKS38 = 0x0045u, /* tcpwm[0].clocks[38] */ 103 PCLK_TCPWM0_CLOCKS39 = 0x0046u, /* tcpwm[0].clocks[39] */ 104 PCLK_TCPWM0_CLOCKS40 = 0x0047u, /* tcpwm[0].clocks[40] */ 105 PCLK_TCPWM0_CLOCKS41 = 0x0048u, /* tcpwm[0].clocks[41] */ 106 PCLK_TCPWM0_CLOCKS42 = 0x0049u, /* tcpwm[0].clocks[42] */ 107 PCLK_TCPWM0_CLOCKS43 = 0x004Au, /* tcpwm[0].clocks[43] */ 108 PCLK_TCPWM0_CLOCKS44 = 0x004Bu, /* tcpwm[0].clocks[44] */ 109 PCLK_TCPWM0_CLOCKS45 = 0x004Cu, /* tcpwm[0].clocks[45] */ 110 PCLK_TCPWM0_CLOCKS46 = 0x004Du, /* tcpwm[0].clocks[46] */ 111 PCLK_TCPWM0_CLOCKS47 = 0x004Eu, /* tcpwm[0].clocks[47] */ 112 PCLK_TCPWM0_CLOCKS48 = 0x004Fu, /* tcpwm[0].clocks[48] */ 113 PCLK_TCPWM0_CLOCKS49 = 0x0050u, /* tcpwm[0].clocks[49] */ 114 PCLK_TCPWM0_CLOCKS50 = 0x0051u, /* tcpwm[0].clocks[50] */ 115 PCLK_TCPWM0_CLOCKS51 = 0x0052u, /* tcpwm[0].clocks[51] */ 116 PCLK_TCPWM0_CLOCKS52 = 0x0053u, /* tcpwm[0].clocks[52] */ 117 PCLK_TCPWM0_CLOCKS53 = 0x0054u, /* tcpwm[0].clocks[53] */ 118 PCLK_TCPWM0_CLOCKS54 = 0x0055u, /* tcpwm[0].clocks[54] */ 119 PCLK_TCPWM0_CLOCKS55 = 0x0056u, /* tcpwm[0].clocks[55] */ 120 PCLK_TCPWM0_CLOCKS56 = 0x0057u, /* tcpwm[0].clocks[56] */ 121 PCLK_TCPWM0_CLOCKS57 = 0x0058u, /* tcpwm[0].clocks[57] */ 122 PCLK_TCPWM0_CLOCKS58 = 0x0059u, /* tcpwm[0].clocks[58] */ 123 PCLK_TCPWM0_CLOCKS59 = 0x005Au, /* tcpwm[0].clocks[59] */ 124 PCLK_TCPWM0_CLOCKS60 = 0x005Bu, /* tcpwm[0].clocks[60] */ 125 PCLK_TCPWM0_CLOCKS61 = 0x005Cu, /* tcpwm[0].clocks[61] */ 126 PCLK_TCPWM0_CLOCKS62 = 0x005Du, /* tcpwm[0].clocks[62] */ 127 PCLK_TCPWM0_CLOCKS256 = 0x005Eu, /* tcpwm[0].clocks[256] */ 128 PCLK_TCPWM0_CLOCKS257 = 0x005Fu, /* tcpwm[0].clocks[257] */ 129 PCLK_TCPWM0_CLOCKS258 = 0x0060u, /* tcpwm[0].clocks[258] */ 130 PCLK_TCPWM0_CLOCKS259 = 0x0061u, /* tcpwm[0].clocks[259] */ 131 PCLK_TCPWM0_CLOCKS260 = 0x0062u, /* tcpwm[0].clocks[260] */ 132 PCLK_TCPWM0_CLOCKS261 = 0x0063u, /* tcpwm[0].clocks[261] */ 133 PCLK_TCPWM0_CLOCKS262 = 0x0064u, /* tcpwm[0].clocks[262] */ 134 PCLK_TCPWM0_CLOCKS263 = 0x0065u, /* tcpwm[0].clocks[263] */ 135 PCLK_TCPWM0_CLOCKS264 = 0x0066u, /* tcpwm[0].clocks[264] */ 136 PCLK_TCPWM0_CLOCKS265 = 0x0067u, /* tcpwm[0].clocks[265] */ 137 PCLK_TCPWM0_CLOCKS266 = 0x0068u, /* tcpwm[0].clocks[266] */ 138 PCLK_TCPWM0_CLOCKS267 = 0x0069u, /* tcpwm[0].clocks[267] */ 139 PCLK_TCPWM0_CLOCKS512 = 0x006Au, /* tcpwm[0].clocks[512] */ 140 PCLK_TCPWM0_CLOCKS513 = 0x006Bu, /* tcpwm[0].clocks[513] */ 141 PCLK_TCPWM0_CLOCKS514 = 0x006Cu, /* tcpwm[0].clocks[514] */ 142 PCLK_TCPWM0_CLOCKS515 = 0x006Du /* tcpwm[0].clocks[515] */ 143 } en_clk_dst_t; 144 145 /* Trigger Group */ 146 /* This section contains the enums related to the Trigger multiplexer (TrigMux) driver. 147 * Refer to the Cypress Peripheral Driver Library Documentation, section Trigger multiplexer (TrigMux) -> Enumerated Types for details. 148 */ 149 /* Trigger Group Inputs */ 150 /* Trigger Input Group 0 - P-DMA0 Request Assignments */ 151 typedef enum 152 { 153 TRIG_IN_MUX_0_PDMA0_TR_OUT0 = 0x00000001u, /* cpuss.dw0_tr_out[0] */ 154 TRIG_IN_MUX_0_PDMA0_TR_OUT1 = 0x00000002u, /* cpuss.dw0_tr_out[1] */ 155 TRIG_IN_MUX_0_PDMA0_TR_OUT2 = 0x00000003u, /* cpuss.dw0_tr_out[2] */ 156 TRIG_IN_MUX_0_PDMA0_TR_OUT3 = 0x00000004u, /* cpuss.dw0_tr_out[3] */ 157 TRIG_IN_MUX_0_PDMA0_TR_OUT4 = 0x00000005u, /* cpuss.dw0_tr_out[4] */ 158 TRIG_IN_MUX_0_PDMA0_TR_OUT5 = 0x00000006u, /* cpuss.dw0_tr_out[5] */ 159 TRIG_IN_MUX_0_PDMA0_TR_OUT6 = 0x00000007u, /* cpuss.dw0_tr_out[6] */ 160 TRIG_IN_MUX_0_PDMA0_TR_OUT7 = 0x00000008u, /* cpuss.dw0_tr_out[7] */ 161 TRIG_IN_MUX_0_PDMA0_TR_OUT8 = 0x00000009u, /* cpuss.dw0_tr_out[8] */ 162 TRIG_IN_MUX_0_PDMA0_TR_OUT9 = 0x0000000Au, /* cpuss.dw0_tr_out[9] */ 163 TRIG_IN_MUX_0_PDMA0_TR_OUT10 = 0x0000000Bu, /* cpuss.dw0_tr_out[10] */ 164 TRIG_IN_MUX_0_PDMA0_TR_OUT11 = 0x0000000Cu, /* cpuss.dw0_tr_out[11] */ 165 TRIG_IN_MUX_0_PDMA0_TR_OUT12 = 0x0000000Du, /* cpuss.dw0_tr_out[12] */ 166 TRIG_IN_MUX_0_PDMA0_TR_OUT13 = 0x0000000Eu, /* cpuss.dw0_tr_out[13] */ 167 TRIG_IN_MUX_0_PDMA0_TR_OUT14 = 0x0000000Fu, /* cpuss.dw0_tr_out[14] */ 168 TRIG_IN_MUX_0_PDMA0_TR_OUT15 = 0x00000010u, /* cpuss.dw0_tr_out[15] */ 169 TRIG_IN_MUX_0_PDMA1_TR_OUT0 = 0x00000011u, /* cpuss.dw1_tr_out[0] */ 170 TRIG_IN_MUX_0_PDMA1_TR_OUT1 = 0x00000012u, /* cpuss.dw1_tr_out[1] */ 171 TRIG_IN_MUX_0_PDMA1_TR_OUT2 = 0x00000013u, /* cpuss.dw1_tr_out[2] */ 172 TRIG_IN_MUX_0_PDMA1_TR_OUT3 = 0x00000014u, /* cpuss.dw1_tr_out[3] */ 173 TRIG_IN_MUX_0_PDMA1_TR_OUT4 = 0x00000015u, /* cpuss.dw1_tr_out[4] */ 174 TRIG_IN_MUX_0_PDMA1_TR_OUT5 = 0x00000016u, /* cpuss.dw1_tr_out[5] */ 175 TRIG_IN_MUX_0_PDMA1_TR_OUT6 = 0x00000017u, /* cpuss.dw1_tr_out[6] */ 176 TRIG_IN_MUX_0_PDMA1_TR_OUT7 = 0x00000018u, /* cpuss.dw1_tr_out[7] */ 177 TRIG_IN_MUX_0_MDMA_TR_OUT0 = 0x00000019u, /* cpuss.dmac_tr_out[0] */ 178 TRIG_IN_MUX_0_MDMA_TR_OUT1 = 0x0000001Au, /* cpuss.dmac_tr_out[1] */ 179 TRIG_IN_MUX_0_MDMA_TR_OUT2 = 0x0000001Bu, /* cpuss.dmac_tr_out[2] */ 180 TRIG_IN_MUX_0_MDMA_TR_OUT3 = 0x0000001Cu, /* cpuss.dmac_tr_out[3] */ 181 TRIG_IN_MUX_0_FAULT_TR_OUT0 = 0x0000001Du, /* cpuss.tr_fault[0] */ 182 TRIG_IN_MUX_0_FAULT_TR_OUT1 = 0x0000001Eu, /* cpuss.tr_fault[1] */ 183 TRIG_IN_MUX_0_FAULT_TR_OUT2 = 0x0000001Fu, /* cpuss.tr_fault[2] */ 184 TRIG_IN_MUX_0_FAULT_TR_OUT3 = 0x00000020u, /* cpuss.tr_fault[3] */ 185 TRIG_IN_MUX_0_CTI_TR_OUT0 = 0x00000021u, /* cpuss.cti_tr_out[0] */ 186 TRIG_IN_MUX_0_CTI_TR_OUT1 = 0x00000022u, /* cpuss.cti_tr_out[1] */ 187 TRIG_IN_MUX_0_EVTGEN_TR_OUT3 = 0x00000023u, /* evtgen[0].tr_out[3] */ 188 TRIG_IN_MUX_0_EVTGEN_TR_OUT4 = 0x00000024u, /* evtgen[0].tr_out[4] */ 189 TRIG_IN_MUX_0_EVTGEN_TR_OUT5 = 0x00000025u, /* evtgen[0].tr_out[5] */ 190 TRIG_IN_MUX_0_EVTGEN_TR_OUT6 = 0x00000026u, /* evtgen[0].tr_out[6] */ 191 TRIG_IN_MUX_0_HSIOM_IO_INPUT0 = 0x00000027u, /* peri.tr_io_input[0] */ 192 TRIG_IN_MUX_0_HSIOM_IO_INPUT1 = 0x00000028u, /* peri.tr_io_input[1] */ 193 TRIG_IN_MUX_0_HSIOM_IO_INPUT2 = 0x00000029u, /* peri.tr_io_input[2] */ 194 TRIG_IN_MUX_0_HSIOM_IO_INPUT3 = 0x0000002Au, /* peri.tr_io_input[3] */ 195 TRIG_IN_MUX_0_HSIOM_IO_INPUT4 = 0x0000002Bu, /* peri.tr_io_input[4] */ 196 TRIG_IN_MUX_0_HSIOM_IO_INPUT5 = 0x0000002Cu, /* peri.tr_io_input[5] */ 197 TRIG_IN_MUX_0_HSIOM_IO_INPUT6 = 0x0000002Du, /* peri.tr_io_input[6] */ 198 TRIG_IN_MUX_0_HSIOM_IO_INPUT7 = 0x0000002Eu, /* peri.tr_io_input[7] */ 199 TRIG_IN_MUX_0_HSIOM_IO_INPUT8 = 0x0000002Fu, /* peri.tr_io_input[8] */ 200 TRIG_IN_MUX_0_HSIOM_IO_INPUT9 = 0x00000030u, /* peri.tr_io_input[9] */ 201 TRIG_IN_MUX_0_HSIOM_IO_INPUT10 = 0x00000031u, /* peri.tr_io_input[10] */ 202 TRIG_IN_MUX_0_HSIOM_IO_INPUT11 = 0x00000032u, /* peri.tr_io_input[11] */ 203 TRIG_IN_MUX_0_HSIOM_IO_INPUT12 = 0x00000033u, /* peri.tr_io_input[12] */ 204 TRIG_IN_MUX_0_HSIOM_IO_INPUT13 = 0x00000034u, /* peri.tr_io_input[13] */ 205 TRIG_IN_MUX_0_HSIOM_IO_INPUT14 = 0x00000035u, /* peri.tr_io_input[14] */ 206 TRIG_IN_MUX_0_HSIOM_IO_INPUT15 = 0x00000036u /* peri.tr_io_input[15] */ 207 } en_trig_input_pdma0_tr_0_t; 208 209 /* Trigger Input Group 1 - P-DMA1 Request Assignments */ 210 typedef enum 211 { 212 TRIG_IN_MUX_1_PDMA0_TR_OUT0 = 0x00000101u, /* cpuss.dw0_tr_out[0] */ 213 TRIG_IN_MUX_1_PDMA0_TR_OUT1 = 0x00000102u, /* cpuss.dw0_tr_out[1] */ 214 TRIG_IN_MUX_1_PDMA0_TR_OUT2 = 0x00000103u, /* cpuss.dw0_tr_out[2] */ 215 TRIG_IN_MUX_1_PDMA0_TR_OUT3 = 0x00000104u, /* cpuss.dw0_tr_out[3] */ 216 TRIG_IN_MUX_1_PDMA0_TR_OUT4 = 0x00000105u, /* cpuss.dw0_tr_out[4] */ 217 TRIG_IN_MUX_1_PDMA0_TR_OUT5 = 0x00000106u, /* cpuss.dw0_tr_out[5] */ 218 TRIG_IN_MUX_1_PDMA0_TR_OUT6 = 0x00000107u, /* cpuss.dw0_tr_out[6] */ 219 TRIG_IN_MUX_1_PDMA0_TR_OUT7 = 0x00000108u, /* cpuss.dw0_tr_out[7] */ 220 TRIG_IN_MUX_1_PDMA0_TR_OUT8 = 0x00000109u, /* cpuss.dw0_tr_out[8] */ 221 TRIG_IN_MUX_1_PDMA0_TR_OUT9 = 0x0000010Au, /* cpuss.dw0_tr_out[9] */ 222 TRIG_IN_MUX_1_PDMA0_TR_OUT10 = 0x0000010Bu, /* cpuss.dw0_tr_out[10] */ 223 TRIG_IN_MUX_1_PDMA0_TR_OUT11 = 0x0000010Cu, /* cpuss.dw0_tr_out[11] */ 224 TRIG_IN_MUX_1_PDMA0_TR_OUT12 = 0x0000010Du, /* cpuss.dw0_tr_out[12] */ 225 TRIG_IN_MUX_1_PDMA0_TR_OUT13 = 0x0000010Eu, /* cpuss.dw0_tr_out[13] */ 226 TRIG_IN_MUX_1_PDMA0_TR_OUT14 = 0x0000010Fu, /* cpuss.dw0_tr_out[14] */ 227 TRIG_IN_MUX_1_PDMA0_TR_OUT15 = 0x00000110u, /* cpuss.dw0_tr_out[15] */ 228 TRIG_IN_MUX_1_PDMA1_TR_OUT0 = 0x00000111u, /* cpuss.dw1_tr_out[0] */ 229 TRIG_IN_MUX_1_PDMA1_TR_OUT1 = 0x00000112u, /* cpuss.dw1_tr_out[1] */ 230 TRIG_IN_MUX_1_PDMA1_TR_OUT2 = 0x00000113u, /* cpuss.dw1_tr_out[2] */ 231 TRIG_IN_MUX_1_PDMA1_TR_OUT3 = 0x00000114u, /* cpuss.dw1_tr_out[3] */ 232 TRIG_IN_MUX_1_PDMA1_TR_OUT4 = 0x00000115u, /* cpuss.dw1_tr_out[4] */ 233 TRIG_IN_MUX_1_PDMA1_TR_OUT5 = 0x00000116u, /* cpuss.dw1_tr_out[5] */ 234 TRIG_IN_MUX_1_PDMA1_TR_OUT6 = 0x00000117u, /* cpuss.dw1_tr_out[6] */ 235 TRIG_IN_MUX_1_PDMA1_TR_OUT7 = 0x00000118u, /* cpuss.dw1_tr_out[7] */ 236 TRIG_IN_MUX_1_MDMA_TR_OUT0 = 0x00000119u, /* cpuss.dmac_tr_out[0] */ 237 TRIG_IN_MUX_1_MDMA_TR_OUT1 = 0x0000011Au, /* cpuss.dmac_tr_out[1] */ 238 TRIG_IN_MUX_1_MDMA_TR_OUT2 = 0x0000011Bu, /* cpuss.dmac_tr_out[2] */ 239 TRIG_IN_MUX_1_MDMA_TR_OUT3 = 0x0000011Cu, /* cpuss.dmac_tr_out[3] */ 240 TRIG_IN_MUX_1_FAULT_TR_OUT0 = 0x0000011Du, /* cpuss.tr_fault[0] */ 241 TRIG_IN_MUX_1_FAULT_TR_OUT1 = 0x0000011Eu, /* cpuss.tr_fault[1] */ 242 TRIG_IN_MUX_1_FAULT_TR_OUT2 = 0x0000011Fu, /* cpuss.tr_fault[2] */ 243 TRIG_IN_MUX_1_FAULT_TR_OUT3 = 0x00000120u, /* cpuss.tr_fault[3] */ 244 TRIG_IN_MUX_1_CTI_TR_OUT0 = 0x00000121u, /* cpuss.cti_tr_out[0] */ 245 TRIG_IN_MUX_1_CTI_TR_OUT1 = 0x00000122u, /* cpuss.cti_tr_out[1] */ 246 TRIG_IN_MUX_1_EVTGEN_TR_OUT7 = 0x00000123u, /* evtgen[0].tr_out[7] */ 247 TRIG_IN_MUX_1_EVTGEN_TR_OUT8 = 0x00000124u, /* evtgen[0].tr_out[8] */ 248 TRIG_IN_MUX_1_EVTGEN_TR_OUT9 = 0x00000125u, /* evtgen[0].tr_out[9] */ 249 TRIG_IN_MUX_1_EVTGEN_TR_OUT10 = 0x00000126u, /* evtgen[0].tr_out[10] */ 250 TRIG_IN_MUX_1_HSIOM_IO_INPUT16 = 0x00000127u, /* peri.tr_io_input[16] */ 251 TRIG_IN_MUX_1_HSIOM_IO_INPUT17 = 0x00000128u, /* peri.tr_io_input[17] */ 252 TRIG_IN_MUX_1_HSIOM_IO_INPUT18 = 0x00000129u, /* peri.tr_io_input[18] */ 253 TRIG_IN_MUX_1_HSIOM_IO_INPUT19 = 0x0000012Au, /* peri.tr_io_input[19] */ 254 TRIG_IN_MUX_1_HSIOM_IO_INPUT20 = 0x0000012Bu, /* peri.tr_io_input[20] */ 255 TRIG_IN_MUX_1_HSIOM_IO_INPUT21 = 0x0000012Cu, /* peri.tr_io_input[21] */ 256 TRIG_IN_MUX_1_HSIOM_IO_INPUT22 = 0x0000012Du, /* peri.tr_io_input[22] */ 257 TRIG_IN_MUX_1_HSIOM_IO_INPUT23 = 0x0000012Eu, /* peri.tr_io_input[23] */ 258 TRIG_IN_MUX_1_HSIOM_IO_INPUT24 = 0x0000012Fu, /* peri.tr_io_input[24] */ 259 TRIG_IN_MUX_1_HSIOM_IO_INPUT25 = 0x00000130u, /* peri.tr_io_input[25] */ 260 TRIG_IN_MUX_1_HSIOM_IO_INPUT26 = 0x00000131u, /* peri.tr_io_input[26] */ 261 TRIG_IN_MUX_1_HSIOM_IO_INPUT27 = 0x00000132u, /* peri.tr_io_input[27] */ 262 TRIG_IN_MUX_1_HSIOM_IO_INPUT28 = 0x00000133u, /* peri.tr_io_input[28] */ 263 TRIG_IN_MUX_1_HSIOM_IO_INPUT29 = 0x00000134u, /* peri.tr_io_input[29] */ 264 TRIG_IN_MUX_1_HSIOM_IO_INPUT30 = 0x00000135u, /* peri.tr_io_input[30] */ 265 TRIG_IN_MUX_1_HSIOM_IO_INPUT31 = 0x00000136u, /* peri.tr_io_input[31] */ 266 TRIG_IN_MUX_1_PASS_GEN_TR_OUT0 = 0x00000137u, /* pass[0].tr_sar_gen_out[0] */ 267 TRIG_IN_MUX_1_PASS_GEN_TR_OUT1 = 0x00000138u, /* pass[0].tr_sar_gen_out[1] */ 268 TRIG_IN_MUX_1_PASS_GEN_TR_OUT2 = 0x00000139u, /* pass[0].tr_sar_gen_out[2] */ 269 TRIG_IN_MUX_1_PASS_GEN_TR_OUT3 = 0x0000013Au, /* pass[0].tr_sar_gen_out[3] */ 270 TRIG_IN_MUX_1_PASS_GEN_TR_OUT4 = 0x0000013Bu, /* pass[0].tr_sar_gen_out[4] */ 271 TRIG_IN_MUX_1_PASS_GEN_TR_OUT5 = 0x0000013Cu /* pass[0].tr_sar_gen_out[5] */ 272 } en_trig_input_pdma1_tr_t; 273 274 /* Trigger Input Group 2 - DMA Request Assignments */ 275 typedef enum 276 { 277 TRIG_IN_MUX_2_MDMA_TR_OUT0 = 0x00000201u, /* cpuss.dmac_tr_out[0] */ 278 TRIG_IN_MUX_2_MDMA_TR_OUT1 = 0x00000202u, /* cpuss.dmac_tr_out[1] */ 279 TRIG_IN_MUX_2_MDMA_TR_OUT2 = 0x00000203u, /* cpuss.dmac_tr_out[2] */ 280 TRIG_IN_MUX_2_MDMA_TR_OUT3 = 0x00000204u /* cpuss.dmac_tr_out[3] */ 281 } en_trig_input_mdma_t; 282 283 /* Trigger Input Group 3 - Dedicated mux for counter to P-DMA0 triggers */ 284 typedef enum 285 { 286 TRIG_IN_MUX_3_TCPWM_32_TR_OUT00 = 0x00000301u, /* tcpwm[0].tr_out0[512] */ 287 TRIG_IN_MUX_3_TCPWM_32_TR_OUT01 = 0x00000302u, /* tcpwm[0].tr_out0[513] */ 288 TRIG_IN_MUX_3_TCPWM_32_TR_OUT02 = 0x00000303u, /* tcpwm[0].tr_out0[514] */ 289 TRIG_IN_MUX_3_TCPWM_32_TR_OUT03 = 0x00000304u, /* tcpwm[0].tr_out0[515] */ 290 TRIG_IN_MUX_3_TCPWM_16M_TR_OUT00 = 0x00000305u, /* tcpwm[0].tr_out0[256] */ 291 TRIG_IN_MUX_3_TCPWM_16M_TR_OUT01 = 0x00000306u, /* tcpwm[0].tr_out0[257] */ 292 TRIG_IN_MUX_3_TCPWM_16M_TR_OUT02 = 0x00000307u, /* tcpwm[0].tr_out0[258] */ 293 TRIG_IN_MUX_3_TCPWM_16M_TR_OUT03 = 0x00000308u, /* tcpwm[0].tr_out0[259] */ 294 TRIG_IN_MUX_3_TCPWM_16M_TR_OUT04 = 0x00000309u, /* tcpwm[0].tr_out0[260] */ 295 TRIG_IN_MUX_3_TCPWM_16M_TR_OUT05 = 0x0000030Au, /* tcpwm[0].tr_out0[261] */ 296 TRIG_IN_MUX_3_TCPWM_16M_TR_OUT06 = 0x0000030Bu, /* tcpwm[0].tr_out0[262] */ 297 TRIG_IN_MUX_3_TCPWM_16M_TR_OUT07 = 0x0000030Cu, /* tcpwm[0].tr_out0[263] */ 298 TRIG_IN_MUX_3_TCPWM_16M_TR_OUT08 = 0x0000030Du, /* tcpwm[0].tr_out0[264] */ 299 TRIG_IN_MUX_3_TCPWM_16M_TR_OUT09 = 0x0000030Eu, /* tcpwm[0].tr_out0[265] */ 300 TRIG_IN_MUX_3_TCPWM_16M_TR_OUT010 = 0x0000030Fu, /* tcpwm[0].tr_out0[266] */ 301 TRIG_IN_MUX_3_TCPWM_16M_TR_OUT011 = 0x00000310u, /* tcpwm[0].tr_out0[267] */ 302 TRIG_IN_MUX_3_TCPWM_16_TR_OUT00 = 0x00000311u, /* tcpwm[0].tr_out0[0] */ 303 TRIG_IN_MUX_3_TCPWM_16_TR_OUT01 = 0x00000312u, /* tcpwm[0].tr_out0[1] */ 304 TRIG_IN_MUX_3_TCPWM_16_TR_OUT02 = 0x00000313u, /* tcpwm[0].tr_out0[2] */ 305 TRIG_IN_MUX_3_TCPWM_16_TR_OUT03 = 0x00000314u, /* tcpwm[0].tr_out0[3] */ 306 TRIG_IN_MUX_3_TCPWM_16_TR_OUT04 = 0x00000315u, /* tcpwm[0].tr_out0[4] */ 307 TRIG_IN_MUX_3_TCPWM_16_TR_OUT05 = 0x00000316u, /* tcpwm[0].tr_out0[5] */ 308 TRIG_IN_MUX_3_TCPWM_16_TR_OUT06 = 0x00000317u, /* tcpwm[0].tr_out0[6] */ 309 TRIG_IN_MUX_3_TCPWM_16_TR_OUT07 = 0x00000318u, /* tcpwm[0].tr_out0[7] */ 310 TRIG_IN_MUX_3_TCPWM_16_TR_OUT08 = 0x00000319u, /* tcpwm[0].tr_out0[8] */ 311 TRIG_IN_MUX_3_TCPWM_16_TR_OUT09 = 0x0000031Au, /* tcpwm[0].tr_out0[9] */ 312 TRIG_IN_MUX_3_TCPWM_16_TR_OUT010 = 0x0000031Bu, /* tcpwm[0].tr_out0[10] */ 313 TRIG_IN_MUX_3_TCPWM_16_TR_OUT011 = 0x0000031Cu, /* tcpwm[0].tr_out0[11] */ 314 TRIG_IN_MUX_3_TCPWM_16_TR_OUT012 = 0x0000031Du, /* tcpwm[0].tr_out0[12] */ 315 TRIG_IN_MUX_3_TCPWM_16_TR_OUT013 = 0x0000031Eu, /* tcpwm[0].tr_out0[13] */ 316 TRIG_IN_MUX_3_TCPWM_16_TR_OUT014 = 0x0000031Fu, /* tcpwm[0].tr_out0[14] */ 317 TRIG_IN_MUX_3_TCPWM_16_TR_OUT015 = 0x00000320u, /* tcpwm[0].tr_out0[15] */ 318 TRIG_IN_MUX_3_TCPWM_16_TR_OUT016 = 0x00000321u, /* tcpwm[0].tr_out0[16] */ 319 TRIG_IN_MUX_3_TCPWM_16_TR_OUT017 = 0x00000322u, /* tcpwm[0].tr_out0[17] */ 320 TRIG_IN_MUX_3_TCPWM_16_TR_OUT018 = 0x00000323u, /* tcpwm[0].tr_out0[18] */ 321 TRIG_IN_MUX_3_TCPWM_16_TR_OUT019 = 0x00000324u, /* tcpwm[0].tr_out0[19] */ 322 TRIG_IN_MUX_3_TCPWM_16_TR_OUT020 = 0x00000325u, /* tcpwm[0].tr_out0[20] */ 323 TRIG_IN_MUX_3_TCPWM_16_TR_OUT021 = 0x00000326u, /* tcpwm[0].tr_out0[21] */ 324 TRIG_IN_MUX_3_TCPWM_16_TR_OUT022 = 0x00000327u, /* tcpwm[0].tr_out0[22] */ 325 TRIG_IN_MUX_3_TCPWM_16_TR_OUT023 = 0x00000328u, /* tcpwm[0].tr_out0[23] */ 326 TRIG_IN_MUX_3_TCPWM_16_TR_OUT024 = 0x00000329u, /* tcpwm[0].tr_out0[24] */ 327 TRIG_IN_MUX_3_TCPWM_16_TR_OUT025 = 0x0000032Au, /* tcpwm[0].tr_out0[25] */ 328 TRIG_IN_MUX_3_TCPWM_16_TR_OUT026 = 0x0000032Bu, /* tcpwm[0].tr_out0[26] */ 329 TRIG_IN_MUX_3_TCPWM_16_TR_OUT027 = 0x0000032Cu, /* tcpwm[0].tr_out0[27] */ 330 TRIG_IN_MUX_3_TCPWM_16_TR_OUT028 = 0x0000032Du, /* tcpwm[0].tr_out0[28] */ 331 TRIG_IN_MUX_3_TCPWM_16_TR_OUT029 = 0x0000032Eu, /* tcpwm[0].tr_out0[29] */ 332 TRIG_IN_MUX_3_TCPWM_16_TR_OUT030 = 0x0000032Fu, /* tcpwm[0].tr_out0[30] */ 333 TRIG_IN_MUX_3_TCPWM_16_TR_OUT031 = 0x00000330u, /* tcpwm[0].tr_out0[31] */ 334 TRIG_IN_MUX_3_TCPWM_16_TR_OUT032 = 0x00000331u, /* tcpwm[0].tr_out0[32] */ 335 TRIG_IN_MUX_3_TCPWM_16_TR_OUT033 = 0x00000332u, /* tcpwm[0].tr_out0[33] */ 336 TRIG_IN_MUX_3_TCPWM_16_TR_OUT034 = 0x00000333u, /* tcpwm[0].tr_out0[34] */ 337 TRIG_IN_MUX_3_TCPWM_16_TR_OUT035 = 0x00000334u, /* tcpwm[0].tr_out0[35] */ 338 TRIG_IN_MUX_3_TCPWM_16_TR_OUT036 = 0x00000335u, /* tcpwm[0].tr_out0[36] */ 339 TRIG_IN_MUX_3_TCPWM_16_TR_OUT037 = 0x00000336u, /* tcpwm[0].tr_out0[37] */ 340 TRIG_IN_MUX_3_TCPWM_16_TR_OUT038 = 0x00000337u, /* tcpwm[0].tr_out0[38] */ 341 TRIG_IN_MUX_3_TCPWM_16_TR_OUT039 = 0x00000338u, /* tcpwm[0].tr_out0[39] */ 342 TRIG_IN_MUX_3_TCPWM_16_TR_OUT040 = 0x00000339u, /* tcpwm[0].tr_out0[40] */ 343 TRIG_IN_MUX_3_TCPWM_16_TR_OUT041 = 0x0000033Au, /* tcpwm[0].tr_out0[41] */ 344 TRIG_IN_MUX_3_TCPWM_16_TR_OUT042 = 0x0000033Bu, /* tcpwm[0].tr_out0[42] */ 345 TRIG_IN_MUX_3_TCPWM_16_TR_OUT043 = 0x0000033Cu, /* tcpwm[0].tr_out0[43] */ 346 TRIG_IN_MUX_3_TCPWM_16_TR_OUT044 = 0x0000033Du, /* tcpwm[0].tr_out0[44] */ 347 TRIG_IN_MUX_3_TCPWM_16_TR_OUT045 = 0x0000033Eu, /* tcpwm[0].tr_out0[45] */ 348 TRIG_IN_MUX_3_TCPWM_16_TR_OUT046 = 0x0000033Fu, /* tcpwm[0].tr_out0[46] */ 349 TRIG_IN_MUX_3_TCPWM_16_TR_OUT047 = 0x00000340u, /* tcpwm[0].tr_out0[47] */ 350 TRIG_IN_MUX_3_TCPWM_16_TR_OUT048 = 0x00000341u, /* tcpwm[0].tr_out0[48] */ 351 TRIG_IN_MUX_3_TCPWM_16_TR_OUT049 = 0x00000342u, /* tcpwm[0].tr_out0[49] */ 352 TRIG_IN_MUX_3_TCPWM_16_TR_OUT050 = 0x00000343u, /* tcpwm[0].tr_out0[50] */ 353 TRIG_IN_MUX_3_TCPWM_16_TR_OUT051 = 0x00000344u, /* tcpwm[0].tr_out0[51] */ 354 TRIG_IN_MUX_3_TCPWM_16_TR_OUT052 = 0x00000345u, /* tcpwm[0].tr_out0[52] */ 355 TRIG_IN_MUX_3_TCPWM_16_TR_OUT053 = 0x00000346u, /* tcpwm[0].tr_out0[53] */ 356 TRIG_IN_MUX_3_TCPWM_16_TR_OUT054 = 0x00000347u, /* tcpwm[0].tr_out0[54] */ 357 TRIG_IN_MUX_3_TCPWM_16_TR_OUT055 = 0x00000348u, /* tcpwm[0].tr_out0[55] */ 358 TRIG_IN_MUX_3_TCPWM_16_TR_OUT056 = 0x00000349u, /* tcpwm[0].tr_out0[56] */ 359 TRIG_IN_MUX_3_TCPWM_16_TR_OUT057 = 0x0000034Au, /* tcpwm[0].tr_out0[57] */ 360 TRIG_IN_MUX_3_TCPWM_16_TR_OUT058 = 0x0000034Bu, /* tcpwm[0].tr_out0[58] */ 361 TRIG_IN_MUX_3_TCPWM_16_TR_OUT059 = 0x0000034Cu, /* tcpwm[0].tr_out0[59] */ 362 TRIG_IN_MUX_3_TCPWM_16_TR_OUT060 = 0x0000034Du, /* tcpwm[0].tr_out0[60] */ 363 TRIG_IN_MUX_3_TCPWM_16_TR_OUT061 = 0x0000034Eu, /* tcpwm[0].tr_out0[61] */ 364 TRIG_IN_MUX_3_TCPWM_16_TR_OUT062 = 0x0000034Fu, /* tcpwm[0].tr_out0[62] */ 365 TRIG_IN_MUX_3_CAN0_TT_TR_OUT0 = 0x00000350u, /* canfd[0].tr_tmp_rtp_out[0] */ 366 TRIG_IN_MUX_3_CAN0_TT_TR_OUT1 = 0x00000351u, /* canfd[0].tr_tmp_rtp_out[1] */ 367 TRIG_IN_MUX_3_CAN0_TT_TR_OUT2 = 0x00000352u, /* canfd[0].tr_tmp_rtp_out[2] */ 368 TRIG_IN_MUX_3_CAN1_TT_TR_OUT0 = 0x00000353u, /* canfd[1].tr_tmp_rtp_out[0] */ 369 TRIG_IN_MUX_3_CAN1_TT_TR_OUT1 = 0x00000354u, /* canfd[1].tr_tmp_rtp_out[1] */ 370 TRIG_IN_MUX_3_CAN1_TT_TR_OUT2 = 0x00000355u /* canfd[1].tr_tmp_rtp_out[2] */ 371 } en_trig_input_pdma0_tr_1_t; 372 373 /* Trigger Input Group 4 - Reduces tcpwm output triggers to 16 signals, to allow chaining TCPWMs */ 374 typedef enum 375 { 376 TRIG_IN_MUX_4_TCPWM_32_TR_OUT00 = 0x00000401u, /* tcpwm[0].tr_out0[512] */ 377 TRIG_IN_MUX_4_TCPWM_32_TR_OUT01 = 0x00000402u, /* tcpwm[0].tr_out0[513] */ 378 TRIG_IN_MUX_4_TCPWM_32_TR_OUT02 = 0x00000403u, /* tcpwm[0].tr_out0[514] */ 379 TRIG_IN_MUX_4_TCPWM_32_TR_OUT03 = 0x00000404u, /* tcpwm[0].tr_out0[515] */ 380 TRIG_IN_MUX_4_TCPWM_16M_TR_OUT00 = 0x00000405u, /* tcpwm[0].tr_out0[256] */ 381 TRIG_IN_MUX_4_TCPWM_16M_TR_OUT01 = 0x00000406u, /* tcpwm[0].tr_out0[257] */ 382 TRIG_IN_MUX_4_TCPWM_16M_TR_OUT02 = 0x00000407u, /* tcpwm[0].tr_out0[258] */ 383 TRIG_IN_MUX_4_TCPWM_16M_TR_OUT03 = 0x00000408u, /* tcpwm[0].tr_out0[259] */ 384 TRIG_IN_MUX_4_TCPWM_16M_TR_OUT04 = 0x00000409u, /* tcpwm[0].tr_out0[260] */ 385 TRIG_IN_MUX_4_TCPWM_16M_TR_OUT05 = 0x0000040Au, /* tcpwm[0].tr_out0[261] */ 386 TRIG_IN_MUX_4_TCPWM_16M_TR_OUT06 = 0x0000040Bu, /* tcpwm[0].tr_out0[262] */ 387 TRIG_IN_MUX_4_TCPWM_16M_TR_OUT07 = 0x0000040Cu, /* tcpwm[0].tr_out0[263] */ 388 TRIG_IN_MUX_4_TCPWM_16M_TR_OUT08 = 0x0000040Du, /* tcpwm[0].tr_out0[264] */ 389 TRIG_IN_MUX_4_TCPWM_16M_TR_OUT09 = 0x0000040Eu, /* tcpwm[0].tr_out0[265] */ 390 TRIG_IN_MUX_4_TCPWM_16M_TR_OUT010 = 0x0000040Fu, /* tcpwm[0].tr_out0[266] */ 391 TRIG_IN_MUX_4_TCPWM_16M_TR_OUT011 = 0x00000410u, /* tcpwm[0].tr_out0[267] */ 392 TRIG_IN_MUX_4_TCPWM_16_TR_OUT00 = 0x00000411u, /* tcpwm[0].tr_out0[0] */ 393 TRIG_IN_MUX_4_TCPWM_16_TR_OUT01 = 0x00000412u, /* tcpwm[0].tr_out0[1] */ 394 TRIG_IN_MUX_4_TCPWM_16_TR_OUT02 = 0x00000413u, /* tcpwm[0].tr_out0[2] */ 395 TRIG_IN_MUX_4_TCPWM_16_TR_OUT03 = 0x00000414u, /* tcpwm[0].tr_out0[3] */ 396 TRIG_IN_MUX_4_TCPWM_16_TR_OUT04 = 0x00000415u, /* tcpwm[0].tr_out0[4] */ 397 TRIG_IN_MUX_4_TCPWM_16_TR_OUT05 = 0x00000416u, /* tcpwm[0].tr_out0[5] */ 398 TRIG_IN_MUX_4_TCPWM_16_TR_OUT06 = 0x00000417u, /* tcpwm[0].tr_out0[6] */ 399 TRIG_IN_MUX_4_TCPWM_16_TR_OUT07 = 0x00000418u, /* tcpwm[0].tr_out0[7] */ 400 TRIG_IN_MUX_4_TCPWM_16_TR_OUT08 = 0x00000419u, /* tcpwm[0].tr_out0[8] */ 401 TRIG_IN_MUX_4_TCPWM_16_TR_OUT09 = 0x0000041Au, /* tcpwm[0].tr_out0[9] */ 402 TRIG_IN_MUX_4_TCPWM_16_TR_OUT010 = 0x0000041Bu, /* tcpwm[0].tr_out0[10] */ 403 TRIG_IN_MUX_4_TCPWM_16_TR_OUT011 = 0x0000041Cu, /* tcpwm[0].tr_out0[11] */ 404 TRIG_IN_MUX_4_TCPWM_16_TR_OUT012 = 0x0000041Du, /* tcpwm[0].tr_out0[12] */ 405 TRIG_IN_MUX_4_TCPWM_16_TR_OUT013 = 0x0000041Eu, /* tcpwm[0].tr_out0[13] */ 406 TRIG_IN_MUX_4_TCPWM_16_TR_OUT014 = 0x0000041Fu, /* tcpwm[0].tr_out0[14] */ 407 TRIG_IN_MUX_4_TCPWM_16_TR_OUT015 = 0x00000420u, /* tcpwm[0].tr_out0[15] */ 408 TRIG_IN_MUX_4_TCPWM_16_TR_OUT016 = 0x00000421u, /* tcpwm[0].tr_out0[16] */ 409 TRIG_IN_MUX_4_TCPWM_16_TR_OUT017 = 0x00000422u, /* tcpwm[0].tr_out0[17] */ 410 TRIG_IN_MUX_4_TCPWM_16_TR_OUT018 = 0x00000423u, /* tcpwm[0].tr_out0[18] */ 411 TRIG_IN_MUX_4_TCPWM_16_TR_OUT019 = 0x00000424u, /* tcpwm[0].tr_out0[19] */ 412 TRIG_IN_MUX_4_TCPWM_16_TR_OUT020 = 0x00000425u, /* tcpwm[0].tr_out0[20] */ 413 TRIG_IN_MUX_4_TCPWM_16_TR_OUT021 = 0x00000426u, /* tcpwm[0].tr_out0[21] */ 414 TRIG_IN_MUX_4_TCPWM_16_TR_OUT022 = 0x00000427u, /* tcpwm[0].tr_out0[22] */ 415 TRIG_IN_MUX_4_TCPWM_16_TR_OUT023 = 0x00000428u, /* tcpwm[0].tr_out0[23] */ 416 TRIG_IN_MUX_4_TCPWM_16_TR_OUT024 = 0x00000429u, /* tcpwm[0].tr_out0[24] */ 417 TRIG_IN_MUX_4_TCPWM_16_TR_OUT025 = 0x0000042Au, /* tcpwm[0].tr_out0[25] */ 418 TRIG_IN_MUX_4_TCPWM_16_TR_OUT026 = 0x0000042Bu, /* tcpwm[0].tr_out0[26] */ 419 TRIG_IN_MUX_4_TCPWM_16_TR_OUT027 = 0x0000042Cu, /* tcpwm[0].tr_out0[27] */ 420 TRIG_IN_MUX_4_TCPWM_16_TR_OUT028 = 0x0000042Du, /* tcpwm[0].tr_out0[28] */ 421 TRIG_IN_MUX_4_TCPWM_16_TR_OUT029 = 0x0000042Eu, /* tcpwm[0].tr_out0[29] */ 422 TRIG_IN_MUX_4_TCPWM_16_TR_OUT030 = 0x0000042Fu, /* tcpwm[0].tr_out0[30] */ 423 TRIG_IN_MUX_4_TCPWM_16_TR_OUT031 = 0x00000430u, /* tcpwm[0].tr_out0[31] */ 424 TRIG_IN_MUX_4_TCPWM_16_TR_OUT032 = 0x00000431u, /* tcpwm[0].tr_out0[32] */ 425 TRIG_IN_MUX_4_TCPWM_16_TR_OUT033 = 0x00000432u, /* tcpwm[0].tr_out0[33] */ 426 TRIG_IN_MUX_4_TCPWM_16_TR_OUT034 = 0x00000433u, /* tcpwm[0].tr_out0[34] */ 427 TRIG_IN_MUX_4_TCPWM_16_TR_OUT035 = 0x00000434u, /* tcpwm[0].tr_out0[35] */ 428 TRIG_IN_MUX_4_TCPWM_16_TR_OUT036 = 0x00000435u, /* tcpwm[0].tr_out0[36] */ 429 TRIG_IN_MUX_4_TCPWM_16_TR_OUT037 = 0x00000436u, /* tcpwm[0].tr_out0[37] */ 430 TRIG_IN_MUX_4_TCPWM_16_TR_OUT038 = 0x00000437u, /* tcpwm[0].tr_out0[38] */ 431 TRIG_IN_MUX_4_TCPWM_16_TR_OUT039 = 0x00000438u, /* tcpwm[0].tr_out0[39] */ 432 TRIG_IN_MUX_4_TCPWM_16_TR_OUT040 = 0x00000439u, /* tcpwm[0].tr_out0[40] */ 433 TRIG_IN_MUX_4_TCPWM_16_TR_OUT041 = 0x0000043Au, /* tcpwm[0].tr_out0[41] */ 434 TRIG_IN_MUX_4_TCPWM_16_TR_OUT042 = 0x0000043Bu, /* tcpwm[0].tr_out0[42] */ 435 TRIG_IN_MUX_4_TCPWM_16_TR_OUT043 = 0x0000043Cu, /* tcpwm[0].tr_out0[43] */ 436 TRIG_IN_MUX_4_TCPWM_16_TR_OUT044 = 0x0000043Du, /* tcpwm[0].tr_out0[44] */ 437 TRIG_IN_MUX_4_TCPWM_16_TR_OUT045 = 0x0000043Eu, /* tcpwm[0].tr_out0[45] */ 438 TRIG_IN_MUX_4_TCPWM_16_TR_OUT046 = 0x0000043Fu, /* tcpwm[0].tr_out0[46] */ 439 TRIG_IN_MUX_4_TCPWM_16_TR_OUT047 = 0x00000440u, /* tcpwm[0].tr_out0[47] */ 440 TRIG_IN_MUX_4_TCPWM_16_TR_OUT048 = 0x00000441u, /* tcpwm[0].tr_out0[48] */ 441 TRIG_IN_MUX_4_TCPWM_16_TR_OUT049 = 0x00000442u, /* tcpwm[0].tr_out0[49] */ 442 TRIG_IN_MUX_4_TCPWM_16_TR_OUT050 = 0x00000443u, /* tcpwm[0].tr_out0[50] */ 443 TRIG_IN_MUX_4_TCPWM_16_TR_OUT051 = 0x00000444u, /* tcpwm[0].tr_out0[51] */ 444 TRIG_IN_MUX_4_TCPWM_16_TR_OUT052 = 0x00000445u, /* tcpwm[0].tr_out0[52] */ 445 TRIG_IN_MUX_4_TCPWM_16_TR_OUT053 = 0x00000446u, /* tcpwm[0].tr_out0[53] */ 446 TRIG_IN_MUX_4_TCPWM_16_TR_OUT054 = 0x00000447u, /* tcpwm[0].tr_out0[54] */ 447 TRIG_IN_MUX_4_TCPWM_16_TR_OUT055 = 0x00000448u, /* tcpwm[0].tr_out0[55] */ 448 TRIG_IN_MUX_4_TCPWM_16_TR_OUT056 = 0x00000449u, /* tcpwm[0].tr_out0[56] */ 449 TRIG_IN_MUX_4_TCPWM_16_TR_OUT057 = 0x0000044Au, /* tcpwm[0].tr_out0[57] */ 450 TRIG_IN_MUX_4_TCPWM_16_TR_OUT058 = 0x0000044Bu, /* tcpwm[0].tr_out0[58] */ 451 TRIG_IN_MUX_4_TCPWM_16_TR_OUT059 = 0x0000044Cu, /* tcpwm[0].tr_out0[59] */ 452 TRIG_IN_MUX_4_TCPWM_16_TR_OUT060 = 0x0000044Du, /* tcpwm[0].tr_out0[60] */ 453 TRIG_IN_MUX_4_TCPWM_16_TR_OUT061 = 0x0000044Eu, /* tcpwm[0].tr_out0[61] */ 454 TRIG_IN_MUX_4_TCPWM_16_TR_OUT062 = 0x0000044Fu, /* tcpwm[0].tr_out0[62] */ 455 TRIG_IN_MUX_4_TCPWM_16_TR_OUT10 = 0x00000450u, /* tcpwm[0].tr_out1[0] */ 456 TRIG_IN_MUX_4_TCPWM_16_TR_OUT11 = 0x00000451u, /* tcpwm[0].tr_out1[1] */ 457 TRIG_IN_MUX_4_TCPWM_16_TR_OUT12 = 0x00000452u, /* tcpwm[0].tr_out1[2] */ 458 TRIG_IN_MUX_4_TCPWM_16_TR_OUT13 = 0x00000453u, /* tcpwm[0].tr_out1[3] */ 459 TRIG_IN_MUX_4_TCPWM_16_TR_OUT14 = 0x00000454u, /* tcpwm[0].tr_out1[4] */ 460 TRIG_IN_MUX_4_TCPWM_16_TR_OUT15 = 0x00000455u, /* tcpwm[0].tr_out1[5] */ 461 TRIG_IN_MUX_4_TCPWM_16_TR_OUT16 = 0x00000456u, /* tcpwm[0].tr_out1[6] */ 462 TRIG_IN_MUX_4_TCPWM_16_TR_OUT17 = 0x00000457u, /* tcpwm[0].tr_out1[7] */ 463 TRIG_IN_MUX_4_CAN0_TT_TR_OUT0 = 0x00000458u, /* canfd[0].tr_tmp_rtp_out[0] */ 464 TRIG_IN_MUX_4_CAN0_TT_TR_OUT1 = 0x00000459u, /* canfd[0].tr_tmp_rtp_out[1] */ 465 TRIG_IN_MUX_4_CAN0_TT_TR_OUT2 = 0x0000045Au, /* canfd[0].tr_tmp_rtp_out[2] */ 466 TRIG_IN_MUX_4_CAN1_TT_TR_OUT0 = 0x0000045Bu, /* canfd[1].tr_tmp_rtp_out[0] */ 467 TRIG_IN_MUX_4_CAN1_TT_TR_OUT1 = 0x0000045Cu, /* canfd[1].tr_tmp_rtp_out[1] */ 468 TRIG_IN_MUX_4_CAN1_TT_TR_OUT2 = 0x0000045Du /* canfd[1].tr_tmp_rtp_out[2] */ 469 } en_trig_input_tcpwm_out_t; 470 471 /* Trigger Input Group 5 - TCPWM trigger inputs */ 472 typedef enum 473 { 474 TRIG_IN_MUX_5_PDMA0_TR_OUT0 = 0x00000501u, /* cpuss.dw0_tr_out[0] */ 475 TRIG_IN_MUX_5_PDMA0_TR_OUT1 = 0x00000502u, /* cpuss.dw0_tr_out[1] */ 476 TRIG_IN_MUX_5_PDMA0_TR_OUT2 = 0x00000503u, /* cpuss.dw0_tr_out[2] */ 477 TRIG_IN_MUX_5_PDMA0_TR_OUT3 = 0x00000504u, /* cpuss.dw0_tr_out[3] */ 478 TRIG_IN_MUX_5_PDMA0_TR_OUT4 = 0x00000505u, /* cpuss.dw0_tr_out[4] */ 479 TRIG_IN_MUX_5_PDMA0_TR_OUT5 = 0x00000506u, /* cpuss.dw0_tr_out[5] */ 480 TRIG_IN_MUX_5_PDMA0_TR_OUT6 = 0x00000507u, /* cpuss.dw0_tr_out[6] */ 481 TRIG_IN_MUX_5_PDMA0_TR_OUT7 = 0x00000508u, /* cpuss.dw0_tr_out[7] */ 482 TRIG_IN_MUX_5_PDMA0_TR_OUT8 = 0x00000509u, /* cpuss.dw0_tr_out[8] */ 483 TRIG_IN_MUX_5_PDMA0_TR_OUT9 = 0x0000050Au, /* cpuss.dw0_tr_out[9] */ 484 TRIG_IN_MUX_5_PDMA0_TR_OUT10 = 0x0000050Bu, /* cpuss.dw0_tr_out[10] */ 485 TRIG_IN_MUX_5_PDMA0_TR_OUT11 = 0x0000050Cu, /* cpuss.dw0_tr_out[11] */ 486 TRIG_IN_MUX_5_PDMA0_TR_OUT12 = 0x0000050Du, /* cpuss.dw0_tr_out[12] */ 487 TRIG_IN_MUX_5_PDMA0_TR_OUT13 = 0x0000050Eu, /* cpuss.dw0_tr_out[13] */ 488 TRIG_IN_MUX_5_PDMA0_TR_OUT14 = 0x0000050Fu, /* cpuss.dw0_tr_out[14] */ 489 TRIG_IN_MUX_5_PDMA0_TR_OUT15 = 0x00000510u, /* cpuss.dw0_tr_out[15] */ 490 TRIG_IN_MUX_5_PDMA1_TR_OUT0 = 0x00000511u, /* cpuss.dw1_tr_out[0] */ 491 TRIG_IN_MUX_5_PDMA1_TR_OUT1 = 0x00000512u, /* cpuss.dw1_tr_out[1] */ 492 TRIG_IN_MUX_5_PDMA1_TR_OUT2 = 0x00000513u, /* cpuss.dw1_tr_out[2] */ 493 TRIG_IN_MUX_5_PDMA1_TR_OUT3 = 0x00000514u, /* cpuss.dw1_tr_out[3] */ 494 TRIG_IN_MUX_5_PDMA1_TR_OUT4 = 0x00000515u, /* cpuss.dw1_tr_out[4] */ 495 TRIG_IN_MUX_5_PDMA1_TR_OUT5 = 0x00000516u, /* cpuss.dw1_tr_out[5] */ 496 TRIG_IN_MUX_5_PDMA1_TR_OUT6 = 0x00000517u, /* cpuss.dw1_tr_out[6] */ 497 TRIG_IN_MUX_5_PDMA1_TR_OUT7 = 0x00000518u, /* cpuss.dw1_tr_out[7] */ 498 TRIG_IN_MUX_5_MDMA_TR_OUT0 = 0x00000519u, /* cpuss.dmac_tr_out[0] */ 499 TRIG_IN_MUX_5_MDMA_TR_OUT1 = 0x0000051Au, /* cpuss.dmac_tr_out[1] */ 500 TRIG_IN_MUX_5_MDMA_TR_OUT2 = 0x0000051Bu, /* cpuss.dmac_tr_out[2] */ 501 TRIG_IN_MUX_5_MDMA_TR_OUT3 = 0x0000051Cu, /* cpuss.dmac_tr_out[3] */ 502 TRIG_IN_MUX_5_CTI_TR_OUT0 = 0x0000051Du, /* cpuss.cti_tr_out[0] */ 503 TRIG_IN_MUX_5_CTI_TR_OUT1 = 0x0000051Eu, /* cpuss.cti_tr_out[1] */ 504 TRIG_IN_MUX_5_FAULT_TR_OUT0 = 0x0000051Fu, /* cpuss.tr_fault[0] */ 505 TRIG_IN_MUX_5_FAULT_TR_OUT1 = 0x00000520u, /* cpuss.tr_fault[1] */ 506 TRIG_IN_MUX_5_FAULT_TR_OUT2 = 0x00000521u, /* cpuss.tr_fault[2] */ 507 TRIG_IN_MUX_5_FAULT_TR_OUT3 = 0x00000522u, /* cpuss.tr_fault[3] */ 508 TRIG_IN_MUX_5_PASS_GEN_TR_OUT0 = 0x00000523u, /* pass[0].tr_sar_gen_out[0] */ 509 TRIG_IN_MUX_5_PASS_GEN_TR_OUT1 = 0x00000524u, /* pass[0].tr_sar_gen_out[1] */ 510 TRIG_IN_MUX_5_PASS_GEN_TR_OUT2 = 0x00000525u, /* pass[0].tr_sar_gen_out[2] */ 511 TRIG_IN_MUX_5_PASS_GEN_TR_OUT3 = 0x00000526u, /* pass[0].tr_sar_gen_out[3] */ 512 TRIG_IN_MUX_5_PASS_GEN_TR_OUT4 = 0x00000527u, /* pass[0].tr_sar_gen_out[4] */ 513 TRIG_IN_MUX_5_PASS_GEN_TR_OUT5 = 0x00000528u, /* pass[0].tr_sar_gen_out[5] */ 514 TRIG_IN_MUX_5_HSIOM_IO_INPUT0 = 0x00000529u, /* peri.tr_io_input[0] */ 515 TRIG_IN_MUX_5_HSIOM_IO_INPUT1 = 0x0000052Au, /* peri.tr_io_input[1] */ 516 TRIG_IN_MUX_5_HSIOM_IO_INPUT2 = 0x0000052Bu, /* peri.tr_io_input[2] */ 517 TRIG_IN_MUX_5_HSIOM_IO_INPUT3 = 0x0000052Cu, /* peri.tr_io_input[3] */ 518 TRIG_IN_MUX_5_HSIOM_IO_INPUT4 = 0x0000052Du, /* peri.tr_io_input[4] */ 519 TRIG_IN_MUX_5_HSIOM_IO_INPUT5 = 0x0000052Eu, /* peri.tr_io_input[5] */ 520 TRIG_IN_MUX_5_HSIOM_IO_INPUT6 = 0x0000052Fu, /* peri.tr_io_input[6] */ 521 TRIG_IN_MUX_5_HSIOM_IO_INPUT7 = 0x00000530u, /* peri.tr_io_input[7] */ 522 TRIG_IN_MUX_5_HSIOM_IO_INPUT8 = 0x00000531u, /* peri.tr_io_input[8] */ 523 TRIG_IN_MUX_5_HSIOM_IO_INPUT9 = 0x00000532u, /* peri.tr_io_input[9] */ 524 TRIG_IN_MUX_5_HSIOM_IO_INPUT10 = 0x00000533u, /* peri.tr_io_input[10] */ 525 TRIG_IN_MUX_5_HSIOM_IO_INPUT11 = 0x00000534u, /* peri.tr_io_input[11] */ 526 TRIG_IN_MUX_5_HSIOM_IO_INPUT12 = 0x00000535u, /* peri.tr_io_input[12] */ 527 TRIG_IN_MUX_5_HSIOM_IO_INPUT13 = 0x00000536u, /* peri.tr_io_input[13] */ 528 TRIG_IN_MUX_5_HSIOM_IO_INPUT14 = 0x00000537u, /* peri.tr_io_input[14] */ 529 TRIG_IN_MUX_5_HSIOM_IO_INPUT15 = 0x00000538u, /* peri.tr_io_input[15] */ 530 TRIG_IN_MUX_5_HSIOM_IO_INPUT16 = 0x00000539u, /* peri.tr_io_input[16] */ 531 TRIG_IN_MUX_5_HSIOM_IO_INPUT17 = 0x0000053Au, /* peri.tr_io_input[17] */ 532 TRIG_IN_MUX_5_HSIOM_IO_INPUT18 = 0x0000053Bu, /* peri.tr_io_input[18] */ 533 TRIG_IN_MUX_5_HSIOM_IO_INPUT19 = 0x0000053Cu, /* peri.tr_io_input[19] */ 534 TRIG_IN_MUX_5_HSIOM_IO_INPUT20 = 0x0000053Du, /* peri.tr_io_input[20] */ 535 TRIG_IN_MUX_5_HSIOM_IO_INPUT21 = 0x0000053Eu, /* peri.tr_io_input[21] */ 536 TRIG_IN_MUX_5_HSIOM_IO_INPUT22 = 0x0000053Fu, /* peri.tr_io_input[22] */ 537 TRIG_IN_MUX_5_HSIOM_IO_INPUT23 = 0x00000540u, /* peri.tr_io_input[23] */ 538 TRIG_IN_MUX_5_HSIOM_IO_INPUT24 = 0x00000541u, /* peri.tr_io_input[24] */ 539 TRIG_IN_MUX_5_HSIOM_IO_INPUT25 = 0x00000542u, /* peri.tr_io_input[25] */ 540 TRIG_IN_MUX_5_HSIOM_IO_INPUT26 = 0x00000543u, /* peri.tr_io_input[26] */ 541 TRIG_IN_MUX_5_HSIOM_IO_INPUT27 = 0x00000544u, /* peri.tr_io_input[27] */ 542 TRIG_IN_MUX_5_HSIOM_IO_INPUT28 = 0x00000545u, /* peri.tr_io_input[28] */ 543 TRIG_IN_MUX_5_HSIOM_IO_INPUT29 = 0x00000546u, /* peri.tr_io_input[29] */ 544 TRIG_IN_MUX_5_HSIOM_IO_INPUT30 = 0x00000547u, /* peri.tr_io_input[30] */ 545 TRIG_IN_MUX_5_HSIOM_IO_INPUT31 = 0x00000548u, /* peri.tr_io_input[31] */ 546 TRIG_IN_MUX_5_SCB_TX_TR_OUT0 = 0x00000549u, /* scb[0].tr_tx_req */ 547 TRIG_IN_MUX_5_SCB_RX_TR_OUT0 = 0x0000054Au, /* scb[0].tr_rx_req */ 548 TRIG_IN_MUX_5_SCB_I2C_SCL_TR_OUT0 = 0x0000054Bu, /* scb[0].tr_i2c_scl_filtered */ 549 TRIG_IN_MUX_5_SCB_TX_TR_OUT1 = 0x0000054Cu, /* scb[1].tr_tx_req */ 550 TRIG_IN_MUX_5_SCB_RX_TR_OUT1 = 0x0000054Du, /* scb[1].tr_rx_req */ 551 TRIG_IN_MUX_5_SCB_I2C_SCL_TR_OUT1 = 0x0000054Eu, /* scb[1].tr_i2c_scl_filtered */ 552 TRIG_IN_MUX_5_SCB_TX_TR_OUT2 = 0x0000054Fu, /* scb[2].tr_tx_req */ 553 TRIG_IN_MUX_5_SCB_RX_TR_OUT2 = 0x00000550u, /* scb[2].tr_rx_req */ 554 TRIG_IN_MUX_5_SCB_I2C_SCL_TR_OUT2 = 0x00000551u, /* scb[2].tr_i2c_scl_filtered */ 555 TRIG_IN_MUX_5_SCB_TX_TR_OUT3 = 0x00000552u, /* scb[3].tr_tx_req */ 556 TRIG_IN_MUX_5_SCB_RX_TR_OUT3 = 0x00000553u, /* scb[3].tr_rx_req */ 557 TRIG_IN_MUX_5_SCB_I2C_SCL_TR_OUT3 = 0x00000554u, /* scb[3].tr_i2c_scl_filtered */ 558 TRIG_IN_MUX_5_SCB_TX_TR_OUT4 = 0x00000555u, /* scb[4].tr_tx_req */ 559 TRIG_IN_MUX_5_SCB_RX_TR_OUT4 = 0x00000556u, /* scb[4].tr_rx_req */ 560 TRIG_IN_MUX_5_SCB_I2C_SCL_TR_OUT4 = 0x00000557u, /* scb[4].tr_i2c_scl_filtered */ 561 TRIG_IN_MUX_5_SCB_TX_TR_OUT5 = 0x00000558u, /* scb[5].tr_tx_req */ 562 TRIG_IN_MUX_5_SCB_RX_TR_OUT5 = 0x00000559u, /* scb[5].tr_rx_req */ 563 TRIG_IN_MUX_5_SCB_I2C_SCL_TR_OUT5 = 0x0000055Au, /* scb[5].tr_i2c_scl_filtered */ 564 TRIG_IN_MUX_5_SCB_TX_TR_OUT6 = 0x0000055Bu, /* scb[6].tr_tx_req */ 565 TRIG_IN_MUX_5_SCB_RX_TR_OUT6 = 0x0000055Cu, /* scb[6].tr_rx_req */ 566 TRIG_IN_MUX_5_SCB_I2C_SCL_TR_OUT6 = 0x0000055Du, /* scb[6].tr_i2c_scl_filtered */ 567 TRIG_IN_MUX_5_SCB_TX_TR_OUT7 = 0x0000055Eu, /* scb[7].tr_tx_req */ 568 TRIG_IN_MUX_5_SCB_RX_TR_OUT7 = 0x0000055Fu, /* scb[7].tr_rx_req */ 569 TRIG_IN_MUX_5_SCB_I2C_SCL_TR_OUT7 = 0x00000560u, /* scb[7].tr_i2c_scl_filtered */ 570 TRIG_IN_MUX_5_CAN0_DBG_TR_OUT0 = 0x00000561u, /* canfd[0].tr_dbg_dma_req[0] */ 571 TRIG_IN_MUX_5_CAN0_DBG_TR_OUT1 = 0x00000562u, /* canfd[0].tr_dbg_dma_req[1] */ 572 TRIG_IN_MUX_5_CAN0_DBG_TR_OUT2 = 0x00000563u, /* canfd[0].tr_dbg_dma_req[2] */ 573 TRIG_IN_MUX_5_CAN0_FIFO0_TR_OUT0 = 0x00000564u, /* canfd[0].tr_fifo0[0] */ 574 TRIG_IN_MUX_5_CAN0_FIFO0_TR_OUT1 = 0x00000565u, /* canfd[0].tr_fifo0[1] */ 575 TRIG_IN_MUX_5_CAN0_FIFO0_TR_OUT2 = 0x00000566u, /* canfd[0].tr_fifo0[2] */ 576 TRIG_IN_MUX_5_CAN0_FIFO1_TR_OUT0 = 0x00000567u, /* canfd[0].tr_fifo1[0] */ 577 TRIG_IN_MUX_5_CAN0_FIFO1_TR_OUT1 = 0x00000568u, /* canfd[0].tr_fifo1[1] */ 578 TRIG_IN_MUX_5_CAN0_FIFO1_TR_OUT2 = 0x00000569u, /* canfd[0].tr_fifo1[2] */ 579 TRIG_IN_MUX_5_CAN1_DBG_TR_OUT0 = 0x0000056Au, /* canfd[1].tr_dbg_dma_req[0] */ 580 TRIG_IN_MUX_5_CAN1_DBG_TR_OUT1 = 0x0000056Bu, /* canfd[1].tr_dbg_dma_req[1] */ 581 TRIG_IN_MUX_5_CAN1_DBG_TR_OUT2 = 0x0000056Cu, /* canfd[1].tr_dbg_dma_req[2] */ 582 TRIG_IN_MUX_5_CAN1_FIFO0_TR_OUT0 = 0x0000056Du, /* canfd[1].tr_fifo0[0] */ 583 TRIG_IN_MUX_5_CAN1_FIFO0_TR_OUT1 = 0x0000056Eu, /* canfd[1].tr_fifo0[1] */ 584 TRIG_IN_MUX_5_CAN1_FIFO0_TR_OUT2 = 0x0000056Fu, /* canfd[1].tr_fifo0[2] */ 585 TRIG_IN_MUX_5_CAN1_FIFO1_TR_OUT0 = 0x00000570u, /* canfd[1].tr_fifo1[0] */ 586 TRIG_IN_MUX_5_CAN1_FIFO1_TR_OUT1 = 0x00000571u, /* canfd[1].tr_fifo1[1] */ 587 TRIG_IN_MUX_5_CAN1_FIFO1_TR_OUT2 = 0x00000572u, /* canfd[1].tr_fifo1[2] */ 588 TRIG_IN_MUX_5_EVTGEN_TR_OUT3 = 0x00000573u, /* evtgen[0].tr_out[3] */ 589 TRIG_IN_MUX_5_EVTGEN_TR_OUT4 = 0x00000574u, /* evtgen[0].tr_out[4] */ 590 TRIG_IN_MUX_5_EVTGEN_TR_OUT5 = 0x00000575u, /* evtgen[0].tr_out[5] */ 591 TRIG_IN_MUX_5_EVTGEN_TR_OUT6 = 0x00000576u, /* evtgen[0].tr_out[6] */ 592 TRIG_IN_MUX_5_EVTGEN_TR_OUT7 = 0x00000577u, /* evtgen[0].tr_out[7] */ 593 TRIG_IN_MUX_5_EVTGEN_TR_OUT8 = 0x00000578u, /* evtgen[0].tr_out[8] */ 594 TRIG_IN_MUX_5_EVTGEN_TR_OUT9 = 0x00000579u, /* evtgen[0].tr_out[9] */ 595 TRIG_IN_MUX_5_EVTGEN_TR_OUT10 = 0x0000057Au /* evtgen[0].tr_out[10] */ 596 } en_trig_input_tcpwm_in_t; 597 598 /* Trigger Input Group 6 - PASS trigger multiplexer */ 599 typedef enum 600 { 601 TRIG_IN_MUX_6_PDMA0_TR_OUT0 = 0x00000601u, /* cpuss.dw0_tr_out[0] */ 602 TRIG_IN_MUX_6_PDMA0_TR_OUT1 = 0x00000602u, /* cpuss.dw0_tr_out[1] */ 603 TRIG_IN_MUX_6_PDMA0_TR_OUT2 = 0x00000603u, /* cpuss.dw0_tr_out[2] */ 604 TRIG_IN_MUX_6_PDMA0_TR_OUT3 = 0x00000604u, /* cpuss.dw0_tr_out[3] */ 605 TRIG_IN_MUX_6_PDMA0_TR_OUT4 = 0x00000605u, /* cpuss.dw0_tr_out[4] */ 606 TRIG_IN_MUX_6_PDMA0_TR_OUT5 = 0x00000606u, /* cpuss.dw0_tr_out[5] */ 607 TRIG_IN_MUX_6_PDMA0_TR_OUT6 = 0x00000607u, /* cpuss.dw0_tr_out[6] */ 608 TRIG_IN_MUX_6_PDMA0_TR_OUT7 = 0x00000608u, /* cpuss.dw0_tr_out[7] */ 609 TRIG_IN_MUX_6_PDMA0_TR_OUT8 = 0x00000609u, /* cpuss.dw0_tr_out[8] */ 610 TRIG_IN_MUX_6_PDMA0_TR_OUT9 = 0x0000060Au, /* cpuss.dw0_tr_out[9] */ 611 TRIG_IN_MUX_6_PDMA0_TR_OUT10 = 0x0000060Bu, /* cpuss.dw0_tr_out[10] */ 612 TRIG_IN_MUX_6_PDMA0_TR_OUT11 = 0x0000060Cu, /* cpuss.dw0_tr_out[11] */ 613 TRIG_IN_MUX_6_PDMA0_TR_OUT12 = 0x0000060Du, /* cpuss.dw0_tr_out[12] */ 614 TRIG_IN_MUX_6_PDMA0_TR_OUT13 = 0x0000060Eu, /* cpuss.dw0_tr_out[13] */ 615 TRIG_IN_MUX_6_PDMA0_TR_OUT14 = 0x0000060Fu, /* cpuss.dw0_tr_out[14] */ 616 TRIG_IN_MUX_6_PDMA0_TR_OUT15 = 0x00000610u, /* cpuss.dw0_tr_out[15] */ 617 TRIG_IN_MUX_6_CTI_TR_OUT0 = 0x00000611u, /* cpuss.cti_tr_out[0] */ 618 TRIG_IN_MUX_6_CTI_TR_OUT1 = 0x00000612u, /* cpuss.cti_tr_out[1] */ 619 TRIG_IN_MUX_6_FAULT_TR_OUT0 = 0x00000613u, /* cpuss.tr_fault[0] */ 620 TRIG_IN_MUX_6_FAULT_TR_OUT1 = 0x00000614u, /* cpuss.tr_fault[1] */ 621 TRIG_IN_MUX_6_FAULT_TR_OUT2 = 0x00000615u, /* cpuss.tr_fault[2] */ 622 TRIG_IN_MUX_6_FAULT_TR_OUT3 = 0x00000616u, /* cpuss.tr_fault[3] */ 623 TRIG_IN_MUX_6_EVTGEN_TR_OUT0 = 0x00000617u, /* evtgen[0].tr_out[0] */ 624 TRIG_IN_MUX_6_EVTGEN_TR_OUT1 = 0x00000618u, /* evtgen[0].tr_out[1] */ 625 TRIG_IN_MUX_6_EVTGEN_TR_OUT2 = 0x00000619u, /* evtgen[0].tr_out[2] */ 626 TRIG_IN_MUX_6_PASS_GEN_TR_OUT0 = 0x0000061Au, /* pass[0].tr_sar_gen_out[0] */ 627 TRIG_IN_MUX_6_PASS_GEN_TR_OUT1 = 0x0000061Bu, /* pass[0].tr_sar_gen_out[1] */ 628 TRIG_IN_MUX_6_PASS_GEN_TR_OUT2 = 0x0000061Cu, /* pass[0].tr_sar_gen_out[2] */ 629 TRIG_IN_MUX_6_PASS_GEN_TR_OUT3 = 0x0000061Du, /* pass[0].tr_sar_gen_out[3] */ 630 TRIG_IN_MUX_6_PASS_GEN_TR_OUT4 = 0x0000061Eu, /* pass[0].tr_sar_gen_out[4] */ 631 TRIG_IN_MUX_6_PASS_GEN_TR_OUT5 = 0x0000061Fu, /* pass[0].tr_sar_gen_out[5] */ 632 TRIG_IN_MUX_6_HSIOM_IO_INPUT0 = 0x00000620u, /* peri.tr_io_input[0] */ 633 TRIG_IN_MUX_6_HSIOM_IO_INPUT1 = 0x00000621u, /* peri.tr_io_input[1] */ 634 TRIG_IN_MUX_6_HSIOM_IO_INPUT2 = 0x00000622u, /* peri.tr_io_input[2] */ 635 TRIG_IN_MUX_6_HSIOM_IO_INPUT3 = 0x00000623u, /* peri.tr_io_input[3] */ 636 TRIG_IN_MUX_6_HSIOM_IO_INPUT4 = 0x00000624u, /* peri.tr_io_input[4] */ 637 TRIG_IN_MUX_6_HSIOM_IO_INPUT5 = 0x00000625u, /* peri.tr_io_input[5] */ 638 TRIG_IN_MUX_6_HSIOM_IO_INPUT6 = 0x00000626u, /* peri.tr_io_input[6] */ 639 TRIG_IN_MUX_6_HSIOM_IO_INPUT7 = 0x00000627u, /* peri.tr_io_input[7] */ 640 TRIG_IN_MUX_6_HSIOM_IO_INPUT8 = 0x00000628u, /* peri.tr_io_input[8] */ 641 TRIG_IN_MUX_6_HSIOM_IO_INPUT9 = 0x00000629u, /* peri.tr_io_input[9] */ 642 TRIG_IN_MUX_6_HSIOM_IO_INPUT10 = 0x0000062Au, /* peri.tr_io_input[10] */ 643 TRIG_IN_MUX_6_HSIOM_IO_INPUT11 = 0x0000062Bu, /* peri.tr_io_input[11] */ 644 TRIG_IN_MUX_6_HSIOM_IO_INPUT12 = 0x0000062Cu, /* peri.tr_io_input[12] */ 645 TRIG_IN_MUX_6_HSIOM_IO_INPUT13 = 0x0000062Du, /* peri.tr_io_input[13] */ 646 TRIG_IN_MUX_6_HSIOM_IO_INPUT14 = 0x0000062Eu, /* peri.tr_io_input[14] */ 647 TRIG_IN_MUX_6_HSIOM_IO_INPUT15 = 0x0000062Fu, /* peri.tr_io_input[15] */ 648 TRIG_IN_MUX_6_HSIOM_IO_INPUT16 = 0x00000630u, /* peri.tr_io_input[16] */ 649 TRIG_IN_MUX_6_HSIOM_IO_INPUT17 = 0x00000631u, /* peri.tr_io_input[17] */ 650 TRIG_IN_MUX_6_HSIOM_IO_INPUT18 = 0x00000632u, /* peri.tr_io_input[18] */ 651 TRIG_IN_MUX_6_HSIOM_IO_INPUT19 = 0x00000633u, /* peri.tr_io_input[19] */ 652 TRIG_IN_MUX_6_HSIOM_IO_INPUT20 = 0x00000634u, /* peri.tr_io_input[20] */ 653 TRIG_IN_MUX_6_HSIOM_IO_INPUT21 = 0x00000635u, /* peri.tr_io_input[21] */ 654 TRIG_IN_MUX_6_HSIOM_IO_INPUT22 = 0x00000636u, /* peri.tr_io_input[22] */ 655 TRIG_IN_MUX_6_HSIOM_IO_INPUT23 = 0x00000637u, /* peri.tr_io_input[23] */ 656 TRIG_IN_MUX_6_HSIOM_IO_INPUT24 = 0x00000638u, /* peri.tr_io_input[24] */ 657 TRIG_IN_MUX_6_HSIOM_IO_INPUT25 = 0x00000639u, /* peri.tr_io_input[25] */ 658 TRIG_IN_MUX_6_HSIOM_IO_INPUT26 = 0x0000063Au, /* peri.tr_io_input[26] */ 659 TRIG_IN_MUX_6_HSIOM_IO_INPUT27 = 0x0000063Bu, /* peri.tr_io_input[27] */ 660 TRIG_IN_MUX_6_HSIOM_IO_INPUT28 = 0x0000063Cu, /* peri.tr_io_input[28] */ 661 TRIG_IN_MUX_6_HSIOM_IO_INPUT29 = 0x0000063Du, /* peri.tr_io_input[29] */ 662 TRIG_IN_MUX_6_HSIOM_IO_INPUT30 = 0x0000063Eu, /* peri.tr_io_input[30] */ 663 TRIG_IN_MUX_6_HSIOM_IO_INPUT31 = 0x0000063Fu, /* peri.tr_io_input[31] */ 664 TRIG_IN_MUX_6_TCPWM_32_TR_OUT10 = 0x00000640u, /* tcpwm[0].tr_out1[512] */ 665 TRIG_IN_MUX_6_TCPWM_32_TR_OUT11 = 0x00000641u, /* tcpwm[0].tr_out1[513] */ 666 TRIG_IN_MUX_6_TCPWM_32_TR_OUT12 = 0x00000642u, /* tcpwm[0].tr_out1[514] */ 667 TRIG_IN_MUX_6_TCPWM_32_TR_OUT13 = 0x00000643u, /* tcpwm[0].tr_out1[515] */ 668 TRIG_IN_MUX_6_TCPWM_16M_TR_OUT10 = 0x00000644u, /* tcpwm[0].tr_out1[256] */ 669 TRIG_IN_MUX_6_TCPWM_16M_TR_OUT11 = 0x00000645u, /* tcpwm[0].tr_out1[257] */ 670 TRIG_IN_MUX_6_TCPWM_16M_TR_OUT12 = 0x00000646u, /* tcpwm[0].tr_out1[258] */ 671 TRIG_IN_MUX_6_TCPWM_16M_TR_OUT13 = 0x00000647u, /* tcpwm[0].tr_out1[259] */ 672 TRIG_IN_MUX_6_TCPWM_16M_TR_OUT14 = 0x00000648u, /* tcpwm[0].tr_out1[260] */ 673 TRIG_IN_MUX_6_TCPWM_16M_TR_OUT15 = 0x00000649u, /* tcpwm[0].tr_out1[261] */ 674 TRIG_IN_MUX_6_TCPWM_16M_TR_OUT16 = 0x0000064Au, /* tcpwm[0].tr_out1[262] */ 675 TRIG_IN_MUX_6_TCPWM_16M_TR_OUT17 = 0x0000064Bu, /* tcpwm[0].tr_out1[263] */ 676 TRIG_IN_MUX_6_TCPWM_16M_TR_OUT18 = 0x0000064Cu, /* tcpwm[0].tr_out1[264] */ 677 TRIG_IN_MUX_6_TCPWM_16M_TR_OUT19 = 0x0000064Du, /* tcpwm[0].tr_out1[265] */ 678 TRIG_IN_MUX_6_TCPWM_16M_TR_OUT110 = 0x0000064Eu, /* tcpwm[0].tr_out1[266] */ 679 TRIG_IN_MUX_6_TCPWM_16M_TR_OUT111 = 0x0000064Fu /* tcpwm[0].tr_out1[267] */ 680 } en_trig_input_pass_t; 681 682 /* Trigger Input Group 7 - CAN TT Synchronization triggers */ 683 typedef enum 684 { 685 TRIG_IN_MUX_7_CAN0_TT_TR_OUT0 = 0x00000701u, /* canfd[0].tr_tmp_rtp_out[0] */ 686 TRIG_IN_MUX_7_CAN0_TT_TR_OUT1 = 0x00000702u, /* canfd[0].tr_tmp_rtp_out[1] */ 687 TRIG_IN_MUX_7_CAN0_TT_TR_OUT2 = 0x00000703u, /* canfd[0].tr_tmp_rtp_out[2] */ 688 TRIG_IN_MUX_7_CAN1_TT_TR_OUT0 = 0x00000704u, /* canfd[1].tr_tmp_rtp_out[0] */ 689 TRIG_IN_MUX_7_CAN1_TT_TR_OUT1 = 0x00000705u, /* canfd[1].tr_tmp_rtp_out[1] */ 690 TRIG_IN_MUX_7_CAN1_TT_TR_OUT2 = 0x00000706u /* canfd[1].tr_tmp_rtp_out[2] */ 691 } en_trig_input_cantt_t; 692 693 /* Trigger Input Group 8 - 2nd level MUX using input from MUX_9/10 */ 694 typedef enum 695 { 696 TRIG_IN_MUX_8_TR_GROUP9_OUTPUT0 = 0x00000801u, /* tr_group[9].output[0] */ 697 TRIG_IN_MUX_8_TR_GROUP9_OUTPUT1 = 0x00000802u, /* tr_group[9].output[1] */ 698 TRIG_IN_MUX_8_TR_GROUP9_OUTPUT2 = 0x00000803u, /* tr_group[9].output[2] */ 699 TRIG_IN_MUX_8_TR_GROUP9_OUTPUT3 = 0x00000804u, /* tr_group[9].output[3] */ 700 TRIG_IN_MUX_8_TR_GROUP9_OUTPUT4 = 0x00000805u, /* tr_group[9].output[4] */ 701 TRIG_IN_MUX_8_TR_GROUP10_OUTPUT0 = 0x00000806u, /* tr_group[10].output[0] */ 702 TRIG_IN_MUX_8_TR_GROUP10_OUTPUT1 = 0x00000807u, /* tr_group[10].output[1] */ 703 TRIG_IN_MUX_8_TR_GROUP10_OUTPUT2 = 0x00000808u, /* tr_group[10].output[2] */ 704 TRIG_IN_MUX_8_TR_GROUP10_OUTPUT3 = 0x00000809u, /* tr_group[10].output[3] */ 705 TRIG_IN_MUX_8_TR_GROUP10_OUTPUT4 = 0x0000080Au /* tr_group[10].output[4] */ 706 } en_trig_input_debugmain_t; 707 708 /* Trigger Input Group 9 - Makes half of all possible triggers visible as I/O signals for debug purposes, or to build external circuitry */ 709 typedef enum 710 { 711 TRIG_IN_MUX_9_PDMA0_TR_OUT0 = 0x00000901u, /* cpuss.dw0_tr_out[0] */ 712 TRIG_IN_MUX_9_PDMA0_TR_OUT1 = 0x00000902u, /* cpuss.dw0_tr_out[1] */ 713 TRIG_IN_MUX_9_PDMA0_TR_OUT2 = 0x00000903u, /* cpuss.dw0_tr_out[2] */ 714 TRIG_IN_MUX_9_PDMA0_TR_OUT3 = 0x00000904u, /* cpuss.dw0_tr_out[3] */ 715 TRIG_IN_MUX_9_PDMA0_TR_OUT4 = 0x00000905u, /* cpuss.dw0_tr_out[4] */ 716 TRIG_IN_MUX_9_PDMA0_TR_OUT5 = 0x00000906u, /* cpuss.dw0_tr_out[5] */ 717 TRIG_IN_MUX_9_PDMA0_TR_OUT6 = 0x00000907u, /* cpuss.dw0_tr_out[6] */ 718 TRIG_IN_MUX_9_PDMA0_TR_OUT7 = 0x00000908u, /* cpuss.dw0_tr_out[7] */ 719 TRIG_IN_MUX_9_PDMA0_TR_OUT8 = 0x00000909u, /* cpuss.dw0_tr_out[8] */ 720 TRIG_IN_MUX_9_PDMA0_TR_OUT9 = 0x0000090Au, /* cpuss.dw0_tr_out[9] */ 721 TRIG_IN_MUX_9_PDMA0_TR_OUT10 = 0x0000090Bu, /* cpuss.dw0_tr_out[10] */ 722 TRIG_IN_MUX_9_PDMA0_TR_OUT11 = 0x0000090Cu, /* cpuss.dw0_tr_out[11] */ 723 TRIG_IN_MUX_9_PDMA0_TR_OUT12 = 0x0000090Du, /* cpuss.dw0_tr_out[12] */ 724 TRIG_IN_MUX_9_PDMA0_TR_OUT13 = 0x0000090Eu, /* cpuss.dw0_tr_out[13] */ 725 TRIG_IN_MUX_9_PDMA0_TR_OUT14 = 0x0000090Fu, /* cpuss.dw0_tr_out[14] */ 726 TRIG_IN_MUX_9_PDMA0_TR_OUT15 = 0x00000910u, /* cpuss.dw0_tr_out[15] */ 727 TRIG_IN_MUX_9_PDMA0_TR_OUT16 = 0x00000911u, /* cpuss.dw0_tr_out[16] */ 728 TRIG_IN_MUX_9_PDMA0_TR_OUT17 = 0x00000912u, /* cpuss.dw0_tr_out[17] */ 729 TRIG_IN_MUX_9_PDMA0_TR_OUT18 = 0x00000913u, /* cpuss.dw0_tr_out[18] */ 730 TRIG_IN_MUX_9_PDMA0_TR_OUT19 = 0x00000914u, /* cpuss.dw0_tr_out[19] */ 731 TRIG_IN_MUX_9_PDMA0_TR_OUT20 = 0x00000915u, /* cpuss.dw0_tr_out[20] */ 732 TRIG_IN_MUX_9_PDMA0_TR_OUT21 = 0x00000916u, /* cpuss.dw0_tr_out[21] */ 733 TRIG_IN_MUX_9_PDMA0_TR_OUT22 = 0x00000917u, /* cpuss.dw0_tr_out[22] */ 734 TRIG_IN_MUX_9_PDMA0_TR_OUT23 = 0x00000918u, /* cpuss.dw0_tr_out[23] */ 735 TRIG_IN_MUX_9_PDMA0_TR_OUT24 = 0x00000919u, /* cpuss.dw0_tr_out[24] */ 736 TRIG_IN_MUX_9_PDMA0_TR_OUT25 = 0x0000091Au, /* cpuss.dw0_tr_out[25] */ 737 TRIG_IN_MUX_9_PDMA0_TR_OUT26 = 0x0000091Bu, /* cpuss.dw0_tr_out[26] */ 738 TRIG_IN_MUX_9_PDMA0_TR_OUT27 = 0x0000091Cu, /* cpuss.dw0_tr_out[27] */ 739 TRIG_IN_MUX_9_PDMA0_TR_OUT28 = 0x0000091Du, /* cpuss.dw0_tr_out[28] */ 740 TRIG_IN_MUX_9_PDMA0_TR_OUT29 = 0x0000091Eu, /* cpuss.dw0_tr_out[29] */ 741 TRIG_IN_MUX_9_PDMA0_TR_OUT30 = 0x0000091Fu, /* cpuss.dw0_tr_out[30] */ 742 TRIG_IN_MUX_9_PDMA0_TR_OUT31 = 0x00000920u, /* cpuss.dw0_tr_out[31] */ 743 TRIG_IN_MUX_9_PDMA0_TR_OUT32 = 0x00000921u, /* cpuss.dw0_tr_out[32] */ 744 TRIG_IN_MUX_9_PDMA0_TR_OUT33 = 0x00000922u, /* cpuss.dw0_tr_out[33] */ 745 TRIG_IN_MUX_9_PDMA0_TR_OUT34 = 0x00000923u, /* cpuss.dw0_tr_out[34] */ 746 TRIG_IN_MUX_9_PDMA0_TR_OUT35 = 0x00000924u, /* cpuss.dw0_tr_out[35] */ 747 TRIG_IN_MUX_9_PDMA0_TR_OUT36 = 0x00000925u, /* cpuss.dw0_tr_out[36] */ 748 TRIG_IN_MUX_9_PDMA0_TR_OUT37 = 0x00000926u, /* cpuss.dw0_tr_out[37] */ 749 TRIG_IN_MUX_9_PDMA0_TR_OUT38 = 0x00000927u, /* cpuss.dw0_tr_out[38] */ 750 TRIG_IN_MUX_9_PDMA0_TR_OUT39 = 0x00000928u, /* cpuss.dw0_tr_out[39] */ 751 TRIG_IN_MUX_9_PDMA0_TR_OUT40 = 0x00000929u, /* cpuss.dw0_tr_out[40] */ 752 TRIG_IN_MUX_9_PDMA0_TR_OUT41 = 0x0000092Au, /* cpuss.dw0_tr_out[41] */ 753 TRIG_IN_MUX_9_PDMA0_TR_OUT42 = 0x0000092Bu, /* cpuss.dw0_tr_out[42] */ 754 TRIG_IN_MUX_9_PDMA0_TR_OUT43 = 0x0000092Cu, /* cpuss.dw0_tr_out[43] */ 755 TRIG_IN_MUX_9_PDMA0_TR_OUT44 = 0x0000092Du, /* cpuss.dw0_tr_out[44] */ 756 TRIG_IN_MUX_9_PDMA0_TR_OUT45 = 0x0000092Eu, /* cpuss.dw0_tr_out[45] */ 757 TRIG_IN_MUX_9_PDMA0_TR_OUT46 = 0x0000092Fu, /* cpuss.dw0_tr_out[46] */ 758 TRIG_IN_MUX_9_PDMA0_TR_OUT47 = 0x00000930u, /* cpuss.dw0_tr_out[47] */ 759 TRIG_IN_MUX_9_PDMA0_TR_OUT48 = 0x00000931u, /* cpuss.dw0_tr_out[48] */ 760 TRIG_IN_MUX_9_PDMA0_TR_OUT49 = 0x00000932u, /* cpuss.dw0_tr_out[49] */ 761 TRIG_IN_MUX_9_PDMA0_TR_OUT50 = 0x00000933u, /* cpuss.dw0_tr_out[50] */ 762 TRIG_IN_MUX_9_PDMA0_TR_OUT51 = 0x00000934u, /* cpuss.dw0_tr_out[51] */ 763 TRIG_IN_MUX_9_PDMA0_TR_OUT52 = 0x00000935u, /* cpuss.dw0_tr_out[52] */ 764 TRIG_IN_MUX_9_PDMA0_TR_OUT53 = 0x00000936u, /* cpuss.dw0_tr_out[53] */ 765 TRIG_IN_MUX_9_PDMA0_TR_OUT54 = 0x00000937u, /* cpuss.dw0_tr_out[54] */ 766 TRIG_IN_MUX_9_PDMA0_TR_OUT55 = 0x00000938u, /* cpuss.dw0_tr_out[55] */ 767 TRIG_IN_MUX_9_PDMA0_TR_OUT56 = 0x00000939u, /* cpuss.dw0_tr_out[56] */ 768 TRIG_IN_MUX_9_PDMA0_TR_OUT57 = 0x0000093Au, /* cpuss.dw0_tr_out[57] */ 769 TRIG_IN_MUX_9_PDMA0_TR_OUT58 = 0x0000093Bu, /* cpuss.dw0_tr_out[58] */ 770 TRIG_IN_MUX_9_PDMA0_TR_OUT59 = 0x0000093Cu, /* cpuss.dw0_tr_out[59] */ 771 TRIG_IN_MUX_9_PDMA0_TR_OUT60 = 0x0000093Du, /* cpuss.dw0_tr_out[60] */ 772 TRIG_IN_MUX_9_PDMA0_TR_OUT61 = 0x0000093Eu, /* cpuss.dw0_tr_out[61] */ 773 TRIG_IN_MUX_9_PDMA0_TR_OUT62 = 0x0000093Fu, /* cpuss.dw0_tr_out[62] */ 774 TRIG_IN_MUX_9_PDMA0_TR_OUT63 = 0x00000940u, /* cpuss.dw0_tr_out[63] */ 775 TRIG_IN_MUX_9_PDMA0_TR_OUT64 = 0x00000941u, /* cpuss.dw0_tr_out[64] */ 776 TRIG_IN_MUX_9_PDMA0_TR_OUT65 = 0x00000942u, /* cpuss.dw0_tr_out[65] */ 777 TRIG_IN_MUX_9_PDMA0_TR_OUT66 = 0x00000943u, /* cpuss.dw0_tr_out[66] */ 778 TRIG_IN_MUX_9_PDMA0_TR_OUT67 = 0x00000944u, /* cpuss.dw0_tr_out[67] */ 779 TRIG_IN_MUX_9_PDMA0_TR_OUT68 = 0x00000945u, /* cpuss.dw0_tr_out[68] */ 780 TRIG_IN_MUX_9_PDMA0_TR_OUT69 = 0x00000946u, /* cpuss.dw0_tr_out[69] */ 781 TRIG_IN_MUX_9_PDMA0_TR_OUT70 = 0x00000947u, /* cpuss.dw0_tr_out[70] */ 782 TRIG_IN_MUX_9_PDMA0_TR_OUT71 = 0x00000948u, /* cpuss.dw0_tr_out[71] */ 783 TRIG_IN_MUX_9_PDMA0_TR_OUT72 = 0x00000949u, /* cpuss.dw0_tr_out[72] */ 784 TRIG_IN_MUX_9_PDMA0_TR_OUT73 = 0x0000094Au, /* cpuss.dw0_tr_out[73] */ 785 TRIG_IN_MUX_9_PDMA0_TR_OUT74 = 0x0000094Bu, /* cpuss.dw0_tr_out[74] */ 786 TRIG_IN_MUX_9_PDMA0_TR_OUT75 = 0x0000094Cu, /* cpuss.dw0_tr_out[75] */ 787 TRIG_IN_MUX_9_PDMA0_TR_OUT76 = 0x0000094Du, /* cpuss.dw0_tr_out[76] */ 788 TRIG_IN_MUX_9_PDMA0_TR_OUT77 = 0x0000094Eu, /* cpuss.dw0_tr_out[77] */ 789 TRIG_IN_MUX_9_PDMA0_TR_OUT78 = 0x0000094Fu, /* cpuss.dw0_tr_out[78] */ 790 TRIG_IN_MUX_9_PDMA0_TR_OUT79 = 0x00000950u, /* cpuss.dw0_tr_out[79] */ 791 TRIG_IN_MUX_9_PDMA0_TR_OUT80 = 0x00000951u, /* cpuss.dw0_tr_out[80] */ 792 TRIG_IN_MUX_9_PDMA0_TR_OUT81 = 0x00000952u, /* cpuss.dw0_tr_out[81] */ 793 TRIG_IN_MUX_9_PDMA0_TR_OUT82 = 0x00000953u, /* cpuss.dw0_tr_out[82] */ 794 TRIG_IN_MUX_9_PDMA0_TR_OUT83 = 0x00000954u, /* cpuss.dw0_tr_out[83] */ 795 TRIG_IN_MUX_9_PDMA0_TR_OUT84 = 0x00000955u, /* cpuss.dw0_tr_out[84] */ 796 TRIG_IN_MUX_9_PDMA0_TR_OUT85 = 0x00000956u, /* cpuss.dw0_tr_out[85] */ 797 TRIG_IN_MUX_9_PDMA0_TR_OUT86 = 0x00000957u, /* cpuss.dw0_tr_out[86] */ 798 TRIG_IN_MUX_9_PDMA0_TR_OUT87 = 0x00000958u, /* cpuss.dw0_tr_out[87] */ 799 TRIG_IN_MUX_9_PDMA0_TR_OUT88 = 0x00000959u, /* cpuss.dw0_tr_out[88] */ 800 TRIG_IN_MUX_9_SCB_TX_TR_OUT0 = 0x0000095Au, /* scb[0].tr_tx_req */ 801 TRIG_IN_MUX_9_SCB_TX_TR_OUT1 = 0x0000095Bu, /* scb[1].tr_tx_req */ 802 TRIG_IN_MUX_9_SCB_TX_TR_OUT2 = 0x0000095Cu, /* scb[2].tr_tx_req */ 803 TRIG_IN_MUX_9_SCB_TX_TR_OUT3 = 0x0000095Du, /* scb[3].tr_tx_req */ 804 TRIG_IN_MUX_9_SCB_TX_TR_OUT4 = 0x0000095Eu, /* scb[4].tr_tx_req */ 805 TRIG_IN_MUX_9_SCB_TX_TR_OUT5 = 0x0000095Fu, /* scb[5].tr_tx_req */ 806 TRIG_IN_MUX_9_SCB_TX_TR_OUT6 = 0x00000960u, /* scb[6].tr_tx_req */ 807 TRIG_IN_MUX_9_SCB_TX_TR_OUT7 = 0x00000961u, /* scb[7].tr_tx_req */ 808 TRIG_IN_MUX_9_SCB_RX_TR_OUT0 = 0x00000962u, /* scb[0].tr_rx_req */ 809 TRIG_IN_MUX_9_SCB_RX_TR_OUT1 = 0x00000963u, /* scb[1].tr_rx_req */ 810 TRIG_IN_MUX_9_SCB_RX_TR_OUT2 = 0x00000964u, /* scb[2].tr_rx_req */ 811 TRIG_IN_MUX_9_SCB_RX_TR_OUT3 = 0x00000965u, /* scb[3].tr_rx_req */ 812 TRIG_IN_MUX_9_SCB_RX_TR_OUT4 = 0x00000966u, /* scb[4].tr_rx_req */ 813 TRIG_IN_MUX_9_SCB_RX_TR_OUT5 = 0x00000967u, /* scb[5].tr_rx_req */ 814 TRIG_IN_MUX_9_SCB_RX_TR_OUT6 = 0x00000968u, /* scb[6].tr_rx_req */ 815 TRIG_IN_MUX_9_SCB_RX_TR_OUT7 = 0x00000969u, /* scb[7].tr_rx_req */ 816 TRIG_IN_MUX_9_SCB_I2C_SCL_TR_OUT0 = 0x0000096Au, /* scb[0].tr_i2c_scl_filtered */ 817 TRIG_IN_MUX_9_SCB_I2C_SCL_TR_OUT1 = 0x0000096Bu, /* scb[1].tr_i2c_scl_filtered */ 818 TRIG_IN_MUX_9_SCB_I2C_SCL_TR_OUT2 = 0x0000096Cu, /* scb[2].tr_i2c_scl_filtered */ 819 TRIG_IN_MUX_9_SCB_I2C_SCL_TR_OUT3 = 0x0000096Du, /* scb[3].tr_i2c_scl_filtered */ 820 TRIG_IN_MUX_9_SCB_I2C_SCL_TR_OUT4 = 0x0000096Eu, /* scb[4].tr_i2c_scl_filtered */ 821 TRIG_IN_MUX_9_SCB_I2C_SCL_TR_OUT5 = 0x0000096Fu, /* scb[5].tr_i2c_scl_filtered */ 822 TRIG_IN_MUX_9_SCB_I2C_SCL_TR_OUT6 = 0x00000970u, /* scb[6].tr_i2c_scl_filtered */ 823 TRIG_IN_MUX_9_SCB_I2C_SCL_TR_OUT7 = 0x00000971u, /* scb[7].tr_i2c_scl_filtered */ 824 TRIG_IN_MUX_9_CAN0_DBG_TR_OUT0 = 0x00000972u, /* canfd[0].tr_dbg_dma_req[0] */ 825 TRIG_IN_MUX_9_CAN0_DBG_TR_OUT1 = 0x00000973u, /* canfd[0].tr_dbg_dma_req[1] */ 826 TRIG_IN_MUX_9_CAN0_DBG_TR_OUT2 = 0x00000974u, /* canfd[0].tr_dbg_dma_req[2] */ 827 TRIG_IN_MUX_9_CAN0_FIFO0_TR_OUT0 = 0x00000975u, /* canfd[0].tr_fifo0[0] */ 828 TRIG_IN_MUX_9_CAN0_FIFO0_TR_OUT1 = 0x00000976u, /* canfd[0].tr_fifo0[1] */ 829 TRIG_IN_MUX_9_CAN0_FIFO0_TR_OUT2 = 0x00000977u, /* canfd[0].tr_fifo0[2] */ 830 TRIG_IN_MUX_9_CAN0_FIFO1_TR_OUT0 = 0x00000978u, /* canfd[0].tr_fifo1[0] */ 831 TRIG_IN_MUX_9_CAN0_FIFO1_TR_OUT1 = 0x00000979u, /* canfd[0].tr_fifo1[1] */ 832 TRIG_IN_MUX_9_CAN0_FIFO1_TR_OUT2 = 0x0000097Au, /* canfd[0].tr_fifo1[2] */ 833 TRIG_IN_MUX_9_CAN0_TT_TR_OUT0 = 0x0000097Bu, /* canfd[0].tr_tmp_rtp_out[0] */ 834 TRIG_IN_MUX_9_CAN0_TT_TR_OUT1 = 0x0000097Cu, /* canfd[0].tr_tmp_rtp_out[1] */ 835 TRIG_IN_MUX_9_CAN0_TT_TR_OUT2 = 0x0000097Du, /* canfd[0].tr_tmp_rtp_out[2] */ 836 TRIG_IN_MUX_9_CAN1_DBG_TR_OUT0 = 0x0000097Eu, /* canfd[1].tr_dbg_dma_req[0] */ 837 TRIG_IN_MUX_9_CAN1_DBG_TR_OUT1 = 0x0000097Fu, /* canfd[1].tr_dbg_dma_req[1] */ 838 TRIG_IN_MUX_9_CAN1_DBG_TR_OUT2 = 0x00000980u, /* canfd[1].tr_dbg_dma_req[2] */ 839 TRIG_IN_MUX_9_CAN1_FIFO0_TR_OUT0 = 0x00000981u, /* canfd[1].tr_fifo0[0] */ 840 TRIG_IN_MUX_9_CAN1_FIFO0_TR_OUT1 = 0x00000982u, /* canfd[1].tr_fifo0[1] */ 841 TRIG_IN_MUX_9_CAN1_FIFO0_TR_OUT2 = 0x00000983u, /* canfd[1].tr_fifo0[2] */ 842 TRIG_IN_MUX_9_CAN1_FIFO1_TR_OUT0 = 0x00000984u, /* canfd[1].tr_fifo1[0] */ 843 TRIG_IN_MUX_9_CAN1_FIFO1_TR_OUT1 = 0x00000985u, /* canfd[1].tr_fifo1[1] */ 844 TRIG_IN_MUX_9_CAN1_FIFO1_TR_OUT2 = 0x00000986u, /* canfd[1].tr_fifo1[2] */ 845 TRIG_IN_MUX_9_CAN1_TT_TR_OUT0 = 0x00000987u, /* canfd[1].tr_tmp_rtp_out[0] */ 846 TRIG_IN_MUX_9_CAN1_TT_TR_OUT1 = 0x00000988u, /* canfd[1].tr_tmp_rtp_out[1] */ 847 TRIG_IN_MUX_9_CAN1_TT_TR_OUT2 = 0x00000989u, /* canfd[1].tr_tmp_rtp_out[2] */ 848 TRIG_IN_MUX_9_CTI_TR_OUT0 = 0x0000098Au, /* cpuss.cti_tr_out[0] */ 849 TRIG_IN_MUX_9_CTI_TR_OUT1 = 0x0000098Bu, /* cpuss.cti_tr_out[1] */ 850 TRIG_IN_MUX_9_FAULT_TR_OUT0 = 0x0000098Cu, /* cpuss.tr_fault[0] */ 851 TRIG_IN_MUX_9_FAULT_TR_OUT1 = 0x0000098Du, /* cpuss.tr_fault[1] */ 852 TRIG_IN_MUX_9_FAULT_TR_OUT2 = 0x0000098Eu, /* cpuss.tr_fault[2] */ 853 TRIG_IN_MUX_9_FAULT_TR_OUT3 = 0x0000098Fu, /* cpuss.tr_fault[3] */ 854 TRIG_IN_MUX_9_TCPWM_32_TR_OUT00 = 0x00000990u, /* tcpwm[0].tr_out0[512] */ 855 TRIG_IN_MUX_9_TCPWM_32_TR_OUT01 = 0x00000991u, /* tcpwm[0].tr_out0[513] */ 856 TRIG_IN_MUX_9_TCPWM_32_TR_OUT02 = 0x00000992u, /* tcpwm[0].tr_out0[514] */ 857 TRIG_IN_MUX_9_TCPWM_32_TR_OUT03 = 0x00000993u, /* tcpwm[0].tr_out0[515] */ 858 TRIG_IN_MUX_9_TCPWM_16M_TR_OUT00 = 0x00000994u, /* tcpwm[0].tr_out0[256] */ 859 TRIG_IN_MUX_9_TCPWM_16M_TR_OUT01 = 0x00000995u, /* tcpwm[0].tr_out0[257] */ 860 TRIG_IN_MUX_9_TCPWM_16M_TR_OUT02 = 0x00000996u, /* tcpwm[0].tr_out0[258] */ 861 TRIG_IN_MUX_9_TCPWM_16M_TR_OUT03 = 0x00000997u, /* tcpwm[0].tr_out0[259] */ 862 TRIG_IN_MUX_9_TCPWM_16M_TR_OUT04 = 0x00000998u, /* tcpwm[0].tr_out0[260] */ 863 TRIG_IN_MUX_9_TCPWM_16M_TR_OUT05 = 0x00000999u, /* tcpwm[0].tr_out0[261] */ 864 TRIG_IN_MUX_9_TCPWM_16M_TR_OUT06 = 0x0000099Au, /* tcpwm[0].tr_out0[262] */ 865 TRIG_IN_MUX_9_TCPWM_16M_TR_OUT07 = 0x0000099Bu, /* tcpwm[0].tr_out0[263] */ 866 TRIG_IN_MUX_9_TCPWM_16M_TR_OUT08 = 0x0000099Cu, /* tcpwm[0].tr_out0[264] */ 867 TRIG_IN_MUX_9_TCPWM_16M_TR_OUT09 = 0x0000099Du, /* tcpwm[0].tr_out0[265] */ 868 TRIG_IN_MUX_9_TCPWM_16M_TR_OUT010 = 0x0000099Eu, /* tcpwm[0].tr_out0[266] */ 869 TRIG_IN_MUX_9_TCPWM_16M_TR_OUT011 = 0x0000099Fu, /* tcpwm[0].tr_out0[267] */ 870 TRIG_IN_MUX_9_TCPWM_16_TR_OUT00 = 0x000009A0u, /* tcpwm[0].tr_out0[0] */ 871 TRIG_IN_MUX_9_TCPWM_16_TR_OUT01 = 0x000009A1u, /* tcpwm[0].tr_out0[1] */ 872 TRIG_IN_MUX_9_TCPWM_16_TR_OUT02 = 0x000009A2u, /* tcpwm[0].tr_out0[2] */ 873 TRIG_IN_MUX_9_TCPWM_16_TR_OUT03 = 0x000009A3u, /* tcpwm[0].tr_out0[3] */ 874 TRIG_IN_MUX_9_TCPWM_16_TR_OUT04 = 0x000009A4u, /* tcpwm[0].tr_out0[4] */ 875 TRIG_IN_MUX_9_TCPWM_16_TR_OUT05 = 0x000009A5u, /* tcpwm[0].tr_out0[5] */ 876 TRIG_IN_MUX_9_TCPWM_16_TR_OUT06 = 0x000009A6u, /* tcpwm[0].tr_out0[6] */ 877 TRIG_IN_MUX_9_TCPWM_16_TR_OUT07 = 0x000009A7u, /* tcpwm[0].tr_out0[7] */ 878 TRIG_IN_MUX_9_TCPWM_16_TR_OUT08 = 0x000009A8u, /* tcpwm[0].tr_out0[8] */ 879 TRIG_IN_MUX_9_TCPWM_16_TR_OUT09 = 0x000009A9u, /* tcpwm[0].tr_out0[9] */ 880 TRIG_IN_MUX_9_TCPWM_16_TR_OUT010 = 0x000009AAu, /* tcpwm[0].tr_out0[10] */ 881 TRIG_IN_MUX_9_TCPWM_16_TR_OUT011 = 0x000009ABu, /* tcpwm[0].tr_out0[11] */ 882 TRIG_IN_MUX_9_TCPWM_16_TR_OUT012 = 0x000009ACu, /* tcpwm[0].tr_out0[12] */ 883 TRIG_IN_MUX_9_TCPWM_16_TR_OUT013 = 0x000009ADu, /* tcpwm[0].tr_out0[13] */ 884 TRIG_IN_MUX_9_TCPWM_16_TR_OUT014 = 0x000009AEu, /* tcpwm[0].tr_out0[14] */ 885 TRIG_IN_MUX_9_TCPWM_16_TR_OUT015 = 0x000009AFu, /* tcpwm[0].tr_out0[15] */ 886 TRIG_IN_MUX_9_TCPWM_16_TR_OUT016 = 0x000009B0u, /* tcpwm[0].tr_out0[16] */ 887 TRIG_IN_MUX_9_TCPWM_16_TR_OUT017 = 0x000009B1u, /* tcpwm[0].tr_out0[17] */ 888 TRIG_IN_MUX_9_TCPWM_16_TR_OUT018 = 0x000009B2u, /* tcpwm[0].tr_out0[18] */ 889 TRIG_IN_MUX_9_TCPWM_16_TR_OUT019 = 0x000009B3u, /* tcpwm[0].tr_out0[19] */ 890 TRIG_IN_MUX_9_TCPWM_16_TR_OUT020 = 0x000009B4u, /* tcpwm[0].tr_out0[20] */ 891 TRIG_IN_MUX_9_TCPWM_16_TR_OUT021 = 0x000009B5u, /* tcpwm[0].tr_out0[21] */ 892 TRIG_IN_MUX_9_TCPWM_16_TR_OUT022 = 0x000009B6u, /* tcpwm[0].tr_out0[22] */ 893 TRIG_IN_MUX_9_TCPWM_16_TR_OUT023 = 0x000009B7u, /* tcpwm[0].tr_out0[23] */ 894 TRIG_IN_MUX_9_TCPWM_16_TR_OUT024 = 0x000009B8u, /* tcpwm[0].tr_out0[24] */ 895 TRIG_IN_MUX_9_TCPWM_16_TR_OUT025 = 0x000009B9u, /* tcpwm[0].tr_out0[25] */ 896 TRIG_IN_MUX_9_TCPWM_16_TR_OUT026 = 0x000009BAu, /* tcpwm[0].tr_out0[26] */ 897 TRIG_IN_MUX_9_TCPWM_16_TR_OUT027 = 0x000009BBu, /* tcpwm[0].tr_out0[27] */ 898 TRIG_IN_MUX_9_TCPWM_16_TR_OUT028 = 0x000009BCu, /* tcpwm[0].tr_out0[28] */ 899 TRIG_IN_MUX_9_TCPWM_16_TR_OUT029 = 0x000009BDu, /* tcpwm[0].tr_out0[29] */ 900 TRIG_IN_MUX_9_TCPWM_16_TR_OUT030 = 0x000009BEu, /* tcpwm[0].tr_out0[30] */ 901 TRIG_IN_MUX_9_TCPWM_16_TR_OUT031 = 0x000009BFu, /* tcpwm[0].tr_out0[31] */ 902 TRIG_IN_MUX_9_TCPWM_16_TR_OUT032 = 0x000009C0u, /* tcpwm[0].tr_out0[32] */ 903 TRIG_IN_MUX_9_TCPWM_16_TR_OUT033 = 0x000009C1u, /* tcpwm[0].tr_out0[33] */ 904 TRIG_IN_MUX_9_TCPWM_16_TR_OUT034 = 0x000009C2u, /* tcpwm[0].tr_out0[34] */ 905 TRIG_IN_MUX_9_TCPWM_16_TR_OUT035 = 0x000009C3u, /* tcpwm[0].tr_out0[35] */ 906 TRIG_IN_MUX_9_TCPWM_16_TR_OUT036 = 0x000009C4u, /* tcpwm[0].tr_out0[36] */ 907 TRIG_IN_MUX_9_TCPWM_16_TR_OUT037 = 0x000009C5u, /* tcpwm[0].tr_out0[37] */ 908 TRIG_IN_MUX_9_TCPWM_16_TR_OUT038 = 0x000009C6u, /* tcpwm[0].tr_out0[38] */ 909 TRIG_IN_MUX_9_TCPWM_16_TR_OUT039 = 0x000009C7u, /* tcpwm[0].tr_out0[39] */ 910 TRIG_IN_MUX_9_TCPWM_16_TR_OUT040 = 0x000009C8u, /* tcpwm[0].tr_out0[40] */ 911 TRIG_IN_MUX_9_TCPWM_16_TR_OUT041 = 0x000009C9u, /* tcpwm[0].tr_out0[41] */ 912 TRIG_IN_MUX_9_TCPWM_16_TR_OUT042 = 0x000009CAu, /* tcpwm[0].tr_out0[42] */ 913 TRIG_IN_MUX_9_TCPWM_16_TR_OUT043 = 0x000009CBu, /* tcpwm[0].tr_out0[43] */ 914 TRIG_IN_MUX_9_TCPWM_16_TR_OUT044 = 0x000009CCu, /* tcpwm[0].tr_out0[44] */ 915 TRIG_IN_MUX_9_TCPWM_16_TR_OUT045 = 0x000009CDu, /* tcpwm[0].tr_out0[45] */ 916 TRIG_IN_MUX_9_TCPWM_16_TR_OUT046 = 0x000009CEu, /* tcpwm[0].tr_out0[46] */ 917 TRIG_IN_MUX_9_TCPWM_16_TR_OUT047 = 0x000009CFu, /* tcpwm[0].tr_out0[47] */ 918 TRIG_IN_MUX_9_TCPWM_16_TR_OUT048 = 0x000009D0u, /* tcpwm[0].tr_out0[48] */ 919 TRIG_IN_MUX_9_TCPWM_16_TR_OUT049 = 0x000009D1u, /* tcpwm[0].tr_out0[49] */ 920 TRIG_IN_MUX_9_TCPWM_16_TR_OUT050 = 0x000009D2u, /* tcpwm[0].tr_out0[50] */ 921 TRIG_IN_MUX_9_TCPWM_16_TR_OUT051 = 0x000009D3u, /* tcpwm[0].tr_out0[51] */ 922 TRIG_IN_MUX_9_TCPWM_16_TR_OUT052 = 0x000009D4u, /* tcpwm[0].tr_out0[52] */ 923 TRIG_IN_MUX_9_TCPWM_16_TR_OUT053 = 0x000009D5u, /* tcpwm[0].tr_out0[53] */ 924 TRIG_IN_MUX_9_TCPWM_16_TR_OUT054 = 0x000009D6u, /* tcpwm[0].tr_out0[54] */ 925 TRIG_IN_MUX_9_TCPWM_16_TR_OUT055 = 0x000009D7u, /* tcpwm[0].tr_out0[55] */ 926 TRIG_IN_MUX_9_TCPWM_16_TR_OUT056 = 0x000009D8u, /* tcpwm[0].tr_out0[56] */ 927 TRIG_IN_MUX_9_TCPWM_16_TR_OUT057 = 0x000009D9u, /* tcpwm[0].tr_out0[57] */ 928 TRIG_IN_MUX_9_TCPWM_16_TR_OUT058 = 0x000009DAu, /* tcpwm[0].tr_out0[58] */ 929 TRIG_IN_MUX_9_TCPWM_16_TR_OUT059 = 0x000009DBu, /* tcpwm[0].tr_out0[59] */ 930 TRIG_IN_MUX_9_TCPWM_16_TR_OUT060 = 0x000009DCu, /* tcpwm[0].tr_out0[60] */ 931 TRIG_IN_MUX_9_TCPWM_16_TR_OUT061 = 0x000009DDu, /* tcpwm[0].tr_out0[61] */ 932 TRIG_IN_MUX_9_TCPWM_16_TR_OUT062 = 0x000009DEu /* tcpwm[0].tr_out0[62] */ 933 } en_trig_input_debugreduction1_t; 934 935 /* Trigger Input Group 10 - Makes all possible triggers visible as I/O signals for debug purposes, or to build external circuitry */ 936 typedef enum 937 { 938 TRIG_IN_MUX_10_PDMA1_TR_OUT0 = 0x00000A01u, /* cpuss.dw1_tr_out[0] */ 939 TRIG_IN_MUX_10_PDMA1_TR_OUT1 = 0x00000A02u, /* cpuss.dw1_tr_out[1] */ 940 TRIG_IN_MUX_10_PDMA1_TR_OUT2 = 0x00000A03u, /* cpuss.dw1_tr_out[2] */ 941 TRIG_IN_MUX_10_PDMA1_TR_OUT3 = 0x00000A04u, /* cpuss.dw1_tr_out[3] */ 942 TRIG_IN_MUX_10_PDMA1_TR_OUT4 = 0x00000A05u, /* cpuss.dw1_tr_out[4] */ 943 TRIG_IN_MUX_10_PDMA1_TR_OUT5 = 0x00000A06u, /* cpuss.dw1_tr_out[5] */ 944 TRIG_IN_MUX_10_PDMA1_TR_OUT6 = 0x00000A07u, /* cpuss.dw1_tr_out[6] */ 945 TRIG_IN_MUX_10_PDMA1_TR_OUT7 = 0x00000A08u, /* cpuss.dw1_tr_out[7] */ 946 TRIG_IN_MUX_10_PDMA1_TR_OUT8 = 0x00000A09u, /* cpuss.dw1_tr_out[8] */ 947 TRIG_IN_MUX_10_PDMA1_TR_OUT9 = 0x00000A0Au, /* cpuss.dw1_tr_out[9] */ 948 TRIG_IN_MUX_10_PDMA1_TR_OUT10 = 0x00000A0Bu, /* cpuss.dw1_tr_out[10] */ 949 TRIG_IN_MUX_10_PDMA1_TR_OUT11 = 0x00000A0Cu, /* cpuss.dw1_tr_out[11] */ 950 TRIG_IN_MUX_10_PDMA1_TR_OUT12 = 0x00000A0Du, /* cpuss.dw1_tr_out[12] */ 951 TRIG_IN_MUX_10_PDMA1_TR_OUT13 = 0x00000A0Eu, /* cpuss.dw1_tr_out[13] */ 952 TRIG_IN_MUX_10_PDMA1_TR_OUT14 = 0x00000A0Fu, /* cpuss.dw1_tr_out[14] */ 953 TRIG_IN_MUX_10_PDMA1_TR_OUT15 = 0x00000A10u, /* cpuss.dw1_tr_out[15] */ 954 TRIG_IN_MUX_10_PDMA1_TR_OUT16 = 0x00000A11u, /* cpuss.dw1_tr_out[16] */ 955 TRIG_IN_MUX_10_PDMA1_TR_OUT17 = 0x00000A12u, /* cpuss.dw1_tr_out[17] */ 956 TRIG_IN_MUX_10_PDMA1_TR_OUT18 = 0x00000A13u, /* cpuss.dw1_tr_out[18] */ 957 TRIG_IN_MUX_10_PDMA1_TR_OUT19 = 0x00000A14u, /* cpuss.dw1_tr_out[19] */ 958 TRIG_IN_MUX_10_PDMA1_TR_OUT20 = 0x00000A15u, /* cpuss.dw1_tr_out[20] */ 959 TRIG_IN_MUX_10_PDMA1_TR_OUT21 = 0x00000A16u, /* cpuss.dw1_tr_out[21] */ 960 TRIG_IN_MUX_10_PDMA1_TR_OUT22 = 0x00000A17u, /* cpuss.dw1_tr_out[22] */ 961 TRIG_IN_MUX_10_PDMA1_TR_OUT23 = 0x00000A18u, /* cpuss.dw1_tr_out[23] */ 962 TRIG_IN_MUX_10_PDMA1_TR_OUT24 = 0x00000A19u, /* cpuss.dw1_tr_out[24] */ 963 TRIG_IN_MUX_10_PDMA1_TR_OUT25 = 0x00000A1Au, /* cpuss.dw1_tr_out[25] */ 964 TRIG_IN_MUX_10_PDMA1_TR_OUT26 = 0x00000A1Bu, /* cpuss.dw1_tr_out[26] */ 965 TRIG_IN_MUX_10_PDMA1_TR_OUT27 = 0x00000A1Cu, /* cpuss.dw1_tr_out[27] */ 966 TRIG_IN_MUX_10_PDMA1_TR_OUT28 = 0x00000A1Du, /* cpuss.dw1_tr_out[28] */ 967 TRIG_IN_MUX_10_PDMA1_TR_OUT29 = 0x00000A1Eu, /* cpuss.dw1_tr_out[29] */ 968 TRIG_IN_MUX_10_PDMA1_TR_OUT30 = 0x00000A1Fu, /* cpuss.dw1_tr_out[30] */ 969 TRIG_IN_MUX_10_PDMA1_TR_OUT31 = 0x00000A20u, /* cpuss.dw1_tr_out[31] */ 970 TRIG_IN_MUX_10_PDMA1_TR_OUT32 = 0x00000A21u, /* cpuss.dw1_tr_out[32] */ 971 TRIG_IN_MUX_10_MDMA_TR_OUT0 = 0x00000A22u, /* cpuss.dmac_tr_out[0] */ 972 TRIG_IN_MUX_10_MDMA_TR_OUT1 = 0x00000A23u, /* cpuss.dmac_tr_out[1] */ 973 TRIG_IN_MUX_10_MDMA_TR_OUT2 = 0x00000A24u, /* cpuss.dmac_tr_out[2] */ 974 TRIG_IN_MUX_10_MDMA_TR_OUT3 = 0x00000A25u, /* cpuss.dmac_tr_out[3] */ 975 TRIG_IN_MUX_10_TCPWM_32_TR_OUT10 = 0x00000A26u, /* tcpwm[0].tr_out1[512] */ 976 TRIG_IN_MUX_10_TCPWM_32_TR_OUT11 = 0x00000A27u, /* tcpwm[0].tr_out1[513] */ 977 TRIG_IN_MUX_10_TCPWM_32_TR_OUT12 = 0x00000A28u, /* tcpwm[0].tr_out1[514] */ 978 TRIG_IN_MUX_10_TCPWM_32_TR_OUT13 = 0x00000A29u, /* tcpwm[0].tr_out1[515] */ 979 TRIG_IN_MUX_10_TCPWM_16M_TR_OUT10 = 0x00000A2Au, /* tcpwm[0].tr_out1[256] */ 980 TRIG_IN_MUX_10_TCPWM_16M_TR_OUT11 = 0x00000A2Bu, /* tcpwm[0].tr_out1[257] */ 981 TRIG_IN_MUX_10_TCPWM_16M_TR_OUT12 = 0x00000A2Cu, /* tcpwm[0].tr_out1[258] */ 982 TRIG_IN_MUX_10_TCPWM_16M_TR_OUT13 = 0x00000A2Du, /* tcpwm[0].tr_out1[259] */ 983 TRIG_IN_MUX_10_TCPWM_16M_TR_OUT14 = 0x00000A2Eu, /* tcpwm[0].tr_out1[260] */ 984 TRIG_IN_MUX_10_TCPWM_16M_TR_OUT15 = 0x00000A2Fu, /* tcpwm[0].tr_out1[261] */ 985 TRIG_IN_MUX_10_TCPWM_16M_TR_OUT16 = 0x00000A30u, /* tcpwm[0].tr_out1[262] */ 986 TRIG_IN_MUX_10_TCPWM_16M_TR_OUT17 = 0x00000A31u, /* tcpwm[0].tr_out1[263] */ 987 TRIG_IN_MUX_10_TCPWM_16M_TR_OUT18 = 0x00000A32u, /* tcpwm[0].tr_out1[264] */ 988 TRIG_IN_MUX_10_TCPWM_16M_TR_OUT19 = 0x00000A33u, /* tcpwm[0].tr_out1[265] */ 989 TRIG_IN_MUX_10_TCPWM_16M_TR_OUT110 = 0x00000A34u, /* tcpwm[0].tr_out1[266] */ 990 TRIG_IN_MUX_10_TCPWM_16M_TR_OUT111 = 0x00000A35u, /* tcpwm[0].tr_out1[267] */ 991 TRIG_IN_MUX_10_TCPWM_16_TR_OUT10 = 0x00000A36u, /* tcpwm[0].tr_out1[0] */ 992 TRIG_IN_MUX_10_TCPWM_16_TR_OUT11 = 0x00000A37u, /* tcpwm[0].tr_out1[1] */ 993 TRIG_IN_MUX_10_TCPWM_16_TR_OUT12 = 0x00000A38u, /* tcpwm[0].tr_out1[2] */ 994 TRIG_IN_MUX_10_TCPWM_16_TR_OUT13 = 0x00000A39u, /* tcpwm[0].tr_out1[3] */ 995 TRIG_IN_MUX_10_TCPWM_16_TR_OUT14 = 0x00000A3Au, /* tcpwm[0].tr_out1[4] */ 996 TRIG_IN_MUX_10_TCPWM_16_TR_OUT15 = 0x00000A3Bu, /* tcpwm[0].tr_out1[5] */ 997 TRIG_IN_MUX_10_TCPWM_16_TR_OUT16 = 0x00000A3Cu, /* tcpwm[0].tr_out1[6] */ 998 TRIG_IN_MUX_10_TCPWM_16_TR_OUT17 = 0x00000A3Du, /* tcpwm[0].tr_out1[7] */ 999 TRIG_IN_MUX_10_TCPWM_16_TR_OUT18 = 0x00000A3Eu, /* tcpwm[0].tr_out1[8] */ 1000 TRIG_IN_MUX_10_TCPWM_16_TR_OUT19 = 0x00000A3Fu, /* tcpwm[0].tr_out1[9] */ 1001 TRIG_IN_MUX_10_TCPWM_16_TR_OUT110 = 0x00000A40u, /* tcpwm[0].tr_out1[10] */ 1002 TRIG_IN_MUX_10_TCPWM_16_TR_OUT111 = 0x00000A41u, /* tcpwm[0].tr_out1[11] */ 1003 TRIG_IN_MUX_10_TCPWM_16_TR_OUT112 = 0x00000A42u, /* tcpwm[0].tr_out1[12] */ 1004 TRIG_IN_MUX_10_TCPWM_16_TR_OUT113 = 0x00000A43u, /* tcpwm[0].tr_out1[13] */ 1005 TRIG_IN_MUX_10_TCPWM_16_TR_OUT114 = 0x00000A44u, /* tcpwm[0].tr_out1[14] */ 1006 TRIG_IN_MUX_10_TCPWM_16_TR_OUT115 = 0x00000A45u, /* tcpwm[0].tr_out1[15] */ 1007 TRIG_IN_MUX_10_TCPWM_16_TR_OUT116 = 0x00000A46u, /* tcpwm[0].tr_out1[16] */ 1008 TRIG_IN_MUX_10_TCPWM_16_TR_OUT117 = 0x00000A47u, /* tcpwm[0].tr_out1[17] */ 1009 TRIG_IN_MUX_10_TCPWM_16_TR_OUT118 = 0x00000A48u, /* tcpwm[0].tr_out1[18] */ 1010 TRIG_IN_MUX_10_TCPWM_16_TR_OUT119 = 0x00000A49u, /* tcpwm[0].tr_out1[19] */ 1011 TRIG_IN_MUX_10_TCPWM_16_TR_OUT120 = 0x00000A4Au, /* tcpwm[0].tr_out1[20] */ 1012 TRIG_IN_MUX_10_TCPWM_16_TR_OUT121 = 0x00000A4Bu, /* tcpwm[0].tr_out1[21] */ 1013 TRIG_IN_MUX_10_TCPWM_16_TR_OUT122 = 0x00000A4Cu, /* tcpwm[0].tr_out1[22] */ 1014 TRIG_IN_MUX_10_TCPWM_16_TR_OUT123 = 0x00000A4Du, /* tcpwm[0].tr_out1[23] */ 1015 TRIG_IN_MUX_10_TCPWM_16_TR_OUT124 = 0x00000A4Eu, /* tcpwm[0].tr_out1[24] */ 1016 TRIG_IN_MUX_10_TCPWM_16_TR_OUT125 = 0x00000A4Fu, /* tcpwm[0].tr_out1[25] */ 1017 TRIG_IN_MUX_10_TCPWM_16_TR_OUT126 = 0x00000A50u, /* tcpwm[0].tr_out1[26] */ 1018 TRIG_IN_MUX_10_TCPWM_16_TR_OUT127 = 0x00000A51u, /* tcpwm[0].tr_out1[27] */ 1019 TRIG_IN_MUX_10_TCPWM_16_TR_OUT128 = 0x00000A52u, /* tcpwm[0].tr_out1[28] */ 1020 TRIG_IN_MUX_10_TCPWM_16_TR_OUT129 = 0x00000A53u, /* tcpwm[0].tr_out1[29] */ 1021 TRIG_IN_MUX_10_TCPWM_16_TR_OUT130 = 0x00000A54u, /* tcpwm[0].tr_out1[30] */ 1022 TRIG_IN_MUX_10_TCPWM_16_TR_OUT131 = 0x00000A55u, /* tcpwm[0].tr_out1[31] */ 1023 TRIG_IN_MUX_10_TCPWM_16_TR_OUT132 = 0x00000A56u, /* tcpwm[0].tr_out1[32] */ 1024 TRIG_IN_MUX_10_TCPWM_16_TR_OUT133 = 0x00000A57u, /* tcpwm[0].tr_out1[33] */ 1025 TRIG_IN_MUX_10_TCPWM_16_TR_OUT134 = 0x00000A58u, /* tcpwm[0].tr_out1[34] */ 1026 TRIG_IN_MUX_10_TCPWM_16_TR_OUT135 = 0x00000A59u, /* tcpwm[0].tr_out1[35] */ 1027 TRIG_IN_MUX_10_TCPWM_16_TR_OUT136 = 0x00000A5Au, /* tcpwm[0].tr_out1[36] */ 1028 TRIG_IN_MUX_10_TCPWM_16_TR_OUT137 = 0x00000A5Bu, /* tcpwm[0].tr_out1[37] */ 1029 TRIG_IN_MUX_10_TCPWM_16_TR_OUT138 = 0x00000A5Cu, /* tcpwm[0].tr_out1[38] */ 1030 TRIG_IN_MUX_10_TCPWM_16_TR_OUT139 = 0x00000A5Du, /* tcpwm[0].tr_out1[39] */ 1031 TRIG_IN_MUX_10_TCPWM_16_TR_OUT140 = 0x00000A5Eu, /* tcpwm[0].tr_out1[40] */ 1032 TRIG_IN_MUX_10_TCPWM_16_TR_OUT141 = 0x00000A5Fu, /* tcpwm[0].tr_out1[41] */ 1033 TRIG_IN_MUX_10_TCPWM_16_TR_OUT142 = 0x00000A60u, /* tcpwm[0].tr_out1[42] */ 1034 TRIG_IN_MUX_10_TCPWM_16_TR_OUT143 = 0x00000A61u, /* tcpwm[0].tr_out1[43] */ 1035 TRIG_IN_MUX_10_TCPWM_16_TR_OUT144 = 0x00000A62u, /* tcpwm[0].tr_out1[44] */ 1036 TRIG_IN_MUX_10_TCPWM_16_TR_OUT145 = 0x00000A63u, /* tcpwm[0].tr_out1[45] */ 1037 TRIG_IN_MUX_10_TCPWM_16_TR_OUT146 = 0x00000A64u, /* tcpwm[0].tr_out1[46] */ 1038 TRIG_IN_MUX_10_TCPWM_16_TR_OUT147 = 0x00000A65u, /* tcpwm[0].tr_out1[47] */ 1039 TRIG_IN_MUX_10_TCPWM_16_TR_OUT148 = 0x00000A66u, /* tcpwm[0].tr_out1[48] */ 1040 TRIG_IN_MUX_10_TCPWM_16_TR_OUT149 = 0x00000A67u, /* tcpwm[0].tr_out1[49] */ 1041 TRIG_IN_MUX_10_TCPWM_16_TR_OUT150 = 0x00000A68u, /* tcpwm[0].tr_out1[50] */ 1042 TRIG_IN_MUX_10_TCPWM_16_TR_OUT151 = 0x00000A69u, /* tcpwm[0].tr_out1[51] */ 1043 TRIG_IN_MUX_10_TCPWM_16_TR_OUT152 = 0x00000A6Au, /* tcpwm[0].tr_out1[52] */ 1044 TRIG_IN_MUX_10_TCPWM_16_TR_OUT153 = 0x00000A6Bu, /* tcpwm[0].tr_out1[53] */ 1045 TRIG_IN_MUX_10_TCPWM_16_TR_OUT154 = 0x00000A6Cu, /* tcpwm[0].tr_out1[54] */ 1046 TRIG_IN_MUX_10_TCPWM_16_TR_OUT155 = 0x00000A6Du, /* tcpwm[0].tr_out1[55] */ 1047 TRIG_IN_MUX_10_TCPWM_16_TR_OUT156 = 0x00000A6Eu, /* tcpwm[0].tr_out1[56] */ 1048 TRIG_IN_MUX_10_TCPWM_16_TR_OUT157 = 0x00000A6Fu, /* tcpwm[0].tr_out1[57] */ 1049 TRIG_IN_MUX_10_TCPWM_16_TR_OUT158 = 0x00000A70u, /* tcpwm[0].tr_out1[58] */ 1050 TRIG_IN_MUX_10_TCPWM_16_TR_OUT159 = 0x00000A71u, /* tcpwm[0].tr_out1[59] */ 1051 TRIG_IN_MUX_10_TCPWM_16_TR_OUT160 = 0x00000A72u, /* tcpwm[0].tr_out1[60] */ 1052 TRIG_IN_MUX_10_TCPWM_16_TR_OUT161 = 0x00000A73u, /* tcpwm[0].tr_out1[61] */ 1053 TRIG_IN_MUX_10_TCPWM_16_TR_OUT162 = 0x00000A74u, /* tcpwm[0].tr_out1[62] */ 1054 TRIG_IN_MUX_10_PASS_GEN_TR_OUT0 = 0x00000A75u, /* pass[0].tr_sar_gen_out[0] */ 1055 TRIG_IN_MUX_10_PASS_GEN_TR_OUT1 = 0x00000A76u, /* pass[0].tr_sar_gen_out[1] */ 1056 TRIG_IN_MUX_10_PASS_GEN_TR_OUT2 = 0x00000A77u, /* pass[0].tr_sar_gen_out[2] */ 1057 TRIG_IN_MUX_10_PASS_GEN_TR_OUT3 = 0x00000A78u, /* pass[0].tr_sar_gen_out[3] */ 1058 TRIG_IN_MUX_10_PASS_GEN_TR_OUT4 = 0x00000A79u, /* pass[0].tr_sar_gen_out[4] */ 1059 TRIG_IN_MUX_10_PASS_GEN_TR_OUT5 = 0x00000A7Au, /* pass[0].tr_sar_gen_out[5] */ 1060 TRIG_IN_MUX_10_EVTGEN_TR_OUT0 = 0x00000A7Bu, /* evtgen[0].tr_out[0] */ 1061 TRIG_IN_MUX_10_EVTGEN_TR_OUT1 = 0x00000A7Cu, /* evtgen[0].tr_out[1] */ 1062 TRIG_IN_MUX_10_EVTGEN_TR_OUT2 = 0x00000A7Du, /* evtgen[0].tr_out[2] */ 1063 TRIG_IN_MUX_10_EVTGEN_TR_OUT3 = 0x00000A7Eu, /* evtgen[0].tr_out[3] */ 1064 TRIG_IN_MUX_10_EVTGEN_TR_OUT4 = 0x00000A7Fu, /* evtgen[0].tr_out[4] */ 1065 TRIG_IN_MUX_10_EVTGEN_TR_OUT5 = 0x00000A80u, /* evtgen[0].tr_out[5] */ 1066 TRIG_IN_MUX_10_EVTGEN_TR_OUT6 = 0x00000A81u, /* evtgen[0].tr_out[6] */ 1067 TRIG_IN_MUX_10_EVTGEN_TR_OUT7 = 0x00000A82u, /* evtgen[0].tr_out[7] */ 1068 TRIG_IN_MUX_10_EVTGEN_TR_OUT8 = 0x00000A83u, /* evtgen[0].tr_out[8] */ 1069 TRIG_IN_MUX_10_EVTGEN_TR_OUT9 = 0x00000A84u, /* evtgen[0].tr_out[9] */ 1070 TRIG_IN_MUX_10_EVTGEN_TR_OUT10 = 0x00000A85u /* evtgen[0].tr_out[10] */ 1071 } en_trig_input_debugreduction2_t; 1072 1073 /* Trigger Group Outputs */ 1074 /* Trigger Output Group 0 - P-DMA0 Request Assignments */ 1075 typedef enum 1076 { 1077 TRIG_OUT_MUX_0_PDMA0_TR_IN0 = 0x40000000u, /* cpuss.dw0_tr_in[0] */ 1078 TRIG_OUT_MUX_0_PDMA0_TR_IN1 = 0x40000001u, /* cpuss.dw0_tr_in[1] */ 1079 TRIG_OUT_MUX_0_PDMA0_TR_IN2 = 0x40000002u, /* cpuss.dw0_tr_in[2] */ 1080 TRIG_OUT_MUX_0_PDMA0_TR_IN3 = 0x40000003u, /* cpuss.dw0_tr_in[3] */ 1081 TRIG_OUT_MUX_0_PDMA0_TR_IN4 = 0x40000004u, /* cpuss.dw0_tr_in[4] */ 1082 TRIG_OUT_MUX_0_PDMA0_TR_IN5 = 0x40000005u, /* cpuss.dw0_tr_in[5] */ 1083 TRIG_OUT_MUX_0_PDMA0_TR_IN6 = 0x40000006u, /* cpuss.dw0_tr_in[6] */ 1084 TRIG_OUT_MUX_0_PDMA0_TR_IN7 = 0x40000007u /* cpuss.dw0_tr_in[7] */ 1085 } en_trig_output_pdma0_tr_0_t; 1086 1087 /* Trigger Output Group 1 - P-DMA1 Request Assignments */ 1088 typedef enum 1089 { 1090 TRIG_OUT_MUX_1_PDMA1_TR_IN0 = 0x40000100u, /* cpuss.dw1_tr_in[0] */ 1091 TRIG_OUT_MUX_1_PDMA1_TR_IN1 = 0x40000101u, /* cpuss.dw1_tr_in[1] */ 1092 TRIG_OUT_MUX_1_PDMA1_TR_IN2 = 0x40000102u, /* cpuss.dw1_tr_in[2] */ 1093 TRIG_OUT_MUX_1_PDMA1_TR_IN3 = 0x40000103u, /* cpuss.dw1_tr_in[3] */ 1094 TRIG_OUT_MUX_1_PDMA1_TR_IN4 = 0x40000104u, /* cpuss.dw1_tr_in[4] */ 1095 TRIG_OUT_MUX_1_PDMA1_TR_IN5 = 0x40000105u, /* cpuss.dw1_tr_in[5] */ 1096 TRIG_OUT_MUX_1_PDMA1_TR_IN6 = 0x40000106u, /* cpuss.dw1_tr_in[6] */ 1097 TRIG_OUT_MUX_1_PDMA1_TR_IN7 = 0x40000107u /* cpuss.dw1_tr_in[7] */ 1098 } en_trig_output_pdma1_tr_t; 1099 1100 /* Trigger Output Group 2 - DMA Request Assignments */ 1101 typedef enum 1102 { 1103 TRIG_OUT_MUX_2_MDMA_TR_IN0 = 0x40000200u, /* cpuss.dmac_tr_in[0] */ 1104 TRIG_OUT_MUX_2_MDMA_TR_IN1 = 0x40000201u, /* cpuss.dmac_tr_in[1] */ 1105 TRIG_OUT_MUX_2_MDMA_TR_IN2 = 0x40000202u, /* cpuss.dmac_tr_in[2] */ 1106 TRIG_OUT_MUX_2_MDMA_TR_IN3 = 0x40000203u /* cpuss.dmac_tr_in[3] */ 1107 } en_trig_output_mdma_t; 1108 1109 /* Trigger Output Group 3 - Dedicated mux for counter to P-DMA0 triggers */ 1110 typedef enum 1111 { 1112 TRIG_OUT_MUX_3_PDMA0_TR_IN8 = 0x40000300u, /* cpuss.dw0_tr_in[8] */ 1113 TRIG_OUT_MUX_3_PDMA0_TR_IN9 = 0x40000301u, /* cpuss.dw0_tr_in[9] */ 1114 TRIG_OUT_MUX_3_PDMA0_TR_IN10 = 0x40000302u, /* cpuss.dw0_tr_in[10] */ 1115 TRIG_OUT_MUX_3_PDMA0_TR_IN11 = 0x40000303u, /* cpuss.dw0_tr_in[11] */ 1116 TRIG_OUT_MUX_3_PDMA0_TR_IN12 = 0x40000304u, /* cpuss.dw0_tr_in[12] */ 1117 TRIG_OUT_MUX_3_PDMA0_TR_IN13 = 0x40000305u, /* cpuss.dw0_tr_in[13] */ 1118 TRIG_OUT_MUX_3_PDMA0_TR_IN14 = 0x40000306u, /* cpuss.dw0_tr_in[14] */ 1119 TRIG_OUT_MUX_3_PDMA0_TR_IN15 = 0x40000307u /* cpuss.dw0_tr_in[15] */ 1120 } en_trig_output_pdma0_tr_1_t; 1121 1122 /* Trigger Output Group 4 - Reduces tcpwm output triggers to 16 signals, to allow chaining TCPWMs */ 1123 typedef enum 1124 { 1125 TRIG_OUT_MUX_4_TCPWM_ALL_CNT_TR_IN0 = 0x40000400u, /* tcpwm[0].tr_all_cnt_in[0] */ 1126 TRIG_OUT_MUX_4_TCPWM_ALL_CNT_TR_IN1 = 0x40000401u, /* tcpwm[0].tr_all_cnt_in[1] */ 1127 TRIG_OUT_MUX_4_TCPWM_ALL_CNT_TR_IN2 = 0x40000402u, /* tcpwm[0].tr_all_cnt_in[2] */ 1128 TRIG_OUT_MUX_4_TCPWM_ALL_CNT_TR_IN3 = 0x40000403u, /* tcpwm[0].tr_all_cnt_in[3] */ 1129 TRIG_OUT_MUX_4_TCPWM_ALL_CNT_TR_IN4 = 0x40000404u, /* tcpwm[0].tr_all_cnt_in[4] */ 1130 TRIG_OUT_MUX_4_TCPWM_ALL_CNT_TR_IN5 = 0x40000405u, /* tcpwm[0].tr_all_cnt_in[5] */ 1131 TRIG_OUT_MUX_4_TCPWM_ALL_CNT_TR_IN6 = 0x40000406u, /* tcpwm[0].tr_all_cnt_in[6] */ 1132 TRIG_OUT_MUX_4_TCPWM_ALL_CNT_TR_IN7 = 0x40000407u, /* tcpwm[0].tr_all_cnt_in[7] */ 1133 TRIG_OUT_MUX_4_TCPWM_ALL_CNT_TR_IN8 = 0x40000408u, /* tcpwm[0].tr_all_cnt_in[8] */ 1134 TRIG_OUT_MUX_4_TCPWM_ALL_CNT_TR_IN9 = 0x40000409u, /* tcpwm[0].tr_all_cnt_in[9] */ 1135 TRIG_OUT_MUX_4_TCPWM_ALL_CNT_TR_IN10 = 0x4000040Au, /* tcpwm[0].tr_all_cnt_in[10] */ 1136 TRIG_OUT_MUX_4_TCPWM_ALL_CNT_TR_IN11 = 0x4000040Bu, /* tcpwm[0].tr_all_cnt_in[11] */ 1137 TRIG_OUT_MUX_4_TCPWM_ALL_CNT_TR_IN12 = 0x4000040Cu, /* tcpwm[0].tr_all_cnt_in[12] */ 1138 TRIG_OUT_MUX_4_TCPWM_ALL_CNT_TR_IN13 = 0x4000040Du, /* tcpwm[0].tr_all_cnt_in[13] */ 1139 TRIG_OUT_MUX_4_TCPWM_ALL_CNT_TR_IN14 = 0x4000040Eu, /* tcpwm[0].tr_all_cnt_in[14] */ 1140 TRIG_OUT_MUX_4_TCPWM_ALL_CNT_TR_IN15 = 0x4000040Fu /* tcpwm[0].tr_all_cnt_in[15] */ 1141 } en_trig_output_tcpwm_out_t; 1142 1143 /* Trigger Output Group 5 - TCPWM trigger inputs */ 1144 typedef enum 1145 { 1146 TRIG_OUT_MUX_5_TCPWM_ALL_CNT_TR_IN16 = 0x40000500u, /* tcpwm[0].tr_all_cnt_in[16] */ 1147 TRIG_OUT_MUX_5_TCPWM_ALL_CNT_TR_IN17 = 0x40000501u, /* tcpwm[0].tr_all_cnt_in[17] */ 1148 TRIG_OUT_MUX_5_TCPWM_ALL_CNT_TR_IN18 = 0x40000502u, /* tcpwm[0].tr_all_cnt_in[18] */ 1149 TRIG_OUT_MUX_5_TCPWM_ALL_CNT_TR_IN19 = 0x40000503u, /* tcpwm[0].tr_all_cnt_in[19] */ 1150 TRIG_OUT_MUX_5_TCPWM_ALL_CNT_TR_IN20 = 0x40000504u, /* tcpwm[0].tr_all_cnt_in[20] */ 1151 TRIG_OUT_MUX_5_TCPWM_ALL_CNT_TR_IN21 = 0x40000505u, /* tcpwm[0].tr_all_cnt_in[21] */ 1152 TRIG_OUT_MUX_5_TCPWM_ALL_CNT_TR_IN22 = 0x40000506u, /* tcpwm[0].tr_all_cnt_in[22] */ 1153 TRIG_OUT_MUX_5_TCPWM_ALL_CNT_TR_IN23 = 0x40000507u, /* tcpwm[0].tr_all_cnt_in[23] */ 1154 TRIG_OUT_MUX_5_TCPWM_ALL_CNT_TR_IN24 = 0x40000508u, /* tcpwm[0].tr_all_cnt_in[24] */ 1155 TRIG_OUT_MUX_5_TCPWM_ALL_CNT_TR_IN25 = 0x40000509u, /* tcpwm[0].tr_all_cnt_in[25] */ 1156 TRIG_OUT_MUX_5_TCPWM_ALL_CNT_TR_IN26 = 0x4000050Au /* tcpwm[0].tr_all_cnt_in[26] */ 1157 } en_trig_output_tcpwm_in_t; 1158 1159 /* Trigger Output Group 6 - PASS trigger multiplexer */ 1160 typedef enum 1161 { 1162 TRIG_OUT_MUX_6_PASS_GEN_TR_IN0 = 0x40000600u, /* pass[0].tr_sar_gen_in[0] */ 1163 TRIG_OUT_MUX_6_PASS_GEN_TR_IN1 = 0x40000601u, /* pass[0].tr_sar_gen_in[1] */ 1164 TRIG_OUT_MUX_6_PASS_GEN_TR_IN2 = 0x40000602u, /* pass[0].tr_sar_gen_in[2] */ 1165 TRIG_OUT_MUX_6_PASS_GEN_TR_IN3 = 0x40000603u, /* pass[0].tr_sar_gen_in[3] */ 1166 TRIG_OUT_MUX_6_PASS_GEN_TR_IN4 = 0x40000604u, /* pass[0].tr_sar_gen_in[4] */ 1167 TRIG_OUT_MUX_6_PASS_GEN_TR_IN5 = 0x40000605u, /* pass[0].tr_sar_gen_in[5] */ 1168 TRIG_OUT_MUX_6_PASS_GEN_TR_IN6 = 0x40000606u, /* pass[0].tr_sar_gen_in[6] */ 1169 TRIG_OUT_MUX_6_PASS_GEN_TR_IN7 = 0x40000607u, /* pass[0].tr_sar_gen_in[7] */ 1170 TRIG_OUT_MUX_6_PASS_GEN_TR_IN8 = 0x40000608u, /* pass[0].tr_sar_gen_in[8] */ 1171 TRIG_OUT_MUX_6_PASS_GEN_TR_IN9 = 0x40000609u, /* pass[0].tr_sar_gen_in[9] */ 1172 TRIG_OUT_MUX_6_PASS_GEN_TR_IN10 = 0x4000060Au, /* pass[0].tr_sar_gen_in[10] */ 1173 TRIG_OUT_MUX_6_PASS_GEN_TR_IN11 = 0x4000060Bu /* pass[0].tr_sar_gen_in[11] */ 1174 } en_trig_output_pass_t; 1175 1176 /* Trigger Output Group 7 - CAN TT Synchronization triggers */ 1177 typedef enum 1178 { 1179 TRIG_OUT_MUX_7_CAN0_TT_TR_IN0 = 0x40000700u, /* canfd[0].tr_evt_swt_in[0] */ 1180 TRIG_OUT_MUX_7_CAN0_TT_TR_IN1 = 0x40000701u, /* canfd[0].tr_evt_swt_in[1] */ 1181 TRIG_OUT_MUX_7_CAN0_TT_TR_IN2 = 0x40000702u, /* canfd[0].tr_evt_swt_in[2] */ 1182 TRIG_OUT_MUX_7_CAN1_TT_TR_IN0 = 0x40000703u, /* canfd[1].tr_evt_swt_in[0] */ 1183 TRIG_OUT_MUX_7_CAN1_TT_TR_IN1 = 0x40000704u, /* canfd[1].tr_evt_swt_in[1] */ 1184 TRIG_OUT_MUX_7_CAN1_TT_TR_IN2 = 0x40000705u /* canfd[1].tr_evt_swt_in[2] */ 1185 } en_trig_output_cantt_t; 1186 1187 /* Trigger Output Group 8 - 2nd level MUX using input from MUX_9/10 */ 1188 typedef enum 1189 { 1190 TRIG_OUT_MUX_8_HSIOM_IO_OUTPUT0 = 0x40000800u, /* peri.tr_io_output[0] */ 1191 TRIG_OUT_MUX_8_HSIOM_IO_OUTPUT1 = 0x40000801u, /* peri.tr_io_output[1] */ 1192 TRIG_OUT_MUX_8_CTI_TR_IN0 = 0x40000802u, /* cpuss.cti_tr_in[0] */ 1193 TRIG_OUT_MUX_8_CTI_TR_IN1 = 0x40000803u, /* cpuss.cti_tr_in[1] */ 1194 TRIG_OUT_MUX_8_PERI_DEBUG_FREEZE_TR_IN = 0x40000804u, /* peri.tr_dbg_freeze */ 1195 TRIG_OUT_MUX_8_PASS_DEBUG_FREEZE_TR_IN = 0x40000805u, /* pass[0].tr_debug_freeze */ 1196 TRIG_OUT_MUX_8_SRSS_WDT_DEBUG_FREEZE_TR_IN = 0x40000806u, /* srss.tr_debug_freeze_wdt */ 1197 TRIG_OUT_MUX_8_SRSS_MCWDT_DEBUG_FREEZE_TR_IN0 = 0x40000807u, /* srss.tr_debug_freeze_mcwdt[0] */ 1198 TRIG_OUT_MUX_8_SRSS_MCWDT_DEBUG_FREEZE_TR_IN1 = 0x40000808u, /* srss.tr_debug_freeze_mcwdt[1] */ 1199 TRIG_OUT_MUX_8_TCPWM_DEBUG_FREEZE_TR_IN = 0x40000809u /* tcpwm[0].tr_debug_freeze */ 1200 } en_trig_output_debugmain_t; 1201 1202 /* Trigger Output Group 9 - Makes half of all possible triggers visible as I/O signals for debug purposes, or to build external circuitry */ 1203 typedef enum 1204 { 1205 TRIG_OUT_MUX_9_TR_GROUP8_INPUT1 = 0x40000900u, /* tr_group[8].input[1] */ 1206 TRIG_OUT_MUX_9_TR_GROUP8_INPUT2 = 0x40000901u, /* tr_group[8].input[2] */ 1207 TRIG_OUT_MUX_9_TR_GROUP8_INPUT3 = 0x40000902u, /* tr_group[8].input[3] */ 1208 TRIG_OUT_MUX_9_TR_GROUP8_INPUT4 = 0x40000903u, /* tr_group[8].input[4] */ 1209 TRIG_OUT_MUX_9_TR_GROUP8_INPUT5 = 0x40000904u /* tr_group[8].input[5] */ 1210 } en_trig_output_debugreduction1_t; 1211 1212 /* Trigger Output Group 10 - Makes all possible triggers visible as I/O signals for debug purposes, or to build external circuitry */ 1213 typedef enum 1214 { 1215 TRIG_OUT_MUX_10_TR_GROUP8_INPUT6 = 0x40000A00u, /* tr_group[8].input[6] */ 1216 TRIG_OUT_MUX_10_TR_GROUP8_INPUT7 = 0x40000A01u, /* tr_group[8].input[7] */ 1217 TRIG_OUT_MUX_10_TR_GROUP8_INPUT8 = 0x40000A02u, /* tr_group[8].input[8] */ 1218 TRIG_OUT_MUX_10_TR_GROUP8_INPUT9 = 0x40000A03u, /* tr_group[8].input[9] */ 1219 TRIG_OUT_MUX_10_TR_GROUP8_INPUT10 = 0x40000A04u /* tr_group[8].input[10] */ 1220 } en_trig_output_debugreduction2_t; 1221 1222 /* Trigger Output Group 0 - TCPWM to LIN (OneToOne) */ 1223 typedef enum 1224 { 1225 TRIG_OUT_1TO1_0_TCPWM_TO_LIN_TR3 = 0x40001000u, /* From tcpwm[0].tr_out0[0] to lin[0].tr_cmd_tx_header[0] */ 1226 TRIG_OUT_1TO1_0_TCPWM_TO_LIN_TR4 = 0x40001001u, /* From tcpwm[0].tr_out0[1] to lin[0].tr_cmd_tx_header[1] */ 1227 TRIG_OUT_1TO1_0_TCPWM_TO_LIN_TR5 = 0x40001002u, /* From tcpwm[0].tr_out0[2] to lin[0].tr_cmd_tx_header[2] */ 1228 TRIG_OUT_1TO1_0_TCPWM_TO_LIN_TR6 = 0x40001003u, /* From tcpwm[0].tr_out0[3] to lin[0].tr_cmd_tx_header[3] */ 1229 TRIG_OUT_1TO1_0_TCPWM_TO_LIN_TR7 = 0x40001004u, /* From tcpwm[0].tr_out0[4] to lin[0].tr_cmd_tx_header[4] */ 1230 TRIG_OUT_1TO1_0_TCPWM_TO_LIN_TR8 = 0x40001005u, /* From tcpwm[0].tr_out0[5] to lin[0].tr_cmd_tx_header[5] */ 1231 TRIG_OUT_1TO1_0_TCPWM_TO_LIN_TR9 = 0x40001006u, /* From tcpwm[0].tr_out0[6] to lin[0].tr_cmd_tx_header[6] */ 1232 TRIG_OUT_1TO1_0_TCPWM_TO_LIN_TR10 = 0x40001007u /* From tcpwm[0].tr_out0[7] to lin[0].tr_cmd_tx_header[7] */ 1233 } en_trig_output_1to1_tcpwm_to_lin_t; 1234 1235 /* Trigger Output Group 1 - PWM Group 0 to PASS direct connect (OneToOne) */ 1236 typedef enum 1237 { 1238 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR0 = 0x40001100u, /* From tcpwm[0].tr_out1[256] to pass[0].tr_sar_ch_in[0] */ 1239 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR1 = 0x40001101u, /* From tcpwm[0].tr_out1[259] to pass[0].tr_sar_ch_in[1] */ 1240 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR2 = 0x40001102u, /* From tcpwm[0].tr_out1[262] to pass[0].tr_sar_ch_in[2] */ 1241 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR3 = 0x40001103u, /* From tcpwm[0].tr_out1[265] to pass[0].tr_sar_ch_in[3] */ 1242 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR4 = 0x40001104u, /* From tcpwm[0].tr_out1[0] to pass[0].tr_sar_ch_in[4] */ 1243 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR5 = 0x40001105u, /* From tcpwm[0].tr_out1[1] to pass[0].tr_sar_ch_in[5] */ 1244 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR6 = 0x40001106u, /* From tcpwm[0].tr_out1[2] to pass[0].tr_sar_ch_in[6] */ 1245 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR7 = 0x40001107u, /* From tcpwm[0].tr_out1[3] to pass[0].tr_sar_ch_in[7] */ 1246 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR8 = 0x40001108u, /* From tcpwm[0].tr_out1[4] to pass[0].tr_sar_ch_in[8] */ 1247 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR9 = 0x40001109u, /* From tcpwm[0].tr_out1[5] to pass[0].tr_sar_ch_in[9] */ 1248 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR10 = 0x4000110Au, /* From tcpwm[0].tr_out1[6] to pass[0].tr_sar_ch_in[10] */ 1249 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR11 = 0x4000110Bu, /* From tcpwm[0].tr_out1[7] to pass[0].tr_sar_ch_in[11] */ 1250 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR12 = 0x4000110Cu, /* From tcpwm[0].tr_out1[8] to pass[0].tr_sar_ch_in[12] */ 1251 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR13 = 0x4000110Du, /* From tcpwm[0].tr_out1[9] to pass[0].tr_sar_ch_in[13] */ 1252 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR14 = 0x4000110Eu, /* From tcpwm[0].tr_out1[10] to pass[0].tr_sar_ch_in[14] */ 1253 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR15 = 0x4000110Fu, /* From tcpwm[0].tr_out1[11] to pass[0].tr_sar_ch_in[15] */ 1254 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR16 = 0x40001110u, /* From tcpwm[0].tr_out1[12] to pass[0].tr_sar_ch_in[16] */ 1255 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR17 = 0x40001111u, /* From tcpwm[0].tr_out1[13] to pass[0].tr_sar_ch_in[17] */ 1256 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR18 = 0x40001112u, /* From tcpwm[0].tr_out1[14] to pass[0].tr_sar_ch_in[18] */ 1257 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR19 = 0x40001113u, /* From tcpwm[0].tr_out1[15] to pass[0].tr_sar_ch_in[19] */ 1258 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR20 = 0x40001114u, /* From tcpwm[0].tr_out1[16] to pass[0].tr_sar_ch_in[20] */ 1259 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR21 = 0x40001115u, /* From tcpwm[0].tr_out1[17] to pass[0].tr_sar_ch_in[21] */ 1260 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR22 = 0x40001116u, /* From tcpwm[0].tr_out1[18] to pass[0].tr_sar_ch_in[22] */ 1261 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR23 = 0x40001117u, /* From tcpwm[0].tr_out1[19] to pass[0].tr_sar_ch_in[23] */ 1262 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR32 = 0x40001118u, /* From tcpwm[0].tr_out1[257] to pass[0].tr_sar_ch_in[32] */ 1263 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR33 = 0x40001119u, /* From tcpwm[0].tr_out1[260] to pass[0].tr_sar_ch_in[33] */ 1264 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR34 = 0x4000111Au, /* From tcpwm[0].tr_out1[263] to pass[0].tr_sar_ch_in[34] */ 1265 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR35 = 0x4000111Bu, /* From tcpwm[0].tr_out1[266] to pass[0].tr_sar_ch_in[35] */ 1266 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR36 = 0x4000111Cu, /* From tcpwm[0].tr_out1[20] to pass[0].tr_sar_ch_in[36] */ 1267 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR37 = 0x4000111Du, /* From tcpwm[0].tr_out1[21] to pass[0].tr_sar_ch_in[37] */ 1268 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR38 = 0x4000111Eu, /* From tcpwm[0].tr_out1[22] to pass[0].tr_sar_ch_in[38] */ 1269 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR39 = 0x4000111Fu, /* From tcpwm[0].tr_out1[23] to pass[0].tr_sar_ch_in[39] */ 1270 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR40 = 0x40001120u, /* From tcpwm[0].tr_out1[24] to pass[0].tr_sar_ch_in[40] */ 1271 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR41 = 0x40001121u, /* From tcpwm[0].tr_out1[25] to pass[0].tr_sar_ch_in[41] */ 1272 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR42 = 0x40001122u, /* From tcpwm[0].tr_out1[26] to pass[0].tr_sar_ch_in[42] */ 1273 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR43 = 0x40001123u, /* From tcpwm[0].tr_out1[27] to pass[0].tr_sar_ch_in[43] */ 1274 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR44 = 0x40001124u, /* From tcpwm[0].tr_out1[28] to pass[0].tr_sar_ch_in[44] */ 1275 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR45 = 0x40001125u, /* From tcpwm[0].tr_out1[29] to pass[0].tr_sar_ch_in[45] */ 1276 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR46 = 0x40001126u, /* From tcpwm[0].tr_out1[30] to pass[0].tr_sar_ch_in[46] */ 1277 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR47 = 0x40001127u, /* From tcpwm[0].tr_out1[31] to pass[0].tr_sar_ch_in[47] */ 1278 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR48 = 0x40001128u, /* From tcpwm[0].tr_out1[32] to pass[0].tr_sar_ch_in[48] */ 1279 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR49 = 0x40001129u, /* From tcpwm[0].tr_out1[33] to pass[0].tr_sar_ch_in[49] */ 1280 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR50 = 0x4000112Au, /* From tcpwm[0].tr_out1[34] to pass[0].tr_sar_ch_in[50] */ 1281 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR51 = 0x4000112Bu, /* From tcpwm[0].tr_out1[35] to pass[0].tr_sar_ch_in[51] */ 1282 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR52 = 0x4000112Cu, /* From tcpwm[0].tr_out1[36] to pass[0].tr_sar_ch_in[52] */ 1283 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR53 = 0x4000112Du, /* From tcpwm[0].tr_out1[37] to pass[0].tr_sar_ch_in[53] */ 1284 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR54 = 0x4000112Eu, /* From tcpwm[0].tr_out1[38] to pass[0].tr_sar_ch_in[54] */ 1285 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR55 = 0x4000112Fu, /* From tcpwm[0].tr_out1[39] to pass[0].tr_sar_ch_in[55] */ 1286 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR56 = 0x40001130u, /* From tcpwm[0].tr_out1[40] to pass[0].tr_sar_ch_in[56] */ 1287 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR57 = 0x40001131u, /* From tcpwm[0].tr_out1[41] to pass[0].tr_sar_ch_in[57] */ 1288 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR58 = 0x40001132u, /* From tcpwm[0].tr_out1[42] to pass[0].tr_sar_ch_in[58] */ 1289 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR59 = 0x40001133u, /* From tcpwm[0].tr_out1[43] to pass[0].tr_sar_ch_in[59] */ 1290 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR60 = 0x40001134u, /* From tcpwm[0].tr_out1[44] to pass[0].tr_sar_ch_in[60] */ 1291 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR61 = 0x40001135u, /* From tcpwm[0].tr_out1[45] to pass[0].tr_sar_ch_in[61] */ 1292 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR62 = 0x40001136u, /* From tcpwm[0].tr_out1[46] to pass[0].tr_sar_ch_in[62] */ 1293 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR63 = 0x40001137u, /* From tcpwm[0].tr_out1[47] to pass[0].tr_sar_ch_in[63] */ 1294 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR64 = 0x40001138u, /* From tcpwm[0].tr_out1[258] to pass[0].tr_sar_ch_in[64] */ 1295 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR65 = 0x40001139u, /* From tcpwm[0].tr_out1[261] to pass[0].tr_sar_ch_in[65] */ 1296 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR66 = 0x4000113Au, /* From tcpwm[0].tr_out1[264] to pass[0].tr_sar_ch_in[66] */ 1297 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR67 = 0x4000113Bu, /* From tcpwm[0].tr_out1[267] to pass[0].tr_sar_ch_in[67] */ 1298 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR68 = 0x4000113Cu, /* From tcpwm[0].tr_out1[48] to pass[0].tr_sar_ch_in[68] */ 1299 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR69 = 0x4000113Du, /* From tcpwm[0].tr_out1[49] to pass[0].tr_sar_ch_in[69] */ 1300 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR70 = 0x4000113Eu, /* From tcpwm[0].tr_out1[50] to pass[0].tr_sar_ch_in[70] */ 1301 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR71 = 0x4000113Fu /* From tcpwm[0].tr_out1[51] to pass[0].tr_sar_ch_in[71] */ 1302 } en_trig_output_1to1_pwm0_to_pass_t; 1303 1304 /* Trigger Output Group 2 - PASS to DW0 direct connect (OneToOne) */ 1305 typedef enum 1306 { 1307 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA00 = 0x40001200u, /* From pass[0].tr_sar_ch_done[0] to cpuss.dw0_tr_in[25] */ 1308 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA01 = 0x40001201u, /* From pass[0].tr_sar_ch_done[1] to cpuss.dw0_tr_in[26] */ 1309 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA02 = 0x40001202u, /* From pass[0].tr_sar_ch_done[2] to cpuss.dw0_tr_in[27] */ 1310 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA03 = 0x40001203u, /* From pass[0].tr_sar_ch_done[3] to cpuss.dw0_tr_in[28] */ 1311 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA04 = 0x40001204u, /* From pass[0].tr_sar_ch_done[4] to cpuss.dw0_tr_in[29] */ 1312 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA05 = 0x40001205u, /* From pass[0].tr_sar_ch_done[5] to cpuss.dw0_tr_in[30] */ 1313 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA06 = 0x40001206u, /* From pass[0].tr_sar_ch_done[6] to cpuss.dw0_tr_in[31] */ 1314 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA07 = 0x40001207u, /* From pass[0].tr_sar_ch_done[7] to cpuss.dw0_tr_in[32] */ 1315 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA08 = 0x40001208u, /* From pass[0].tr_sar_ch_done[8] to cpuss.dw0_tr_in[33] */ 1316 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA09 = 0x40001209u, /* From pass[0].tr_sar_ch_done[9] to cpuss.dw0_tr_in[34] */ 1317 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA010 = 0x4000120Au, /* From pass[0].tr_sar_ch_done[10] to cpuss.dw0_tr_in[35] */ 1318 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA011 = 0x4000120Bu, /* From pass[0].tr_sar_ch_done[11] to cpuss.dw0_tr_in[36] */ 1319 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA012 = 0x4000120Cu, /* From pass[0].tr_sar_ch_done[12] to cpuss.dw0_tr_in[37] */ 1320 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA013 = 0x4000120Du, /* From pass[0].tr_sar_ch_done[13] to cpuss.dw0_tr_in[38] */ 1321 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA014 = 0x4000120Eu, /* From pass[0].tr_sar_ch_done[14] to cpuss.dw0_tr_in[39] */ 1322 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA015 = 0x4000120Fu, /* From pass[0].tr_sar_ch_done[15] to cpuss.dw0_tr_in[40] */ 1323 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA016 = 0x40001210u, /* From pass[0].tr_sar_ch_done[16] to cpuss.dw0_tr_in[41] */ 1324 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA017 = 0x40001211u, /* From pass[0].tr_sar_ch_done[17] to cpuss.dw0_tr_in[42] */ 1325 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA018 = 0x40001212u, /* From pass[0].tr_sar_ch_done[18] to cpuss.dw0_tr_in[43] */ 1326 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA019 = 0x40001213u, /* From pass[0].tr_sar_ch_done[19] to cpuss.dw0_tr_in[44] */ 1327 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA020 = 0x40001214u, /* From pass[0].tr_sar_ch_done[20] to cpuss.dw0_tr_in[45] */ 1328 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA021 = 0x40001215u, /* From pass[0].tr_sar_ch_done[21] to cpuss.dw0_tr_in[46] */ 1329 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA022 = 0x40001216u, /* From pass[0].tr_sar_ch_done[22] to cpuss.dw0_tr_in[47] */ 1330 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA023 = 0x40001217u, /* From pass[0].tr_sar_ch_done[23] to cpuss.dw0_tr_in[48] */ 1331 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA032 = 0x40001218u, /* From pass[0].tr_sar_ch_done[32] to cpuss.dw0_tr_in[49] */ 1332 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA033 = 0x40001219u, /* From pass[0].tr_sar_ch_done[33] to cpuss.dw0_tr_in[50] */ 1333 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA034 = 0x4000121Au, /* From pass[0].tr_sar_ch_done[34] to cpuss.dw0_tr_in[51] */ 1334 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA035 = 0x4000121Bu, /* From pass[0].tr_sar_ch_done[35] to cpuss.dw0_tr_in[52] */ 1335 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA036 = 0x4000121Cu, /* From pass[0].tr_sar_ch_done[36] to cpuss.dw0_tr_in[53] */ 1336 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA037 = 0x4000121Du, /* From pass[0].tr_sar_ch_done[37] to cpuss.dw0_tr_in[54] */ 1337 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA038 = 0x4000121Eu, /* From pass[0].tr_sar_ch_done[38] to cpuss.dw0_tr_in[55] */ 1338 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA039 = 0x4000121Fu, /* From pass[0].tr_sar_ch_done[39] to cpuss.dw0_tr_in[56] */ 1339 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA040 = 0x40001220u, /* From pass[0].tr_sar_ch_done[40] to cpuss.dw0_tr_in[57] */ 1340 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA041 = 0x40001221u, /* From pass[0].tr_sar_ch_done[41] to cpuss.dw0_tr_in[58] */ 1341 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA042 = 0x40001222u, /* From pass[0].tr_sar_ch_done[42] to cpuss.dw0_tr_in[59] */ 1342 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA043 = 0x40001223u, /* From pass[0].tr_sar_ch_done[43] to cpuss.dw0_tr_in[60] */ 1343 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA044 = 0x40001224u, /* From pass[0].tr_sar_ch_done[44] to cpuss.dw0_tr_in[61] */ 1344 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA045 = 0x40001225u, /* From pass[0].tr_sar_ch_done[45] to cpuss.dw0_tr_in[62] */ 1345 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA046 = 0x40001226u, /* From pass[0].tr_sar_ch_done[46] to cpuss.dw0_tr_in[63] */ 1346 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA047 = 0x40001227u, /* From pass[0].tr_sar_ch_done[47] to cpuss.dw0_tr_in[64] */ 1347 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA048 = 0x40001228u, /* From pass[0].tr_sar_ch_done[48] to cpuss.dw0_tr_in[65] */ 1348 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA049 = 0x40001229u, /* From pass[0].tr_sar_ch_done[49] to cpuss.dw0_tr_in[66] */ 1349 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA050 = 0x4000122Au, /* From pass[0].tr_sar_ch_done[50] to cpuss.dw0_tr_in[67] */ 1350 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA051 = 0x4000122Bu, /* From pass[0].tr_sar_ch_done[51] to cpuss.dw0_tr_in[68] */ 1351 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA052 = 0x4000122Cu, /* From pass[0].tr_sar_ch_done[52] to cpuss.dw0_tr_in[69] */ 1352 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA053 = 0x4000122Du, /* From pass[0].tr_sar_ch_done[53] to cpuss.dw0_tr_in[70] */ 1353 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA054 = 0x4000122Eu, /* From pass[0].tr_sar_ch_done[54] to cpuss.dw0_tr_in[71] */ 1354 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA055 = 0x4000122Fu, /* From pass[0].tr_sar_ch_done[55] to cpuss.dw0_tr_in[72] */ 1355 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA056 = 0x40001230u, /* From pass[0].tr_sar_ch_done[56] to cpuss.dw0_tr_in[73] */ 1356 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA057 = 0x40001231u, /* From pass[0].tr_sar_ch_done[57] to cpuss.dw0_tr_in[74] */ 1357 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA058 = 0x40001232u, /* From pass[0].tr_sar_ch_done[58] to cpuss.dw0_tr_in[75] */ 1358 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA059 = 0x40001233u, /* From pass[0].tr_sar_ch_done[59] to cpuss.dw0_tr_in[76] */ 1359 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA060 = 0x40001234u, /* From pass[0].tr_sar_ch_done[60] to cpuss.dw0_tr_in[77] */ 1360 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA061 = 0x40001235u, /* From pass[0].tr_sar_ch_done[61] to cpuss.dw0_tr_in[78] */ 1361 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA062 = 0x40001236u, /* From pass[0].tr_sar_ch_done[62] to cpuss.dw0_tr_in[79] */ 1362 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA063 = 0x40001237u, /* From pass[0].tr_sar_ch_done[63] to cpuss.dw0_tr_in[80] */ 1363 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA064 = 0x40001238u, /* From pass[0].tr_sar_ch_done[64] to cpuss.dw0_tr_in[81] */ 1364 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA065 = 0x40001239u, /* From pass[0].tr_sar_ch_done[65] to cpuss.dw0_tr_in[82] */ 1365 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA066 = 0x4000123Au, /* From pass[0].tr_sar_ch_done[66] to cpuss.dw0_tr_in[83] */ 1366 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA067 = 0x4000123Bu, /* From pass[0].tr_sar_ch_done[67] to cpuss.dw0_tr_in[84] */ 1367 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA068 = 0x4000123Cu, /* From pass[0].tr_sar_ch_done[68] to cpuss.dw0_tr_in[85] */ 1368 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA069 = 0x4000123Du, /* From pass[0].tr_sar_ch_done[69] to cpuss.dw0_tr_in[86] */ 1369 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA070 = 0x4000123Eu, /* From pass[0].tr_sar_ch_done[70] to cpuss.dw0_tr_in[87] */ 1370 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA071 = 0x4000123Fu /* From pass[0].tr_sar_ch_done[71] to cpuss.dw0_tr_in[88] */ 1371 } en_trig_output_1to1_pass_to_dw0_t; 1372 1373 /* Trigger Output Group 3 - PASS to PWM direct connect (OneToOne) */ 1374 typedef enum 1375 { 1376 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL0 = 0x40001300u, /* From pass[0].tr_sar_ch_rangevio[0] to tcpwm[0].tr_one_cnt_in[770] */ 1377 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL1 = 0x40001301u, /* From pass[0].tr_sar_ch_rangevio[1] to tcpwm[0].tr_one_cnt_in[779] */ 1378 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL2 = 0x40001302u, /* From pass[0].tr_sar_ch_rangevio[2] to tcpwm[0].tr_one_cnt_in[788] */ 1379 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL3 = 0x40001303u, /* From pass[0].tr_sar_ch_rangevio[3] to tcpwm[0].tr_one_cnt_in[797] */ 1380 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL4 = 0x40001304u, /* From pass[0].tr_sar_ch_rangevio[4] to tcpwm[0].tr_one_cnt_in[2] */ 1381 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL5 = 0x40001305u, /* From pass[0].tr_sar_ch_rangevio[5] to tcpwm[0].tr_one_cnt_in[5] */ 1382 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL6 = 0x40001306u, /* From pass[0].tr_sar_ch_rangevio[6] to tcpwm[0].tr_one_cnt_in[8] */ 1383 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL7 = 0x40001307u, /* From pass[0].tr_sar_ch_rangevio[7] to tcpwm[0].tr_one_cnt_in[11] */ 1384 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL8 = 0x40001308u, /* From pass[0].tr_sar_ch_rangevio[8] to tcpwm[0].tr_one_cnt_in[14] */ 1385 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL9 = 0x40001309u, /* From pass[0].tr_sar_ch_rangevio[9] to tcpwm[0].tr_one_cnt_in[17] */ 1386 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL10 = 0x4000130Au, /* From pass[0].tr_sar_ch_rangevio[10] to tcpwm[0].tr_one_cnt_in[20] */ 1387 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL11 = 0x4000130Bu, /* From pass[0].tr_sar_ch_rangevio[11] to tcpwm[0].tr_one_cnt_in[23] */ 1388 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL12 = 0x4000130Cu, /* From pass[0].tr_sar_ch_rangevio[12] to tcpwm[0].tr_one_cnt_in[26] */ 1389 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL13 = 0x4000130Du, /* From pass[0].tr_sar_ch_rangevio[13] to tcpwm[0].tr_one_cnt_in[29] */ 1390 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL14 = 0x4000130Eu, /* From pass[0].tr_sar_ch_rangevio[14] to tcpwm[0].tr_one_cnt_in[32] */ 1391 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL15 = 0x4000130Fu, /* From pass[0].tr_sar_ch_rangevio[15] to tcpwm[0].tr_one_cnt_in[35] */ 1392 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL16 = 0x40001310u, /* From pass[0].tr_sar_ch_rangevio[16] to tcpwm[0].tr_one_cnt_in[38] */ 1393 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL17 = 0x40001311u, /* From pass[0].tr_sar_ch_rangevio[17] to tcpwm[0].tr_one_cnt_in[41] */ 1394 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL18 = 0x40001312u, /* From pass[0].tr_sar_ch_rangevio[18] to tcpwm[0].tr_one_cnt_in[44] */ 1395 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL19 = 0x40001313u, /* From pass[0].tr_sar_ch_rangevio[19] to tcpwm[0].tr_one_cnt_in[47] */ 1396 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL20 = 0x40001314u, /* From pass[0].tr_sar_ch_rangevio[20] to tcpwm[0].tr_one_cnt_in[50] */ 1397 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL21 = 0x40001315u, /* From pass[0].tr_sar_ch_rangevio[21] to tcpwm[0].tr_one_cnt_in[53] */ 1398 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL22 = 0x40001316u, /* From pass[0].tr_sar_ch_rangevio[22] to tcpwm[0].tr_one_cnt_in[56] */ 1399 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL23 = 0x40001317u, /* From pass[0].tr_sar_ch_rangevio[23] to tcpwm[0].tr_one_cnt_in[59] */ 1400 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL24 = 0x40001318u, /* From pass[0].tr_sar_ch_rangevio[32] to tcpwm[0].tr_one_cnt_in[773] */ 1401 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL25 = 0x40001319u, /* From pass[0].tr_sar_ch_rangevio[33] to tcpwm[0].tr_one_cnt_in[782] */ 1402 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL26 = 0x4000131Au, /* From pass[0].tr_sar_ch_rangevio[34] to tcpwm[0].tr_one_cnt_in[791] */ 1403 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL27 = 0x4000131Bu, /* From pass[0].tr_sar_ch_rangevio[35] to tcpwm[0].tr_one_cnt_in[800] */ 1404 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL28 = 0x4000131Cu, /* From pass[0].tr_sar_ch_rangevio[36] to tcpwm[0].tr_one_cnt_in[62] */ 1405 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL29 = 0x4000131Du, /* From pass[0].tr_sar_ch_rangevio[37] to tcpwm[0].tr_one_cnt_in[65] */ 1406 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL30 = 0x4000131Eu, /* From pass[0].tr_sar_ch_rangevio[38] to tcpwm[0].tr_one_cnt_in[68] */ 1407 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL31 = 0x4000131Fu, /* From pass[0].tr_sar_ch_rangevio[39] to tcpwm[0].tr_one_cnt_in[71] */ 1408 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL32 = 0x40001320u, /* From pass[0].tr_sar_ch_rangevio[40] to tcpwm[0].tr_one_cnt_in[74] */ 1409 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL33 = 0x40001321u, /* From pass[0].tr_sar_ch_rangevio[41] to tcpwm[0].tr_one_cnt_in[77] */ 1410 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL34 = 0x40001322u, /* From pass[0].tr_sar_ch_rangevio[42] to tcpwm[0].tr_one_cnt_in[80] */ 1411 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL35 = 0x40001323u, /* From pass[0].tr_sar_ch_rangevio[43] to tcpwm[0].tr_one_cnt_in[83] */ 1412 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL36 = 0x40001324u, /* From pass[0].tr_sar_ch_rangevio[44] to tcpwm[0].tr_one_cnt_in[86] */ 1413 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL37 = 0x40001325u, /* From pass[0].tr_sar_ch_rangevio[45] to tcpwm[0].tr_one_cnt_in[89] */ 1414 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL38 = 0x40001326u, /* From pass[0].tr_sar_ch_rangevio[46] to tcpwm[0].tr_one_cnt_in[92] */ 1415 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL39 = 0x40001327u, /* From pass[0].tr_sar_ch_rangevio[47] to tcpwm[0].tr_one_cnt_in[95] */ 1416 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL40 = 0x40001328u, /* From pass[0].tr_sar_ch_rangevio[48] to tcpwm[0].tr_one_cnt_in[98] */ 1417 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL41 = 0x40001329u, /* From pass[0].tr_sar_ch_rangevio[49] to tcpwm[0].tr_one_cnt_in[101] */ 1418 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL42 = 0x4000132Au, /* From pass[0].tr_sar_ch_rangevio[50] to tcpwm[0].tr_one_cnt_in[104] */ 1419 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL43 = 0x4000132Bu, /* From pass[0].tr_sar_ch_rangevio[51] to tcpwm[0].tr_one_cnt_in[107] */ 1420 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL44 = 0x4000132Cu, /* From pass[0].tr_sar_ch_rangevio[52] to tcpwm[0].tr_one_cnt_in[110] */ 1421 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL45 = 0x4000132Du, /* From pass[0].tr_sar_ch_rangevio[53] to tcpwm[0].tr_one_cnt_in[113] */ 1422 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL46 = 0x4000132Eu, /* From pass[0].tr_sar_ch_rangevio[54] to tcpwm[0].tr_one_cnt_in[116] */ 1423 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL47 = 0x4000132Fu, /* From pass[0].tr_sar_ch_rangevio[55] to tcpwm[0].tr_one_cnt_in[119] */ 1424 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL48 = 0x40001330u, /* From pass[0].tr_sar_ch_rangevio[56] to tcpwm[0].tr_one_cnt_in[122] */ 1425 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL49 = 0x40001331u, /* From pass[0].tr_sar_ch_rangevio[57] to tcpwm[0].tr_one_cnt_in[125] */ 1426 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL50 = 0x40001332u, /* From pass[0].tr_sar_ch_rangevio[58] to tcpwm[0].tr_one_cnt_in[128] */ 1427 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL51 = 0x40001333u, /* From pass[0].tr_sar_ch_rangevio[59] to tcpwm[0].tr_one_cnt_in[131] */ 1428 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL52 = 0x40001334u, /* From pass[0].tr_sar_ch_rangevio[60] to tcpwm[0].tr_one_cnt_in[134] */ 1429 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL53 = 0x40001335u, /* From pass[0].tr_sar_ch_rangevio[61] to tcpwm[0].tr_one_cnt_in[137] */ 1430 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL54 = 0x40001336u, /* From pass[0].tr_sar_ch_rangevio[62] to tcpwm[0].tr_one_cnt_in[140] */ 1431 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL55 = 0x40001337u, /* From pass[0].tr_sar_ch_rangevio[63] to tcpwm[0].tr_one_cnt_in[143] */ 1432 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL56 = 0x40001338u, /* From pass[0].tr_sar_ch_rangevio[64] to tcpwm[0].tr_one_cnt_in[776] */ 1433 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL57 = 0x40001339u, /* From pass[0].tr_sar_ch_rangevio[65] to tcpwm[0].tr_one_cnt_in[785] */ 1434 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL58 = 0x4000133Au, /* From pass[0].tr_sar_ch_rangevio[66] to tcpwm[0].tr_one_cnt_in[794] */ 1435 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL59 = 0x4000133Bu, /* From pass[0].tr_sar_ch_rangevio[67] to tcpwm[0].tr_one_cnt_in[803] */ 1436 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL60 = 0x4000133Cu, /* From pass[0].tr_sar_ch_rangevio[68] to tcpwm[0].tr_one_cnt_in[146] */ 1437 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL61 = 0x4000133Du, /* From pass[0].tr_sar_ch_rangevio[69] to tcpwm[0].tr_one_cnt_in[149] */ 1438 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL62 = 0x4000133Eu, /* From pass[0].tr_sar_ch_rangevio[70] to tcpwm[0].tr_one_cnt_in[152] */ 1439 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL63 = 0x4000133Fu /* From pass[0].tr_sar_ch_rangevio[71] to tcpwm[0].tr_one_cnt_in[155] */ 1440 } en_trig_output_1to1_pass_to_pwm_t; 1441 1442 /* Trigger Output Group 4 - CAN DW0 Triggers (OneToOne) */ 1443 typedef enum 1444 { 1445 TRIG_OUT_1TO1_4_CAN0_DBG_TO_PDMA0_0 = 0x40001400u, /* From canfd[0].tr_dbg_dma_req[0] to cpuss.dw0_tr_in[16] */ 1446 TRIG_OUT_1TO1_4_CAN0_FIFO0_TO_PDMA0_0 = 0x40001401u, /* From canfd[0].tr_fifo0[0] to cpuss.dw0_tr_in[17] */ 1447 TRIG_OUT_1TO1_4_CAN0_FIFO1_TO_PDMA0_0 = 0x40001402u, /* From canfd[0].tr_fifo1[0] to cpuss.dw0_tr_in[18] */ 1448 TRIG_OUT_1TO1_4_CAN0_DBG_TO_PDMA0_1 = 0x40001403u, /* From canfd[0].tr_dbg_dma_req[1] to cpuss.dw0_tr_in[19] */ 1449 TRIG_OUT_1TO1_4_CAN0_FIFO0_TO_PDMA0_1 = 0x40001404u, /* From canfd[0].tr_fifo0[1] to cpuss.dw0_tr_in[20] */ 1450 TRIG_OUT_1TO1_4_CAN0_FIFO1_TO_PDMA0_1 = 0x40001405u, /* From canfd[0].tr_fifo1[1] to cpuss.dw0_tr_in[21] */ 1451 TRIG_OUT_1TO1_4_CAN0_DBG_TO_PDMA0_2 = 0x40001406u, /* From canfd[0].tr_dbg_dma_req[2] to cpuss.dw0_tr_in[22] */ 1452 TRIG_OUT_1TO1_4_CAN0_FIFO0_TO_PDMA0_2 = 0x40001407u, /* From canfd[0].tr_fifo0[2] to cpuss.dw0_tr_in[23] */ 1453 TRIG_OUT_1TO1_4_CAN0_FIFO1_TO_PDMA0_2 = 0x40001408u /* From canfd[0].tr_fifo1[2] to cpuss.dw0_tr_in[24] */ 1454 } en_trig_output_1to1_can0_dw_tr_t; 1455 1456 /* Trigger Output Group 5 - CAN DW1 triggers (on DW1 to share BW) (OneToOne) */ 1457 typedef enum 1458 { 1459 TRIG_OUT_1TO1_5_CAN1_DBG_TO_PDMA1_0 = 0x40001500u, /* From canfd[1].tr_dbg_dma_req[0] to cpuss.dw1_tr_in[24] */ 1460 TRIG_OUT_1TO1_5_CAN1_FIFO0_TO_PDMA1_0 = 0x40001501u, /* From canfd[1].tr_fifo0[0] to cpuss.dw1_tr_in[25] */ 1461 TRIG_OUT_1TO1_5_CAN1_FIFO1_TO_PDMA1_0 = 0x40001502u, /* From canfd[1].tr_fifo1[0] to cpuss.dw1_tr_in[26] */ 1462 TRIG_OUT_1TO1_5_CAN1_DBG_TO_PDMA1_1 = 0x40001503u, /* From canfd[1].tr_dbg_dma_req[1] to cpuss.dw1_tr_in[27] */ 1463 TRIG_OUT_1TO1_5_CAN1_FIFO0_TO_PDMA1_1 = 0x40001504u, /* From canfd[1].tr_fifo0[1] to cpuss.dw1_tr_in[28] */ 1464 TRIG_OUT_1TO1_5_CAN1_FIFO1_TO_PDMA1_1 = 0x40001505u, /* From canfd[1].tr_fifo1[1] to cpuss.dw1_tr_in[29] */ 1465 TRIG_OUT_1TO1_5_CAN1_DBG_TO_PDMA1_2 = 0x40001506u, /* From canfd[1].tr_dbg_dma_req[2] to cpuss.dw1_tr_in[30] */ 1466 TRIG_OUT_1TO1_5_CAN1_FIFO0_TO_PDMA1_2 = 0x40001507u, /* From canfd[1].tr_fifo0[2] to cpuss.dw1_tr_in[31] */ 1467 TRIG_OUT_1TO1_5_CAN1_FIFO1_TO_PDMA1_2 = 0x40001508u /* From canfd[1].tr_fifo1[2] to cpuss.dw1_tr_in[32] */ 1468 } en_trig_output_1to1_can1_dw_tr_t; 1469 1470 /* Trigger Output Group 6 - Acknowledge dma request triggers from DW0 to CAN (OneToOne) */ 1471 typedef enum 1472 { 1473 TRIG_OUT_1TO1_6_PDMA0_ACK_TO_CAN0_0 = 0x40001600u, /* From cpuss.dw0_tr_out[16] to canfd[0].tr_dbg_dma_ack[0] */ 1474 TRIG_OUT_1TO1_6_PDMA0_ACK_TO_CAN0_1 = 0x40001601u, /* From cpuss.dw0_tr_out[19] to canfd[0].tr_dbg_dma_ack[1] */ 1475 TRIG_OUT_1TO1_6_PDMA0_ACK_TO_CAN0_2 = 0x40001602u /* From cpuss.dw0_tr_out[22] to canfd[0].tr_dbg_dma_ack[2] */ 1476 } en_trig_output_1to1_can0_dw_ack_t; 1477 1478 /* Trigger Output Group 7 - Acknowledge dma request triggers from DW1 to CAN (OneToOne) */ 1479 typedef enum 1480 { 1481 TRIG_OUT_1TO1_7_PDMA1_ACK_TO_CAN1_0 = 0x40001700u, /* From cpuss.dw1_tr_out[24] to canfd[1].tr_dbg_dma_ack[0] */ 1482 TRIG_OUT_1TO1_7_PDMA1_ACK_TO_CAN1_1 = 0x40001701u, /* From cpuss.dw1_tr_out[27] to canfd[1].tr_dbg_dma_ack[1] */ 1483 TRIG_OUT_1TO1_7_PDMA1_ACK_TO_CAN1_2 = 0x40001702u /* From cpuss.dw1_tr_out[30] to canfd[1].tr_dbg_dma_ack[2] */ 1484 } en_trig_output_1to1_can1_dw_ack_t; 1485 1486 /* Trigger Output Group 8 - SCB DW Triggers (OneToOne) */ 1487 typedef enum 1488 { 1489 TRIG_OUT_1TO1_8_SCB_TX_TO_PDMA10 = 0x40001800u, /* From scb[0].tr_tx_req to cpuss.dw1_tr_in[8] */ 1490 TRIG_OUT_1TO1_8_SCB_RX_TO_PDMA10 = 0x40001801u, /* From scb[0].tr_rx_req to cpuss.dw1_tr_in[9] */ 1491 TRIG_OUT_1TO1_8_SCB_TX_TO_PDMA11 = 0x40001802u, /* From scb[1].tr_tx_req to cpuss.dw1_tr_in[10] */ 1492 TRIG_OUT_1TO1_8_SCB_RX_TO_PDMA11 = 0x40001803u, /* From scb[1].tr_rx_req to cpuss.dw1_tr_in[11] */ 1493 TRIG_OUT_1TO1_8_SCB_TX_TO_PDMA12 = 0x40001804u, /* From scb[2].tr_tx_req to cpuss.dw1_tr_in[12] */ 1494 TRIG_OUT_1TO1_8_SCB_RX_TO_PDMA12 = 0x40001805u, /* From scb[2].tr_rx_req to cpuss.dw1_tr_in[13] */ 1495 TRIG_OUT_1TO1_8_SCB_TX_TO_PDMA13 = 0x40001806u, /* From scb[3].tr_tx_req to cpuss.dw1_tr_in[14] */ 1496 TRIG_OUT_1TO1_8_SCB_RX_TO_PDMA13 = 0x40001807u, /* From scb[3].tr_rx_req to cpuss.dw1_tr_in[15] */ 1497 TRIG_OUT_1TO1_8_SCB_TX_TO_PDMA14 = 0x40001808u, /* From scb[4].tr_tx_req to cpuss.dw1_tr_in[16] */ 1498 TRIG_OUT_1TO1_8_SCB_RX_TO_PDMA14 = 0x40001809u, /* From scb[4].tr_rx_req to cpuss.dw1_tr_in[17] */ 1499 TRIG_OUT_1TO1_8_SCB_TX_TO_PDMA15 = 0x4000180Au, /* From scb[5].tr_tx_req to cpuss.dw1_tr_in[18] */ 1500 TRIG_OUT_1TO1_8_SCB_RX_TO_PDMA15 = 0x4000180Bu, /* From scb[5].tr_rx_req to cpuss.dw1_tr_in[19] */ 1501 TRIG_OUT_1TO1_8_SCB_TX_TO_PDMA16 = 0x4000180Cu, /* From scb[6].tr_tx_req to cpuss.dw1_tr_in[20] */ 1502 TRIG_OUT_1TO1_8_SCB_RX_TO_PDMA16 = 0x4000180Du, /* From scb[6].tr_rx_req to cpuss.dw1_tr_in[21] */ 1503 TRIG_OUT_1TO1_8_SCB_TX_TO_PDMA17 = 0x4000180Eu, /* From scb[7].tr_tx_req to cpuss.dw1_tr_in[22] */ 1504 TRIG_OUT_1TO1_8_SCB_RX_TO_PDMA17 = 0x4000180Fu /* From scb[7].tr_rx_req to cpuss.dw1_tr_in[23] */ 1505 } en_trig_output_1to1_scb_dw_tr_t; 1506 1507 /* Level or edge detection setting for a trigger mux */ 1508 typedef enum 1509 { 1510 /* The trigger is a simple level output */ 1511 TRIGGER_TYPE_LEVEL = 0u, 1512 /* The trigger is synchronized to the consumer blocks clock 1513 and a two cycle pulse is generated on this clock */ 1514 TRIGGER_TYPE_EDGE = 1u 1515 } en_trig_type_t; 1516 1517 /* Trigger Type Defines */ 1518 /* CANFD Trigger Types */ 1519 #define TRIGGER_TYPE_CANFD_TR_DBG_DMA_ACK TRIGGER_TYPE_EDGE 1520 #define TRIGGER_TYPE_CANFD_TR_DBG_DMA_REQ TRIGGER_TYPE_LEVEL 1521 #define TRIGGER_TYPE_CANFD_TR_EVT_SWT_IN TRIGGER_TYPE_EDGE 1522 #define TRIGGER_TYPE_CANFD_TR_FIFO0 TRIGGER_TYPE_LEVEL 1523 #define TRIGGER_TYPE_CANFD_TR_FIFO1 TRIGGER_TYPE_LEVEL 1524 #define TRIGGER_TYPE_CANFD_TR_TMP_RTP_OUT TRIGGER_TYPE_EDGE 1525 /* CPUSS Trigger Types */ 1526 #define TRIGGER_TYPE_CPUSS_CTI_TR_IN TRIGGER_TYPE_EDGE 1527 #define TRIGGER_TYPE_CPUSS_CTI_TR_OUT TRIGGER_TYPE_EDGE 1528 #define TRIGGER_TYPE_CPUSS_DMAC_TR_IN__LEVEL TRIGGER_TYPE_LEVEL 1529 #define TRIGGER_TYPE_CPUSS_DMAC_TR_IN__EDGE TRIGGER_TYPE_EDGE 1530 #define TRIGGER_TYPE_CPUSS_DMAC_TR_OUT TRIGGER_TYPE_EDGE 1531 #define TRIGGER_TYPE_CPUSS_DW0_TR_IN__LEVEL TRIGGER_TYPE_LEVEL 1532 #define TRIGGER_TYPE_CPUSS_DW0_TR_IN__EDGE TRIGGER_TYPE_EDGE 1533 #define TRIGGER_TYPE_CPUSS_DW0_TR_OUT TRIGGER_TYPE_EDGE 1534 #define TRIGGER_TYPE_CPUSS_DW1_TR_IN__LEVEL TRIGGER_TYPE_LEVEL 1535 #define TRIGGER_TYPE_CPUSS_DW1_TR_IN__EDGE TRIGGER_TYPE_EDGE 1536 #define TRIGGER_TYPE_CPUSS_DW1_TR_OUT TRIGGER_TYPE_EDGE 1537 #define TRIGGER_TYPE_CPUSS_TR_FAULT TRIGGER_TYPE_EDGE 1538 /* LIN Trigger Types */ 1539 #define TRIGGER_TYPE_LIN_TR_CMD_TX_HEADER TRIGGER_TYPE_EDGE 1540 /* PASS Trigger Types */ 1541 #define TRIGGER_TYPE_PASS_TR_DEBUG_FREEZE TRIGGER_TYPE_LEVEL 1542 #define TRIGGER_TYPE_PASS_TR_SAR_CH_DONE__LEVEL TRIGGER_TYPE_LEVEL 1543 #define TRIGGER_TYPE_PASS_TR_SAR_CH_DONE__EDGE TRIGGER_TYPE_EDGE 1544 #define TRIGGER_TYPE_PASS_TR_SAR_CH_IN__LEVEL TRIGGER_TYPE_LEVEL 1545 #define TRIGGER_TYPE_PASS_TR_SAR_CH_IN__EDGE TRIGGER_TYPE_EDGE 1546 #define TRIGGER_TYPE_PASS_TR_SAR_CH_RANGEVIO TRIGGER_TYPE_EDGE 1547 #define TRIGGER_TYPE_PASS_TR_SAR_GEN_IN__LEVEL TRIGGER_TYPE_LEVEL 1548 #define TRIGGER_TYPE_PASS_TR_SAR_GEN_IN__EDGE TRIGGER_TYPE_EDGE 1549 #define TRIGGER_TYPE_PASS_TR_SAR_GEN_OUT__LEVEL TRIGGER_TYPE_LEVEL 1550 #define TRIGGER_TYPE_PASS_TR_SAR_GEN_OUT__EDGE TRIGGER_TYPE_EDGE 1551 /* PERI Trigger Types */ 1552 #define TRIGGER_TYPE_PERI_TR_DBG_FREEZE TRIGGER_TYPE_LEVEL 1553 #define TRIGGER_TYPE_PERI_TR_IO_INPUT__LEVEL TRIGGER_TYPE_LEVEL 1554 #define TRIGGER_TYPE_PERI_TR_IO_INPUT__EDGE TRIGGER_TYPE_EDGE 1555 #define TRIGGER_TYPE_PERI_TR_IO_OUTPUT__LEVEL TRIGGER_TYPE_LEVEL 1556 #define TRIGGER_TYPE_PERI_TR_IO_OUTPUT__EDGE TRIGGER_TYPE_EDGE 1557 /* SCB Trigger Types */ 1558 #define TRIGGER_TYPE_SCB_TR_I2C_SCL_FILTERED TRIGGER_TYPE_LEVEL 1559 #define TRIGGER_TYPE_SCB_TR_RX_REQ TRIGGER_TYPE_LEVEL 1560 #define TRIGGER_TYPE_SCB_TR_TX_REQ TRIGGER_TYPE_LEVEL 1561 /* SRSS Trigger Types */ 1562 #define TRIGGER_TYPE_SRSS_TR_DEBUG_FREEZE_MCWDT TRIGGER_TYPE_LEVEL 1563 #define TRIGGER_TYPE_SRSS_TR_DEBUG_FREEZE_WDT TRIGGER_TYPE_LEVEL 1564 /* TCPWM Trigger Types */ 1565 #define TRIGGER_TYPE_TCPWM_TR_DEBUG_FREEZE TRIGGER_TYPE_LEVEL 1566 /* TR_GROUP Trigger Types */ 1567 #define TRIGGER_TYPE_TR_GROUP_OUTPUT__LEVEL TRIGGER_TYPE_LEVEL 1568 #define TRIGGER_TYPE_TR_GROUP_OUTPUT__EDGE TRIGGER_TYPE_EDGE 1569 #define TRIGGER_TYPE_TR_GROUP_INPUT__LEVEL TRIGGER_TYPE_LEVEL 1570 #define TRIGGER_TYPE_TR_GROUP_INPUT__EDGE TRIGGER_TYPE_EDGE 1571 1572 /* Fault connections */ 1573 typedef enum 1574 { 1575 CPUSS_MPU_VIO_0 = 0x0000u, 1576 CPUSS_MPU_VIO_1 = 0x0001u, 1577 CPUSS_MPU_VIO_2 = 0x0002u, 1578 CPUSS_MPU_VIO_3 = 0x0003u, 1579 CPUSS_MPU_VIO_4 = 0x0004u, 1580 CPUSS_MPU_VIO_15 = 0x000Fu, 1581 CPUSS_MPU_VIO_16 = 0x0010u, 1582 CPUSS_MPU_VIO_17 = 0x0011u, 1583 CPUSS_MPU_VIO_18 = 0x0012u, 1584 PERI_PERI_C_ECC = 0x001Au, 1585 PERI_PERI_NC_ECC = 0x001Bu, 1586 PERI_MS_VIO_0 = 0x001Cu, 1587 PERI_MS_VIO_1 = 0x001Du, 1588 PERI_MS_VIO_2 = 0x001Eu, 1589 PERI_MS_VIO_3 = 0x001Fu, 1590 PERI_GROUP_VIO_0 = 0x0020u, 1591 PERI_GROUP_VIO_1 = 0x0021u, 1592 PERI_GROUP_VIO_2 = 0x0022u, 1593 PERI_GROUP_VIO_3 = 0x0023u, 1594 PERI_GROUP_VIO_5 = 0x0025u, 1595 PERI_GROUP_VIO_6 = 0x0026u, 1596 PERI_GROUP_VIO_9 = 0x0029u, 1597 CPUSS_FLASHC_MAIN_BUS_ERR = 0x0030u, 1598 CPUSS_FLASHC_MAIN_C_ECC = 0x0031u, 1599 CPUSS_FLASHC_MAIN_NC_ECC = 0x0032u, 1600 CPUSS_FLASHC_WORK_BUS_ERR = 0x0033u, 1601 CPUSS_FLASHC_WORK_C_ECC = 0x0034u, 1602 CPUSS_FLASHC_WORK_NC_ECC = 0x0035u, 1603 CPUSS_FLASHC_CM0_CA_C_ECC = 0x0036u, 1604 CPUSS_FLASHC_CM0_CA_NC_ECC = 0x0037u, 1605 CPUSS_FLASHC_CM4_CA_C_ECC = 0x0038u, 1606 CPUSS_FLASHC_CM4_CA_NC_ECC = 0x0039u, 1607 CPUSS_RAMC0_C_ECC = 0x003Au, 1608 CPUSS_RAMC0_NC_ECC = 0x003Bu, 1609 CPUSS_RAMC1_C_ECC = 0x003Cu, 1610 CPUSS_RAMC1_NC_ECC = 0x003Du, 1611 CPUSS_CRYPTO_C_ECC = 0x0040u, 1612 CPUSS_CRYPTO_NC_ECC = 0x0041u, 1613 CPUSS_DW0_C_ECC = 0x0046u, 1614 CPUSS_DW0_NC_ECC = 0x0047u, 1615 CPUSS_DW1_C_ECC = 0x0048u, 1616 CPUSS_DW1_NC_ECC = 0x0049u, 1617 CPUSS_FM_SRAM_C_ECC = 0x004Au, 1618 CPUSS_FM_SRAM_NC_ECC = 0x004Bu, 1619 CANFD_0_CAN_C_ECC = 0x0050u, 1620 CANFD_0_CAN_NC_ECC = 0x0051u, 1621 CANFD_1_CAN_C_ECC = 0x0052u, 1622 CANFD_1_CAN_NC_ECC = 0x0053u, 1623 SRSS_FAULT_CSV = 0x005Au, 1624 SRSS_FAULT_SSV = 0x005Bu, 1625 SRSS_FAULT_MCWDT0 = 0x005Cu, 1626 SRSS_FAULT_MCWDT1 = 0x005Du 1627 } en_sysfault_source_t; 1628 1629 /* Bus masters */ 1630 typedef enum 1631 { 1632 CPUSS_MS_ID_CM0 = 0, 1633 CPUSS_MS_ID_CRYPTO = 1, 1634 CPUSS_MS_ID_DW0 = 2, 1635 CPUSS_MS_ID_DW1 = 3, 1636 CPUSS_MS_ID_DMAC = 4, 1637 CPUSS_MS_ID_SLOW0 = 5, 1638 CPUSS_MS_ID_SLOW1 = 6, 1639 CPUSS_MS_ID_CM4 = 14, 1640 CPUSS_MS_ID_TC = 15 1641 } en_prot_master_t; 1642 1643 /* Pointer to device configuration structure */ 1644 #define CY_DEVICE_CFG (&cy_deviceIpBlockCfgTVIIBE1M) 1645 1646 /* Include IP definitions */ 1647 #include "ip/cyip_sflash_v2_tviibe1m.h" 1648 #include "ip/cyip_peri_v2.h" 1649 #include "ip/cyip_peri_ms_v2.h" 1650 #include "ip/cyip_crypto_v2.h" 1651 #include "ip/cyip_cpuss_v2.h" 1652 #include "ip/cyip_fault_v2.h" 1653 #include "ip/cyip_ipc_v2.h" 1654 #include "ip/cyip_prot_v2.h" 1655 #include "ip/cyip_flashc_v2_ect.h" 1656 #include "ip/cyip_srss_v2.h" 1657 #include "ip/cyip_backup_v2.h" 1658 #include "ip/cyip_dw_v2.h" 1659 #include "ip/cyip_dmac_v2.h" 1660 #include "ip/cyip_efuse_v2.h" 1661 #include "ip/cyip_efuse_data_v2_tviibe1m.h" 1662 #include "ip/cyip_hsiom_v2.h" 1663 #include "ip/cyip_gpio_v2.h" 1664 #include "ip/cyip_smartio_v2.h" 1665 #include "ip/cyip_tcpwm_v2.h" 1666 #include "ip/cyip_evtgen.h" 1667 #include "ip/cyip_lin.h" 1668 #include "ip/cyip_canfd.h" 1669 #include "ip/cyip_scb_v2.h" 1670 #include "ip/cyip_epass.h" 1671 1672 /* IP type definitions */ 1673 typedef SFLASH_V2_Type SFLASH_Type; 1674 typedef PERI_GR_V2_Type PERI_GR_Type; 1675 typedef PERI_TR_GR_V2_Type PERI_TR_GR_Type; 1676 typedef PERI_TR_1TO1_GR_V2_Type PERI_TR_1TO1_GR_Type; 1677 typedef PERI_V2_Type PERI_Type; 1678 typedef PERI_MS_PPU_PR_V2_Type PERI_MS_PPU_PR_Type; 1679 typedef PERI_MS_PPU_FX_V2_Type PERI_MS_PPU_FX_Type; 1680 typedef PERI_MS_V2_Type PERI_MS_Type; 1681 typedef CRYPTO_V2_Type CRYPTO_Type; 1682 typedef CPUSS_V2_Type CPUSS_Type; 1683 typedef FAULT_STRUCT_V2_Type FAULT_STRUCT_Type; 1684 typedef FAULT_V2_Type FAULT_Type; 1685 typedef IPC_STRUCT_V2_Type IPC_STRUCT_Type; 1686 typedef IPC_INTR_STRUCT_V2_Type IPC_INTR_STRUCT_Type; 1687 typedef IPC_V2_Type IPC_Type; 1688 typedef PROT_SMPU_SMPU_STRUCT_V2_Type PROT_SMPU_SMPU_STRUCT_Type; 1689 typedef PROT_SMPU_V2_Type PROT_SMPU_Type; 1690 typedef PROT_MPU_MPU_STRUCT_V2_Type PROT_MPU_MPU_STRUCT_Type; 1691 typedef PROT_MPU_V2_Type PROT_MPU_Type; 1692 typedef PROT_V2_Type PROT_Type; 1693 typedef FLASHC_FM_CTL_ECT_V2_Type FLASHC_FM_CTL_ECT_Type; 1694 typedef FLASHC_V2_Type FLASHC_Type; 1695 typedef CSV_HF_CSV_V2_Type CSV_HF_CSV_Type; 1696 typedef CSV_HF_V2_Type CSV_HF_Type; 1697 typedef CSV_REF_CSV_V2_Type CSV_REF_CSV_Type; 1698 typedef CSV_REF_V2_Type CSV_REF_Type; 1699 typedef CSV_LF_CSV_V2_Type CSV_LF_CSV_Type; 1700 typedef CSV_LF_V2_Type CSV_LF_Type; 1701 typedef CSV_ILO_CSV_V2_Type CSV_ILO_CSV_Type; 1702 typedef CSV_ILO_V2_Type CSV_ILO_Type; 1703 typedef MCWDT_CTR_V2_Type MCWDT_CTR_Type; 1704 typedef MCWDT_V2_Type MCWDT_Type; 1705 typedef WDT_V2_Type WDT_Type; 1706 typedef SRSS_V2_Type SRSS_Type; 1707 typedef BACKUP_V2_Type BACKUP_Type; 1708 typedef DW_CH_STRUCT_V2_Type DW_CH_STRUCT_Type; 1709 typedef DW_V2_Type DW_Type; 1710 typedef DMAC_CH_V2_Type DMAC_CH_Type; 1711 typedef DMAC_V2_Type DMAC_Type; 1712 typedef EFUSE_V2_Type EFUSE_Type; 1713 typedef HSIOM_PRT_V2_Type HSIOM_PRT_Type; 1714 typedef HSIOM_V2_Type HSIOM_Type; 1715 typedef GPIO_PRT_V2_Type GPIO_PRT_Type; 1716 typedef GPIO_V2_Type GPIO_Type; 1717 typedef SMARTIO_PRT_V2_Type SMARTIO_PRT_Type; 1718 typedef SMARTIO_V2_Type SMARTIO_Type; 1719 typedef TCPWM_GRP_CNT_V2_Type TCPWM_GRP_CNT_Type; 1720 typedef TCPWM_GRP_V2_Type TCPWM_GRP_Type; 1721 typedef TCPWM_V2_Type TCPWM_Type; 1722 typedef EVTGEN_COMP_STRUCT_V1_Type EVTGEN_COMP_STRUCT_Type; 1723 typedef EVTGEN_V1_Type EVTGEN_Type; 1724 typedef LIN_CH_V1_Type LIN_CH_Type; 1725 typedef LIN_V1_Type LIN_Type; 1726 typedef CANFD_CH_M_TTCAN_V1_Type CANFD_CH_M_TTCAN_Type; 1727 typedef CANFD_CH_V1_Type CANFD_CH_Type; 1728 typedef CANFD_V1_Type CANFD_Type; 1729 typedef CySCB_V2_Type CySCB_Type; 1730 typedef PASS_SAR_CH_V1_Type PASS_SAR_CH_Type; 1731 typedef PASS_SAR_V1_Type PASS_SAR_Type; 1732 typedef PASS_EPASS_MMIO_V1_Type PASS_EPASS_MMIO_Type; 1733 typedef PASS_V1_Type PASS_Type; 1734 1735 /* Parameter Defines */ 1736 /* Number of TTCAN instances */ 1737 #define CANFD0_CAN_NR 3u 1738 /* ECC logic present or not */ 1739 #define CANFD0_ECC_PRESENT 1u 1740 /* address included in ECC logic or not */ 1741 #define CANFD0_ECC_ADDR_PRESENT 1u 1742 /* Time Stamp counter present or not (required for instance 0, otherwise not 1743 allowed) */ 1744 #define CANFD0_TS_PRESENT 1u 1745 /* Message RAM size in KB */ 1746 #define CANFD0_MRAM_SIZE 24u 1747 /* Message RAM address width */ 1748 #define CANFD0_MRAM_ADDR_WIDTH 13u 1749 /* Number of TTCAN instances */ 1750 #define CANFD1_CAN_NR 3u 1751 /* ECC logic present or not */ 1752 #define CANFD1_ECC_PRESENT 1u 1753 /* address included in ECC logic or not */ 1754 #define CANFD1_ECC_ADDR_PRESENT 1u 1755 /* Time Stamp counter present or not (required for instance 0, otherwise not 1756 allowed) */ 1757 #define CANFD1_TS_PRESENT 0u 1758 /* Message RAM size in KB */ 1759 #define CANFD1_MRAM_SIZE 24u 1760 /* Message RAM address width */ 1761 #define CANFD1_MRAM_ADDR_WIDTH 13u 1762 /* UDB present or not ('0': no, '1': yes) */ 1763 #define CPUSS_UDB_PRESENT 0u 1764 /* MBIST MMIO for Synopsys MBIST ('0': no, '1': yes). Set this to '1' only for the 1765 chips which doesn't use mxdft. */ 1766 #define CPUSS_MBIST_MMIO_PRESENT 0u 1767 /* System RAM 0 size in KB */ 1768 #define CPUSS_SRAM0_SIZE 64u 1769 /* Number of macros used to implement system RAM 0. Example: 8 if 256 KB system 1770 SRAM 0 is implemented with 8 32KB macros. */ 1771 #define CPUSS_RAMC0_MACRO_NR 2u 1772 /* System RAM 1 present or not ('0': no, '1': yes) */ 1773 #define CPUSS_RAMC1_PRESENT 1u 1774 /* System RAM 1 size in KB */ 1775 #define CPUSS_SRAM1_SIZE 64u 1776 /* Number of macros used to implement system RAM 1. */ 1777 #define CPUSS_RAMC1_MACRO_NR 2u 1778 /* System RAM 2 present or not ('0': no, '1': yes) */ 1779 #define CPUSS_RAMC2_PRESENT 0u 1780 /* System RAM 2 size in KB */ 1781 #define CPUSS_SRAM2_SIZE 1u 1782 /* Number of macros used to implement System RAM 2. */ 1783 #define CPUSS_RAMC2_MACRO_NR 0u 1784 /* System SRAM(s) ECC present or not ('0': no, '1': yes) */ 1785 #define CPUSS_RAMC_ECC_PRESENT 1u 1786 /* System SRAM(s) address ECC present or not ('0': no, '1': yes) */ 1787 #define CPUSS_RAMC_ECC_ADDR_PRESENT 1u 1788 /* ECC present in either system RAM or interrupt handler (RAMC_ECC_PRESENT) */ 1789 #define CPUSS_ECC_PRESENT 1u 1790 /* DataWire SRAMs ECC present or not ('0': no, '1': yes) */ 1791 #define CPUSS_DW_ECC_PRESENT 1u 1792 /* DataWire SRAMs address ECC present or not ('0': no, '1': yes) */ 1793 #define CPUSS_DW_ECC_ADDR_PRESENT 1u 1794 /* System ROM size in KB */ 1795 #define CPUSS_ROM_SIZE 32u 1796 /* Number of macros used to implement system ROM. Example: 4 if 512 KB system ROM 1797 is implemented with 4 128KB macros. */ 1798 #define CPUSS_ROMC_MACRO_NR 1u 1799 /* Flash memory present or not ('0': no, '1': yes) */ 1800 #define CPUSS_FLASHC_PRESENT 1u 1801 /* Flash memory type ('0' : SONOS, '1': ECT) */ 1802 #define CPUSS_FLASHC_ECT 1u 1803 /* Flash main region size in KB */ 1804 #define CPUSS_FLASH_SIZE 1024u 1805 /* Flash work region size in KB (EEPROM emulation, data) */ 1806 #define CPUSS_WFLASH_SIZE 96u 1807 /* Flash supervisory region size in KB */ 1808 #define CPUSS_SFLASH_SIZE 32u 1809 /* Flash data output word size (in Bytes) */ 1810 #define CPUSS_FLASHC_MAIN_DATA_WIDTH 32u 1811 /* SONOS Flash RWW present or not ('0': no, '1': yes) When RWW is '0', No special 1812 sectors present in Flash. Part of main sector 0 is allowcated for Supervisory 1813 Flash, and no Work Flash present. */ 1814 #define CPUSS_FLASHC_SONOS_RWW 0u 1815 /* SONOS Flash, number of main sectors. */ 1816 #define CPUSS_FLASHC_SONOS_MAIN_SECTORS 0u 1817 /* SONOS Flash, number of rows per main sector. */ 1818 #define CPUSS_FLASHC_SONOS_MAIN_ROWS 0u 1819 /* SONOS Flash, number of words per row of main sector. */ 1820 #define CPUSS_FLASHC_SONOS_MAIN_WORDS 0u 1821 /* SONOS Flash, number of special sectors. */ 1822 #define CPUSS_FLASHC_SONOS_SPL_SECTORS 0u 1823 /* SONOS Flash, number of rows per special sector. */ 1824 #define CPUSS_FLASHC_SONOS_SPL_ROWS 0u 1825 /* Flash memory ECC present or not ('0': no, '1': yes) */ 1826 #define CPUSS_FLASHC_FLASH_ECC_PRESENT 1u 1827 /* Flash cache SRAM(s) ECC present or not ('0': no, '1': yes) */ 1828 #define CPUSS_FLASHC_RAM_ECC_PRESENT 1u 1829 /* Number of external slaves directly connected to slow AHB-Lite infrastructure. 1830 Maximum nubmer of slave supported is 4. Width of this parameter is 4-bits. 1831 1-bit mask for each slave indicating present or not. Example: 4'b0011 - slave 1832 0 and slave 1 are present. Note: The SLOW_SLx_ADDR and SLOW_SLx_MASK 1833 parameters (for the slaves present) should be derived from the Memory Map. */ 1834 #define CPUSS_SLOW_SL_PRESENT 0u 1835 /* Number of external slaves directly connected to fast AHB-Lite infrastructure. 1836 Maximum nubmer of slave supported is 4. Width of this parameter is 4-bits. 1837 1-bit mask for each slave indicating present or not. Example: 4'b0011 - slave 1838 0 and slave 1 are present. Note: The FAST_SLx_ADDR and FAST_SLx_MASK 1839 parameters (for the slaves present) should be derived from the Memory Map. */ 1840 #define CPUSS_FAST_SL_PRESENT 0u 1841 /* Number of external masters driving the slow AHB-Lite infrastructure. Maximum 1842 number of masters supported is 2. Width of this parameter is 2-bits. 1-bit 1843 mask for each master indicating present or not. Example: 2'b01 - master 0 is 1844 present. */ 1845 #define CPUSS_SLOW_MS_PRESENT 0u 1846 /* System interrupt functionality present or not ('0': no; '1': yes). Not used for 1847 CM0+ PCU, which always uses system interrupt functionality. */ 1848 #define CPUSS_SYSTEM_IRQ_PRESENT 1u 1849 /* Number of system interrupt inputs to CPUSS */ 1850 #define CPUSS_SYSTEM_INT_NR 353u 1851 /* Number of DeepSleep system interrupt inputs to CPUSS */ 1852 #define CPUSS_SYSTEM_DPSLP_INT_NR 45u 1853 /* Width of the CM4 interrupt priority bits. Legal range [3,8] Example: 3 = 8 1854 levels of priority 8 = 256 levels of priority */ 1855 #define CPUSS_CM4_LVL_WIDTH 3u 1856 /* CM4 Floating point unit present or not ('0': no, '1': yes) */ 1857 #define CPUSS_CM4_FPU_PRESENT 1u 1858 /* Debug level. Legal range [0,3] */ 1859 #define CPUSS_DEBUG_LVL 3u 1860 /* Trace level. Legal range [0,2] Note: CM4 HTM is not supported. Hence vaule 3 1861 for trace level is not supported in CPUSS. */ 1862 #define CPUSS_TRACE_LVL 2u 1863 /* Embedded Trace Buffer present or not ('0': no, '1': yes) */ 1864 #define CPUSS_ETB_PRESENT 1u 1865 /* CM0+ MTB SRAM buffer size in kilobytes. Legal vaules 4, 8 or 16 */ 1866 #define CPUSS_MTB_SRAM_SIZE 4u 1867 /* CM4 ETB SRAM buffer size in kilobytes. Legal vaules 4, 8 or 16 */ 1868 #define CPUSS_ETB_SRAM_SIZE 8u 1869 /* PTM interface present (0=No, 1=Yes) */ 1870 #define CPUSS_PTM_PRESENT 0u 1871 /* Width of the PTM interface in bits ([2,32]) */ 1872 #define CPUSS_PTM_WIDTH 1u 1873 /* Width of the TPIU interface in bits ([1,4]) */ 1874 #define CPUSS_TPIU_WIDTH 4u 1875 /* CoreSight Part Identification Number */ 1876 #define CPUSS_JEPID 52u 1877 /* CoreSight Part Identification Number */ 1878 #define CPUSS_JEPCONTINUATION 0u 1879 /* CoreSight Part Identification Number */ 1880 #define CPUSS_FAMILYID 257u 1881 /* ROM trim register width (for ARM 3, for Synopsys 5) */ 1882 #define CPUSS_ROM_TRIM_WIDTH 3u 1883 /* ROM trim register default (for both ARM and Synopsys 0x0000_0002) */ 1884 #define CPUSS_ROM_TRIM_DEFAULT 2u 1885 /* RAM trim register width (for ARM 8, for Synopsys 15) */ 1886 #define CPUSS_RAM_TRIM_WIDTH 8u 1887 /* RAM trim register default (for ARM 0x0000_0062 and for Synopsys 0x0000_6012) */ 1888 #define CPUSS_RAM_TRIM_DEFAULT 98u 1889 /* Cryptography IP present or not ('0': no, '1': yes) */ 1890 #define CPUSS_CRYPTO_PRESENT 1u 1891 /* DataWire and DMAC SW trigger per channel present or not ('0': no, '1': yes) */ 1892 #define CPUSS_SW_TR_PRESENT 1u 1893 /* DataWire 0 present or not ('0': no, '1': yes) */ 1894 #define CPUSS_DW0_PRESENT 1u 1895 /* Number of DataWire 0 channels ([1, 1024]) */ 1896 #define CPUSS_DW0_CH_NR 89u 1897 /* DataWire 1 present or not ('0': no, '1': yes) */ 1898 #define CPUSS_DW1_PRESENT 1u 1899 /* Number of DataWire 1 channels ([1, 1024]) */ 1900 #define CPUSS_DW1_CH_NR 33u 1901 /* DMA controller present or not ('0': no, '1': yes) */ 1902 #define CPUSS_DMAC_PRESENT 1u 1903 /* Number of DMA controller channels ([1, 8]) */ 1904 #define CPUSS_DMAC_CH_NR 4u 1905 /* DMAC SW trigger per channel present or not ('0': no, '1': yes) */ 1906 #define CPUSS_CH_SW_TR_PRESENT 1u 1907 /* See MMIO2 instantiation or not */ 1908 #define CPUSS_CHIP_TOP_PROFILER_PRESENT 0u 1909 /* ETAS Calibration support pin out present (automotive only) */ 1910 #define CPUSS_CHIP_TOP_CAL_SUP_NZ_PRESENT 1u 1911 /* TRACE_LVL>0 */ 1912 #define CPUSS_CHIP_TOP_TRACE_PRESENT 1u 1913 /* DataWire SW trigger per channel present or not ('0': no, '1': yes) */ 1914 #define CPUSS_CH_STRUCT_SW_TR_PRESENT 1u 1915 /* Number of DataWire controllers present (max 2) (same as DW.NR above) */ 1916 #define CPUSS_CPUSS_DW_DW_NR 2u 1917 /* Number of channels in each DataWire controller */ 1918 #define CPUSS_CPUSS_DW_DW_NR0_DW_CH_NR 89u 1919 /* Width of a channel number in bits */ 1920 #define CPUSS_CPUSS_DW_DW_NR0_DW_CH_NR_WIDTH 7u 1921 /* Number of channels in each DataWire controller */ 1922 #define CPUSS_CPUSS_DW_DW_NR1_DW_CH_NR 33u 1923 /* Width of a channel number in bits */ 1924 #define CPUSS_CPUSS_DW_DW_NR1_DW_CH_NR_WIDTH 6u 1925 /* Cryptography SRAMs ECC present or not ('0': no, '1': yes) */ 1926 #define CPUSS_CRYPTO_ECC_PRESENT 1u 1927 /* Cryptography SRAMs address ECC present or not ('0': no, '1': yes) */ 1928 #define CPUSS_CRYPTO_ECC_ADDR_PRESENT 1u 1929 /* AES cipher support ('0': no, '1': yes) */ 1930 #define CPUSS_CRYPTO_AES 1u 1931 /* (Tripple) DES cipher support ('0': no, '1': yes) */ 1932 #define CPUSS_CRYPTO_DES 1u 1933 /* Chacha support ('0': no, '1': yes) */ 1934 #define CPUSS_CRYPTO_CHACHA 1u 1935 /* Pseudo random number generation support ('0': no, '1': yes) */ 1936 #define CPUSS_CRYPTO_PR 1u 1937 /* SHA1 hash support ('0': no, '1': yes) */ 1938 #define CPUSS_CRYPTO_SHA1 1u 1939 /* SHA2 hash support ('0': no, '1': yes) */ 1940 #define CPUSS_CRYPTO_SHA2 1u 1941 /* SHA3 hash support ('0': no, '1': yes) */ 1942 #define CPUSS_CRYPTO_SHA3 1u 1943 /* Cyclic Redundancy Check support ('0': no, '1': yes) */ 1944 #define CPUSS_CRYPTO_CRC 1u 1945 /* True random number generation support ('0': no, '1': yes) */ 1946 #define CPUSS_CRYPTO_TR 1u 1947 /* Vector unit support ('0': no, '1': yes) */ 1948 #define CPUSS_CRYPTO_VU 1u 1949 /* Galios/Counter Mode (GCM) support ('0': no, '1': yes) */ 1950 #define CPUSS_CRYPTO_GCM 1u 1951 /* Number of 32-bit words in the IP internal memory buffer (from the set [64, 128, 1952 256, 512, 1024, 2048, 4096], to allow for a 256 B, 512 B, 1 kB, 2 kB, 4 kB, 8 1953 kB and 16 kB memory buffer) */ 1954 #define CPUSS_CRYPTO_BUFF_SIZE 2048u 1955 /* Number of DMA controller channels ([1, 8]) */ 1956 #define CPUSS_DMAC_CH_NR 4u 1957 /* Number of DataWire controllers present (max 2) */ 1958 #define CPUSS_DW_NR 2u 1959 /* DataWire SRAMs ECC present or not ('0': no, '1': yes) */ 1960 #define CPUSS_DW_ECC_PRESENT 1u 1961 /* Number of fault structures. Legal range [1, 4] */ 1962 #define CPUSS_FAULT_FAULT_NR 4u 1963 /* Number of Flash BIST_DATA registers */ 1964 #define CPUSS_FLASHC_FLASHC_BIST_DATA_NR 8u 1965 /* Page size in # of 32-bit words (1: 4 bytes, 2: 8 bytes, ... */ 1966 #define CPUSS_FLASHC_PA_SIZE 128u 1967 /* SONOS Flash is used or not ('0': no, '1': yes) */ 1968 #define CPUSS_FLASHC_FLASHC_IS_SONOS 0u 1969 /* eCT Flash is used or not ('0': no, '1': yes) */ 1970 #define CPUSS_FLASHC_FLASHC_IS_ECT 1u 1971 /* Number of IPC structures. Legal range [1, 16] */ 1972 #define CPUSS_IPC_IPC_NR 8u 1973 /* Number of IPC interrupt structures. Legal range [1, 16] */ 1974 #define CPUSS_IPC_IPC_IRQ_NR 8u 1975 /* Master 0 protect contexts minus one */ 1976 #define CPUSS_PROT_SMPU_MS0_PC_NR_MINUS1 7u 1977 /* Master 1 protect contexts minus one */ 1978 #define CPUSS_PROT_SMPU_MS1_PC_NR_MINUS1 0u 1979 /* Master 2 protect contexts minus one */ 1980 #define CPUSS_PROT_SMPU_MS2_PC_NR_MINUS1 0u 1981 /* Master 3 protect contexts minus one */ 1982 #define CPUSS_PROT_SMPU_MS3_PC_NR_MINUS1 0u 1983 /* Master 4 protect contexts minus one */ 1984 #define CPUSS_PROT_SMPU_MS4_PC_NR_MINUS1 0u 1985 /* Master 5 protect contexts minus one */ 1986 #define CPUSS_PROT_SMPU_MS5_PC_NR_MINUS1 0u 1987 /* Master 6 protect contexts minus one */ 1988 #define CPUSS_PROT_SMPU_MS6_PC_NR_MINUS1 0u 1989 /* Master 7 protect contexts minus one */ 1990 #define CPUSS_PROT_SMPU_MS7_PC_NR_MINUS1 0u 1991 /* Master 8 protect contexts minus one */ 1992 #define CPUSS_PROT_SMPU_MS8_PC_NR_MINUS1 0u 1993 /* Master 9 protect contexts minus one */ 1994 #define CPUSS_PROT_SMPU_MS9_PC_NR_MINUS1 0u 1995 /* Master 10 protect contexts minus one */ 1996 #define CPUSS_PROT_SMPU_MS10_PC_NR_MINUS1 0u 1997 /* Master 11 protect contexts minus one */ 1998 #define CPUSS_PROT_SMPU_MS11_PC_NR_MINUS1 0u 1999 /* Master 12 protect contexts minus one */ 2000 #define CPUSS_PROT_SMPU_MS12_PC_NR_MINUS1 0u 2001 /* Master 13 protect contexts minus one */ 2002 #define CPUSS_PROT_SMPU_MS13_PC_NR_MINUS1 0u 2003 /* Master 14 protect contexts minus one */ 2004 #define CPUSS_PROT_SMPU_MS14_PC_NR_MINUS1 7u 2005 /* Master 15 protect contexts minus one */ 2006 #define CPUSS_PROT_SMPU_MS15_PC_NR_MINUS1 7u 2007 /* Number of SMPU protection structures */ 2008 #define CPUSS_PROT_SMPU_STRUCT_NR 16u 2009 /* Number of protection contexts supported minus 1. Legal range [1,16] */ 2010 #define CPUSS_SMPU_STRUCT_PC_NR_MINUS1 7u 2011 /* Number of HFCLK roots present. Must be > 0. Must be same as set for SRSS */ 2012 #define DFT_NUM_HFROOT 3u 2013 /* Width of clk_occ_fast output bus (number of external OCCs) */ 2014 #define DFT_EXT_OCC 2u 2015 /* Number of MBIST controllers with corresponding mbist(pg)_done and mbist(pg)_go 2016 signals. Value defined by CIC during Pass 1 */ 2017 #define DFT_MBIST_C_NUM 6u 2018 /* Number of instantiated eFUSE macros (256 bit macros). Legal range [1, 16] */ 2019 #define EFUSE_EFUSE_NR 4u 2020 /* Number of comparator structures ([1, 32]) */ 2021 #define EVTGEN_COMP_STRUCT_NR 11u 2022 /* Number of GPIO ports in range 0..31 */ 2023 #define IOSS_GPIO_GPIO_PORT_NR_0_31 24u 2024 /* Number of GPIO ports in range 32..63 */ 2025 #define IOSS_GPIO_GPIO_PORT_NR_32_63 0u 2026 /* Number of GPIO ports in range 64..95 */ 2027 #define IOSS_GPIO_GPIO_PORT_NR_64_95 0u 2028 /* Number of GPIO ports in range 96..127 */ 2029 #define IOSS_GPIO_GPIO_PORT_NR_96_127 0u 2030 /* Number of ports in device */ 2031 #define IOSS_GPIO_GPIO_PORT_NR 24u 2032 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2033 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_GPIO 1u 2034 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2035 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SIO 0u 2036 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2037 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_AUTOLVL 1u 2038 /* Indicates that pin #0 exists for this port with slew control feature (SIO, OVT, 2039 and ENH cell types) */ 2040 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO0 1u 2041 /* Indicates that pin #1 exists for this port with slew control feature */ 2042 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO1 1u 2043 /* Indicates that pin #2 exists for this port with slew control feature */ 2044 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO2 1u 2045 /* Indicates that pin #3 exists for this port with slew control feature */ 2046 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO3 1u 2047 /* Indicates that pin #4 exists for this port with slew control feature */ 2048 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO4 0u 2049 /* Indicates that pin #5 exists for this port with slew control feature */ 2050 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO5 0u 2051 /* Indicates that pin #6 exists for this port with slew control feature */ 2052 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO6 0u 2053 /* Indicates that pin #7 exists for this port with slew control feature */ 2054 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO7 0u 2055 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2056 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_GPIO 1u 2057 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2058 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SIO 0u 2059 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2060 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_AUTOLVL 1u 2061 /* Indicates that pin #0 exists for this port with slew control feature (SIO, OVT, 2062 and ENH cell types) */ 2063 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO0 0u 2064 /* Indicates that pin #1 exists for this port with slew control feature */ 2065 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO1 0u 2066 /* Indicates that pin #2 exists for this port with slew control feature */ 2067 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO2 0u 2068 /* Indicates that pin #3 exists for this port with slew control feature */ 2069 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO3 0u 2070 /* Indicates that pin #4 exists for this port with slew control feature */ 2071 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO4 0u 2072 /* Indicates that pin #5 exists for this port with slew control feature */ 2073 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO5 0u 2074 /* Indicates that pin #6 exists for this port with slew control feature */ 2075 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO6 0u 2076 /* Indicates that pin #7 exists for this port with slew control feature */ 2077 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO7 0u 2078 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2079 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_GPIO 1u 2080 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2081 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SIO 0u 2082 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2083 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_AUTOLVL 1u 2084 /* Indicates that pin #0 exists for this port with slew control feature (SIO, OVT, 2085 and ENH cell types) */ 2086 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO0 0u 2087 /* Indicates that pin #1 exists for this port with slew control feature */ 2088 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO1 0u 2089 /* Indicates that pin #2 exists for this port with slew control feature */ 2090 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO2 0u 2091 /* Indicates that pin #3 exists for this port with slew control feature */ 2092 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO3 0u 2093 /* Indicates that pin #4 exists for this port with slew control feature */ 2094 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO4 0u 2095 /* Indicates that pin #5 exists for this port with slew control feature */ 2096 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO5 0u 2097 /* Indicates that pin #6 exists for this port with slew control feature */ 2098 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO6 0u 2099 /* Indicates that pin #7 exists for this port with slew control feature */ 2100 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO7 0u 2101 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2102 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_GPIO 1u 2103 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2104 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SIO 0u 2105 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2106 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_AUTOLVL 1u 2107 /* Indicates that pin #0 exists for this port with slew control feature (SIO, OVT, 2108 and ENH cell types) */ 2109 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO0 0u 2110 /* Indicates that pin #1 exists for this port with slew control feature */ 2111 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO1 0u 2112 /* Indicates that pin #2 exists for this port with slew control feature */ 2113 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO2 0u 2114 /* Indicates that pin #3 exists for this port with slew control feature */ 2115 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO3 0u 2116 /* Indicates that pin #4 exists for this port with slew control feature */ 2117 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO4 0u 2118 /* Indicates that pin #5 exists for this port with slew control feature */ 2119 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO5 0u 2120 /* Indicates that pin #6 exists for this port with slew control feature */ 2121 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO6 0u 2122 /* Indicates that pin #7 exists for this port with slew control feature */ 2123 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO7 0u 2124 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2125 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_GPIO 1u 2126 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2127 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SIO 0u 2128 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2129 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_AUTOLVL 1u 2130 /* Indicates that pin #0 exists for this port with slew control feature (SIO, OVT, 2131 and ENH cell types) */ 2132 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO0 0u 2133 /* Indicates that pin #1 exists for this port with slew control feature */ 2134 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO1 0u 2135 /* Indicates that pin #2 exists for this port with slew control feature */ 2136 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO2 0u 2137 /* Indicates that pin #3 exists for this port with slew control feature */ 2138 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO3 0u 2139 /* Indicates that pin #4 exists for this port with slew control feature */ 2140 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO4 0u 2141 /* Indicates that pin #5 exists for this port with slew control feature */ 2142 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO5 0u 2143 /* Indicates that pin #6 exists for this port with slew control feature */ 2144 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO6 0u 2145 /* Indicates that pin #7 exists for this port with slew control feature */ 2146 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO7 0u 2147 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2148 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_GPIO 1u 2149 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2150 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SIO 0u 2151 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2152 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_AUTOLVL 1u 2153 /* Indicates that pin #0 exists for this port with slew control feature (SIO, OVT, 2154 and ENH cell types) */ 2155 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO0 0u 2156 /* Indicates that pin #1 exists for this port with slew control feature */ 2157 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO1 0u 2158 /* Indicates that pin #2 exists for this port with slew control feature */ 2159 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO2 0u 2160 /* Indicates that pin #3 exists for this port with slew control feature */ 2161 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO3 0u 2162 /* Indicates that pin #4 exists for this port with slew control feature */ 2163 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO4 0u 2164 /* Indicates that pin #5 exists for this port with slew control feature */ 2165 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO5 0u 2166 /* Indicates that pin #6 exists for this port with slew control feature */ 2167 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO6 0u 2168 /* Indicates that pin #7 exists for this port with slew control feature */ 2169 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO7 0u 2170 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2171 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_GPIO 1u 2172 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2173 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SIO 0u 2174 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2175 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_AUTOLVL 1u 2176 /* Indicates that pin #0 exists for this port with slew control feature (SIO, OVT, 2177 and ENH cell types) */ 2178 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO0 0u 2179 /* Indicates that pin #1 exists for this port with slew control feature */ 2180 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO1 0u 2181 /* Indicates that pin #2 exists for this port with slew control feature */ 2182 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO2 0u 2183 /* Indicates that pin #3 exists for this port with slew control feature */ 2184 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO3 0u 2185 /* Indicates that pin #4 exists for this port with slew control feature */ 2186 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO4 0u 2187 /* Indicates that pin #5 exists for this port with slew control feature */ 2188 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO5 0u 2189 /* Indicates that pin #6 exists for this port with slew control feature */ 2190 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO6 0u 2191 /* Indicates that pin #7 exists for this port with slew control feature */ 2192 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO7 0u 2193 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2194 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_GPIO 1u 2195 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2196 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SIO 0u 2197 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2198 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_AUTOLVL 1u 2199 /* Indicates that pin #0 exists for this port with slew control feature (SIO, OVT, 2200 and ENH cell types) */ 2201 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO0 0u 2202 /* Indicates that pin #1 exists for this port with slew control feature */ 2203 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO1 0u 2204 /* Indicates that pin #2 exists for this port with slew control feature */ 2205 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO2 0u 2206 /* Indicates that pin #3 exists for this port with slew control feature */ 2207 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO3 0u 2208 /* Indicates that pin #4 exists for this port with slew control feature */ 2209 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO4 0u 2210 /* Indicates that pin #5 exists for this port with slew control feature */ 2211 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO5 0u 2212 /* Indicates that pin #6 exists for this port with slew control feature */ 2213 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO6 0u 2214 /* Indicates that pin #7 exists for this port with slew control feature */ 2215 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO7 0u 2216 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2217 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_GPIO 1u 2218 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2219 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SIO 0u 2220 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2221 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_AUTOLVL 1u 2222 /* Indicates that pin #0 exists for this port with slew control feature (SIO, OVT, 2223 and ENH cell types) */ 2224 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO0 0u 2225 /* Indicates that pin #1 exists for this port with slew control feature */ 2226 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO1 0u 2227 /* Indicates that pin #2 exists for this port with slew control feature */ 2228 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO2 0u 2229 /* Indicates that pin #3 exists for this port with slew control feature */ 2230 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO3 0u 2231 /* Indicates that pin #4 exists for this port with slew control feature */ 2232 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO4 0u 2233 /* Indicates that pin #5 exists for this port with slew control feature */ 2234 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO5 0u 2235 /* Indicates that pin #6 exists for this port with slew control feature */ 2236 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO6 0u 2237 /* Indicates that pin #7 exists for this port with slew control feature */ 2238 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO7 0u 2239 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2240 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_GPIO 1u 2241 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2242 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SIO 0u 2243 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2244 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_AUTOLVL 1u 2245 /* Indicates that pin #0 exists for this port with slew control feature (SIO, OVT, 2246 and ENH cell types) */ 2247 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO0 0u 2248 /* Indicates that pin #1 exists for this port with slew control feature */ 2249 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO1 0u 2250 /* Indicates that pin #2 exists for this port with slew control feature */ 2251 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO2 0u 2252 /* Indicates that pin #3 exists for this port with slew control feature */ 2253 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO3 0u 2254 /* Indicates that pin #4 exists for this port with slew control feature */ 2255 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO4 0u 2256 /* Indicates that pin #5 exists for this port with slew control feature */ 2257 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO5 0u 2258 /* Indicates that pin #6 exists for this port with slew control feature */ 2259 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO6 0u 2260 /* Indicates that pin #7 exists for this port with slew control feature */ 2261 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO7 0u 2262 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2263 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_GPIO 1u 2264 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2265 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SIO 0u 2266 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2267 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_AUTOLVL 1u 2268 /* Indicates that pin #0 exists for this port with slew control feature (SIO, OVT, 2269 and ENH cell types) */ 2270 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO0 0u 2271 /* Indicates that pin #1 exists for this port with slew control feature */ 2272 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO1 0u 2273 /* Indicates that pin #2 exists for this port with slew control feature */ 2274 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO2 0u 2275 /* Indicates that pin #3 exists for this port with slew control feature */ 2276 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO3 0u 2277 /* Indicates that pin #4 exists for this port with slew control feature */ 2278 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO4 0u 2279 /* Indicates that pin #5 exists for this port with slew control feature */ 2280 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO5 0u 2281 /* Indicates that pin #6 exists for this port with slew control feature */ 2282 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO6 0u 2283 /* Indicates that pin #7 exists for this port with slew control feature */ 2284 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO7 0u 2285 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2286 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_GPIO 1u 2287 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2288 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SIO 0u 2289 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2290 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_AUTOLVL 1u 2291 /* Indicates that pin #0 exists for this port with slew control feature (SIO, OVT, 2292 and ENH cell types) */ 2293 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO0 0u 2294 /* Indicates that pin #1 exists for this port with slew control feature */ 2295 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO1 0u 2296 /* Indicates that pin #2 exists for this port with slew control feature */ 2297 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO2 0u 2298 /* Indicates that pin #3 exists for this port with slew control feature */ 2299 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO3 0u 2300 /* Indicates that pin #4 exists for this port with slew control feature */ 2301 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO4 0u 2302 /* Indicates that pin #5 exists for this port with slew control feature */ 2303 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO5 0u 2304 /* Indicates that pin #6 exists for this port with slew control feature */ 2305 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO6 0u 2306 /* Indicates that pin #7 exists for this port with slew control feature */ 2307 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO7 0u 2308 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2309 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_GPIO 1u 2310 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2311 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SIO 0u 2312 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2313 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_AUTOLVL 1u 2314 /* Indicates that pin #0 exists for this port with slew control feature (SIO, OVT, 2315 and ENH cell types) */ 2316 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO0 0u 2317 /* Indicates that pin #1 exists for this port with slew control feature */ 2318 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO1 0u 2319 /* Indicates that pin #2 exists for this port with slew control feature */ 2320 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO2 0u 2321 /* Indicates that pin #3 exists for this port with slew control feature */ 2322 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO3 0u 2323 /* Indicates that pin #4 exists for this port with slew control feature */ 2324 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO4 0u 2325 /* Indicates that pin #5 exists for this port with slew control feature */ 2326 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO5 0u 2327 /* Indicates that pin #6 exists for this port with slew control feature */ 2328 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO6 0u 2329 /* Indicates that pin #7 exists for this port with slew control feature */ 2330 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO7 0u 2331 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2332 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_GPIO 1u 2333 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2334 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SIO 0u 2335 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2336 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_AUTOLVL 1u 2337 /* Indicates that pin #0 exists for this port with slew control feature (SIO, OVT, 2338 and ENH cell types) */ 2339 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO0 0u 2340 /* Indicates that pin #1 exists for this port with slew control feature */ 2341 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO1 0u 2342 /* Indicates that pin #2 exists for this port with slew control feature */ 2343 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO2 0u 2344 /* Indicates that pin #3 exists for this port with slew control feature */ 2345 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO3 0u 2346 /* Indicates that pin #4 exists for this port with slew control feature */ 2347 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO4 0u 2348 /* Indicates that pin #5 exists for this port with slew control feature */ 2349 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO5 0u 2350 /* Indicates that pin #6 exists for this port with slew control feature */ 2351 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO6 0u 2352 /* Indicates that pin #7 exists for this port with slew control feature */ 2353 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO7 0u 2354 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2355 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_GPIO 1u 2356 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2357 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SIO 0u 2358 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2359 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_AUTOLVL 1u 2360 /* Indicates that pin #0 exists for this port with slew control feature (SIO, OVT, 2361 and ENH cell types) */ 2362 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO0 0u 2363 /* Indicates that pin #1 exists for this port with slew control feature */ 2364 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO1 0u 2365 /* Indicates that pin #2 exists for this port with slew control feature */ 2366 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO2 0u 2367 /* Indicates that pin #3 exists for this port with slew control feature */ 2368 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO3 0u 2369 /* Indicates that pin #4 exists for this port with slew control feature */ 2370 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO4 0u 2371 /* Indicates that pin #5 exists for this port with slew control feature */ 2372 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO5 0u 2373 /* Indicates that pin #6 exists for this port with slew control feature */ 2374 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO6 0u 2375 /* Indicates that pin #7 exists for this port with slew control feature */ 2376 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO7 0u 2377 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2378 #define IOSS_GPIO_GPIO_PORT_NR15_GPIO_PRT_GPIO 1u 2379 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2380 #define IOSS_GPIO_GPIO_PORT_NR15_GPIO_PRT_SIO 0u 2381 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2382 #define IOSS_GPIO_GPIO_PORT_NR15_GPIO_PRT_AUTOLVL 1u 2383 /* Indicates that pin #0 exists for this port with slew control feature (SIO, OVT, 2384 and ENH cell types) */ 2385 #define IOSS_GPIO_GPIO_PORT_NR15_GPIO_PRT_SLOW_IO0 0u 2386 /* Indicates that pin #1 exists for this port with slew control feature */ 2387 #define IOSS_GPIO_GPIO_PORT_NR15_GPIO_PRT_SLOW_IO1 0u 2388 /* Indicates that pin #2 exists for this port with slew control feature */ 2389 #define IOSS_GPIO_GPIO_PORT_NR15_GPIO_PRT_SLOW_IO2 0u 2390 /* Indicates that pin #3 exists for this port with slew control feature */ 2391 #define IOSS_GPIO_GPIO_PORT_NR15_GPIO_PRT_SLOW_IO3 0u 2392 /* Indicates that pin #4 exists for this port with slew control feature */ 2393 #define IOSS_GPIO_GPIO_PORT_NR15_GPIO_PRT_SLOW_IO4 0u 2394 /* Indicates that pin #5 exists for this port with slew control feature */ 2395 #define IOSS_GPIO_GPIO_PORT_NR15_GPIO_PRT_SLOW_IO5 0u 2396 /* Indicates that pin #6 exists for this port with slew control feature */ 2397 #define IOSS_GPIO_GPIO_PORT_NR15_GPIO_PRT_SLOW_IO6 0u 2398 /* Indicates that pin #7 exists for this port with slew control feature */ 2399 #define IOSS_GPIO_GPIO_PORT_NR15_GPIO_PRT_SLOW_IO7 0u 2400 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2401 #define IOSS_GPIO_GPIO_PORT_NR16_GPIO_PRT_GPIO 1u 2402 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2403 #define IOSS_GPIO_GPIO_PORT_NR16_GPIO_PRT_SIO 0u 2404 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2405 #define IOSS_GPIO_GPIO_PORT_NR16_GPIO_PRT_AUTOLVL 1u 2406 /* Indicates that pin #0 exists for this port with slew control feature (SIO, OVT, 2407 and ENH cell types) */ 2408 #define IOSS_GPIO_GPIO_PORT_NR16_GPIO_PRT_SLOW_IO0 0u 2409 /* Indicates that pin #1 exists for this port with slew control feature */ 2410 #define IOSS_GPIO_GPIO_PORT_NR16_GPIO_PRT_SLOW_IO1 0u 2411 /* Indicates that pin #2 exists for this port with slew control feature */ 2412 #define IOSS_GPIO_GPIO_PORT_NR16_GPIO_PRT_SLOW_IO2 0u 2413 /* Indicates that pin #3 exists for this port with slew control feature */ 2414 #define IOSS_GPIO_GPIO_PORT_NR16_GPIO_PRT_SLOW_IO3 0u 2415 /* Indicates that pin #4 exists for this port with slew control feature */ 2416 #define IOSS_GPIO_GPIO_PORT_NR16_GPIO_PRT_SLOW_IO4 0u 2417 /* Indicates that pin #5 exists for this port with slew control feature */ 2418 #define IOSS_GPIO_GPIO_PORT_NR16_GPIO_PRT_SLOW_IO5 0u 2419 /* Indicates that pin #6 exists for this port with slew control feature */ 2420 #define IOSS_GPIO_GPIO_PORT_NR16_GPIO_PRT_SLOW_IO6 0u 2421 /* Indicates that pin #7 exists for this port with slew control feature */ 2422 #define IOSS_GPIO_GPIO_PORT_NR16_GPIO_PRT_SLOW_IO7 0u 2423 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2424 #define IOSS_GPIO_GPIO_PORT_NR17_GPIO_PRT_GPIO 1u 2425 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2426 #define IOSS_GPIO_GPIO_PORT_NR17_GPIO_PRT_SIO 0u 2427 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2428 #define IOSS_GPIO_GPIO_PORT_NR17_GPIO_PRT_AUTOLVL 1u 2429 /* Indicates that pin #0 exists for this port with slew control feature (SIO, OVT, 2430 and ENH cell types) */ 2431 #define IOSS_GPIO_GPIO_PORT_NR17_GPIO_PRT_SLOW_IO0 0u 2432 /* Indicates that pin #1 exists for this port with slew control feature */ 2433 #define IOSS_GPIO_GPIO_PORT_NR17_GPIO_PRT_SLOW_IO1 0u 2434 /* Indicates that pin #2 exists for this port with slew control feature */ 2435 #define IOSS_GPIO_GPIO_PORT_NR17_GPIO_PRT_SLOW_IO2 0u 2436 /* Indicates that pin #3 exists for this port with slew control feature */ 2437 #define IOSS_GPIO_GPIO_PORT_NR17_GPIO_PRT_SLOW_IO3 0u 2438 /* Indicates that pin #4 exists for this port with slew control feature */ 2439 #define IOSS_GPIO_GPIO_PORT_NR17_GPIO_PRT_SLOW_IO4 0u 2440 /* Indicates that pin #5 exists for this port with slew control feature */ 2441 #define IOSS_GPIO_GPIO_PORT_NR17_GPIO_PRT_SLOW_IO5 0u 2442 /* Indicates that pin #6 exists for this port with slew control feature */ 2443 #define IOSS_GPIO_GPIO_PORT_NR17_GPIO_PRT_SLOW_IO6 0u 2444 /* Indicates that pin #7 exists for this port with slew control feature */ 2445 #define IOSS_GPIO_GPIO_PORT_NR17_GPIO_PRT_SLOW_IO7 0u 2446 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2447 #define IOSS_GPIO_GPIO_PORT_NR18_GPIO_PRT_GPIO 1u 2448 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2449 #define IOSS_GPIO_GPIO_PORT_NR18_GPIO_PRT_SIO 0u 2450 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2451 #define IOSS_GPIO_GPIO_PORT_NR18_GPIO_PRT_AUTOLVL 1u 2452 /* Indicates that pin #0 exists for this port with slew control feature (SIO, OVT, 2453 and ENH cell types) */ 2454 #define IOSS_GPIO_GPIO_PORT_NR18_GPIO_PRT_SLOW_IO0 0u 2455 /* Indicates that pin #1 exists for this port with slew control feature */ 2456 #define IOSS_GPIO_GPIO_PORT_NR18_GPIO_PRT_SLOW_IO1 0u 2457 /* Indicates that pin #2 exists for this port with slew control feature */ 2458 #define IOSS_GPIO_GPIO_PORT_NR18_GPIO_PRT_SLOW_IO2 0u 2459 /* Indicates that pin #3 exists for this port with slew control feature */ 2460 #define IOSS_GPIO_GPIO_PORT_NR18_GPIO_PRT_SLOW_IO3 0u 2461 /* Indicates that pin #4 exists for this port with slew control feature */ 2462 #define IOSS_GPIO_GPIO_PORT_NR18_GPIO_PRT_SLOW_IO4 0u 2463 /* Indicates that pin #5 exists for this port with slew control feature */ 2464 #define IOSS_GPIO_GPIO_PORT_NR18_GPIO_PRT_SLOW_IO5 0u 2465 /* Indicates that pin #6 exists for this port with slew control feature */ 2466 #define IOSS_GPIO_GPIO_PORT_NR18_GPIO_PRT_SLOW_IO6 0u 2467 /* Indicates that pin #7 exists for this port with slew control feature */ 2468 #define IOSS_GPIO_GPIO_PORT_NR18_GPIO_PRT_SLOW_IO7 0u 2469 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2470 #define IOSS_GPIO_GPIO_PORT_NR19_GPIO_PRT_GPIO 1u 2471 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2472 #define IOSS_GPIO_GPIO_PORT_NR19_GPIO_PRT_SIO 0u 2473 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2474 #define IOSS_GPIO_GPIO_PORT_NR19_GPIO_PRT_AUTOLVL 1u 2475 /* Indicates that pin #0 exists for this port with slew control feature (SIO, OVT, 2476 and ENH cell types) */ 2477 #define IOSS_GPIO_GPIO_PORT_NR19_GPIO_PRT_SLOW_IO0 0u 2478 /* Indicates that pin #1 exists for this port with slew control feature */ 2479 #define IOSS_GPIO_GPIO_PORT_NR19_GPIO_PRT_SLOW_IO1 0u 2480 /* Indicates that pin #2 exists for this port with slew control feature */ 2481 #define IOSS_GPIO_GPIO_PORT_NR19_GPIO_PRT_SLOW_IO2 0u 2482 /* Indicates that pin #3 exists for this port with slew control feature */ 2483 #define IOSS_GPIO_GPIO_PORT_NR19_GPIO_PRT_SLOW_IO3 0u 2484 /* Indicates that pin #4 exists for this port with slew control feature */ 2485 #define IOSS_GPIO_GPIO_PORT_NR19_GPIO_PRT_SLOW_IO4 0u 2486 /* Indicates that pin #5 exists for this port with slew control feature */ 2487 #define IOSS_GPIO_GPIO_PORT_NR19_GPIO_PRT_SLOW_IO5 0u 2488 /* Indicates that pin #6 exists for this port with slew control feature */ 2489 #define IOSS_GPIO_GPIO_PORT_NR19_GPIO_PRT_SLOW_IO6 0u 2490 /* Indicates that pin #7 exists for this port with slew control feature */ 2491 #define IOSS_GPIO_GPIO_PORT_NR19_GPIO_PRT_SLOW_IO7 0u 2492 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2493 #define IOSS_GPIO_GPIO_PORT_NR20_GPIO_PRT_GPIO 1u 2494 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2495 #define IOSS_GPIO_GPIO_PORT_NR20_GPIO_PRT_SIO 0u 2496 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2497 #define IOSS_GPIO_GPIO_PORT_NR20_GPIO_PRT_AUTOLVL 1u 2498 /* Indicates that pin #0 exists for this port with slew control feature (SIO, OVT, 2499 and ENH cell types) */ 2500 #define IOSS_GPIO_GPIO_PORT_NR20_GPIO_PRT_SLOW_IO0 0u 2501 /* Indicates that pin #1 exists for this port with slew control feature */ 2502 #define IOSS_GPIO_GPIO_PORT_NR20_GPIO_PRT_SLOW_IO1 0u 2503 /* Indicates that pin #2 exists for this port with slew control feature */ 2504 #define IOSS_GPIO_GPIO_PORT_NR20_GPIO_PRT_SLOW_IO2 0u 2505 /* Indicates that pin #3 exists for this port with slew control feature */ 2506 #define IOSS_GPIO_GPIO_PORT_NR20_GPIO_PRT_SLOW_IO3 0u 2507 /* Indicates that pin #4 exists for this port with slew control feature */ 2508 #define IOSS_GPIO_GPIO_PORT_NR20_GPIO_PRT_SLOW_IO4 0u 2509 /* Indicates that pin #5 exists for this port with slew control feature */ 2510 #define IOSS_GPIO_GPIO_PORT_NR20_GPIO_PRT_SLOW_IO5 0u 2511 /* Indicates that pin #6 exists for this port with slew control feature */ 2512 #define IOSS_GPIO_GPIO_PORT_NR20_GPIO_PRT_SLOW_IO6 0u 2513 /* Indicates that pin #7 exists for this port with slew control feature */ 2514 #define IOSS_GPIO_GPIO_PORT_NR20_GPIO_PRT_SLOW_IO7 0u 2515 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2516 #define IOSS_GPIO_GPIO_PORT_NR21_GPIO_PRT_GPIO 1u 2517 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2518 #define IOSS_GPIO_GPIO_PORT_NR21_GPIO_PRT_SIO 0u 2519 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2520 #define IOSS_GPIO_GPIO_PORT_NR21_GPIO_PRT_AUTOLVL 1u 2521 /* Indicates that pin #0 exists for this port with slew control feature (SIO, OVT, 2522 and ENH cell types) */ 2523 #define IOSS_GPIO_GPIO_PORT_NR21_GPIO_PRT_SLOW_IO0 0u 2524 /* Indicates that pin #1 exists for this port with slew control feature */ 2525 #define IOSS_GPIO_GPIO_PORT_NR21_GPIO_PRT_SLOW_IO1 0u 2526 /* Indicates that pin #2 exists for this port with slew control feature */ 2527 #define IOSS_GPIO_GPIO_PORT_NR21_GPIO_PRT_SLOW_IO2 0u 2528 /* Indicates that pin #3 exists for this port with slew control feature */ 2529 #define IOSS_GPIO_GPIO_PORT_NR21_GPIO_PRT_SLOW_IO3 0u 2530 /* Indicates that pin #4 exists for this port with slew control feature */ 2531 #define IOSS_GPIO_GPIO_PORT_NR21_GPIO_PRT_SLOW_IO4 0u 2532 /* Indicates that pin #5 exists for this port with slew control feature */ 2533 #define IOSS_GPIO_GPIO_PORT_NR21_GPIO_PRT_SLOW_IO5 0u 2534 /* Indicates that pin #6 exists for this port with slew control feature */ 2535 #define IOSS_GPIO_GPIO_PORT_NR21_GPIO_PRT_SLOW_IO6 0u 2536 /* Indicates that pin #7 exists for this port with slew control feature */ 2537 #define IOSS_GPIO_GPIO_PORT_NR21_GPIO_PRT_SLOW_IO7 0u 2538 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2539 #define IOSS_GPIO_GPIO_PORT_NR22_GPIO_PRT_GPIO 1u 2540 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2541 #define IOSS_GPIO_GPIO_PORT_NR22_GPIO_PRT_SIO 0u 2542 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2543 #define IOSS_GPIO_GPIO_PORT_NR22_GPIO_PRT_AUTOLVL 1u 2544 /* Indicates that pin #0 exists for this port with slew control feature (SIO, OVT, 2545 and ENH cell types) */ 2546 #define IOSS_GPIO_GPIO_PORT_NR22_GPIO_PRT_SLOW_IO0 0u 2547 /* Indicates that pin #1 exists for this port with slew control feature */ 2548 #define IOSS_GPIO_GPIO_PORT_NR22_GPIO_PRT_SLOW_IO1 0u 2549 /* Indicates that pin #2 exists for this port with slew control feature */ 2550 #define IOSS_GPIO_GPIO_PORT_NR22_GPIO_PRT_SLOW_IO2 0u 2551 /* Indicates that pin #3 exists for this port with slew control feature */ 2552 #define IOSS_GPIO_GPIO_PORT_NR22_GPIO_PRT_SLOW_IO3 0u 2553 /* Indicates that pin #4 exists for this port with slew control feature */ 2554 #define IOSS_GPIO_GPIO_PORT_NR22_GPIO_PRT_SLOW_IO4 0u 2555 /* Indicates that pin #5 exists for this port with slew control feature */ 2556 #define IOSS_GPIO_GPIO_PORT_NR22_GPIO_PRT_SLOW_IO5 0u 2557 /* Indicates that pin #6 exists for this port with slew control feature */ 2558 #define IOSS_GPIO_GPIO_PORT_NR22_GPIO_PRT_SLOW_IO6 0u 2559 /* Indicates that pin #7 exists for this port with slew control feature */ 2560 #define IOSS_GPIO_GPIO_PORT_NR22_GPIO_PRT_SLOW_IO7 0u 2561 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2562 #define IOSS_GPIO_GPIO_PORT_NR23_GPIO_PRT_GPIO 1u 2563 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2564 #define IOSS_GPIO_GPIO_PORT_NR23_GPIO_PRT_SIO 0u 2565 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2566 #define IOSS_GPIO_GPIO_PORT_NR23_GPIO_PRT_AUTOLVL 1u 2567 /* Indicates that pin #0 exists for this port with slew control feature (SIO, OVT, 2568 and ENH cell types) */ 2569 #define IOSS_GPIO_GPIO_PORT_NR23_GPIO_PRT_SLOW_IO0 0u 2570 /* Indicates that pin #1 exists for this port with slew control feature */ 2571 #define IOSS_GPIO_GPIO_PORT_NR23_GPIO_PRT_SLOW_IO1 0u 2572 /* Indicates that pin #2 exists for this port with slew control feature */ 2573 #define IOSS_GPIO_GPIO_PORT_NR23_GPIO_PRT_SLOW_IO2 0u 2574 /* Indicates that pin #3 exists for this port with slew control feature */ 2575 #define IOSS_GPIO_GPIO_PORT_NR23_GPIO_PRT_SLOW_IO3 0u 2576 /* Indicates that pin #4 exists for this port with slew control feature */ 2577 #define IOSS_GPIO_GPIO_PORT_NR23_GPIO_PRT_SLOW_IO4 0u 2578 /* Indicates that pin #5 exists for this port with slew control feature */ 2579 #define IOSS_GPIO_GPIO_PORT_NR23_GPIO_PRT_SLOW_IO5 0u 2580 /* Indicates that pin #6 exists for this port with slew control feature */ 2581 #define IOSS_GPIO_GPIO_PORT_NR23_GPIO_PRT_SLOW_IO6 0u 2582 /* Indicates that pin #7 exists for this port with slew control feature */ 2583 #define IOSS_GPIO_GPIO_PORT_NR23_GPIO_PRT_SLOW_IO7 0u 2584 /* Number of AMUX splitter cells */ 2585 #define IOSS_HSIOM_AMUX_SPLIT_NR 3u 2586 /* Number of HSIOM ports in device (same as GPIO.GPIO_PRT_NR) */ 2587 #define IOSS_HSIOM_HSIOM_PORT_NR 24u 2588 /* Number of PWR/GND MONITOR CELLs in the device */ 2589 #define IOSS_HSIOM_MONITOR_NR 21u 2590 /* Number of PWR/GND MONITOR CELLs in range 0..31 */ 2591 #define IOSS_HSIOM_MONITOR_NR_0_31 21u 2592 /* Number of PWR/GND MONITOR CELLs in range 32..63 */ 2593 #define IOSS_HSIOM_MONITOR_NR_32_63 0u 2594 /* Number of PWR/GND MONITOR CELLs in range 64..95 */ 2595 #define IOSS_HSIOM_MONITOR_NR_64_95 0u 2596 /* Number of PWR/GND MONITOR CELLs in range 96..127 */ 2597 #define IOSS_HSIOM_MONITOR_NR_96_127 0u 2598 /* Indicates the presence of alternate JTAG interface */ 2599 #define IOSS_HSIOM_ALTJTAG_PRESENT 1u 2600 /* Mask of SMARTIO instances presence */ 2601 #define IOSS_SMARTIO_SMARTIO_MASK 0x0002F000u 2602 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 2603 #define LIN_MASTER_WIDTH 8u 2604 /* Number of LIN channels ([2, 32]). For test functionality (two channels are 2605 connected), the minimal number of LIN channels is 2. */ 2606 #define LIN_CH_NR 8u 2607 /* Platform variant (0=ULL65, 1=MXS40S-ULP, 2=MXS40E, 3=M0S8, 4=MXS40S-HD) */ 2608 #define LIN_CHIP_TOP_PLATFORM_VARIANT 2u 2609 /* Number of SAR blocks */ 2610 #define PASS_SAR_ADC_NR 3u 2611 /* Number of ADC slices. Each slice will contain one SARMUX block and optionally a 2612 SAR and associated sequencer logic. */ 2613 #define PASS_SAR_SLICE_NR 3u 2614 /* Number of SAR sequencer channels (per SAR) */ 2615 #define PASS_SAR_SLICE_NR0_SAR_SAR_CHAN_NR 24u 2616 /* Number of MUX inputs (per SAR), must be 8, 16, 24, or 32 */ 2617 #define PASS_SAR_SLICE_NR0_SAR_SAR_MUX_IN 24u 2618 /* Is ADC is present on slice (1 = Yes, 0 = No). Calculated from SAR_ADC_NR such 2619 that lower numbered slices contain the ADCs that are present. */ 2620 #define PASS_SAR_SLICE_NR0_SAR_SAR_ADC_PRESENT 1u 2621 /* Averaging logic present in SAR */ 2622 #define PASS_SAR_SLICE_NR0_SAR_SAR_AVERAGE 1u 2623 /* Range detect logic present in SAR */ 2624 #define PASS_SAR_SLICE_NR0_SAR_SAR_RANGEDET 1u 2625 /* Pulse detect logic present in SAR */ 2626 #define PASS_SAR_SLICE_NR0_SAR_SAR_PULSEDET 1u 2627 /* Number of SAR sequencer channels (per SAR) */ 2628 #define PASS_SAR_SLICE_NR1_SAR_SAR_CHAN_NR 32u 2629 /* Number of MUX inputs (per SAR), must be 8, 16, 24, or 32 */ 2630 #define PASS_SAR_SLICE_NR1_SAR_SAR_MUX_IN 32u 2631 /* Is ADC is present on slice (1 = Yes, 0 = No). Calculated from SAR_ADC_NR such 2632 that lower numbered slices contain the ADCs that are present. */ 2633 #define PASS_SAR_SLICE_NR1_SAR_SAR_ADC_PRESENT 1u 2634 /* Averaging logic present in SAR */ 2635 #define PASS_SAR_SLICE_NR1_SAR_SAR_AVERAGE 1u 2636 /* Range detect logic present in SAR */ 2637 #define PASS_SAR_SLICE_NR1_SAR_SAR_RANGEDET 1u 2638 /* Pulse detect logic present in SAR */ 2639 #define PASS_SAR_SLICE_NR1_SAR_SAR_PULSEDET 1u 2640 /* Number of SAR sequencer channels (per SAR) */ 2641 #define PASS_SAR_SLICE_NR2_SAR_SAR_CHAN_NR 8u 2642 /* Number of MUX inputs (per SAR), must be 8, 16, 24, or 32 */ 2643 #define PASS_SAR_SLICE_NR2_SAR_SAR_MUX_IN 8u 2644 /* Is ADC is present on slice (1 = Yes, 0 = No). Calculated from SAR_ADC_NR such 2645 that lower numbered slices contain the ADCs that are present. */ 2646 #define PASS_SAR_SLICE_NR2_SAR_SAR_ADC_PRESENT 1u 2647 /* Averaging logic present in SAR */ 2648 #define PASS_SAR_SLICE_NR2_SAR_SAR_AVERAGE 1u 2649 /* Range detect logic present in SAR */ 2650 #define PASS_SAR_SLICE_NR2_SAR_SAR_RANGEDET 1u 2651 /* Pulse detect logic present in SAR */ 2652 #define PASS_SAR_SLICE_NR2_SAR_SAR_PULSEDET 1u 2653 /* Parameter that is 1 for ADC0 only if ADC1 exists */ 2654 #define PASS_SAR_SAR_ADC0 1u 2655 /* The number of protection contexts ([2, 16]). */ 2656 #define PERI_PC_NR 8u 2657 /* Master interface presence mask (4 bits) */ 2658 #define PERI_MS_PRESENT 15u 2659 /* Protection structures SRAM ECC present or not ('0': no, '1': yes) */ 2660 #define PERI_ECC_PRESENT 1u 2661 /* Protection structures SRAM address ECC present or not ('0': no, '1': yes) */ 2662 #define PERI_ECC_ADDR_PRESENT 1u 2663 /* Clock control functionality present ('0': no, '1': yes) */ 2664 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u 2665 /* Slave present (0:No, 1:Yes) */ 2666 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL0_PRESENT 1u 2667 /* Slave present (0:No, 1:Yes) */ 2668 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL1_PRESENT 1u 2669 /* Slave present (0:No, 1:Yes) */ 2670 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL2_PRESENT 0u 2671 /* Slave present (0:No, 1:Yes) */ 2672 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL3_PRESENT 0u 2673 /* Slave present (0:No, 1:Yes) */ 2674 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL4_PRESENT 0u 2675 /* Slave present (0:No, 1:Yes) */ 2676 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL5_PRESENT 0u 2677 /* Slave present (0:No, 1:Yes) */ 2678 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL6_PRESENT 0u 2679 /* Slave present (0:No, 1:Yes) */ 2680 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL7_PRESENT 0u 2681 /* Slave present (0:No, 1:Yes) */ 2682 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL8_PRESENT 0u 2683 /* Slave present (0:No, 1:Yes) */ 2684 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL9_PRESENT 0u 2685 /* Slave present (0:No, 1:Yes) */ 2686 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL10_PRESENT 0u 2687 /* Slave present (0:No, 1:Yes) */ 2688 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL11_PRESENT 0u 2689 /* Slave present (0:No, 1:Yes) */ 2690 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL12_PRESENT 0u 2691 /* Slave present (0:No, 1:Yes) */ 2692 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL13_PRESENT 0u 2693 /* Slave present (0:No, 1:Yes) */ 2694 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL14_PRESENT 0u 2695 /* Slave present (0:No, 1:Yes) */ 2696 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL15_PRESENT 0u 2697 /* Clock control functionality present ('0': no, '1': yes) */ 2698 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u 2699 /* Slave present (0:No, 1:Yes) */ 2700 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL0_PRESENT 1u 2701 /* Slave present (0:No, 1:Yes) */ 2702 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL1_PRESENT 0u 2703 /* Slave present (0:No, 1:Yes) */ 2704 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL2_PRESENT 0u 2705 /* Slave present (0:No, 1:Yes) */ 2706 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL3_PRESENT 0u 2707 /* Slave present (0:No, 1:Yes) */ 2708 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL4_PRESENT 0u 2709 /* Slave present (0:No, 1:Yes) */ 2710 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL5_PRESENT 0u 2711 /* Slave present (0:No, 1:Yes) */ 2712 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL6_PRESENT 0u 2713 /* Slave present (0:No, 1:Yes) */ 2714 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL7_PRESENT 0u 2715 /* Slave present (0:No, 1:Yes) */ 2716 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL8_PRESENT 0u 2717 /* Slave present (0:No, 1:Yes) */ 2718 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL9_PRESENT 0u 2719 /* Slave present (0:No, 1:Yes) */ 2720 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL10_PRESENT 0u 2721 /* Slave present (0:No, 1:Yes) */ 2722 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL11_PRESENT 0u 2723 /* Slave present (0:No, 1:Yes) */ 2724 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL12_PRESENT 0u 2725 /* Slave present (0:No, 1:Yes) */ 2726 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL13_PRESENT 0u 2727 /* Slave present (0:No, 1:Yes) */ 2728 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL14_PRESENT 0u 2729 /* Slave present (0:No, 1:Yes) */ 2730 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL15_PRESENT 0u 2731 /* Clock control functionality present ('0': no, '1': yes) */ 2732 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u 2733 /* Slave present (0:No, 1:Yes) */ 2734 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL0_PRESENT 1u 2735 /* Slave present (0:No, 1:Yes) */ 2736 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL1_PRESENT 1u 2737 /* Slave present (0:No, 1:Yes) */ 2738 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL2_PRESENT 1u 2739 /* Slave present (0:No, 1:Yes) */ 2740 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL3_PRESENT 1u 2741 /* Slave present (0:No, 1:Yes) */ 2742 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL4_PRESENT 1u 2743 /* Slave present (0:No, 1:Yes) */ 2744 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL5_PRESENT 1u 2745 /* Slave present (0:No, 1:Yes) */ 2746 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL6_PRESENT 1u 2747 /* Slave present (0:No, 1:Yes) */ 2748 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL7_PRESENT 1u 2749 /* Slave present (0:No, 1:Yes) */ 2750 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL8_PRESENT 1u 2751 /* Slave present (0:No, 1:Yes) */ 2752 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL9_PRESENT 1u 2753 /* Slave present (0:No, 1:Yes) */ 2754 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL10_PRESENT 1u 2755 /* Slave present (0:No, 1:Yes) */ 2756 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL11_PRESENT 1u 2757 /* Slave present (0:No, 1:Yes) */ 2758 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL12_PRESENT 0u 2759 /* Slave present (0:No, 1:Yes) */ 2760 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL13_PRESENT 0u 2761 /* Slave present (0:No, 1:Yes) */ 2762 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL14_PRESENT 0u 2763 /* Slave present (0:No, 1:Yes) */ 2764 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL15_PRESENT 0u 2765 /* Clock control functionality present ('0': no, '1': yes) */ 2766 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 2767 /* Slave present (0:No, 1:Yes) */ 2768 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL0_PRESENT 1u 2769 /* Slave present (0:No, 1:Yes) */ 2770 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL1_PRESENT 1u 2771 /* Slave present (0:No, 1:Yes) */ 2772 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL2_PRESENT 1u 2773 /* Slave present (0:No, 1:Yes) */ 2774 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL3_PRESENT 1u 2775 /* Slave present (0:No, 1:Yes) */ 2776 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL4_PRESENT 1u 2777 /* Slave present (0:No, 1:Yes) */ 2778 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL5_PRESENT 0u 2779 /* Slave present (0:No, 1:Yes) */ 2780 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL6_PRESENT 0u 2781 /* Slave present (0:No, 1:Yes) */ 2782 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL7_PRESENT 0u 2783 /* Slave present (0:No, 1:Yes) */ 2784 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL8_PRESENT 0u 2785 /* Slave present (0:No, 1:Yes) */ 2786 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL9_PRESENT 0u 2787 /* Slave present (0:No, 1:Yes) */ 2788 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL10_PRESENT 0u 2789 /* Slave present (0:No, 1:Yes) */ 2790 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL11_PRESENT 0u 2791 /* Slave present (0:No, 1:Yes) */ 2792 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL12_PRESENT 0u 2793 /* Slave present (0:No, 1:Yes) */ 2794 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL13_PRESENT 0u 2795 /* Slave present (0:No, 1:Yes) */ 2796 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL14_PRESENT 0u 2797 /* Slave present (0:No, 1:Yes) */ 2798 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL15_PRESENT 0u 2799 /* Clock control functionality present ('0': no, '1': yes) */ 2800 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u 2801 /* Slave present (0:No, 1:Yes) */ 2802 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL0_PRESENT 0u 2803 /* Slave present (0:No, 1:Yes) */ 2804 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL1_PRESENT 0u 2805 /* Slave present (0:No, 1:Yes) */ 2806 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL2_PRESENT 0u 2807 /* Slave present (0:No, 1:Yes) */ 2808 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL3_PRESENT 0u 2809 /* Slave present (0:No, 1:Yes) */ 2810 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL4_PRESENT 0u 2811 /* Slave present (0:No, 1:Yes) */ 2812 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL5_PRESENT 0u 2813 /* Slave present (0:No, 1:Yes) */ 2814 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL6_PRESENT 0u 2815 /* Slave present (0:No, 1:Yes) */ 2816 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL7_PRESENT 0u 2817 /* Slave present (0:No, 1:Yes) */ 2818 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL8_PRESENT 0u 2819 /* Slave present (0:No, 1:Yes) */ 2820 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL9_PRESENT 0u 2821 /* Slave present (0:No, 1:Yes) */ 2822 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL10_PRESENT 0u 2823 /* Slave present (0:No, 1:Yes) */ 2824 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL11_PRESENT 0u 2825 /* Slave present (0:No, 1:Yes) */ 2826 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL12_PRESENT 0u 2827 /* Slave present (0:No, 1:Yes) */ 2828 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL13_PRESENT 0u 2829 /* Slave present (0:No, 1:Yes) */ 2830 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL14_PRESENT 0u 2831 /* Slave present (0:No, 1:Yes) */ 2832 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL15_PRESENT 0u 2833 /* Clock control functionality present ('0': no, '1': yes) */ 2834 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 2835 /* Slave present (0:No, 1:Yes) */ 2836 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL0_PRESENT 1u 2837 /* Slave present (0:No, 1:Yes) */ 2838 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL1_PRESENT 1u 2839 /* Slave present (0:No, 1:Yes) */ 2840 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL2_PRESENT 1u 2841 /* Slave present (0:No, 1:Yes) */ 2842 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL3_PRESENT 0u 2843 /* Slave present (0:No, 1:Yes) */ 2844 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL4_PRESENT 0u 2845 /* Slave present (0:No, 1:Yes) */ 2846 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL5_PRESENT 0u 2847 /* Slave present (0:No, 1:Yes) */ 2848 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL6_PRESENT 0u 2849 /* Slave present (0:No, 1:Yes) */ 2850 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL7_PRESENT 0u 2851 /* Slave present (0:No, 1:Yes) */ 2852 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL8_PRESENT 0u 2853 /* Slave present (0:No, 1:Yes) */ 2854 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL9_PRESENT 0u 2855 /* Slave present (0:No, 1:Yes) */ 2856 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL10_PRESENT 0u 2857 /* Slave present (0:No, 1:Yes) */ 2858 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL11_PRESENT 0u 2859 /* Slave present (0:No, 1:Yes) */ 2860 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL12_PRESENT 0u 2861 /* Slave present (0:No, 1:Yes) */ 2862 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL13_PRESENT 0u 2863 /* Slave present (0:No, 1:Yes) */ 2864 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL14_PRESENT 0u 2865 /* Slave present (0:No, 1:Yes) */ 2866 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL15_PRESENT 0u 2867 /* Clock control functionality present ('0': no, '1': yes) */ 2868 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 2869 /* Slave present (0:No, 1:Yes) */ 2870 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL0_PRESENT 1u 2871 /* Slave present (0:No, 1:Yes) */ 2872 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL1_PRESENT 1u 2873 /* Slave present (0:No, 1:Yes) */ 2874 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL2_PRESENT 1u 2875 /* Slave present (0:No, 1:Yes) */ 2876 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL3_PRESENT 1u 2877 /* Slave present (0:No, 1:Yes) */ 2878 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL4_PRESENT 1u 2879 /* Slave present (0:No, 1:Yes) */ 2880 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL5_PRESENT 1u 2881 /* Slave present (0:No, 1:Yes) */ 2882 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL6_PRESENT 1u 2883 /* Slave present (0:No, 1:Yes) */ 2884 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL7_PRESENT 1u 2885 /* Slave present (0:No, 1:Yes) */ 2886 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL8_PRESENT 0u 2887 /* Slave present (0:No, 1:Yes) */ 2888 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL9_PRESENT 0u 2889 /* Slave present (0:No, 1:Yes) */ 2890 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL10_PRESENT 0u 2891 /* Slave present (0:No, 1:Yes) */ 2892 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL11_PRESENT 0u 2893 /* Slave present (0:No, 1:Yes) */ 2894 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL12_PRESENT 0u 2895 /* Slave present (0:No, 1:Yes) */ 2896 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL13_PRESENT 0u 2897 /* Slave present (0:No, 1:Yes) */ 2898 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL14_PRESENT 0u 2899 /* Slave present (0:No, 1:Yes) */ 2900 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL15_PRESENT 0u 2901 /* Clock control functionality present ('0': no, '1': yes) */ 2902 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u 2903 /* Slave present (0:No, 1:Yes) */ 2904 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL0_PRESENT 0u 2905 /* Slave present (0:No, 1:Yes) */ 2906 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL1_PRESENT 0u 2907 /* Slave present (0:No, 1:Yes) */ 2908 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL2_PRESENT 0u 2909 /* Slave present (0:No, 1:Yes) */ 2910 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL3_PRESENT 0u 2911 /* Slave present (0:No, 1:Yes) */ 2912 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL4_PRESENT 0u 2913 /* Slave present (0:No, 1:Yes) */ 2914 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL5_PRESENT 0u 2915 /* Slave present (0:No, 1:Yes) */ 2916 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL6_PRESENT 0u 2917 /* Slave present (0:No, 1:Yes) */ 2918 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL7_PRESENT 0u 2919 /* Slave present (0:No, 1:Yes) */ 2920 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL8_PRESENT 0u 2921 /* Slave present (0:No, 1:Yes) */ 2922 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL9_PRESENT 0u 2923 /* Slave present (0:No, 1:Yes) */ 2924 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL10_PRESENT 0u 2925 /* Slave present (0:No, 1:Yes) */ 2926 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL11_PRESENT 0u 2927 /* Slave present (0:No, 1:Yes) */ 2928 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL12_PRESENT 0u 2929 /* Slave present (0:No, 1:Yes) */ 2930 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL13_PRESENT 0u 2931 /* Slave present (0:No, 1:Yes) */ 2932 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL14_PRESENT 0u 2933 /* Slave present (0:No, 1:Yes) */ 2934 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL15_PRESENT 0u 2935 /* Clock control functionality present ('0': no, '1': yes) */ 2936 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u 2937 /* Slave present (0:No, 1:Yes) */ 2938 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL0_PRESENT 0u 2939 /* Slave present (0:No, 1:Yes) */ 2940 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL1_PRESENT 0u 2941 /* Slave present (0:No, 1:Yes) */ 2942 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL2_PRESENT 0u 2943 /* Slave present (0:No, 1:Yes) */ 2944 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL3_PRESENT 0u 2945 /* Slave present (0:No, 1:Yes) */ 2946 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL4_PRESENT 0u 2947 /* Slave present (0:No, 1:Yes) */ 2948 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL5_PRESENT 0u 2949 /* Slave present (0:No, 1:Yes) */ 2950 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL6_PRESENT 0u 2951 /* Slave present (0:No, 1:Yes) */ 2952 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL7_PRESENT 0u 2953 /* Slave present (0:No, 1:Yes) */ 2954 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL8_PRESENT 0u 2955 /* Slave present (0:No, 1:Yes) */ 2956 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL9_PRESENT 0u 2957 /* Slave present (0:No, 1:Yes) */ 2958 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL10_PRESENT 0u 2959 /* Slave present (0:No, 1:Yes) */ 2960 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL11_PRESENT 0u 2961 /* Slave present (0:No, 1:Yes) */ 2962 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL12_PRESENT 0u 2963 /* Slave present (0:No, 1:Yes) */ 2964 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL13_PRESENT 0u 2965 /* Slave present (0:No, 1:Yes) */ 2966 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL14_PRESENT 0u 2967 /* Slave present (0:No, 1:Yes) */ 2968 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL15_PRESENT 0u 2969 /* Clock control functionality present ('0': no, '1': yes) */ 2970 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 2971 /* Slave present (0:No, 1:Yes) */ 2972 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL0_PRESENT 1u 2973 /* Slave present (0:No, 1:Yes) */ 2974 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL1_PRESENT 0u 2975 /* Slave present (0:No, 1:Yes) */ 2976 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL2_PRESENT 0u 2977 /* Slave present (0:No, 1:Yes) */ 2978 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL3_PRESENT 0u 2979 /* Slave present (0:No, 1:Yes) */ 2980 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL4_PRESENT 0u 2981 /* Slave present (0:No, 1:Yes) */ 2982 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL5_PRESENT 0u 2983 /* Slave present (0:No, 1:Yes) */ 2984 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL6_PRESENT 0u 2985 /* Slave present (0:No, 1:Yes) */ 2986 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL7_PRESENT 0u 2987 /* Slave present (0:No, 1:Yes) */ 2988 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL8_PRESENT 0u 2989 /* Slave present (0:No, 1:Yes) */ 2990 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL9_PRESENT 0u 2991 /* Slave present (0:No, 1:Yes) */ 2992 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL10_PRESENT 0u 2993 /* Slave present (0:No, 1:Yes) */ 2994 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL11_PRESENT 0u 2995 /* Slave present (0:No, 1:Yes) */ 2996 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL12_PRESENT 0u 2997 /* Slave present (0:No, 1:Yes) */ 2998 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL13_PRESENT 0u 2999 /* Slave present (0:No, 1:Yes) */ 3000 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL14_PRESENT 0u 3001 /* Slave present (0:No, 1:Yes) */ 3002 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL15_PRESENT 0u 3003 /* Clock control functionality present ('0': no, '1': yes) */ 3004 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u 3005 /* Slave present (0:No, 1:Yes) */ 3006 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL0_PRESENT 0u 3007 /* Slave present (0:No, 1:Yes) */ 3008 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL1_PRESENT 0u 3009 /* Slave present (0:No, 1:Yes) */ 3010 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL2_PRESENT 0u 3011 /* Slave present (0:No, 1:Yes) */ 3012 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL3_PRESENT 0u 3013 /* Slave present (0:No, 1:Yes) */ 3014 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL4_PRESENT 0u 3015 /* Slave present (0:No, 1:Yes) */ 3016 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL5_PRESENT 0u 3017 /* Slave present (0:No, 1:Yes) */ 3018 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL6_PRESENT 0u 3019 /* Slave present (0:No, 1:Yes) */ 3020 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL7_PRESENT 0u 3021 /* Slave present (0:No, 1:Yes) */ 3022 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL8_PRESENT 0u 3023 /* Slave present (0:No, 1:Yes) */ 3024 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL9_PRESENT 0u 3025 /* Slave present (0:No, 1:Yes) */ 3026 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL10_PRESENT 0u 3027 /* Slave present (0:No, 1:Yes) */ 3028 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL11_PRESENT 0u 3029 /* Slave present (0:No, 1:Yes) */ 3030 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL12_PRESENT 0u 3031 /* Slave present (0:No, 1:Yes) */ 3032 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL13_PRESENT 0u 3033 /* Slave present (0:No, 1:Yes) */ 3034 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL14_PRESENT 0u 3035 /* Slave present (0:No, 1:Yes) */ 3036 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL15_PRESENT 0u 3037 /* Clock control functionality present ('0': no, '1': yes) */ 3038 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u 3039 /* Slave present (0:No, 1:Yes) */ 3040 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL0_PRESENT 0u 3041 /* Slave present (0:No, 1:Yes) */ 3042 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL1_PRESENT 0u 3043 /* Slave present (0:No, 1:Yes) */ 3044 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL2_PRESENT 0u 3045 /* Slave present (0:No, 1:Yes) */ 3046 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL3_PRESENT 0u 3047 /* Slave present (0:No, 1:Yes) */ 3048 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL4_PRESENT 0u 3049 /* Slave present (0:No, 1:Yes) */ 3050 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL5_PRESENT 0u 3051 /* Slave present (0:No, 1:Yes) */ 3052 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL6_PRESENT 0u 3053 /* Slave present (0:No, 1:Yes) */ 3054 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL7_PRESENT 0u 3055 /* Slave present (0:No, 1:Yes) */ 3056 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL8_PRESENT 0u 3057 /* Slave present (0:No, 1:Yes) */ 3058 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL9_PRESENT 0u 3059 /* Slave present (0:No, 1:Yes) */ 3060 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL10_PRESENT 0u 3061 /* Slave present (0:No, 1:Yes) */ 3062 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL11_PRESENT 0u 3063 /* Slave present (0:No, 1:Yes) */ 3064 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL12_PRESENT 0u 3065 /* Slave present (0:No, 1:Yes) */ 3066 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL13_PRESENT 0u 3067 /* Slave present (0:No, 1:Yes) */ 3068 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL14_PRESENT 0u 3069 /* Slave present (0:No, 1:Yes) */ 3070 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL15_PRESENT 0u 3071 /* Clock control functionality present ('0': no, '1': yes) */ 3072 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u 3073 /* Slave present (0:No, 1:Yes) */ 3074 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL0_PRESENT 0u 3075 /* Slave present (0:No, 1:Yes) */ 3076 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL1_PRESENT 0u 3077 /* Slave present (0:No, 1:Yes) */ 3078 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL2_PRESENT 0u 3079 /* Slave present (0:No, 1:Yes) */ 3080 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL3_PRESENT 0u 3081 /* Slave present (0:No, 1:Yes) */ 3082 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL4_PRESENT 0u 3083 /* Slave present (0:No, 1:Yes) */ 3084 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL5_PRESENT 0u 3085 /* Slave present (0:No, 1:Yes) */ 3086 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL6_PRESENT 0u 3087 /* Slave present (0:No, 1:Yes) */ 3088 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL7_PRESENT 0u 3089 /* Slave present (0:No, 1:Yes) */ 3090 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL8_PRESENT 0u 3091 /* Slave present (0:No, 1:Yes) */ 3092 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL9_PRESENT 0u 3093 /* Slave present (0:No, 1:Yes) */ 3094 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL10_PRESENT 0u 3095 /* Slave present (0:No, 1:Yes) */ 3096 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL11_PRESENT 0u 3097 /* Slave present (0:No, 1:Yes) */ 3098 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL12_PRESENT 0u 3099 /* Slave present (0:No, 1:Yes) */ 3100 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL13_PRESENT 0u 3101 /* Slave present (0:No, 1:Yes) */ 3102 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL14_PRESENT 0u 3103 /* Slave present (0:No, 1:Yes) */ 3104 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL15_PRESENT 0u 3105 /* Clock control functionality present ('0': no, '1': yes) */ 3106 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u 3107 /* Slave present (0:No, 1:Yes) */ 3108 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL0_PRESENT 0u 3109 /* Slave present (0:No, 1:Yes) */ 3110 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL1_PRESENT 0u 3111 /* Slave present (0:No, 1:Yes) */ 3112 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL2_PRESENT 0u 3113 /* Slave present (0:No, 1:Yes) */ 3114 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL3_PRESENT 0u 3115 /* Slave present (0:No, 1:Yes) */ 3116 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL4_PRESENT 0u 3117 /* Slave present (0:No, 1:Yes) */ 3118 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL5_PRESENT 0u 3119 /* Slave present (0:No, 1:Yes) */ 3120 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL6_PRESENT 0u 3121 /* Slave present (0:No, 1:Yes) */ 3122 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL7_PRESENT 0u 3123 /* Slave present (0:No, 1:Yes) */ 3124 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL8_PRESENT 0u 3125 /* Slave present (0:No, 1:Yes) */ 3126 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL9_PRESENT 0u 3127 /* Slave present (0:No, 1:Yes) */ 3128 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL10_PRESENT 0u 3129 /* Slave present (0:No, 1:Yes) */ 3130 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL11_PRESENT 0u 3131 /* Slave present (0:No, 1:Yes) */ 3132 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL12_PRESENT 0u 3133 /* Slave present (0:No, 1:Yes) */ 3134 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL13_PRESENT 0u 3135 /* Slave present (0:No, 1:Yes) */ 3136 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL14_PRESENT 0u 3137 /* Slave present (0:No, 1:Yes) */ 3138 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL15_PRESENT 0u 3139 /* Clock control functionality present ('0': no, '1': yes) */ 3140 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u 3141 /* Slave present (0:No, 1:Yes) */ 3142 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL0_PRESENT 0u 3143 /* Slave present (0:No, 1:Yes) */ 3144 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL1_PRESENT 0u 3145 /* Slave present (0:No, 1:Yes) */ 3146 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL2_PRESENT 0u 3147 /* Slave present (0:No, 1:Yes) */ 3148 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL3_PRESENT 0u 3149 /* Slave present (0:No, 1:Yes) */ 3150 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL4_PRESENT 0u 3151 /* Slave present (0:No, 1:Yes) */ 3152 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL5_PRESENT 0u 3153 /* Slave present (0:No, 1:Yes) */ 3154 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL6_PRESENT 0u 3155 /* Slave present (0:No, 1:Yes) */ 3156 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL7_PRESENT 0u 3157 /* Slave present (0:No, 1:Yes) */ 3158 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL8_PRESENT 0u 3159 /* Slave present (0:No, 1:Yes) */ 3160 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL9_PRESENT 0u 3161 /* Slave present (0:No, 1:Yes) */ 3162 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL10_PRESENT 0u 3163 /* Slave present (0:No, 1:Yes) */ 3164 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL11_PRESENT 0u 3165 /* Slave present (0:No, 1:Yes) */ 3166 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL12_PRESENT 0u 3167 /* Slave present (0:No, 1:Yes) */ 3168 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL13_PRESENT 0u 3169 /* Slave present (0:No, 1:Yes) */ 3170 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL14_PRESENT 0u 3171 /* Slave present (0:No, 1:Yes) */ 3172 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL15_PRESENT 0u 3173 /* Clock control functionality present ('0': no, '1': yes) */ 3174 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u 3175 /* Slave present (0:No, 1:Yes) */ 3176 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL0_PRESENT 0u 3177 /* Slave present (0:No, 1:Yes) */ 3178 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL1_PRESENT 0u 3179 /* Slave present (0:No, 1:Yes) */ 3180 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL2_PRESENT 0u 3181 /* Slave present (0:No, 1:Yes) */ 3182 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL3_PRESENT 0u 3183 /* Slave present (0:No, 1:Yes) */ 3184 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL4_PRESENT 0u 3185 /* Slave present (0:No, 1:Yes) */ 3186 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL5_PRESENT 0u 3187 /* Slave present (0:No, 1:Yes) */ 3188 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL6_PRESENT 0u 3189 /* Slave present (0:No, 1:Yes) */ 3190 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL7_PRESENT 0u 3191 /* Slave present (0:No, 1:Yes) */ 3192 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL8_PRESENT 0u 3193 /* Slave present (0:No, 1:Yes) */ 3194 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL9_PRESENT 0u 3195 /* Slave present (0:No, 1:Yes) */ 3196 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL10_PRESENT 0u 3197 /* Slave present (0:No, 1:Yes) */ 3198 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL11_PRESENT 0u 3199 /* Slave present (0:No, 1:Yes) */ 3200 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL12_PRESENT 0u 3201 /* Slave present (0:No, 1:Yes) */ 3202 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL13_PRESENT 0u 3203 /* Slave present (0:No, 1:Yes) */ 3204 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL14_PRESENT 0u 3205 /* Slave present (0:No, 1:Yes) */ 3206 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL15_PRESENT 0u 3207 /* Number of programmable clocks (outputs) */ 3208 #define PERI_CLOCK_NR 110u 3209 /* Number of 8.0 dividers */ 3210 #define PERI_DIV_8_NR 32u 3211 /* Number of 16.0 dividers */ 3212 #define PERI_DIV_16_NR 16u 3213 /* Number of 16.5 (fractional) dividers */ 3214 #define PERI_DIV_16_5_NR 0u 3215 /* Number of 24.5 (fractional) dividers */ 3216 #define PERI_DIV_24_5_NR 8u 3217 /* Divider number width: max(1,roundup(log2(max(DIV_*_NR))) */ 3218 #define PERI_DIV_ADDR_WIDTH 5u 3219 /* Timeout functionality present ('0': no, '1': yes) */ 3220 #define PERI_TIMEOUT_PRESENT 1u 3221 /* Trigger module present (0=No, 1=Yes) */ 3222 #define PERI_TR 1u 3223 /* Number of trigger groups */ 3224 #define PERI_TR_GROUP_NR 11u 3225 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 3226 #define PERI_TR_GROUP_NR0_TR_GROUP_TR_MANIPULATION_PRESENT 1u 3227 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 3228 #define PERI_TR_GROUP_NR1_TR_GROUP_TR_MANIPULATION_PRESENT 1u 3229 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 3230 #define PERI_TR_GROUP_NR2_TR_GROUP_TR_MANIPULATION_PRESENT 1u 3231 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 3232 #define PERI_TR_GROUP_NR3_TR_GROUP_TR_MANIPULATION_PRESENT 1u 3233 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 3234 #define PERI_TR_GROUP_NR4_TR_GROUP_TR_MANIPULATION_PRESENT 1u 3235 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 3236 #define PERI_TR_GROUP_NR5_TR_GROUP_TR_MANIPULATION_PRESENT 1u 3237 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 3238 #define PERI_TR_GROUP_NR6_TR_GROUP_TR_MANIPULATION_PRESENT 1u 3239 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 3240 #define PERI_TR_GROUP_NR7_TR_GROUP_TR_MANIPULATION_PRESENT 1u 3241 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 3242 #define PERI_TR_GROUP_NR8_TR_GROUP_TR_MANIPULATION_PRESENT 1u 3243 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 3244 #define PERI_TR_GROUP_NR9_TR_GROUP_TR_MANIPULATION_PRESENT 0u 3245 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 3246 #define PERI_TR_GROUP_NR10_TR_GROUP_TR_MANIPULATION_PRESENT 0u 3247 /* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 3248 #define PERI_TR_1TO1_GROUP_NR0_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 3249 /* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 3250 #define PERI_TR_1TO1_GROUP_NR1_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 3251 /* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 3252 #define PERI_TR_1TO1_GROUP_NR2_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 3253 /* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 3254 #define PERI_TR_1TO1_GROUP_NR3_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 3255 /* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 3256 #define PERI_TR_1TO1_GROUP_NR4_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 3257 /* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 3258 #define PERI_TR_1TO1_GROUP_NR5_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 3259 /* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 3260 #define PERI_TR_1TO1_GROUP_NR6_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 3261 /* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 3262 #define PERI_TR_1TO1_GROUP_NR7_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 3263 /* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 3264 #define PERI_TR_1TO1_GROUP_NR8_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 3265 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 3266 #define PERI_MASTER_WIDTH 8u 3267 /* DeepSleep support ('0':no, '1': yes) */ 3268 #define SCB0_DEEPSLEEP 1u 3269 /* I2C master support? ('0': no, '1': yes) */ 3270 #define SCB0_I2C_M 1u 3271 /* I2C slave support? ('0': no, '1': yes) */ 3272 #define SCB0_I2C_S 1u 3273 /* I2C glitch filters present? ('0': no, '1': yes) */ 3274 #define SCB0_I2C_GLITCH 1u 3275 /* I2C slave with EC? (I2C_S & I2C_EC) */ 3276 #define SCB0_I2C_S_EC 1u 3277 /* I2C support? (I2C_M | I2C_S) */ 3278 #define SCB0_I2C 1u 3279 /* I2C externally clocked support? ('0': no, '1': yes) */ 3280 #define SCB0_I2C_EC 1u 3281 /* I2C master and slave support? (I2C_M & I2C_S) */ 3282 #define SCB0_I2C_M_S 1u 3283 /* SPI master support? ('0': no, '1': yes) */ 3284 #define SCB0_SPI_M 1u 3285 /* SPI slave support? ('0': no, '1': yes) */ 3286 #define SCB0_SPI_S 1u 3287 /* SPI slave with EC? (SPI_S & SPI_EC) */ 3288 #define SCB0_SPI_S_EC 1u 3289 /* SPI support? (SPI_M | SPI_S) */ 3290 #define SCB0_SPI 1u 3291 /* SPI externally clocked support? ('0': no, '1': yes) */ 3292 #define SCB0_SPI_EC 1u 3293 /* Externally clocked support? ('0': no, '1': yes) */ 3294 #define SCB0_EC 1u 3295 /* UART support? ('0': no, '1': yes) */ 3296 #define SCB0_UART 1u 3297 /* SPI or UART (SPI | UART) */ 3298 #define SCB0_SPI_UART 1u 3299 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 3300 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 3301 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 3302 #define SCB0_EZ_DATA_NR 256u 3303 /* Command/response mode support? ('0': no, '1': yes) */ 3304 #define SCB0_CMD_RESP 1u 3305 /* EZ mode support? ('0': no, '1': yes) */ 3306 #define SCB0_EZ 1u 3307 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 3308 #define SCB0_EZ_CMD_RESP 1u 3309 /* I2C slave with EZ mode (I2C_S & EZ) */ 3310 #define SCB0_I2C_S_EZ 1u 3311 /* SPI slave with EZ mode (SPI_S & EZ) */ 3312 #define SCB0_SPI_S_EZ 1u 3313 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 3314 #define SCB0_MASTER_WIDTH 8u 3315 /* Number of used spi_select signals (max 4) */ 3316 #define SCB0_CHIP_TOP_SPI_SEL_NR 4u 3317 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 3318 #define SCB0_CHIP_TOP_I2C_FAST_PLUS 1u 3319 /* DeepSleep support ('0':no, '1': yes) */ 3320 #define SCB1_DEEPSLEEP 0u 3321 /* I2C master support? ('0': no, '1': yes) */ 3322 #define SCB1_I2C_M 1u 3323 /* I2C slave support? ('0': no, '1': yes) */ 3324 #define SCB1_I2C_S 1u 3325 /* I2C glitch filters present? ('0': no, '1': yes) */ 3326 #define SCB1_I2C_GLITCH 1u 3327 /* I2C slave with EC? (I2C_S & I2C_EC) */ 3328 #define SCB1_I2C_S_EC 0u 3329 /* I2C support? (I2C_M | I2C_S) */ 3330 #define SCB1_I2C 1u 3331 /* I2C externally clocked support? ('0': no, '1': yes) */ 3332 #define SCB1_I2C_EC 0u 3333 /* I2C master and slave support? (I2C_M & I2C_S) */ 3334 #define SCB1_I2C_M_S 1u 3335 /* SPI master support? ('0': no, '1': yes) */ 3336 #define SCB1_SPI_M 1u 3337 /* SPI slave support? ('0': no, '1': yes) */ 3338 #define SCB1_SPI_S 1u 3339 /* SPI slave with EC? (SPI_S & SPI_EC) */ 3340 #define SCB1_SPI_S_EC 1u 3341 /* SPI support? (SPI_M | SPI_S) */ 3342 #define SCB1_SPI 1u 3343 /* SPI externally clocked support? ('0': no, '1': yes) */ 3344 #define SCB1_SPI_EC 1u 3345 /* Externally clocked support? ('0': no, '1': yes) */ 3346 #define SCB1_EC 1u 3347 /* UART support? ('0': no, '1': yes) */ 3348 #define SCB1_UART 1u 3349 /* SPI or UART (SPI | UART) */ 3350 #define SCB1_SPI_UART 1u 3351 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 3352 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 3353 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 3354 #define SCB1_EZ_DATA_NR 256u 3355 /* Command/response mode support? ('0': no, '1': yes) */ 3356 #define SCB1_CMD_RESP 0u 3357 /* EZ mode support? ('0': no, '1': yes) */ 3358 #define SCB1_EZ 1u 3359 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 3360 #define SCB1_EZ_CMD_RESP 1u 3361 /* I2C slave with EZ mode (I2C_S & EZ) */ 3362 #define SCB1_I2C_S_EZ 1u 3363 /* SPI slave with EZ mode (SPI_S & EZ) */ 3364 #define SCB1_SPI_S_EZ 1u 3365 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 3366 #define SCB1_MASTER_WIDTH 8u 3367 /* Number of used spi_select signals (max 4) */ 3368 #define SCB1_CHIP_TOP_SPI_SEL_NR 4u 3369 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 3370 #define SCB1_CHIP_TOP_I2C_FAST_PLUS 1u 3371 /* DeepSleep support ('0':no, '1': yes) */ 3372 #define SCB2_DEEPSLEEP 0u 3373 /* I2C master support? ('0': no, '1': yes) */ 3374 #define SCB2_I2C_M 1u 3375 /* I2C slave support? ('0': no, '1': yes) */ 3376 #define SCB2_I2C_S 1u 3377 /* I2C glitch filters present? ('0': no, '1': yes) */ 3378 #define SCB2_I2C_GLITCH 1u 3379 /* I2C slave with EC? (I2C_S & I2C_EC) */ 3380 #define SCB2_I2C_S_EC 0u 3381 /* I2C support? (I2C_M | I2C_S) */ 3382 #define SCB2_I2C 1u 3383 /* I2C externally clocked support? ('0': no, '1': yes) */ 3384 #define SCB2_I2C_EC 0u 3385 /* I2C master and slave support? (I2C_M & I2C_S) */ 3386 #define SCB2_I2C_M_S 1u 3387 /* SPI master support? ('0': no, '1': yes) */ 3388 #define SCB2_SPI_M 1u 3389 /* SPI slave support? ('0': no, '1': yes) */ 3390 #define SCB2_SPI_S 1u 3391 /* SPI slave with EC? (SPI_S & SPI_EC) */ 3392 #define SCB2_SPI_S_EC 1u 3393 /* SPI support? (SPI_M | SPI_S) */ 3394 #define SCB2_SPI 1u 3395 /* SPI externally clocked support? ('0': no, '1': yes) */ 3396 #define SCB2_SPI_EC 1u 3397 /* Externally clocked support? ('0': no, '1': yes) */ 3398 #define SCB2_EC 1u 3399 /* UART support? ('0': no, '1': yes) */ 3400 #define SCB2_UART 1u 3401 /* SPI or UART (SPI | UART) */ 3402 #define SCB2_SPI_UART 1u 3403 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 3404 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 3405 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 3406 #define SCB2_EZ_DATA_NR 256u 3407 /* Command/response mode support? ('0': no, '1': yes) */ 3408 #define SCB2_CMD_RESP 0u 3409 /* EZ mode support? ('0': no, '1': yes) */ 3410 #define SCB2_EZ 1u 3411 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 3412 #define SCB2_EZ_CMD_RESP 1u 3413 /* I2C slave with EZ mode (I2C_S & EZ) */ 3414 #define SCB2_I2C_S_EZ 1u 3415 /* SPI slave with EZ mode (SPI_S & EZ) */ 3416 #define SCB2_SPI_S_EZ 1u 3417 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 3418 #define SCB2_MASTER_WIDTH 8u 3419 /* Number of used spi_select signals (max 4) */ 3420 #define SCB2_CHIP_TOP_SPI_SEL_NR 4u 3421 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 3422 #define SCB2_CHIP_TOP_I2C_FAST_PLUS 1u 3423 /* DeepSleep support ('0':no, '1': yes) */ 3424 #define SCB3_DEEPSLEEP 0u 3425 /* I2C master support? ('0': no, '1': yes) */ 3426 #define SCB3_I2C_M 1u 3427 /* I2C slave support? ('0': no, '1': yes) */ 3428 #define SCB3_I2C_S 1u 3429 /* I2C glitch filters present? ('0': no, '1': yes) */ 3430 #define SCB3_I2C_GLITCH 1u 3431 /* I2C slave with EC? (I2C_S & I2C_EC) */ 3432 #define SCB3_I2C_S_EC 0u 3433 /* I2C support? (I2C_M | I2C_S) */ 3434 #define SCB3_I2C 1u 3435 /* I2C externally clocked support? ('0': no, '1': yes) */ 3436 #define SCB3_I2C_EC 0u 3437 /* I2C master and slave support? (I2C_M & I2C_S) */ 3438 #define SCB3_I2C_M_S 1u 3439 /* SPI master support? ('0': no, '1': yes) */ 3440 #define SCB3_SPI_M 1u 3441 /* SPI slave support? ('0': no, '1': yes) */ 3442 #define SCB3_SPI_S 1u 3443 /* SPI slave with EC? (SPI_S & SPI_EC) */ 3444 #define SCB3_SPI_S_EC 1u 3445 /* SPI support? (SPI_M | SPI_S) */ 3446 #define SCB3_SPI 1u 3447 /* SPI externally clocked support? ('0': no, '1': yes) */ 3448 #define SCB3_SPI_EC 1u 3449 /* Externally clocked support? ('0': no, '1': yes) */ 3450 #define SCB3_EC 1u 3451 /* UART support? ('0': no, '1': yes) */ 3452 #define SCB3_UART 1u 3453 /* SPI or UART (SPI | UART) */ 3454 #define SCB3_SPI_UART 1u 3455 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 3456 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 3457 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 3458 #define SCB3_EZ_DATA_NR 256u 3459 /* Command/response mode support? ('0': no, '1': yes) */ 3460 #define SCB3_CMD_RESP 0u 3461 /* EZ mode support? ('0': no, '1': yes) */ 3462 #define SCB3_EZ 1u 3463 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 3464 #define SCB3_EZ_CMD_RESP 1u 3465 /* I2C slave with EZ mode (I2C_S & EZ) */ 3466 #define SCB3_I2C_S_EZ 1u 3467 /* SPI slave with EZ mode (SPI_S & EZ) */ 3468 #define SCB3_SPI_S_EZ 1u 3469 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 3470 #define SCB3_MASTER_WIDTH 8u 3471 /* Number of used spi_select signals (max 4) */ 3472 #define SCB3_CHIP_TOP_SPI_SEL_NR 4u 3473 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 3474 #define SCB3_CHIP_TOP_I2C_FAST_PLUS 1u 3475 /* DeepSleep support ('0':no, '1': yes) */ 3476 #define SCB4_DEEPSLEEP 0u 3477 /* I2C master support? ('0': no, '1': yes) */ 3478 #define SCB4_I2C_M 1u 3479 /* I2C slave support? ('0': no, '1': yes) */ 3480 #define SCB4_I2C_S 1u 3481 /* I2C glitch filters present? ('0': no, '1': yes) */ 3482 #define SCB4_I2C_GLITCH 1u 3483 /* I2C slave with EC? (I2C_S & I2C_EC) */ 3484 #define SCB4_I2C_S_EC 0u 3485 /* I2C support? (I2C_M | I2C_S) */ 3486 #define SCB4_I2C 1u 3487 /* I2C externally clocked support? ('0': no, '1': yes) */ 3488 #define SCB4_I2C_EC 0u 3489 /* I2C master and slave support? (I2C_M & I2C_S) */ 3490 #define SCB4_I2C_M_S 1u 3491 /* SPI master support? ('0': no, '1': yes) */ 3492 #define SCB4_SPI_M 1u 3493 /* SPI slave support? ('0': no, '1': yes) */ 3494 #define SCB4_SPI_S 1u 3495 /* SPI slave with EC? (SPI_S & SPI_EC) */ 3496 #define SCB4_SPI_S_EC 1u 3497 /* SPI support? (SPI_M | SPI_S) */ 3498 #define SCB4_SPI 1u 3499 /* SPI externally clocked support? ('0': no, '1': yes) */ 3500 #define SCB4_SPI_EC 1u 3501 /* Externally clocked support? ('0': no, '1': yes) */ 3502 #define SCB4_EC 1u 3503 /* UART support? ('0': no, '1': yes) */ 3504 #define SCB4_UART 1u 3505 /* SPI or UART (SPI | UART) */ 3506 #define SCB4_SPI_UART 1u 3507 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 3508 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 3509 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 3510 #define SCB4_EZ_DATA_NR 256u 3511 /* Command/response mode support? ('0': no, '1': yes) */ 3512 #define SCB4_CMD_RESP 0u 3513 /* EZ mode support? ('0': no, '1': yes) */ 3514 #define SCB4_EZ 1u 3515 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 3516 #define SCB4_EZ_CMD_RESP 1u 3517 /* I2C slave with EZ mode (I2C_S & EZ) */ 3518 #define SCB4_I2C_S_EZ 1u 3519 /* SPI slave with EZ mode (SPI_S & EZ) */ 3520 #define SCB4_SPI_S_EZ 1u 3521 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 3522 #define SCB4_MASTER_WIDTH 8u 3523 /* Number of used spi_select signals (max 4) */ 3524 #define SCB4_CHIP_TOP_SPI_SEL_NR 4u 3525 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 3526 #define SCB4_CHIP_TOP_I2C_FAST_PLUS 1u 3527 /* DeepSleep support ('0':no, '1': yes) */ 3528 #define SCB5_DEEPSLEEP 0u 3529 /* I2C master support? ('0': no, '1': yes) */ 3530 #define SCB5_I2C_M 1u 3531 /* I2C slave support? ('0': no, '1': yes) */ 3532 #define SCB5_I2C_S 1u 3533 /* I2C glitch filters present? ('0': no, '1': yes) */ 3534 #define SCB5_I2C_GLITCH 1u 3535 /* I2C slave with EC? (I2C_S & I2C_EC) */ 3536 #define SCB5_I2C_S_EC 0u 3537 /* I2C support? (I2C_M | I2C_S) */ 3538 #define SCB5_I2C 1u 3539 /* I2C externally clocked support? ('0': no, '1': yes) */ 3540 #define SCB5_I2C_EC 0u 3541 /* I2C master and slave support? (I2C_M & I2C_S) */ 3542 #define SCB5_I2C_M_S 1u 3543 /* SPI master support? ('0': no, '1': yes) */ 3544 #define SCB5_SPI_M 1u 3545 /* SPI slave support? ('0': no, '1': yes) */ 3546 #define SCB5_SPI_S 1u 3547 /* SPI slave with EC? (SPI_S & SPI_EC) */ 3548 #define SCB5_SPI_S_EC 1u 3549 /* SPI support? (SPI_M | SPI_S) */ 3550 #define SCB5_SPI 1u 3551 /* SPI externally clocked support? ('0': no, '1': yes) */ 3552 #define SCB5_SPI_EC 1u 3553 /* Externally clocked support? ('0': no, '1': yes) */ 3554 #define SCB5_EC 1u 3555 /* UART support? ('0': no, '1': yes) */ 3556 #define SCB5_UART 1u 3557 /* SPI or UART (SPI | UART) */ 3558 #define SCB5_SPI_UART 1u 3559 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 3560 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 3561 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 3562 #define SCB5_EZ_DATA_NR 256u 3563 /* Command/response mode support? ('0': no, '1': yes) */ 3564 #define SCB5_CMD_RESP 0u 3565 /* EZ mode support? ('0': no, '1': yes) */ 3566 #define SCB5_EZ 1u 3567 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 3568 #define SCB5_EZ_CMD_RESP 1u 3569 /* I2C slave with EZ mode (I2C_S & EZ) */ 3570 #define SCB5_I2C_S_EZ 1u 3571 /* SPI slave with EZ mode (SPI_S & EZ) */ 3572 #define SCB5_SPI_S_EZ 1u 3573 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 3574 #define SCB5_MASTER_WIDTH 8u 3575 /* Number of used spi_select signals (max 4) */ 3576 #define SCB5_CHIP_TOP_SPI_SEL_NR 4u 3577 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 3578 #define SCB5_CHIP_TOP_I2C_FAST_PLUS 1u 3579 /* DeepSleep support ('0':no, '1': yes) */ 3580 #define SCB6_DEEPSLEEP 0u 3581 /* I2C master support? ('0': no, '1': yes) */ 3582 #define SCB6_I2C_M 1u 3583 /* I2C slave support? ('0': no, '1': yes) */ 3584 #define SCB6_I2C_S 1u 3585 /* I2C glitch filters present? ('0': no, '1': yes) */ 3586 #define SCB6_I2C_GLITCH 1u 3587 /* I2C slave with EC? (I2C_S & I2C_EC) */ 3588 #define SCB6_I2C_S_EC 0u 3589 /* I2C support? (I2C_M | I2C_S) */ 3590 #define SCB6_I2C 1u 3591 /* I2C externally clocked support? ('0': no, '1': yes) */ 3592 #define SCB6_I2C_EC 0u 3593 /* I2C master and slave support? (I2C_M & I2C_S) */ 3594 #define SCB6_I2C_M_S 1u 3595 /* SPI master support? ('0': no, '1': yes) */ 3596 #define SCB6_SPI_M 1u 3597 /* SPI slave support? ('0': no, '1': yes) */ 3598 #define SCB6_SPI_S 1u 3599 /* SPI slave with EC? (SPI_S & SPI_EC) */ 3600 #define SCB6_SPI_S_EC 1u 3601 /* SPI support? (SPI_M | SPI_S) */ 3602 #define SCB6_SPI 1u 3603 /* SPI externally clocked support? ('0': no, '1': yes) */ 3604 #define SCB6_SPI_EC 1u 3605 /* Externally clocked support? ('0': no, '1': yes) */ 3606 #define SCB6_EC 1u 3607 /* UART support? ('0': no, '1': yes) */ 3608 #define SCB6_UART 1u 3609 /* SPI or UART (SPI | UART) */ 3610 #define SCB6_SPI_UART 1u 3611 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 3612 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 3613 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 3614 #define SCB6_EZ_DATA_NR 256u 3615 /* Command/response mode support? ('0': no, '1': yes) */ 3616 #define SCB6_CMD_RESP 0u 3617 /* EZ mode support? ('0': no, '1': yes) */ 3618 #define SCB6_EZ 1u 3619 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 3620 #define SCB6_EZ_CMD_RESP 1u 3621 /* I2C slave with EZ mode (I2C_S & EZ) */ 3622 #define SCB6_I2C_S_EZ 1u 3623 /* SPI slave with EZ mode (SPI_S & EZ) */ 3624 #define SCB6_SPI_S_EZ 1u 3625 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 3626 #define SCB6_MASTER_WIDTH 8u 3627 /* Number of used spi_select signals (max 4) */ 3628 #define SCB6_CHIP_TOP_SPI_SEL_NR 4u 3629 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 3630 #define SCB6_CHIP_TOP_I2C_FAST_PLUS 1u 3631 /* DeepSleep support ('0':no, '1': yes) */ 3632 #define SCB7_DEEPSLEEP 0u 3633 /* I2C master support? ('0': no, '1': yes) */ 3634 #define SCB7_I2C_M 1u 3635 /* I2C slave support? ('0': no, '1': yes) */ 3636 #define SCB7_I2C_S 1u 3637 /* I2C glitch filters present? ('0': no, '1': yes) */ 3638 #define SCB7_I2C_GLITCH 1u 3639 /* I2C slave with EC? (I2C_S & I2C_EC) */ 3640 #define SCB7_I2C_S_EC 0u 3641 /* I2C support? (I2C_M | I2C_S) */ 3642 #define SCB7_I2C 1u 3643 /* I2C externally clocked support? ('0': no, '1': yes) */ 3644 #define SCB7_I2C_EC 0u 3645 /* I2C master and slave support? (I2C_M & I2C_S) */ 3646 #define SCB7_I2C_M_S 1u 3647 /* SPI master support? ('0': no, '1': yes) */ 3648 #define SCB7_SPI_M 1u 3649 /* SPI slave support? ('0': no, '1': yes) */ 3650 #define SCB7_SPI_S 1u 3651 /* SPI slave with EC? (SPI_S & SPI_EC) */ 3652 #define SCB7_SPI_S_EC 1u 3653 /* SPI support? (SPI_M | SPI_S) */ 3654 #define SCB7_SPI 1u 3655 /* SPI externally clocked support? ('0': no, '1': yes) */ 3656 #define SCB7_SPI_EC 1u 3657 /* Externally clocked support? ('0': no, '1': yes) */ 3658 #define SCB7_EC 1u 3659 /* UART support? ('0': no, '1': yes) */ 3660 #define SCB7_UART 1u 3661 /* SPI or UART (SPI | UART) */ 3662 #define SCB7_SPI_UART 1u 3663 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 3664 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 3665 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 3666 #define SCB7_EZ_DATA_NR 256u 3667 /* Command/response mode support? ('0': no, '1': yes) */ 3668 #define SCB7_CMD_RESP 0u 3669 /* EZ mode support? ('0': no, '1': yes) */ 3670 #define SCB7_EZ 1u 3671 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 3672 #define SCB7_EZ_CMD_RESP 1u 3673 /* I2C slave with EZ mode (I2C_S & EZ) */ 3674 #define SCB7_I2C_S_EZ 1u 3675 /* SPI slave with EZ mode (SPI_S & EZ) */ 3676 #define SCB7_SPI_S_EZ 1u 3677 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 3678 #define SCB7_MASTER_WIDTH 8u 3679 /* Number of used spi_select signals (max 4) */ 3680 #define SCB7_CHIP_TOP_SPI_SEL_NR 4u 3681 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 3682 #define SCB7_CHIP_TOP_I2C_FAST_PLUS 1u 3683 /* SONOS Flash is used or not ('0': no, '1': yes) */ 3684 #define SFLASH_FLASHC_IS_SONOS 0u 3685 /* WOUND_PRESENT or not ('0': no, '1': yes) */ 3686 #define SFLASH_WOUND_PRESENT 0u 3687 /* ULP variant. Must be 1 when targeting S40S and 0 otherwise. */ 3688 #define SRSS_ULP_VARIANT 0u 3689 /* HT variant. Must be 1 when targeting S40E and 0 otherwise. */ 3690 #define SRSS_HT_VARIANT 1u 3691 /* Number of regulator modules instantiated within SRSS, start with estimate, 3692 update after CMR feedback */ 3693 #define SRSS_NUM_ACTREG_PWRMOD 3u 3694 /* Number of shorting switches between vccd and vccact (target dynamic voltage 3695 drop < 10mV) */ 3696 #define SRSS_NUM_ACTIVE_SWITCH 4u 3697 /* ULP linear regulator system is present */ 3698 #define SRSS_ULPLINREG_PRESENT 0u 3699 /* HT linear regulator system is present */ 3700 #define SRSS_HTLINREG_PRESENT 1u 3701 /* SIMO buck core regulator is present. Only compatible with ULP linear regulator 3702 system (ULPLINREG_PRESENT==1). */ 3703 #define SRSS_SIMOBUCK_PRESENT 0u 3704 /* Precision ILO (PILO) is present */ 3705 #define SRSS_PILO_PRESENT 0u 3706 /* External Crystal Oscillator is present (high frequency) */ 3707 #define SRSS_ECO_PRESENT 1u 3708 /* System Buck-Boost is present */ 3709 #define SRSS_SYSBB_PRESENT 0u 3710 /* Number of PWR_HIB_DATA registers */ 3711 #define SRSS_NUM_HIBDATA 1u 3712 /* Number of clock paths. Must be > 0 */ 3713 #define SRSS_NUM_CLKPATH 4u 3714 /* Number of PLLs present. Must be <= NUM_CLKPATH */ 3715 #define SRSS_NUM_PLL 1u 3716 /* Total number of PLLs present. */ 3717 #define SRSS_NUM_TOTAL_PLL 1u 3718 /* Number of HFCLK roots present. Must be > 0 */ 3719 #define SRSS_NUM_HFROOT 3u 3720 /* Number of DSI inputs into clock muxes. This is used for logic optimization. */ 3721 #define SRSS_NUM_DSI 0u 3722 /* Alternate high-frequency clock is present. This is used for logic optimization. */ 3723 #define SRSS_ALTHF_PRESENT 0u 3724 /* Alternate low-frequency clock is present. This is used for logic optimization. */ 3725 #define SRSS_ALTLF_PRESENT 0u 3726 /* Backup domain is present */ 3727 #define SRSS_BACKUP_PRESENT 1u 3728 /* CSV present */ 3729 #define SRSS_CSV_PRESENT 1u 3730 /* Number of software watchdog timers. */ 3731 #define SRSS_NUM_MCWDT 2u 3732 /* Use the hardened clkactfllmux block */ 3733 #define SRSS_USE_HARD_CLKACTFLLMUX 1u 3734 /* Number of clock paths, including direct paths in hardened clkactfllmux block */ 3735 #define SRSS_HARD_CLKPATH 8u 3736 /* Number of clock paths with muxes in hardened clkactfllmux block */ 3737 #define SRSS_HARD_CLKPATHMUX 8u 3738 /* Number of HFCLKS present in hardened clkactfllmux block */ 3739 #define SRSS_HARD_HFROOT 8u 3740 /* ECO mux is present in hardened clkactfllmux block */ 3741 #define SRSS_HARD_ECOMUX_PRESENT 1u 3742 /* ALTHF mux is present in hardened clkactfllmux block */ 3743 #define SRSS_HARD_ALTHFMUX_PRESENT 1u 3744 /* POR present. */ 3745 #define SRSS_POR_PRESENT 1u 3746 /* Separate power supply Vbackup is present (only used when BACKUP_PRESENT==1) */ 3747 #define SRSS_BACKUP_VBCK_PRESENT 0u 3748 /* Alarm1 present in RTC */ 3749 #define SRSS_BACKUP_ALM1_PRESENT 1u 3750 /* Alarm2 present in RTC */ 3751 #define SRSS_BACKUP_ALM2_PRESENT 1u 3752 /* Backup memory is present (only used when BACKUP_PRESENT==1) */ 3753 #define SRSS_BACKUP_BMEM_PRESENT 0u 3754 /* Number of Backup registers to include (each is 32b). Only used when 3755 BACKUP_PRESENT==1. */ 3756 #define SRSS_BACKUP_NUM_BREG 4u 3757 /* Mask of HFCLK root clock supervisors (CSV). For each clock root i, bit[i] of 3758 mask indicates presence of a CSV. */ 3759 #define SRSS_CSV_HF_MASK_HFCSV 7u 3760 /* Number of input triggers per counter only routed to one counter (0..8) */ 3761 #define TCPWM_TR_ONE_CNT_NR 3u 3762 /* Number of input triggers routed to all counters (0..254), 3763 NR_TR_ONE_CNT+NR_TR_ALL CNT <= 254 */ 3764 #define TCPWM_TR_ALL_CNT_NR 27u 3765 /* Number of TCPWM counter groups (1..4) */ 3766 #define TCPWM_GRP_NR 3u 3767 /* Counter width in number of bits per TCPWM group (16: 16-bits, 32: 32-bits) */ 3768 #define TCPWM_GRP_NR0_CNT_GRP_CNT_WIDTH 16u 3769 /* Second Capture / Compare Unit is present (0, 1) */ 3770 #define TCPWM_GRP_NR0_CNT_GRP_CC1_PRESENT 1u 3771 /* Advanced Motor Control features are present (0, 1). Should only be 1 when 3772 group_CC1_PRESENT = 1 */ 3773 #define TCPWM_GRP_NR0_CNT_GRP_AMC_PRESENT 0u 3774 /* Stepper Motor Control features are present (0, 1). */ 3775 #define TCPWM_GRP_NR0_CNT_GRP_SMC_PRESENT 0u 3776 /* Number of counters per TCPWM group (1..256) */ 3777 #define TCPWM_GRP_NR0_GRP_GRP_CNT_NR 63u 3778 /* Counter width in number of bits per TCPWM group (16: 16-bits, 32: 32-bits) */ 3779 #define TCPWM_GRP_NR1_CNT_GRP_CNT_WIDTH 16u 3780 /* Second Capture / Compare Unit is present (0, 1) */ 3781 #define TCPWM_GRP_NR1_CNT_GRP_CC1_PRESENT 1u 3782 /* Advanced Motor Control features are present (0, 1). Should only be 1 when 3783 group_CC1_PRESENT = 1 */ 3784 #define TCPWM_GRP_NR1_CNT_GRP_AMC_PRESENT 1u 3785 /* Stepper Motor Control features are present (0, 1). */ 3786 #define TCPWM_GRP_NR1_CNT_GRP_SMC_PRESENT 1u 3787 /* Number of counters per TCPWM group (1..256) */ 3788 #define TCPWM_GRP_NR1_GRP_GRP_CNT_NR 12u 3789 /* Counter width in number of bits per TCPWM group (16: 16-bits, 32: 32-bits) */ 3790 #define TCPWM_GRP_NR2_CNT_GRP_CNT_WIDTH 32u 3791 /* Second Capture / Compare Unit is present (0, 1) */ 3792 #define TCPWM_GRP_NR2_CNT_GRP_CC1_PRESENT 1u 3793 /* Advanced Motor Control features are present (0, 1). Should only be 1 when 3794 group_CC1_PRESENT = 1 */ 3795 #define TCPWM_GRP_NR2_CNT_GRP_AMC_PRESENT 0u 3796 /* Stepper Motor Control features are present (0, 1). */ 3797 #define TCPWM_GRP_NR2_CNT_GRP_SMC_PRESENT 0u 3798 /* Number of counters per TCPWM group (1..256) */ 3799 #define TCPWM_GRP_NR2_GRP_GRP_CNT_NR 4u 3800 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 3801 #define TCPWM_MASTER_WIDTH 8u 3802 3803 /* MMIO Targets Defines */ 3804 /* MMIO1.CRYPTO */ 3805 #define CY_MMIO_CRYPTO_GROUP_NR 1u 3806 #define CY_MMIO_CRYPTO_SLAVE_NR 0u 3807 /* MMIO2.CPUSS */ 3808 #define CY_MMIO_CPUSS_GROUP_NR 2u 3809 #define CY_MMIO_CPUSS_SLAVE_NR 0u 3810 /* MMIO2.FAULT */ 3811 #define CY_MMIO_FAULT_GROUP_NR 2u 3812 #define CY_MMIO_FAULT_SLAVE_NR 1u 3813 /* MMIO2.IPC */ 3814 #define CY_MMIO_IPC_GROUP_NR 2u 3815 #define CY_MMIO_IPC_SLAVE_NR 2u 3816 /* MMIO2.PROT */ 3817 #define CY_MMIO_PROT_GROUP_NR 2u 3818 #define CY_MMIO_PROT_SLAVE_NR 3u 3819 /* MMIO2.FLASHC */ 3820 #define CY_MMIO_FLASHC_GROUP_NR 2u 3821 #define CY_MMIO_FLASHC_SLAVE_NR 4u 3822 /* MMIO2.SRSS */ 3823 #define CY_MMIO_SRSS_GROUP_NR 2u 3824 #define CY_MMIO_SRSS_SLAVE_NR 5u 3825 /* MMIO2.BACKUP */ 3826 #define CY_MMIO_BACKUP_GROUP_NR 2u 3827 #define CY_MMIO_BACKUP_SLAVE_NR 6u 3828 /* MMIO2.DW */ 3829 #define CY_MMIO_DW_GROUP_NR 2u 3830 #define CY_MMIO_DW_SLAVE_NR 7u 3831 /* MMIO2.DMAC */ 3832 #define CY_MMIO_DMAC_GROUP_NR 2u 3833 #define CY_MMIO_DMAC_SLAVE_NR 9u 3834 /* MMIO2.EFUSE */ 3835 #define CY_MMIO_EFUSE_GROUP_NR 2u 3836 #define CY_MMIO_EFUSE_SLAVE_NR 10u 3837 /* MMIO2.DFT */ 3838 #define CY_MMIO_DFT_GROUP_NR 2u 3839 #define CY_MMIO_DFT_SLAVE_NR 11u 3840 /* MMIO3.HSIOM */ 3841 #define CY_MMIO_HSIOM_GROUP_NR 3u 3842 #define CY_MMIO_HSIOM_SLAVE_NR 0u 3843 /* MMIO3.GPIO */ 3844 #define CY_MMIO_GPIO_GROUP_NR 3u 3845 #define CY_MMIO_GPIO_SLAVE_NR 1u 3846 /* MMIO3.SMARTIO */ 3847 #define CY_MMIO_SMARTIO_GROUP_NR 3u 3848 #define CY_MMIO_SMARTIO_SLAVE_NR 2u 3849 /* MMIO3.TCPWM0 */ 3850 #define CY_MMIO_TCPWM0_GROUP_NR 3u 3851 #define CY_MMIO_TCPWM0_SLAVE_NR 3u 3852 /* MMIO3.EVTGEN0 */ 3853 #define CY_MMIO_EVTGEN0_GROUP_NR 3u 3854 #define CY_MMIO_EVTGEN0_SLAVE_NR 4u 3855 /* MMIO5.LIN0 */ 3856 #define CY_MMIO_LIN0_GROUP_NR 5u 3857 #define CY_MMIO_LIN0_SLAVE_NR 0u 3858 /* MMIO5.CANFD0 */ 3859 #define CY_MMIO_CANFD0_GROUP_NR 5u 3860 #define CY_MMIO_CANFD0_SLAVE_NR 1u 3861 /* MMIO5.CANFD1 */ 3862 #define CY_MMIO_CANFD1_GROUP_NR 5u 3863 #define CY_MMIO_CANFD1_SLAVE_NR 2u 3864 /* MMIO6.SCB0 */ 3865 #define CY_MMIO_SCB0_GROUP_NR 6u 3866 #define CY_MMIO_SCB0_SLAVE_NR 0u 3867 /* MMIO6.SCB1 */ 3868 #define CY_MMIO_SCB1_GROUP_NR 6u 3869 #define CY_MMIO_SCB1_SLAVE_NR 1u 3870 /* MMIO6.SCB2 */ 3871 #define CY_MMIO_SCB2_GROUP_NR 6u 3872 #define CY_MMIO_SCB2_SLAVE_NR 2u 3873 /* MMIO6.SCB3 */ 3874 #define CY_MMIO_SCB3_GROUP_NR 6u 3875 #define CY_MMIO_SCB3_SLAVE_NR 3u 3876 /* MMIO6.SCB4 */ 3877 #define CY_MMIO_SCB4_GROUP_NR 6u 3878 #define CY_MMIO_SCB4_SLAVE_NR 4u 3879 /* MMIO6.SCB5 */ 3880 #define CY_MMIO_SCB5_GROUP_NR 6u 3881 #define CY_MMIO_SCB5_SLAVE_NR 5u 3882 /* MMIO6.SCB6 */ 3883 #define CY_MMIO_SCB6_GROUP_NR 6u 3884 #define CY_MMIO_SCB6_SLAVE_NR 6u 3885 /* MMIO6.SCB7 */ 3886 #define CY_MMIO_SCB7_GROUP_NR 6u 3887 #define CY_MMIO_SCB7_SLAVE_NR 7u 3888 /* MMIO9.PASS0 */ 3889 #define CY_MMIO_PASS0_GROUP_NR 9u 3890 #define CY_MMIO_PASS0_SLAVE_NR 0u 3891 3892 /* Backward compatibility definitions */ 3893 #define CPUSS_IRQ_NR CPUSS_SYSTEM_INT_NR 3894 #define CPUSS_DPSLP_IRQ_NR CPUSS_SYSTEM_DPSLP_INT_NR 3895 3896 /* Protection regions */ 3897 typedef enum 3898 { 3899 PROT_PERI_MAIN = 0, /* Address 0x40000000, size 0x00002000 */ 3900 PROT_PERI_SECURE = 1, /* Address 0x40002000, size 0x00000004 */ 3901 PROT_PERI_GR0_GROUP = 2, /* Address 0x40004010, size 0x00000004 */ 3902 PROT_PERI_GR1_GROUP = 3, /* Address 0x40004030, size 0x00000004 */ 3903 PROT_PERI_GR2_GROUP = 4, /* Address 0x40004050, size 0x00000004 */ 3904 PROT_PERI_GR3_GROUP = 5, /* Address 0x40004060, size 0x00000020 */ 3905 PROT_PERI_GR5_GROUP = 6, /* Address 0x400040a0, size 0x00000020 */ 3906 PROT_PERI_GR6_GROUP = 7, /* Address 0x400040c0, size 0x00000020 */ 3907 PROT_PERI_GR9_GROUP = 8, /* Address 0x40004120, size 0x00000020 */ 3908 PROT_PERI_TR = 9, /* Address 0x40008000, size 0x00008000 */ 3909 PROT_CRYPTO_MAIN = 10, /* Address 0x40100000, size 0x00000400 */ 3910 PROT_CRYPTO_CRYPTO = 11, /* Address 0x40101000, size 0x00000800 */ 3911 PROT_CRYPTO_BOOT = 12, /* Address 0x40102000, size 0x00000100 */ 3912 PROT_CRYPTO_KEY0 = 13, /* Address 0x40102100, size 0x00000004 */ 3913 PROT_CRYPTO_KEY1 = 14, /* Address 0x40102120, size 0x00000004 */ 3914 PROT_CRYPTO_BUF = 15, /* Address 0x40108000, size 0x00002000 */ 3915 PROT_CPUSS_CM4 = 16, /* Address 0x40200000, size 0x00000400 */ 3916 PROT_CPUSS_CM0 = 17, /* Address 0x40201000, size 0x00001000 */ 3917 PROT_CPUSS_BOOT = 18, /* Address 0x40202000, size 0x00000200 */ 3918 PROT_CPUSS_CM0_INT = 19, /* Address 0x40208000, size 0x00000800 */ 3919 PROT_CPUSS_CM4_INT = 20, /* Address 0x4020a000, size 0x00000800 */ 3920 PROT_FAULT_STRUCT0_MAIN = 21, /* Address 0x40210000, size 0x00000100 */ 3921 PROT_FAULT_STRUCT1_MAIN = 22, /* Address 0x40210100, size 0x00000100 */ 3922 PROT_FAULT_STRUCT2_MAIN = 23, /* Address 0x40210200, size 0x00000100 */ 3923 PROT_FAULT_STRUCT3_MAIN = 24, /* Address 0x40210300, size 0x00000100 */ 3924 PROT_IPC_STRUCT0_IPC = 25, /* Address 0x40220000, size 0x00000020 */ 3925 PROT_IPC_STRUCT1_IPC = 26, /* Address 0x40220020, size 0x00000020 */ 3926 PROT_IPC_STRUCT2_IPC = 27, /* Address 0x40220040, size 0x00000020 */ 3927 PROT_IPC_STRUCT3_IPC = 28, /* Address 0x40220060, size 0x00000020 */ 3928 PROT_IPC_STRUCT4_IPC = 29, /* Address 0x40220080, size 0x00000020 */ 3929 PROT_IPC_STRUCT5_IPC = 30, /* Address 0x402200a0, size 0x00000020 */ 3930 PROT_IPC_STRUCT6_IPC = 31, /* Address 0x402200c0, size 0x00000020 */ 3931 PROT_IPC_STRUCT7_IPC = 32, /* Address 0x402200e0, size 0x00000020 */ 3932 PROT_IPC_INTR_STRUCT0_INTR = 33, /* Address 0x40221000, size 0x00000010 */ 3933 PROT_IPC_INTR_STRUCT1_INTR = 34, /* Address 0x40221020, size 0x00000010 */ 3934 PROT_IPC_INTR_STRUCT2_INTR = 35, /* Address 0x40221040, size 0x00000010 */ 3935 PROT_IPC_INTR_STRUCT3_INTR = 36, /* Address 0x40221060, size 0x00000010 */ 3936 PROT_IPC_INTR_STRUCT4_INTR = 37, /* Address 0x40221080, size 0x00000010 */ 3937 PROT_IPC_INTR_STRUCT5_INTR = 38, /* Address 0x402210a0, size 0x00000010 */ 3938 PROT_IPC_INTR_STRUCT6_INTR = 39, /* Address 0x402210c0, size 0x00000010 */ 3939 PROT_IPC_INTR_STRUCT7_INTR = 40, /* Address 0x402210e0, size 0x00000010 */ 3940 PROT_PROT_SMPU_MAIN = 41, /* Address 0x40230000, size 0x00000040 */ 3941 PROT_PROT_MPU0_MAIN = 42, /* Address 0x40234000, size 0x00000004 */ 3942 PROT_PROT_MPU14_MAIN = 43, /* Address 0x40237800, size 0x00000004 */ 3943 PROT_PROT_MPU15_MAIN = 44, /* Address 0x40237c00, size 0x00000400 */ 3944 PROT_FLASHC_MAIN = 45, /* Address 0x40240000, size 0x00000008 */ 3945 PROT_FLASHC_CMD = 46, /* Address 0x40240008, size 0x00000004 */ 3946 PROT_FLASHC_DFT = 47, /* Address 0x40240200, size 0x00000100 */ 3947 PROT_FLASHC_CM0 = 48, /* Address 0x40240400, size 0x00000080 */ 3948 PROT_FLASHC_CM4 = 49, /* Address 0x40240480, size 0x00000080 */ 3949 PROT_FLASHC_CRYPTO = 50, /* Address 0x40240500, size 0x00000004 */ 3950 PROT_FLASHC_DW0 = 51, /* Address 0x40240580, size 0x00000004 */ 3951 PROT_FLASHC_DW1 = 52, /* Address 0x40240600, size 0x00000004 */ 3952 PROT_FLASHC_DMAC = 53, /* Address 0x40240680, size 0x00000004 */ 3953 PROT_FLASHC_FlashMgmt = 54, /* Address 0x4024f000, size 0x00000080 */ 3954 PROT_FLASHC_MainSafety = 55, /* Address 0x4024f400, size 0x00000008 */ 3955 PROT_FLASHC_WorkSafety = 56, /* Address 0x4024f500, size 0x00000004 */ 3956 PROT_SRSS_GENERAL = 57, /* Address 0x40260000, size 0x00000400 */ 3957 PROT_SRSS_MAIN = 58, /* Address 0x40261000, size 0x00001000 */ 3958 PROT_SRSS_SECURE = 59, /* Address 0x40262000, size 0x00002000 */ 3959 PROT_MCWDT0_CONFIG = 60, /* Address 0x40268000, size 0x00000080 */ 3960 PROT_MCWDT1_CONFIG = 61, /* Address 0x40268100, size 0x00000080 */ 3961 PROT_MCWDT0_MAIN = 62, /* Address 0x40268080, size 0x00000040 */ 3962 PROT_MCWDT1_MAIN = 63, /* Address 0x40268180, size 0x00000040 */ 3963 PROT_WDT_CONFIG = 64, /* Address 0x4026c000, size 0x00000020 */ 3964 PROT_WDT_MAIN = 65, /* Address 0x4026c040, size 0x00000020 */ 3965 PROT_BACKUP_BACKUP = 66, /* Address 0x40270000, size 0x00010000 */ 3966 PROT_DW0_DW = 67, /* Address 0x40280000, size 0x00000100 */ 3967 PROT_DW1_DW = 68, /* Address 0x40290000, size 0x00000100 */ 3968 PROT_DW0_DW_CRC = 69, /* Address 0x40280100, size 0x00000080 */ 3969 PROT_DW1_DW_CRC = 70, /* Address 0x40290100, size 0x00000080 */ 3970 PROT_DW0_CH_STRUCT0_CH = 71, /* Address 0x40288000, size 0x00000040 */ 3971 PROT_DW0_CH_STRUCT1_CH = 72, /* Address 0x40288040, size 0x00000040 */ 3972 PROT_DW0_CH_STRUCT2_CH = 73, /* Address 0x40288080, size 0x00000040 */ 3973 PROT_DW0_CH_STRUCT3_CH = 74, /* Address 0x402880c0, size 0x00000040 */ 3974 PROT_DW0_CH_STRUCT4_CH = 75, /* Address 0x40288100, size 0x00000040 */ 3975 PROT_DW0_CH_STRUCT5_CH = 76, /* Address 0x40288140, size 0x00000040 */ 3976 PROT_DW0_CH_STRUCT6_CH = 77, /* Address 0x40288180, size 0x00000040 */ 3977 PROT_DW0_CH_STRUCT7_CH = 78, /* Address 0x402881c0, size 0x00000040 */ 3978 PROT_DW0_CH_STRUCT8_CH = 79, /* Address 0x40288200, size 0x00000040 */ 3979 PROT_DW0_CH_STRUCT9_CH = 80, /* Address 0x40288240, size 0x00000040 */ 3980 PROT_DW0_CH_STRUCT10_CH = 81, /* Address 0x40288280, size 0x00000040 */ 3981 PROT_DW0_CH_STRUCT11_CH = 82, /* Address 0x402882c0, size 0x00000040 */ 3982 PROT_DW0_CH_STRUCT12_CH = 83, /* Address 0x40288300, size 0x00000040 */ 3983 PROT_DW0_CH_STRUCT13_CH = 84, /* Address 0x40288340, size 0x00000040 */ 3984 PROT_DW0_CH_STRUCT14_CH = 85, /* Address 0x40288380, size 0x00000040 */ 3985 PROT_DW0_CH_STRUCT15_CH = 86, /* Address 0x402883c0, size 0x00000040 */ 3986 PROT_DW0_CH_STRUCT16_CH = 87, /* Address 0x40288400, size 0x00000040 */ 3987 PROT_DW0_CH_STRUCT17_CH = 88, /* Address 0x40288440, size 0x00000040 */ 3988 PROT_DW0_CH_STRUCT18_CH = 89, /* Address 0x40288480, size 0x00000040 */ 3989 PROT_DW0_CH_STRUCT19_CH = 90, /* Address 0x402884c0, size 0x00000040 */ 3990 PROT_DW0_CH_STRUCT20_CH = 91, /* Address 0x40288500, size 0x00000040 */ 3991 PROT_DW0_CH_STRUCT21_CH = 92, /* Address 0x40288540, size 0x00000040 */ 3992 PROT_DW0_CH_STRUCT22_CH = 93, /* Address 0x40288580, size 0x00000040 */ 3993 PROT_DW0_CH_STRUCT23_CH = 94, /* Address 0x402885c0, size 0x00000040 */ 3994 PROT_DW0_CH_STRUCT24_CH = 95, /* Address 0x40288600, size 0x00000040 */ 3995 PROT_DW0_CH_STRUCT25_CH = 96, /* Address 0x40288640, size 0x00000040 */ 3996 PROT_DW0_CH_STRUCT26_CH = 97, /* Address 0x40288680, size 0x00000040 */ 3997 PROT_DW0_CH_STRUCT27_CH = 98, /* Address 0x402886c0, size 0x00000040 */ 3998 PROT_DW0_CH_STRUCT28_CH = 99, /* Address 0x40288700, size 0x00000040 */ 3999 PROT_DW0_CH_STRUCT29_CH = 100, /* Address 0x40288740, size 0x00000040 */ 4000 PROT_DW0_CH_STRUCT30_CH = 101, /* Address 0x40288780, size 0x00000040 */ 4001 PROT_DW0_CH_STRUCT31_CH = 102, /* Address 0x402887c0, size 0x00000040 */ 4002 PROT_DW0_CH_STRUCT32_CH = 103, /* Address 0x40288800, size 0x00000040 */ 4003 PROT_DW0_CH_STRUCT33_CH = 104, /* Address 0x40288840, size 0x00000040 */ 4004 PROT_DW0_CH_STRUCT34_CH = 105, /* Address 0x40288880, size 0x00000040 */ 4005 PROT_DW0_CH_STRUCT35_CH = 106, /* Address 0x402888c0, size 0x00000040 */ 4006 PROT_DW0_CH_STRUCT36_CH = 107, /* Address 0x40288900, size 0x00000040 */ 4007 PROT_DW0_CH_STRUCT37_CH = 108, /* Address 0x40288940, size 0x00000040 */ 4008 PROT_DW0_CH_STRUCT38_CH = 109, /* Address 0x40288980, size 0x00000040 */ 4009 PROT_DW0_CH_STRUCT39_CH = 110, /* Address 0x402889c0, size 0x00000040 */ 4010 PROT_DW0_CH_STRUCT40_CH = 111, /* Address 0x40288a00, size 0x00000040 */ 4011 PROT_DW0_CH_STRUCT41_CH = 112, /* Address 0x40288a40, size 0x00000040 */ 4012 PROT_DW0_CH_STRUCT42_CH = 113, /* Address 0x40288a80, size 0x00000040 */ 4013 PROT_DW0_CH_STRUCT43_CH = 114, /* Address 0x40288ac0, size 0x00000040 */ 4014 PROT_DW0_CH_STRUCT44_CH = 115, /* Address 0x40288b00, size 0x00000040 */ 4015 PROT_DW0_CH_STRUCT45_CH = 116, /* Address 0x40288b40, size 0x00000040 */ 4016 PROT_DW0_CH_STRUCT46_CH = 117, /* Address 0x40288b80, size 0x00000040 */ 4017 PROT_DW0_CH_STRUCT47_CH = 118, /* Address 0x40288bc0, size 0x00000040 */ 4018 PROT_DW0_CH_STRUCT48_CH = 119, /* Address 0x40288c00, size 0x00000040 */ 4019 PROT_DW0_CH_STRUCT49_CH = 120, /* Address 0x40288c40, size 0x00000040 */ 4020 PROT_DW0_CH_STRUCT50_CH = 121, /* Address 0x40288c80, size 0x00000040 */ 4021 PROT_DW0_CH_STRUCT51_CH = 122, /* Address 0x40288cc0, size 0x00000040 */ 4022 PROT_DW0_CH_STRUCT52_CH = 123, /* Address 0x40288d00, size 0x00000040 */ 4023 PROT_DW0_CH_STRUCT53_CH = 124, /* Address 0x40288d40, size 0x00000040 */ 4024 PROT_DW0_CH_STRUCT54_CH = 125, /* Address 0x40288d80, size 0x00000040 */ 4025 PROT_DW0_CH_STRUCT55_CH = 126, /* Address 0x40288dc0, size 0x00000040 */ 4026 PROT_DW0_CH_STRUCT56_CH = 127, /* Address 0x40288e00, size 0x00000040 */ 4027 PROT_DW0_CH_STRUCT57_CH = 128, /* Address 0x40288e40, size 0x00000040 */ 4028 PROT_DW0_CH_STRUCT58_CH = 129, /* Address 0x40288e80, size 0x00000040 */ 4029 PROT_DW0_CH_STRUCT59_CH = 130, /* Address 0x40288ec0, size 0x00000040 */ 4030 PROT_DW0_CH_STRUCT60_CH = 131, /* Address 0x40288f00, size 0x00000040 */ 4031 PROT_DW0_CH_STRUCT61_CH = 132, /* Address 0x40288f40, size 0x00000040 */ 4032 PROT_DW0_CH_STRUCT62_CH = 133, /* Address 0x40288f80, size 0x00000040 */ 4033 PROT_DW0_CH_STRUCT63_CH = 134, /* Address 0x40288fc0, size 0x00000040 */ 4034 PROT_DW0_CH_STRUCT64_CH = 135, /* Address 0x40289000, size 0x00000040 */ 4035 PROT_DW0_CH_STRUCT65_CH = 136, /* Address 0x40289040, size 0x00000040 */ 4036 PROT_DW0_CH_STRUCT66_CH = 137, /* Address 0x40289080, size 0x00000040 */ 4037 PROT_DW0_CH_STRUCT67_CH = 138, /* Address 0x402890c0, size 0x00000040 */ 4038 PROT_DW0_CH_STRUCT68_CH = 139, /* Address 0x40289100, size 0x00000040 */ 4039 PROT_DW0_CH_STRUCT69_CH = 140, /* Address 0x40289140, size 0x00000040 */ 4040 PROT_DW0_CH_STRUCT70_CH = 141, /* Address 0x40289180, size 0x00000040 */ 4041 PROT_DW0_CH_STRUCT71_CH = 142, /* Address 0x402891c0, size 0x00000040 */ 4042 PROT_DW0_CH_STRUCT72_CH = 143, /* Address 0x40289200, size 0x00000040 */ 4043 PROT_DW0_CH_STRUCT73_CH = 144, /* Address 0x40289240, size 0x00000040 */ 4044 PROT_DW0_CH_STRUCT74_CH = 145, /* Address 0x40289280, size 0x00000040 */ 4045 PROT_DW0_CH_STRUCT75_CH = 146, /* Address 0x402892c0, size 0x00000040 */ 4046 PROT_DW0_CH_STRUCT76_CH = 147, /* Address 0x40289300, size 0x00000040 */ 4047 PROT_DW0_CH_STRUCT77_CH = 148, /* Address 0x40289340, size 0x00000040 */ 4048 PROT_DW0_CH_STRUCT78_CH = 149, /* Address 0x40289380, size 0x00000040 */ 4049 PROT_DW0_CH_STRUCT79_CH = 150, /* Address 0x402893c0, size 0x00000040 */ 4050 PROT_DW0_CH_STRUCT80_CH = 151, /* Address 0x40289400, size 0x00000040 */ 4051 PROT_DW0_CH_STRUCT81_CH = 152, /* Address 0x40289440, size 0x00000040 */ 4052 PROT_DW0_CH_STRUCT82_CH = 153, /* Address 0x40289480, size 0x00000040 */ 4053 PROT_DW0_CH_STRUCT83_CH = 154, /* Address 0x402894c0, size 0x00000040 */ 4054 PROT_DW0_CH_STRUCT84_CH = 155, /* Address 0x40289500, size 0x00000040 */ 4055 PROT_DW0_CH_STRUCT85_CH = 156, /* Address 0x40289540, size 0x00000040 */ 4056 PROT_DW0_CH_STRUCT86_CH = 157, /* Address 0x40289580, size 0x00000040 */ 4057 PROT_DW0_CH_STRUCT87_CH = 158, /* Address 0x402895c0, size 0x00000040 */ 4058 PROT_DW0_CH_STRUCT88_CH = 159, /* Address 0x40289600, size 0x00000040 */ 4059 PROT_DW1_CH_STRUCT0_CH = 160, /* Address 0x40298000, size 0x00000040 */ 4060 PROT_DW1_CH_STRUCT1_CH = 161, /* Address 0x40298040, size 0x00000040 */ 4061 PROT_DW1_CH_STRUCT2_CH = 162, /* Address 0x40298080, size 0x00000040 */ 4062 PROT_DW1_CH_STRUCT3_CH = 163, /* Address 0x402980c0, size 0x00000040 */ 4063 PROT_DW1_CH_STRUCT4_CH = 164, /* Address 0x40298100, size 0x00000040 */ 4064 PROT_DW1_CH_STRUCT5_CH = 165, /* Address 0x40298140, size 0x00000040 */ 4065 PROT_DW1_CH_STRUCT6_CH = 166, /* Address 0x40298180, size 0x00000040 */ 4066 PROT_DW1_CH_STRUCT7_CH = 167, /* Address 0x402981c0, size 0x00000040 */ 4067 PROT_DW1_CH_STRUCT8_CH = 168, /* Address 0x40298200, size 0x00000040 */ 4068 PROT_DW1_CH_STRUCT9_CH = 169, /* Address 0x40298240, size 0x00000040 */ 4069 PROT_DW1_CH_STRUCT10_CH = 170, /* Address 0x40298280, size 0x00000040 */ 4070 PROT_DW1_CH_STRUCT11_CH = 171, /* Address 0x402982c0, size 0x00000040 */ 4071 PROT_DW1_CH_STRUCT12_CH = 172, /* Address 0x40298300, size 0x00000040 */ 4072 PROT_DW1_CH_STRUCT13_CH = 173, /* Address 0x40298340, size 0x00000040 */ 4073 PROT_DW1_CH_STRUCT14_CH = 174, /* Address 0x40298380, size 0x00000040 */ 4074 PROT_DW1_CH_STRUCT15_CH = 175, /* Address 0x402983c0, size 0x00000040 */ 4075 PROT_DW1_CH_STRUCT16_CH = 176, /* Address 0x40298400, size 0x00000040 */ 4076 PROT_DW1_CH_STRUCT17_CH = 177, /* Address 0x40298440, size 0x00000040 */ 4077 PROT_DW1_CH_STRUCT18_CH = 178, /* Address 0x40298480, size 0x00000040 */ 4078 PROT_DW1_CH_STRUCT19_CH = 179, /* Address 0x402984c0, size 0x00000040 */ 4079 PROT_DW1_CH_STRUCT20_CH = 180, /* Address 0x40298500, size 0x00000040 */ 4080 PROT_DW1_CH_STRUCT21_CH = 181, /* Address 0x40298540, size 0x00000040 */ 4081 PROT_DW1_CH_STRUCT22_CH = 182, /* Address 0x40298580, size 0x00000040 */ 4082 PROT_DW1_CH_STRUCT23_CH = 183, /* Address 0x402985c0, size 0x00000040 */ 4083 PROT_DW1_CH_STRUCT24_CH = 184, /* Address 0x40298600, size 0x00000040 */ 4084 PROT_DW1_CH_STRUCT25_CH = 185, /* Address 0x40298640, size 0x00000040 */ 4085 PROT_DW1_CH_STRUCT26_CH = 186, /* Address 0x40298680, size 0x00000040 */ 4086 PROT_DW1_CH_STRUCT27_CH = 187, /* Address 0x402986c0, size 0x00000040 */ 4087 PROT_DW1_CH_STRUCT28_CH = 188, /* Address 0x40298700, size 0x00000040 */ 4088 PROT_DW1_CH_STRUCT29_CH = 189, /* Address 0x40298740, size 0x00000040 */ 4089 PROT_DW1_CH_STRUCT30_CH = 190, /* Address 0x40298780, size 0x00000040 */ 4090 PROT_DW1_CH_STRUCT31_CH = 191, /* Address 0x402987c0, size 0x00000040 */ 4091 PROT_DW1_CH_STRUCT32_CH = 192, /* Address 0x40298800, size 0x00000040 */ 4092 PROT_DMAC_TOP = 193, /* Address 0x402a0000, size 0x00000010 */ 4093 PROT_DMAC_CH0_CH = 194, /* Address 0x402a1000, size 0x00000100 */ 4094 PROT_DMAC_CH1_CH = 195, /* Address 0x402a1100, size 0x00000100 */ 4095 PROT_DMAC_CH2_CH = 196, /* Address 0x402a1200, size 0x00000100 */ 4096 PROT_DMAC_CH3_CH = 197, /* Address 0x402a1300, size 0x00000100 */ 4097 PROT_EFUSE_CTL = 198, /* Address 0x402c0000, size 0x00000200 */ 4098 PROT_EFUSE_DATA = 199, /* Address 0x402c0800, size 0x00000200 */ 4099 PROT_BIST = 200, /* Address 0x402f0000, size 0x00001000 */ 4100 PROT_HSIOM_PRT0_PRT = 201, /* Address 0x40300000, size 0x00000008 */ 4101 PROT_HSIOM_PRT1_PRT = 202, /* Address 0x40300010, size 0x00000008 */ 4102 PROT_HSIOM_PRT2_PRT = 203, /* Address 0x40300020, size 0x00000008 */ 4103 PROT_HSIOM_PRT3_PRT = 204, /* Address 0x40300030, size 0x00000008 */ 4104 PROT_HSIOM_PRT4_PRT = 205, /* Address 0x40300040, size 0x00000008 */ 4105 PROT_HSIOM_PRT5_PRT = 206, /* Address 0x40300050, size 0x00000008 */ 4106 PROT_HSIOM_PRT6_PRT = 207, /* Address 0x40300060, size 0x00000008 */ 4107 PROT_HSIOM_PRT7_PRT = 208, /* Address 0x40300070, size 0x00000008 */ 4108 PROT_HSIOM_PRT8_PRT = 209, /* Address 0x40300080, size 0x00000008 */ 4109 PROT_HSIOM_PRT9_PRT = 210, /* Address 0x40300090, size 0x00000008 */ 4110 PROT_HSIOM_PRT10_PRT = 211, /* Address 0x403000a0, size 0x00000008 */ 4111 PROT_HSIOM_PRT11_PRT = 212, /* Address 0x403000b0, size 0x00000008 */ 4112 PROT_HSIOM_PRT12_PRT = 213, /* Address 0x403000c0, size 0x00000008 */ 4113 PROT_HSIOM_PRT13_PRT = 214, /* Address 0x403000d0, size 0x00000008 */ 4114 PROT_HSIOM_PRT14_PRT = 215, /* Address 0x403000e0, size 0x00000008 */ 4115 PROT_HSIOM_PRT15_PRT = 216, /* Address 0x403000f0, size 0x00000008 */ 4116 PROT_HSIOM_PRT16_PRT = 217, /* Address 0x40300100, size 0x00000008 */ 4117 PROT_HSIOM_PRT17_PRT = 218, /* Address 0x40300110, size 0x00000008 */ 4118 PROT_HSIOM_PRT18_PRT = 219, /* Address 0x40300120, size 0x00000008 */ 4119 PROT_HSIOM_PRT19_PRT = 220, /* Address 0x40300130, size 0x00000008 */ 4120 PROT_HSIOM_PRT20_PRT = 221, /* Address 0x40300140, size 0x00000008 */ 4121 PROT_HSIOM_PRT21_PRT = 222, /* Address 0x40300150, size 0x00000008 */ 4122 PROT_HSIOM_PRT22_PRT = 223, /* Address 0x40300160, size 0x00000008 */ 4123 PROT_HSIOM_PRT23_PRT = 224, /* Address 0x40300170, size 0x00000008 */ 4124 PROT_HSIOM_AMUX = 225, /* Address 0x40302000, size 0x00000010 */ 4125 PROT_HSIOM_MON = 226, /* Address 0x40302200, size 0x00000010 */ 4126 PROT_HSIOM_ALTJTAG = 227, /* Address 0x40302240, size 0x00000004 */ 4127 PROT_GPIO_PRT0_PRT = 228, /* Address 0x40310000, size 0x00000040 */ 4128 PROT_GPIO_PRT1_PRT = 229, /* Address 0x40310080, size 0x00000040 */ 4129 PROT_GPIO_PRT2_PRT = 230, /* Address 0x40310100, size 0x00000040 */ 4130 PROT_GPIO_PRT3_PRT = 231, /* Address 0x40310180, size 0x00000040 */ 4131 PROT_GPIO_PRT4_PRT = 232, /* Address 0x40310200, size 0x00000040 */ 4132 PROT_GPIO_PRT5_PRT = 233, /* Address 0x40310280, size 0x00000040 */ 4133 PROT_GPIO_PRT6_PRT = 234, /* Address 0x40310300, size 0x00000040 */ 4134 PROT_GPIO_PRT7_PRT = 235, /* Address 0x40310380, size 0x00000040 */ 4135 PROT_GPIO_PRT8_PRT = 236, /* Address 0x40310400, size 0x00000040 */ 4136 PROT_GPIO_PRT9_PRT = 237, /* Address 0x40310480, size 0x00000040 */ 4137 PROT_GPIO_PRT10_PRT = 238, /* Address 0x40310500, size 0x00000040 */ 4138 PROT_GPIO_PRT11_PRT = 239, /* Address 0x40310580, size 0x00000040 */ 4139 PROT_GPIO_PRT12_PRT = 240, /* Address 0x40310600, size 0x00000040 */ 4140 PROT_GPIO_PRT13_PRT = 241, /* Address 0x40310680, size 0x00000040 */ 4141 PROT_GPIO_PRT14_PRT = 242, /* Address 0x40310700, size 0x00000040 */ 4142 PROT_GPIO_PRT15_PRT = 243, /* Address 0x40310780, size 0x00000040 */ 4143 PROT_GPIO_PRT16_PRT = 244, /* Address 0x40310800, size 0x00000040 */ 4144 PROT_GPIO_PRT17_PRT = 245, /* Address 0x40310880, size 0x00000040 */ 4145 PROT_GPIO_PRT18_PRT = 246, /* Address 0x40310900, size 0x00000040 */ 4146 PROT_GPIO_PRT19_PRT = 247, /* Address 0x40310980, size 0x00000040 */ 4147 PROT_GPIO_PRT20_PRT = 248, /* Address 0x40310a00, size 0x00000040 */ 4148 PROT_GPIO_PRT21_PRT = 249, /* Address 0x40310a80, size 0x00000040 */ 4149 PROT_GPIO_PRT22_PRT = 250, /* Address 0x40310b00, size 0x00000040 */ 4150 PROT_GPIO_PRT23_PRT = 251, /* Address 0x40310b80, size 0x00000040 */ 4151 PROT_GPIO_PRT0_CFG = 252, /* Address 0x40310040, size 0x00000020 */ 4152 PROT_GPIO_PRT1_CFG = 253, /* Address 0x403100c0, size 0x00000020 */ 4153 PROT_GPIO_PRT2_CFG = 254, /* Address 0x40310140, size 0x00000020 */ 4154 PROT_GPIO_PRT3_CFG = 255, /* Address 0x403101c0, size 0x00000020 */ 4155 PROT_GPIO_PRT4_CFG = 256, /* Address 0x40310240, size 0x00000020 */ 4156 PROT_GPIO_PRT5_CFG = 257, /* Address 0x403102c0, size 0x00000020 */ 4157 PROT_GPIO_PRT6_CFG = 258, /* Address 0x40310340, size 0x00000020 */ 4158 PROT_GPIO_PRT7_CFG = 259, /* Address 0x403103c0, size 0x00000020 */ 4159 PROT_GPIO_PRT8_CFG = 260, /* Address 0x40310440, size 0x00000020 */ 4160 PROT_GPIO_PRT9_CFG = 261, /* Address 0x403104c0, size 0x00000020 */ 4161 PROT_GPIO_PRT10_CFG = 262, /* Address 0x40310540, size 0x00000020 */ 4162 PROT_GPIO_PRT11_CFG = 263, /* Address 0x403105c0, size 0x00000020 */ 4163 PROT_GPIO_PRT12_CFG = 264, /* Address 0x40310640, size 0x00000020 */ 4164 PROT_GPIO_PRT13_CFG = 265, /* Address 0x403106c0, size 0x00000020 */ 4165 PROT_GPIO_PRT14_CFG = 266, /* Address 0x40310740, size 0x00000020 */ 4166 PROT_GPIO_PRT15_CFG = 267, /* Address 0x403107c0, size 0x00000020 */ 4167 PROT_GPIO_PRT16_CFG = 268, /* Address 0x40310840, size 0x00000020 */ 4168 PROT_GPIO_PRT17_CFG = 269, /* Address 0x403108c0, size 0x00000020 */ 4169 PROT_GPIO_PRT18_CFG = 270, /* Address 0x40310940, size 0x00000020 */ 4170 PROT_GPIO_PRT19_CFG = 271, /* Address 0x403109c0, size 0x00000020 */ 4171 PROT_GPIO_PRT20_CFG = 272, /* Address 0x40310a40, size 0x00000020 */ 4172 PROT_GPIO_PRT21_CFG = 273, /* Address 0x40310ac0, size 0x00000020 */ 4173 PROT_GPIO_PRT22_CFG = 274, /* Address 0x40310b40, size 0x00000020 */ 4174 PROT_GPIO_PRT23_CFG = 275, /* Address 0x40310bc0, size 0x00000020 */ 4175 PROT_GPIO_GPIO = 276, /* Address 0x40314000, size 0x00000040 */ 4176 PROT_GPIO_TEST = 277, /* Address 0x40315000, size 0x00000008 */ 4177 PROT_SMARTIO_PRT12_PRT = 278, /* Address 0x40320c00, size 0x00000100 */ 4178 PROT_SMARTIO_PRT13_PRT = 279, /* Address 0x40320d00, size 0x00000100 */ 4179 PROT_SMARTIO_PRT14_PRT = 280, /* Address 0x40320e00, size 0x00000100 */ 4180 PROT_SMARTIO_PRT15_PRT = 281, /* Address 0x40320f00, size 0x00000100 */ 4181 PROT_SMARTIO_PRT17_PRT = 282, /* Address 0x40321100, size 0x00000100 */ 4182 PROT_TCPWM0_GRP0_CNT0_CNT = 283, /* Address 0x40380000, size 0x00000080 */ 4183 PROT_TCPWM0_GRP0_CNT1_CNT = 284, /* Address 0x40380080, size 0x00000080 */ 4184 PROT_TCPWM0_GRP0_CNT2_CNT = 285, /* Address 0x40380100, size 0x00000080 */ 4185 PROT_TCPWM0_GRP0_CNT3_CNT = 286, /* Address 0x40380180, size 0x00000080 */ 4186 PROT_TCPWM0_GRP0_CNT4_CNT = 287, /* Address 0x40380200, size 0x00000080 */ 4187 PROT_TCPWM0_GRP0_CNT5_CNT = 288, /* Address 0x40380280, size 0x00000080 */ 4188 PROT_TCPWM0_GRP0_CNT6_CNT = 289, /* Address 0x40380300, size 0x00000080 */ 4189 PROT_TCPWM0_GRP0_CNT7_CNT = 290, /* Address 0x40380380, size 0x00000080 */ 4190 PROT_TCPWM0_GRP0_CNT8_CNT = 291, /* Address 0x40380400, size 0x00000080 */ 4191 PROT_TCPWM0_GRP0_CNT9_CNT = 292, /* Address 0x40380480, size 0x00000080 */ 4192 PROT_TCPWM0_GRP0_CNT10_CNT = 293, /* Address 0x40380500, size 0x00000080 */ 4193 PROT_TCPWM0_GRP0_CNT11_CNT = 294, /* Address 0x40380580, size 0x00000080 */ 4194 PROT_TCPWM0_GRP0_CNT12_CNT = 295, /* Address 0x40380600, size 0x00000080 */ 4195 PROT_TCPWM0_GRP0_CNT13_CNT = 296, /* Address 0x40380680, size 0x00000080 */ 4196 PROT_TCPWM0_GRP0_CNT14_CNT = 297, /* Address 0x40380700, size 0x00000080 */ 4197 PROT_TCPWM0_GRP0_CNT15_CNT = 298, /* Address 0x40380780, size 0x00000080 */ 4198 PROT_TCPWM0_GRP0_CNT16_CNT = 299, /* Address 0x40380800, size 0x00000080 */ 4199 PROT_TCPWM0_GRP0_CNT17_CNT = 300, /* Address 0x40380880, size 0x00000080 */ 4200 PROT_TCPWM0_GRP0_CNT18_CNT = 301, /* Address 0x40380900, size 0x00000080 */ 4201 PROT_TCPWM0_GRP0_CNT19_CNT = 302, /* Address 0x40380980, size 0x00000080 */ 4202 PROT_TCPWM0_GRP0_CNT20_CNT = 303, /* Address 0x40380a00, size 0x00000080 */ 4203 PROT_TCPWM0_GRP0_CNT21_CNT = 304, /* Address 0x40380a80, size 0x00000080 */ 4204 PROT_TCPWM0_GRP0_CNT22_CNT = 305, /* Address 0x40380b00, size 0x00000080 */ 4205 PROT_TCPWM0_GRP0_CNT23_CNT = 306, /* Address 0x40380b80, size 0x00000080 */ 4206 PROT_TCPWM0_GRP0_CNT24_CNT = 307, /* Address 0x40380c00, size 0x00000080 */ 4207 PROT_TCPWM0_GRP0_CNT25_CNT = 308, /* Address 0x40380c80, size 0x00000080 */ 4208 PROT_TCPWM0_GRP0_CNT26_CNT = 309, /* Address 0x40380d00, size 0x00000080 */ 4209 PROT_TCPWM0_GRP0_CNT27_CNT = 310, /* Address 0x40380d80, size 0x00000080 */ 4210 PROT_TCPWM0_GRP0_CNT28_CNT = 311, /* Address 0x40380e00, size 0x00000080 */ 4211 PROT_TCPWM0_GRP0_CNT29_CNT = 312, /* Address 0x40380e80, size 0x00000080 */ 4212 PROT_TCPWM0_GRP0_CNT30_CNT = 313, /* Address 0x40380f00, size 0x00000080 */ 4213 PROT_TCPWM0_GRP0_CNT31_CNT = 314, /* Address 0x40380f80, size 0x00000080 */ 4214 PROT_TCPWM0_GRP0_CNT32_CNT = 315, /* Address 0x40381000, size 0x00000080 */ 4215 PROT_TCPWM0_GRP0_CNT33_CNT = 316, /* Address 0x40381080, size 0x00000080 */ 4216 PROT_TCPWM0_GRP0_CNT34_CNT = 317, /* Address 0x40381100, size 0x00000080 */ 4217 PROT_TCPWM0_GRP0_CNT35_CNT = 318, /* Address 0x40381180, size 0x00000080 */ 4218 PROT_TCPWM0_GRP0_CNT36_CNT = 319, /* Address 0x40381200, size 0x00000080 */ 4219 PROT_TCPWM0_GRP0_CNT37_CNT = 320, /* Address 0x40381280, size 0x00000080 */ 4220 PROT_TCPWM0_GRP0_CNT38_CNT = 321, /* Address 0x40381300, size 0x00000080 */ 4221 PROT_TCPWM0_GRP0_CNT39_CNT = 322, /* Address 0x40381380, size 0x00000080 */ 4222 PROT_TCPWM0_GRP0_CNT40_CNT = 323, /* Address 0x40381400, size 0x00000080 */ 4223 PROT_TCPWM0_GRP0_CNT41_CNT = 324, /* Address 0x40381480, size 0x00000080 */ 4224 PROT_TCPWM0_GRP0_CNT42_CNT = 325, /* Address 0x40381500, size 0x00000080 */ 4225 PROT_TCPWM0_GRP0_CNT43_CNT = 326, /* Address 0x40381580, size 0x00000080 */ 4226 PROT_TCPWM0_GRP0_CNT44_CNT = 327, /* Address 0x40381600, size 0x00000080 */ 4227 PROT_TCPWM0_GRP0_CNT45_CNT = 328, /* Address 0x40381680, size 0x00000080 */ 4228 PROT_TCPWM0_GRP0_CNT46_CNT = 329, /* Address 0x40381700, size 0x00000080 */ 4229 PROT_TCPWM0_GRP0_CNT47_CNT = 330, /* Address 0x40381780, size 0x00000080 */ 4230 PROT_TCPWM0_GRP0_CNT48_CNT = 331, /* Address 0x40381800, size 0x00000080 */ 4231 PROT_TCPWM0_GRP0_CNT49_CNT = 332, /* Address 0x40381880, size 0x00000080 */ 4232 PROT_TCPWM0_GRP0_CNT50_CNT = 333, /* Address 0x40381900, size 0x00000080 */ 4233 PROT_TCPWM0_GRP0_CNT51_CNT = 334, /* Address 0x40381980, size 0x00000080 */ 4234 PROT_TCPWM0_GRP0_CNT52_CNT = 335, /* Address 0x40381a00, size 0x00000080 */ 4235 PROT_TCPWM0_GRP0_CNT53_CNT = 336, /* Address 0x40381a80, size 0x00000080 */ 4236 PROT_TCPWM0_GRP0_CNT54_CNT = 337, /* Address 0x40381b00, size 0x00000080 */ 4237 PROT_TCPWM0_GRP0_CNT55_CNT = 338, /* Address 0x40381b80, size 0x00000080 */ 4238 PROT_TCPWM0_GRP0_CNT56_CNT = 339, /* Address 0x40381c00, size 0x00000080 */ 4239 PROT_TCPWM0_GRP0_CNT57_CNT = 340, /* Address 0x40381c80, size 0x00000080 */ 4240 PROT_TCPWM0_GRP0_CNT58_CNT = 341, /* Address 0x40381d00, size 0x00000080 */ 4241 PROT_TCPWM0_GRP0_CNT59_CNT = 342, /* Address 0x40381d80, size 0x00000080 */ 4242 PROT_TCPWM0_GRP0_CNT60_CNT = 343, /* Address 0x40381e00, size 0x00000080 */ 4243 PROT_TCPWM0_GRP0_CNT61_CNT = 344, /* Address 0x40381e80, size 0x00000080 */ 4244 PROT_TCPWM0_GRP0_CNT62_CNT = 345, /* Address 0x40381f00, size 0x00000080 */ 4245 PROT_TCPWM0_GRP1_CNT0_CNT = 346, /* Address 0x40388000, size 0x00000080 */ 4246 PROT_TCPWM0_GRP1_CNT1_CNT = 347, /* Address 0x40388080, size 0x00000080 */ 4247 PROT_TCPWM0_GRP1_CNT2_CNT = 348, /* Address 0x40388100, size 0x00000080 */ 4248 PROT_TCPWM0_GRP1_CNT3_CNT = 349, /* Address 0x40388180, size 0x00000080 */ 4249 PROT_TCPWM0_GRP1_CNT4_CNT = 350, /* Address 0x40388200, size 0x00000080 */ 4250 PROT_TCPWM0_GRP1_CNT5_CNT = 351, /* Address 0x40388280, size 0x00000080 */ 4251 PROT_TCPWM0_GRP1_CNT6_CNT = 352, /* Address 0x40388300, size 0x00000080 */ 4252 PROT_TCPWM0_GRP1_CNT7_CNT = 353, /* Address 0x40388380, size 0x00000080 */ 4253 PROT_TCPWM0_GRP1_CNT8_CNT = 354, /* Address 0x40388400, size 0x00000080 */ 4254 PROT_TCPWM0_GRP1_CNT9_CNT = 355, /* Address 0x40388480, size 0x00000080 */ 4255 PROT_TCPWM0_GRP1_CNT10_CNT = 356, /* Address 0x40388500, size 0x00000080 */ 4256 PROT_TCPWM0_GRP1_CNT11_CNT = 357, /* Address 0x40388580, size 0x00000080 */ 4257 PROT_TCPWM0_GRP2_CNT0_CNT = 358, /* Address 0x40390000, size 0x00000080 */ 4258 PROT_TCPWM0_GRP2_CNT1_CNT = 359, /* Address 0x40390080, size 0x00000080 */ 4259 PROT_TCPWM0_GRP2_CNT2_CNT = 360, /* Address 0x40390100, size 0x00000080 */ 4260 PROT_TCPWM0_GRP2_CNT3_CNT = 361, /* Address 0x40390180, size 0x00000080 */ 4261 PROT_EVTGEN0 = 362, /* Address 0x403f0000, size 0x00001000 */ 4262 PROT_LIN0_MAIN = 363, /* Address 0x40500000, size 0x00000008 */ 4263 PROT_LIN0_CH0_CH = 364, /* Address 0x40508000, size 0x00000100 */ 4264 PROT_LIN0_CH1_CH = 365, /* Address 0x40508100, size 0x00000100 */ 4265 PROT_LIN0_CH2_CH = 366, /* Address 0x40508200, size 0x00000100 */ 4266 PROT_LIN0_CH3_CH = 367, /* Address 0x40508300, size 0x00000100 */ 4267 PROT_LIN0_CH4_CH = 368, /* Address 0x40508400, size 0x00000100 */ 4268 PROT_LIN0_CH5_CH = 369, /* Address 0x40508500, size 0x00000100 */ 4269 PROT_LIN0_CH6_CH = 370, /* Address 0x40508600, size 0x00000100 */ 4270 PROT_LIN0_CH7_CH = 371, /* Address 0x40508700, size 0x00000100 */ 4271 PROT_CANFD0_CH0_CH = 372, /* Address 0x40520000, size 0x00000200 */ 4272 PROT_CANFD0_CH1_CH = 373, /* Address 0x40520200, size 0x00000200 */ 4273 PROT_CANFD0_CH2_CH = 374, /* Address 0x40520400, size 0x00000200 */ 4274 PROT_CANFD1_CH0_CH = 375, /* Address 0x40540000, size 0x00000200 */ 4275 PROT_CANFD1_CH1_CH = 376, /* Address 0x40540200, size 0x00000200 */ 4276 PROT_CANFD1_CH2_CH = 377, /* Address 0x40540400, size 0x00000200 */ 4277 PROT_CANFD0_MAIN = 378, /* Address 0x40521000, size 0x00000100 */ 4278 PROT_CANFD1_MAIN = 379, /* Address 0x40541000, size 0x00000100 */ 4279 PROT_CANFD0_BUF = 380, /* Address 0x40530000, size 0x00010000 */ 4280 PROT_CANFD1_BUF = 381, /* Address 0x40550000, size 0x00010000 */ 4281 PROT_SCB0 = 382, /* Address 0x40600000, size 0x00010000 */ 4282 PROT_SCB1 = 383, /* Address 0x40610000, size 0x00010000 */ 4283 PROT_SCB2 = 384, /* Address 0x40620000, size 0x00010000 */ 4284 PROT_SCB3 = 385, /* Address 0x40630000, size 0x00010000 */ 4285 PROT_SCB4 = 386, /* Address 0x40640000, size 0x00010000 */ 4286 PROT_SCB5 = 387, /* Address 0x40650000, size 0x00010000 */ 4287 PROT_SCB6 = 388, /* Address 0x40660000, size 0x00010000 */ 4288 PROT_SCB7 = 389, /* Address 0x40670000, size 0x00010000 */ 4289 PROT_PASS0_SAR0_SAR = 390, /* Address 0x40900000, size 0x00000400 */ 4290 PROT_PASS0_SAR1_SAR = 391, /* Address 0x40901000, size 0x00000400 */ 4291 PROT_PASS0_SAR2_SAR = 392, /* Address 0x40902000, size 0x00000400 */ 4292 PROT_PASS0_SAR0_CH0_CH = 393, /* Address 0x40900800, size 0x00000040 */ 4293 PROT_PASS0_SAR0_CH1_CH = 394, /* Address 0x40900840, size 0x00000040 */ 4294 PROT_PASS0_SAR0_CH2_CH = 395, /* Address 0x40900880, size 0x00000040 */ 4295 PROT_PASS0_SAR0_CH3_CH = 396, /* Address 0x409008c0, size 0x00000040 */ 4296 PROT_PASS0_SAR0_CH4_CH = 397, /* Address 0x40900900, size 0x00000040 */ 4297 PROT_PASS0_SAR0_CH5_CH = 398, /* Address 0x40900940, size 0x00000040 */ 4298 PROT_PASS0_SAR0_CH6_CH = 399, /* Address 0x40900980, size 0x00000040 */ 4299 PROT_PASS0_SAR0_CH7_CH = 400, /* Address 0x409009c0, size 0x00000040 */ 4300 PROT_PASS0_SAR0_CH8_CH = 401, /* Address 0x40900a00, size 0x00000040 */ 4301 PROT_PASS0_SAR0_CH9_CH = 402, /* Address 0x40900a40, size 0x00000040 */ 4302 PROT_PASS0_SAR0_CH10_CH = 403, /* Address 0x40900a80, size 0x00000040 */ 4303 PROT_PASS0_SAR0_CH11_CH = 404, /* Address 0x40900ac0, size 0x00000040 */ 4304 PROT_PASS0_SAR0_CH12_CH = 405, /* Address 0x40900b00, size 0x00000040 */ 4305 PROT_PASS0_SAR0_CH13_CH = 406, /* Address 0x40900b40, size 0x00000040 */ 4306 PROT_PASS0_SAR0_CH14_CH = 407, /* Address 0x40900b80, size 0x00000040 */ 4307 PROT_PASS0_SAR0_CH15_CH = 408, /* Address 0x40900bc0, size 0x00000040 */ 4308 PROT_PASS0_SAR0_CH16_CH = 409, /* Address 0x40900c00, size 0x00000040 */ 4309 PROT_PASS0_SAR0_CH17_CH = 410, /* Address 0x40900c40, size 0x00000040 */ 4310 PROT_PASS0_SAR0_CH18_CH = 411, /* Address 0x40900c80, size 0x00000040 */ 4311 PROT_PASS0_SAR0_CH19_CH = 412, /* Address 0x40900cc0, size 0x00000040 */ 4312 PROT_PASS0_SAR0_CH20_CH = 413, /* Address 0x40900d00, size 0x00000040 */ 4313 PROT_PASS0_SAR0_CH21_CH = 414, /* Address 0x40900d40, size 0x00000040 */ 4314 PROT_PASS0_SAR0_CH22_CH = 415, /* Address 0x40900d80, size 0x00000040 */ 4315 PROT_PASS0_SAR0_CH23_CH = 416, /* Address 0x40900dc0, size 0x00000040 */ 4316 PROT_PASS0_SAR1_CH0_CH = 417, /* Address 0x40901800, size 0x00000040 */ 4317 PROT_PASS0_SAR1_CH1_CH = 418, /* Address 0x40901840, size 0x00000040 */ 4318 PROT_PASS0_SAR1_CH2_CH = 419, /* Address 0x40901880, size 0x00000040 */ 4319 PROT_PASS0_SAR1_CH3_CH = 420, /* Address 0x409018c0, size 0x00000040 */ 4320 PROT_PASS0_SAR1_CH4_CH = 421, /* Address 0x40901900, size 0x00000040 */ 4321 PROT_PASS0_SAR1_CH5_CH = 422, /* Address 0x40901940, size 0x00000040 */ 4322 PROT_PASS0_SAR1_CH6_CH = 423, /* Address 0x40901980, size 0x00000040 */ 4323 PROT_PASS0_SAR1_CH7_CH = 424, /* Address 0x409019c0, size 0x00000040 */ 4324 PROT_PASS0_SAR1_CH8_CH = 425, /* Address 0x40901a00, size 0x00000040 */ 4325 PROT_PASS0_SAR1_CH9_CH = 426, /* Address 0x40901a40, size 0x00000040 */ 4326 PROT_PASS0_SAR1_CH10_CH = 427, /* Address 0x40901a80, size 0x00000040 */ 4327 PROT_PASS0_SAR1_CH11_CH = 428, /* Address 0x40901ac0, size 0x00000040 */ 4328 PROT_PASS0_SAR1_CH12_CH = 429, /* Address 0x40901b00, size 0x00000040 */ 4329 PROT_PASS0_SAR1_CH13_CH = 430, /* Address 0x40901b40, size 0x00000040 */ 4330 PROT_PASS0_SAR1_CH14_CH = 431, /* Address 0x40901b80, size 0x00000040 */ 4331 PROT_PASS0_SAR1_CH15_CH = 432, /* Address 0x40901bc0, size 0x00000040 */ 4332 PROT_PASS0_SAR1_CH16_CH = 433, /* Address 0x40901c00, size 0x00000040 */ 4333 PROT_PASS0_SAR1_CH17_CH = 434, /* Address 0x40901c40, size 0x00000040 */ 4334 PROT_PASS0_SAR1_CH18_CH = 435, /* Address 0x40901c80, size 0x00000040 */ 4335 PROT_PASS0_SAR1_CH19_CH = 436, /* Address 0x40901cc0, size 0x00000040 */ 4336 PROT_PASS0_SAR1_CH20_CH = 437, /* Address 0x40901d00, size 0x00000040 */ 4337 PROT_PASS0_SAR1_CH21_CH = 438, /* Address 0x40901d40, size 0x00000040 */ 4338 PROT_PASS0_SAR1_CH22_CH = 439, /* Address 0x40901d80, size 0x00000040 */ 4339 PROT_PASS0_SAR1_CH23_CH = 440, /* Address 0x40901dc0, size 0x00000040 */ 4340 PROT_PASS0_SAR1_CH24_CH = 441, /* Address 0x40901e00, size 0x00000040 */ 4341 PROT_PASS0_SAR1_CH25_CH = 442, /* Address 0x40901e40, size 0x00000040 */ 4342 PROT_PASS0_SAR1_CH26_CH = 443, /* Address 0x40901e80, size 0x00000040 */ 4343 PROT_PASS0_SAR1_CH27_CH = 444, /* Address 0x40901ec0, size 0x00000040 */ 4344 PROT_PASS0_SAR1_CH28_CH = 445, /* Address 0x40901f00, size 0x00000040 */ 4345 PROT_PASS0_SAR1_CH29_CH = 446, /* Address 0x40901f40, size 0x00000040 */ 4346 PROT_PASS0_SAR1_CH30_CH = 447, /* Address 0x40901f80, size 0x00000040 */ 4347 PROT_PASS0_SAR1_CH31_CH = 448, /* Address 0x40901fc0, size 0x00000040 */ 4348 PROT_PASS0_SAR2_CH0_CH = 449, /* Address 0x40902800, size 0x00000040 */ 4349 PROT_PASS0_SAR2_CH1_CH = 450, /* Address 0x40902840, size 0x00000040 */ 4350 PROT_PASS0_SAR2_CH2_CH = 451, /* Address 0x40902880, size 0x00000040 */ 4351 PROT_PASS0_SAR2_CH3_CH = 452, /* Address 0x409028c0, size 0x00000040 */ 4352 PROT_PASS0_SAR2_CH4_CH = 453, /* Address 0x40902900, size 0x00000040 */ 4353 PROT_PASS0_SAR2_CH5_CH = 454, /* Address 0x40902940, size 0x00000040 */ 4354 PROT_PASS0_SAR2_CH6_CH = 455, /* Address 0x40902980, size 0x00000040 */ 4355 PROT_PASS0_SAR2_CH7_CH = 456, /* Address 0x409029c0, size 0x00000040 */ 4356 PROT_PASS0_TOP = 457 /* Address 0x409f0000, size 0x00001000 */ 4357 } cy_en_prot_region_t; 4358 4359 #endif /* _TVIIBE1M_CONFIG_H_ */ 4360 4361 4362 /* [] END OF FILE */ 4363
