1 /***************************************************************************//** 2 * \file cyhal_triggers_tviibe4m.h 3 * 4 * \brief 5 * TVIIBE4M family HAL triggers header 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYHAL_TRIGGERS_TVIIBE4M_H_ 28 #define _CYHAL_TRIGGERS_TVIIBE4M_H_ 29 30 /** 31 * \addtogroup group_hal_impl_triggers_tviibe4m TVIIBE4M 32 * \ingroup group_hal_impl_triggers 33 * \{ 34 * Trigger connections for tviibe4m 35 */ 36 37 #if defined(__cplusplus) 38 extern "C" { 39 #endif /* __cplusplus */ 40 41 /** \cond INTERNAL */ 42 /** @brief Name of each input trigger. */ 43 typedef enum 44 { 45 _CYHAL_TRIGGER_CPUSS_ZERO = 0, //!< cpuss.zero 46 _CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ0 = 1, //!< canfd[0].tr_dbg_dma_req[0] 47 _CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ1 = 2, //!< canfd[0].tr_dbg_dma_req[1] 48 _CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ2 = 3, //!< canfd[0].tr_dbg_dma_req[2] 49 _CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ3 = 4, //!< canfd[0].tr_dbg_dma_req[3] 50 _CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_REQ0 = 5, //!< canfd[1].tr_dbg_dma_req[0] 51 _CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_REQ1 = 6, //!< canfd[1].tr_dbg_dma_req[1] 52 _CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_REQ2 = 7, //!< canfd[1].tr_dbg_dma_req[2] 53 _CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_REQ3 = 8, //!< canfd[1].tr_dbg_dma_req[3] 54 _CYHAL_TRIGGER_CANFD0_TR_FIFO00 = 9, //!< canfd[0].tr_fifo0[0] 55 _CYHAL_TRIGGER_CANFD0_TR_FIFO01 = 10, //!< canfd[0].tr_fifo0[1] 56 _CYHAL_TRIGGER_CANFD0_TR_FIFO02 = 11, //!< canfd[0].tr_fifo0[2] 57 _CYHAL_TRIGGER_CANFD0_TR_FIFO03 = 12, //!< canfd[0].tr_fifo0[3] 58 _CYHAL_TRIGGER_CANFD1_TR_FIFO00 = 13, //!< canfd[1].tr_fifo0[0] 59 _CYHAL_TRIGGER_CANFD1_TR_FIFO01 = 14, //!< canfd[1].tr_fifo0[1] 60 _CYHAL_TRIGGER_CANFD1_TR_FIFO02 = 15, //!< canfd[1].tr_fifo0[2] 61 _CYHAL_TRIGGER_CANFD1_TR_FIFO03 = 16, //!< canfd[1].tr_fifo0[3] 62 _CYHAL_TRIGGER_CANFD0_TR_FIFO10 = 17, //!< canfd[0].tr_fifo1[0] 63 _CYHAL_TRIGGER_CANFD0_TR_FIFO11 = 18, //!< canfd[0].tr_fifo1[1] 64 _CYHAL_TRIGGER_CANFD0_TR_FIFO12 = 19, //!< canfd[0].tr_fifo1[2] 65 _CYHAL_TRIGGER_CANFD0_TR_FIFO13 = 20, //!< canfd[0].tr_fifo1[3] 66 _CYHAL_TRIGGER_CANFD1_TR_FIFO10 = 21, //!< canfd[1].tr_fifo1[0] 67 _CYHAL_TRIGGER_CANFD1_TR_FIFO11 = 22, //!< canfd[1].tr_fifo1[1] 68 _CYHAL_TRIGGER_CANFD1_TR_FIFO12 = 23, //!< canfd[1].tr_fifo1[2] 69 _CYHAL_TRIGGER_CANFD1_TR_FIFO13 = 24, //!< canfd[1].tr_fifo1[3] 70 _CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT0 = 25, //!< canfd[0].tr_tmp_rtp_out[0] 71 _CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT1 = 26, //!< canfd[0].tr_tmp_rtp_out[1] 72 _CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT2 = 27, //!< canfd[0].tr_tmp_rtp_out[2] 73 _CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT3 = 28, //!< canfd[0].tr_tmp_rtp_out[3] 74 _CYHAL_TRIGGER_CANFD1_TR_TMP_RTP_OUT0 = 29, //!< canfd[1].tr_tmp_rtp_out[0] 75 _CYHAL_TRIGGER_CANFD1_TR_TMP_RTP_OUT1 = 30, //!< canfd[1].tr_tmp_rtp_out[1] 76 _CYHAL_TRIGGER_CANFD1_TR_TMP_RTP_OUT2 = 31, //!< canfd[1].tr_tmp_rtp_out[2] 77 _CYHAL_TRIGGER_CANFD1_TR_TMP_RTP_OUT3 = 32, //!< canfd[1].tr_tmp_rtp_out[3] 78 _CYHAL_TRIGGER_CPUSS_CTI_TR_OUT0 = 33, //!< cpuss.cti_tr_out[0] 79 _CYHAL_TRIGGER_CPUSS_CTI_TR_OUT1 = 34, //!< cpuss.cti_tr_out[1] 80 _CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT0 = 35, //!< cpuss.dmac_tr_out[0] 81 _CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT1 = 36, //!< cpuss.dmac_tr_out[1] 82 _CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT2 = 37, //!< cpuss.dmac_tr_out[2] 83 _CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT3 = 38, //!< cpuss.dmac_tr_out[3] 84 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT0 = 39, //!< cpuss.dw0_tr_out[0] 85 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT1 = 40, //!< cpuss.dw0_tr_out[1] 86 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT2 = 41, //!< cpuss.dw0_tr_out[2] 87 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT3 = 42, //!< cpuss.dw0_tr_out[3] 88 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT4 = 43, //!< cpuss.dw0_tr_out[4] 89 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT5 = 44, //!< cpuss.dw0_tr_out[5] 90 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT6 = 45, //!< cpuss.dw0_tr_out[6] 91 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT7 = 46, //!< cpuss.dw0_tr_out[7] 92 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT8 = 47, //!< cpuss.dw0_tr_out[8] 93 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT9 = 48, //!< cpuss.dw0_tr_out[9] 94 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT10 = 49, //!< cpuss.dw0_tr_out[10] 95 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT11 = 50, //!< cpuss.dw0_tr_out[11] 96 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT12 = 51, //!< cpuss.dw0_tr_out[12] 97 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT13 = 52, //!< cpuss.dw0_tr_out[13] 98 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT14 = 53, //!< cpuss.dw0_tr_out[14] 99 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT15 = 54, //!< cpuss.dw0_tr_out[15] 100 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT16 = 55, //!< cpuss.dw0_tr_out[16] 101 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT17 = 56, //!< cpuss.dw0_tr_out[17] 102 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT18 = 57, //!< cpuss.dw0_tr_out[18] 103 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT19 = 58, //!< cpuss.dw0_tr_out[19] 104 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT20 = 59, //!< cpuss.dw0_tr_out[20] 105 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT21 = 60, //!< cpuss.dw0_tr_out[21] 106 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT22 = 61, //!< cpuss.dw0_tr_out[22] 107 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT23 = 62, //!< cpuss.dw0_tr_out[23] 108 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT24 = 63, //!< cpuss.dw0_tr_out[24] 109 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT25 = 64, //!< cpuss.dw0_tr_out[25] 110 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT26 = 65, //!< cpuss.dw0_tr_out[26] 111 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT27 = 66, //!< cpuss.dw0_tr_out[27] 112 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT28 = 67, //!< cpuss.dw0_tr_out[28] 113 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT29 = 68, //!< cpuss.dw0_tr_out[29] 114 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT30 = 69, //!< cpuss.dw0_tr_out[30] 115 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT31 = 70, //!< cpuss.dw0_tr_out[31] 116 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT32 = 71, //!< cpuss.dw0_tr_out[32] 117 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT33 = 72, //!< cpuss.dw0_tr_out[33] 118 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT34 = 73, //!< cpuss.dw0_tr_out[34] 119 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT35 = 74, //!< cpuss.dw0_tr_out[35] 120 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT36 = 75, //!< cpuss.dw0_tr_out[36] 121 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT37 = 76, //!< cpuss.dw0_tr_out[37] 122 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT38 = 77, //!< cpuss.dw0_tr_out[38] 123 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT39 = 78, //!< cpuss.dw0_tr_out[39] 124 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT40 = 79, //!< cpuss.dw0_tr_out[40] 125 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT41 = 80, //!< cpuss.dw0_tr_out[41] 126 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT42 = 81, //!< cpuss.dw0_tr_out[42] 127 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT43 = 82, //!< cpuss.dw0_tr_out[43] 128 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT44 = 83, //!< cpuss.dw0_tr_out[44] 129 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT45 = 84, //!< cpuss.dw0_tr_out[45] 130 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT46 = 85, //!< cpuss.dw0_tr_out[46] 131 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT47 = 86, //!< cpuss.dw0_tr_out[47] 132 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT48 = 87, //!< cpuss.dw0_tr_out[48] 133 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT49 = 88, //!< cpuss.dw0_tr_out[49] 134 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT50 = 89, //!< cpuss.dw0_tr_out[50] 135 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT51 = 90, //!< cpuss.dw0_tr_out[51] 136 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT52 = 91, //!< cpuss.dw0_tr_out[52] 137 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT53 = 92, //!< cpuss.dw0_tr_out[53] 138 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT54 = 93, //!< cpuss.dw0_tr_out[54] 139 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT55 = 94, //!< cpuss.dw0_tr_out[55] 140 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT56 = 95, //!< cpuss.dw0_tr_out[56] 141 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT57 = 96, //!< cpuss.dw0_tr_out[57] 142 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT58 = 97, //!< cpuss.dw0_tr_out[58] 143 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT59 = 98, //!< cpuss.dw0_tr_out[59] 144 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT60 = 99, //!< cpuss.dw0_tr_out[60] 145 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT61 = 100, //!< cpuss.dw0_tr_out[61] 146 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT62 = 101, //!< cpuss.dw0_tr_out[62] 147 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT63 = 102, //!< cpuss.dw0_tr_out[63] 148 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT64 = 103, //!< cpuss.dw0_tr_out[64] 149 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT65 = 104, //!< cpuss.dw0_tr_out[65] 150 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT66 = 105, //!< cpuss.dw0_tr_out[66] 151 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT67 = 106, //!< cpuss.dw0_tr_out[67] 152 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT68 = 107, //!< cpuss.dw0_tr_out[68] 153 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT69 = 108, //!< cpuss.dw0_tr_out[69] 154 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT70 = 109, //!< cpuss.dw0_tr_out[70] 155 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT71 = 110, //!< cpuss.dw0_tr_out[71] 156 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT72 = 111, //!< cpuss.dw0_tr_out[72] 157 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT73 = 112, //!< cpuss.dw0_tr_out[73] 158 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT74 = 113, //!< cpuss.dw0_tr_out[74] 159 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT75 = 114, //!< cpuss.dw0_tr_out[75] 160 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT76 = 115, //!< cpuss.dw0_tr_out[76] 161 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT77 = 116, //!< cpuss.dw0_tr_out[77] 162 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT78 = 117, //!< cpuss.dw0_tr_out[78] 163 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT79 = 118, //!< cpuss.dw0_tr_out[79] 164 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT80 = 119, //!< cpuss.dw0_tr_out[80] 165 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT81 = 120, //!< cpuss.dw0_tr_out[81] 166 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT82 = 121, //!< cpuss.dw0_tr_out[82] 167 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT83 = 122, //!< cpuss.dw0_tr_out[83] 168 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT84 = 123, //!< cpuss.dw0_tr_out[84] 169 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT85 = 124, //!< cpuss.dw0_tr_out[85] 170 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT86 = 125, //!< cpuss.dw0_tr_out[86] 171 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT87 = 126, //!< cpuss.dw0_tr_out[87] 172 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT88 = 127, //!< cpuss.dw0_tr_out[88] 173 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT89 = 128, //!< cpuss.dw0_tr_out[89] 174 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT90 = 129, //!< cpuss.dw0_tr_out[90] 175 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT91 = 130, //!< cpuss.dw0_tr_out[91] 176 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT0 = 131, //!< cpuss.dw1_tr_out[0] 177 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT1 = 132, //!< cpuss.dw1_tr_out[1] 178 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT2 = 133, //!< cpuss.dw1_tr_out[2] 179 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT3 = 134, //!< cpuss.dw1_tr_out[3] 180 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT4 = 135, //!< cpuss.dw1_tr_out[4] 181 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT5 = 136, //!< cpuss.dw1_tr_out[5] 182 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT6 = 137, //!< cpuss.dw1_tr_out[6] 183 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT7 = 138, //!< cpuss.dw1_tr_out[7] 184 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT8 = 139, //!< cpuss.dw1_tr_out[8] 185 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT9 = 140, //!< cpuss.dw1_tr_out[9] 186 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT10 = 141, //!< cpuss.dw1_tr_out[10] 187 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT11 = 142, //!< cpuss.dw1_tr_out[11] 188 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT12 = 143, //!< cpuss.dw1_tr_out[12] 189 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT13 = 144, //!< cpuss.dw1_tr_out[13] 190 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT14 = 145, //!< cpuss.dw1_tr_out[14] 191 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT15 = 146, //!< cpuss.dw1_tr_out[15] 192 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT16 = 147, //!< cpuss.dw1_tr_out[16] 193 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT17 = 148, //!< cpuss.dw1_tr_out[17] 194 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT18 = 149, //!< cpuss.dw1_tr_out[18] 195 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT19 = 150, //!< cpuss.dw1_tr_out[19] 196 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT20 = 151, //!< cpuss.dw1_tr_out[20] 197 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT21 = 152, //!< cpuss.dw1_tr_out[21] 198 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT22 = 153, //!< cpuss.dw1_tr_out[22] 199 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT23 = 154, //!< cpuss.dw1_tr_out[23] 200 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT24 = 155, //!< cpuss.dw1_tr_out[24] 201 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT25 = 156, //!< cpuss.dw1_tr_out[25] 202 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT26 = 157, //!< cpuss.dw1_tr_out[26] 203 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT27 = 158, //!< cpuss.dw1_tr_out[27] 204 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT28 = 159, //!< cpuss.dw1_tr_out[28] 205 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT29 = 160, //!< cpuss.dw1_tr_out[29] 206 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT30 = 161, //!< cpuss.dw1_tr_out[30] 207 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT31 = 162, //!< cpuss.dw1_tr_out[31] 208 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT32 = 163, //!< cpuss.dw1_tr_out[32] 209 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT33 = 164, //!< cpuss.dw1_tr_out[33] 210 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT34 = 165, //!< cpuss.dw1_tr_out[34] 211 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT35 = 166, //!< cpuss.dw1_tr_out[35] 212 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT36 = 167, //!< cpuss.dw1_tr_out[36] 213 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT37 = 168, //!< cpuss.dw1_tr_out[37] 214 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT38 = 169, //!< cpuss.dw1_tr_out[38] 215 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT39 = 170, //!< cpuss.dw1_tr_out[39] 216 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT40 = 171, //!< cpuss.dw1_tr_out[40] 217 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT41 = 172, //!< cpuss.dw1_tr_out[41] 218 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT42 = 173, //!< cpuss.dw1_tr_out[42] 219 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT43 = 174, //!< cpuss.dw1_tr_out[43] 220 _CYHAL_TRIGGER_CPUSS_TR_FAULT0 = 175, //!< cpuss.tr_fault[0] 221 _CYHAL_TRIGGER_CPUSS_TR_FAULT1 = 176, //!< cpuss.tr_fault[1] 222 _CYHAL_TRIGGER_CPUSS_TR_FAULT2 = 177, //!< cpuss.tr_fault[2] 223 _CYHAL_TRIGGER_CPUSS_TR_FAULT3 = 178, //!< cpuss.tr_fault[3] 224 _CYHAL_TRIGGER_CXPI0_TR_RX_REQ0 = 179, //!< cxpi[0].tr_rx_req[0] 225 _CYHAL_TRIGGER_CXPI0_TR_RX_REQ1 = 180, //!< cxpi[0].tr_rx_req[1] 226 _CYHAL_TRIGGER_CXPI0_TR_RX_REQ2 = 181, //!< cxpi[0].tr_rx_req[2] 227 _CYHAL_TRIGGER_CXPI0_TR_RX_REQ3 = 182, //!< cxpi[0].tr_rx_req[3] 228 _CYHAL_TRIGGER_CXPI0_TR_TX_REQ0 = 183, //!< cxpi[0].tr_tx_req[0] 229 _CYHAL_TRIGGER_CXPI0_TR_TX_REQ1 = 184, //!< cxpi[0].tr_tx_req[1] 230 _CYHAL_TRIGGER_CXPI0_TR_TX_REQ2 = 185, //!< cxpi[0].tr_tx_req[2] 231 _CYHAL_TRIGGER_CXPI0_TR_TX_REQ3 = 186, //!< cxpi[0].tr_tx_req[3] 232 _CYHAL_TRIGGER_EVTGEN0_TR_OUT0 = 187, //!< evtgen[0].tr_out[0] 233 _CYHAL_TRIGGER_EVTGEN0_TR_OUT1 = 188, //!< evtgen[0].tr_out[1] 234 _CYHAL_TRIGGER_EVTGEN0_TR_OUT2 = 189, //!< evtgen[0].tr_out[2] 235 _CYHAL_TRIGGER_EVTGEN0_TR_OUT3 = 190, //!< evtgen[0].tr_out[3] 236 _CYHAL_TRIGGER_EVTGEN0_TR_OUT4 = 191, //!< evtgen[0].tr_out[4] 237 _CYHAL_TRIGGER_EVTGEN0_TR_OUT5 = 192, //!< evtgen[0].tr_out[5] 238 _CYHAL_TRIGGER_EVTGEN0_TR_OUT6 = 193, //!< evtgen[0].tr_out[6] 239 _CYHAL_TRIGGER_EVTGEN0_TR_OUT7 = 194, //!< evtgen[0].tr_out[7] 240 _CYHAL_TRIGGER_EVTGEN0_TR_OUT8 = 195, //!< evtgen[0].tr_out[8] 241 _CYHAL_TRIGGER_EVTGEN0_TR_OUT9 = 196, //!< evtgen[0].tr_out[9] 242 _CYHAL_TRIGGER_EVTGEN0_TR_OUT10 = 197, //!< evtgen[0].tr_out[10] 243 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE0 = 198, //!< pass[0].tr_sar_ch_done[0] 244 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE1 = 199, //!< pass[0].tr_sar_ch_done[1] 245 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE2 = 200, //!< pass[0].tr_sar_ch_done[2] 246 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE3 = 201, //!< pass[0].tr_sar_ch_done[3] 247 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE4 = 202, //!< pass[0].tr_sar_ch_done[4] 248 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE5 = 203, //!< pass[0].tr_sar_ch_done[5] 249 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE6 = 204, //!< pass[0].tr_sar_ch_done[6] 250 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE7 = 205, //!< pass[0].tr_sar_ch_done[7] 251 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE8 = 206, //!< pass[0].tr_sar_ch_done[8] 252 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE9 = 207, //!< pass[0].tr_sar_ch_done[9] 253 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE10 = 208, //!< pass[0].tr_sar_ch_done[10] 254 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE11 = 209, //!< pass[0].tr_sar_ch_done[11] 255 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE12 = 210, //!< pass[0].tr_sar_ch_done[12] 256 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE13 = 211, //!< pass[0].tr_sar_ch_done[13] 257 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE14 = 212, //!< pass[0].tr_sar_ch_done[14] 258 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE15 = 213, //!< pass[0].tr_sar_ch_done[15] 259 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE16 = 214, //!< pass[0].tr_sar_ch_done[16] 260 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE17 = 215, //!< pass[0].tr_sar_ch_done[17] 261 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE18 = 216, //!< pass[0].tr_sar_ch_done[18] 262 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE19 = 217, //!< pass[0].tr_sar_ch_done[19] 263 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE20 = 218, //!< pass[0].tr_sar_ch_done[20] 264 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE21 = 219, //!< pass[0].tr_sar_ch_done[21] 265 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE22 = 220, //!< pass[0].tr_sar_ch_done[22] 266 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE23 = 221, //!< pass[0].tr_sar_ch_done[23] 267 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE32 = 222, //!< pass[0].tr_sar_ch_done[32] 268 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE33 = 223, //!< pass[0].tr_sar_ch_done[33] 269 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE34 = 224, //!< pass[0].tr_sar_ch_done[34] 270 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE35 = 225, //!< pass[0].tr_sar_ch_done[35] 271 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE36 = 226, //!< pass[0].tr_sar_ch_done[36] 272 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE37 = 227, //!< pass[0].tr_sar_ch_done[37] 273 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE38 = 228, //!< pass[0].tr_sar_ch_done[38] 274 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE39 = 229, //!< pass[0].tr_sar_ch_done[39] 275 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE40 = 230, //!< pass[0].tr_sar_ch_done[40] 276 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE41 = 231, //!< pass[0].tr_sar_ch_done[41] 277 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE42 = 232, //!< pass[0].tr_sar_ch_done[42] 278 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE43 = 233, //!< pass[0].tr_sar_ch_done[43] 279 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE44 = 234, //!< pass[0].tr_sar_ch_done[44] 280 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE45 = 235, //!< pass[0].tr_sar_ch_done[45] 281 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE46 = 236, //!< pass[0].tr_sar_ch_done[46] 282 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE47 = 237, //!< pass[0].tr_sar_ch_done[47] 283 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE48 = 238, //!< pass[0].tr_sar_ch_done[48] 284 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE49 = 239, //!< pass[0].tr_sar_ch_done[49] 285 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE50 = 240, //!< pass[0].tr_sar_ch_done[50] 286 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE51 = 241, //!< pass[0].tr_sar_ch_done[51] 287 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE52 = 242, //!< pass[0].tr_sar_ch_done[52] 288 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE53 = 243, //!< pass[0].tr_sar_ch_done[53] 289 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE54 = 244, //!< pass[0].tr_sar_ch_done[54] 290 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE55 = 245, //!< pass[0].tr_sar_ch_done[55] 291 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE56 = 246, //!< pass[0].tr_sar_ch_done[56] 292 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE57 = 247, //!< pass[0].tr_sar_ch_done[57] 293 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE58 = 248, //!< pass[0].tr_sar_ch_done[58] 294 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE59 = 249, //!< pass[0].tr_sar_ch_done[59] 295 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE60 = 250, //!< pass[0].tr_sar_ch_done[60] 296 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE61 = 251, //!< pass[0].tr_sar_ch_done[61] 297 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE62 = 252, //!< pass[0].tr_sar_ch_done[62] 298 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE63 = 253, //!< pass[0].tr_sar_ch_done[63] 299 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE64 = 254, //!< pass[0].tr_sar_ch_done[64] 300 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE65 = 255, //!< pass[0].tr_sar_ch_done[65] 301 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE66 = 256, //!< pass[0].tr_sar_ch_done[66] 302 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE67 = 257, //!< pass[0].tr_sar_ch_done[67] 303 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE68 = 258, //!< pass[0].tr_sar_ch_done[68] 304 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE69 = 259, //!< pass[0].tr_sar_ch_done[69] 305 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE70 = 260, //!< pass[0].tr_sar_ch_done[70] 306 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE71 = 261, //!< pass[0].tr_sar_ch_done[71] 307 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO0 = 262, //!< pass[0].tr_sar_ch_rangevio[0] 308 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO1 = 263, //!< pass[0].tr_sar_ch_rangevio[1] 309 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO2 = 264, //!< pass[0].tr_sar_ch_rangevio[2] 310 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO3 = 265, //!< pass[0].tr_sar_ch_rangevio[3] 311 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO4 = 266, //!< pass[0].tr_sar_ch_rangevio[4] 312 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO5 = 267, //!< pass[0].tr_sar_ch_rangevio[5] 313 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO6 = 268, //!< pass[0].tr_sar_ch_rangevio[6] 314 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO7 = 269, //!< pass[0].tr_sar_ch_rangevio[7] 315 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO8 = 270, //!< pass[0].tr_sar_ch_rangevio[8] 316 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO9 = 271, //!< pass[0].tr_sar_ch_rangevio[9] 317 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO10 = 272, //!< pass[0].tr_sar_ch_rangevio[10] 318 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO11 = 273, //!< pass[0].tr_sar_ch_rangevio[11] 319 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO12 = 274, //!< pass[0].tr_sar_ch_rangevio[12] 320 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO13 = 275, //!< pass[0].tr_sar_ch_rangevio[13] 321 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO14 = 276, //!< pass[0].tr_sar_ch_rangevio[14] 322 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO15 = 277, //!< pass[0].tr_sar_ch_rangevio[15] 323 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO16 = 278, //!< pass[0].tr_sar_ch_rangevio[16] 324 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO17 = 279, //!< pass[0].tr_sar_ch_rangevio[17] 325 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO18 = 280, //!< pass[0].tr_sar_ch_rangevio[18] 326 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO19 = 281, //!< pass[0].tr_sar_ch_rangevio[19] 327 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO20 = 282, //!< pass[0].tr_sar_ch_rangevio[20] 328 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO21 = 283, //!< pass[0].tr_sar_ch_rangevio[21] 329 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO22 = 284, //!< pass[0].tr_sar_ch_rangevio[22] 330 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO23 = 285, //!< pass[0].tr_sar_ch_rangevio[23] 331 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO32 = 286, //!< pass[0].tr_sar_ch_rangevio[32] 332 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO33 = 287, //!< pass[0].tr_sar_ch_rangevio[33] 333 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO34 = 288, //!< pass[0].tr_sar_ch_rangevio[34] 334 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO35 = 289, //!< pass[0].tr_sar_ch_rangevio[35] 335 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO36 = 290, //!< pass[0].tr_sar_ch_rangevio[36] 336 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO37 = 291, //!< pass[0].tr_sar_ch_rangevio[37] 337 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO38 = 292, //!< pass[0].tr_sar_ch_rangevio[38] 338 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO39 = 293, //!< pass[0].tr_sar_ch_rangevio[39] 339 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO40 = 294, //!< pass[0].tr_sar_ch_rangevio[40] 340 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO41 = 295, //!< pass[0].tr_sar_ch_rangevio[41] 341 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO42 = 296, //!< pass[0].tr_sar_ch_rangevio[42] 342 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO43 = 297, //!< pass[0].tr_sar_ch_rangevio[43] 343 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO44 = 298, //!< pass[0].tr_sar_ch_rangevio[44] 344 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO45 = 299, //!< pass[0].tr_sar_ch_rangevio[45] 345 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO46 = 300, //!< pass[0].tr_sar_ch_rangevio[46] 346 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO47 = 301, //!< pass[0].tr_sar_ch_rangevio[47] 347 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO48 = 302, //!< pass[0].tr_sar_ch_rangevio[48] 348 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO49 = 303, //!< pass[0].tr_sar_ch_rangevio[49] 349 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO50 = 304, //!< pass[0].tr_sar_ch_rangevio[50] 350 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO51 = 305, //!< pass[0].tr_sar_ch_rangevio[51] 351 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO52 = 306, //!< pass[0].tr_sar_ch_rangevio[52] 352 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO53 = 307, //!< pass[0].tr_sar_ch_rangevio[53] 353 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO54 = 308, //!< pass[0].tr_sar_ch_rangevio[54] 354 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO55 = 309, //!< pass[0].tr_sar_ch_rangevio[55] 355 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO56 = 310, //!< pass[0].tr_sar_ch_rangevio[56] 356 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO57 = 311, //!< pass[0].tr_sar_ch_rangevio[57] 357 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO58 = 312, //!< pass[0].tr_sar_ch_rangevio[58] 358 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO59 = 313, //!< pass[0].tr_sar_ch_rangevio[59] 359 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO60 = 314, //!< pass[0].tr_sar_ch_rangevio[60] 360 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO61 = 315, //!< pass[0].tr_sar_ch_rangevio[61] 361 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO62 = 316, //!< pass[0].tr_sar_ch_rangevio[62] 362 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO63 = 317, //!< pass[0].tr_sar_ch_rangevio[63] 363 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO64 = 318, //!< pass[0].tr_sar_ch_rangevio[64] 364 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO65 = 319, //!< pass[0].tr_sar_ch_rangevio[65] 365 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO66 = 320, //!< pass[0].tr_sar_ch_rangevio[66] 366 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO67 = 321, //!< pass[0].tr_sar_ch_rangevio[67] 367 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO68 = 322, //!< pass[0].tr_sar_ch_rangevio[68] 368 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO69 = 323, //!< pass[0].tr_sar_ch_rangevio[69] 369 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO70 = 324, //!< pass[0].tr_sar_ch_rangevio[70] 370 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO71 = 325, //!< pass[0].tr_sar_ch_rangevio[71] 371 _CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT0 = 326, //!< pass[0].tr_sar_gen_out[0] 372 _CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT1 = 327, //!< pass[0].tr_sar_gen_out[1] 373 _CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT2 = 328, //!< pass[0].tr_sar_gen_out[2] 374 _CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT3 = 329, //!< pass[0].tr_sar_gen_out[3] 375 _CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT4 = 330, //!< pass[0].tr_sar_gen_out[4] 376 _CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT5 = 331, //!< pass[0].tr_sar_gen_out[5] 377 _CYHAL_TRIGGER_PERI_TR_IO_INPUT0 = 332, //!< peri.tr_io_input[0] 378 _CYHAL_TRIGGER_PERI_TR_IO_INPUT1 = 333, //!< peri.tr_io_input[1] 379 _CYHAL_TRIGGER_PERI_TR_IO_INPUT2 = 334, //!< peri.tr_io_input[2] 380 _CYHAL_TRIGGER_PERI_TR_IO_INPUT3 = 335, //!< peri.tr_io_input[3] 381 _CYHAL_TRIGGER_PERI_TR_IO_INPUT4 = 336, //!< peri.tr_io_input[4] 382 _CYHAL_TRIGGER_PERI_TR_IO_INPUT5 = 337, //!< peri.tr_io_input[5] 383 _CYHAL_TRIGGER_PERI_TR_IO_INPUT6 = 338, //!< peri.tr_io_input[6] 384 _CYHAL_TRIGGER_PERI_TR_IO_INPUT7 = 339, //!< peri.tr_io_input[7] 385 _CYHAL_TRIGGER_PERI_TR_IO_INPUT8 = 340, //!< peri.tr_io_input[8] 386 _CYHAL_TRIGGER_PERI_TR_IO_INPUT9 = 341, //!< peri.tr_io_input[9] 387 _CYHAL_TRIGGER_PERI_TR_IO_INPUT10 = 342, //!< peri.tr_io_input[10] 388 _CYHAL_TRIGGER_PERI_TR_IO_INPUT11 = 343, //!< peri.tr_io_input[11] 389 _CYHAL_TRIGGER_PERI_TR_IO_INPUT12 = 344, //!< peri.tr_io_input[12] 390 _CYHAL_TRIGGER_PERI_TR_IO_INPUT13 = 345, //!< peri.tr_io_input[13] 391 _CYHAL_TRIGGER_PERI_TR_IO_INPUT14 = 346, //!< peri.tr_io_input[14] 392 _CYHAL_TRIGGER_PERI_TR_IO_INPUT15 = 347, //!< peri.tr_io_input[15] 393 _CYHAL_TRIGGER_PERI_TR_IO_INPUT16 = 348, //!< peri.tr_io_input[16] 394 _CYHAL_TRIGGER_PERI_TR_IO_INPUT17 = 349, //!< peri.tr_io_input[17] 395 _CYHAL_TRIGGER_PERI_TR_IO_INPUT18 = 350, //!< peri.tr_io_input[18] 396 _CYHAL_TRIGGER_PERI_TR_IO_INPUT19 = 351, //!< peri.tr_io_input[19] 397 _CYHAL_TRIGGER_PERI_TR_IO_INPUT20 = 352, //!< peri.tr_io_input[20] 398 _CYHAL_TRIGGER_PERI_TR_IO_INPUT21 = 353, //!< peri.tr_io_input[21] 399 _CYHAL_TRIGGER_PERI_TR_IO_INPUT22 = 354, //!< peri.tr_io_input[22] 400 _CYHAL_TRIGGER_PERI_TR_IO_INPUT23 = 355, //!< peri.tr_io_input[23] 401 _CYHAL_TRIGGER_PERI_TR_IO_INPUT24 = 356, //!< peri.tr_io_input[24] 402 _CYHAL_TRIGGER_PERI_TR_IO_INPUT25 = 357, //!< peri.tr_io_input[25] 403 _CYHAL_TRIGGER_PERI_TR_IO_INPUT26 = 358, //!< peri.tr_io_input[26] 404 _CYHAL_TRIGGER_PERI_TR_IO_INPUT27 = 359, //!< peri.tr_io_input[27] 405 _CYHAL_TRIGGER_PERI_TR_IO_INPUT28 = 360, //!< peri.tr_io_input[28] 406 _CYHAL_TRIGGER_PERI_TR_IO_INPUT29 = 361, //!< peri.tr_io_input[29] 407 _CYHAL_TRIGGER_PERI_TR_IO_INPUT30 = 362, //!< peri.tr_io_input[30] 408 _CYHAL_TRIGGER_PERI_TR_IO_INPUT31 = 363, //!< peri.tr_io_input[31] 409 _CYHAL_TRIGGER_SCB0_TR_I2C_SCL_FILTERED = 364, //!< scb[0].tr_i2c_scl_filtered 410 _CYHAL_TRIGGER_SCB1_TR_I2C_SCL_FILTERED = 365, //!< scb[1].tr_i2c_scl_filtered 411 _CYHAL_TRIGGER_SCB2_TR_I2C_SCL_FILTERED = 366, //!< scb[2].tr_i2c_scl_filtered 412 _CYHAL_TRIGGER_SCB3_TR_I2C_SCL_FILTERED = 367, //!< scb[3].tr_i2c_scl_filtered 413 _CYHAL_TRIGGER_SCB4_TR_I2C_SCL_FILTERED = 368, //!< scb[4].tr_i2c_scl_filtered 414 _CYHAL_TRIGGER_SCB5_TR_I2C_SCL_FILTERED = 369, //!< scb[5].tr_i2c_scl_filtered 415 _CYHAL_TRIGGER_SCB6_TR_I2C_SCL_FILTERED = 370, //!< scb[6].tr_i2c_scl_filtered 416 _CYHAL_TRIGGER_SCB7_TR_I2C_SCL_FILTERED = 371, //!< scb[7].tr_i2c_scl_filtered 417 _CYHAL_TRIGGER_SCB0_TR_RX_REQ = 372, //!< scb[0].tr_rx_req 418 _CYHAL_TRIGGER_SCB1_TR_RX_REQ = 373, //!< scb[1].tr_rx_req 419 _CYHAL_TRIGGER_SCB2_TR_RX_REQ = 374, //!< scb[2].tr_rx_req 420 _CYHAL_TRIGGER_SCB3_TR_RX_REQ = 375, //!< scb[3].tr_rx_req 421 _CYHAL_TRIGGER_SCB4_TR_RX_REQ = 376, //!< scb[4].tr_rx_req 422 _CYHAL_TRIGGER_SCB5_TR_RX_REQ = 377, //!< scb[5].tr_rx_req 423 _CYHAL_TRIGGER_SCB6_TR_RX_REQ = 378, //!< scb[6].tr_rx_req 424 _CYHAL_TRIGGER_SCB7_TR_RX_REQ = 379, //!< scb[7].tr_rx_req 425 _CYHAL_TRIGGER_SCB0_TR_TX_REQ = 380, //!< scb[0].tr_tx_req 426 _CYHAL_TRIGGER_SCB1_TR_TX_REQ = 381, //!< scb[1].tr_tx_req 427 _CYHAL_TRIGGER_SCB2_TR_TX_REQ = 382, //!< scb[2].tr_tx_req 428 _CYHAL_TRIGGER_SCB3_TR_TX_REQ = 383, //!< scb[3].tr_tx_req 429 _CYHAL_TRIGGER_SCB4_TR_TX_REQ = 384, //!< scb[4].tr_tx_req 430 _CYHAL_TRIGGER_SCB5_TR_TX_REQ = 385, //!< scb[5].tr_tx_req 431 _CYHAL_TRIGGER_SCB6_TR_TX_REQ = 386, //!< scb[6].tr_tx_req 432 _CYHAL_TRIGGER_SCB7_TR_TX_REQ = 387, //!< scb[7].tr_tx_req 433 _CYHAL_TRIGGER_TCPWM0_TR_OUT00 = 388, //!< tcpwm[0].tr_out0[0] 434 _CYHAL_TRIGGER_TCPWM0_TR_OUT01 = 389, //!< tcpwm[0].tr_out0[1] 435 _CYHAL_TRIGGER_TCPWM0_TR_OUT02 = 390, //!< tcpwm[0].tr_out0[2] 436 _CYHAL_TRIGGER_TCPWM0_TR_OUT03 = 391, //!< tcpwm[0].tr_out0[3] 437 _CYHAL_TRIGGER_TCPWM0_TR_OUT04 = 392, //!< tcpwm[0].tr_out0[4] 438 _CYHAL_TRIGGER_TCPWM0_TR_OUT05 = 393, //!< tcpwm[0].tr_out0[5] 439 _CYHAL_TRIGGER_TCPWM0_TR_OUT06 = 394, //!< tcpwm[0].tr_out0[6] 440 _CYHAL_TRIGGER_TCPWM0_TR_OUT07 = 395, //!< tcpwm[0].tr_out0[7] 441 _CYHAL_TRIGGER_TCPWM0_TR_OUT08 = 396, //!< tcpwm[0].tr_out0[8] 442 _CYHAL_TRIGGER_TCPWM0_TR_OUT09 = 397, //!< tcpwm[0].tr_out0[9] 443 _CYHAL_TRIGGER_TCPWM0_TR_OUT010 = 398, //!< tcpwm[0].tr_out0[10] 444 _CYHAL_TRIGGER_TCPWM0_TR_OUT011 = 399, //!< tcpwm[0].tr_out0[11] 445 _CYHAL_TRIGGER_TCPWM0_TR_OUT012 = 400, //!< tcpwm[0].tr_out0[12] 446 _CYHAL_TRIGGER_TCPWM0_TR_OUT013 = 401, //!< tcpwm[0].tr_out0[13] 447 _CYHAL_TRIGGER_TCPWM0_TR_OUT014 = 402, //!< tcpwm[0].tr_out0[14] 448 _CYHAL_TRIGGER_TCPWM0_TR_OUT015 = 403, //!< tcpwm[0].tr_out0[15] 449 _CYHAL_TRIGGER_TCPWM0_TR_OUT016 = 404, //!< tcpwm[0].tr_out0[16] 450 _CYHAL_TRIGGER_TCPWM0_TR_OUT017 = 405, //!< tcpwm[0].tr_out0[17] 451 _CYHAL_TRIGGER_TCPWM0_TR_OUT018 = 406, //!< tcpwm[0].tr_out0[18] 452 _CYHAL_TRIGGER_TCPWM0_TR_OUT019 = 407, //!< tcpwm[0].tr_out0[19] 453 _CYHAL_TRIGGER_TCPWM0_TR_OUT020 = 408, //!< tcpwm[0].tr_out0[20] 454 _CYHAL_TRIGGER_TCPWM0_TR_OUT021 = 409, //!< tcpwm[0].tr_out0[21] 455 _CYHAL_TRIGGER_TCPWM0_TR_OUT022 = 410, //!< tcpwm[0].tr_out0[22] 456 _CYHAL_TRIGGER_TCPWM0_TR_OUT023 = 411, //!< tcpwm[0].tr_out0[23] 457 _CYHAL_TRIGGER_TCPWM0_TR_OUT024 = 412, //!< tcpwm[0].tr_out0[24] 458 _CYHAL_TRIGGER_TCPWM0_TR_OUT025 = 413, //!< tcpwm[0].tr_out0[25] 459 _CYHAL_TRIGGER_TCPWM0_TR_OUT026 = 414, //!< tcpwm[0].tr_out0[26] 460 _CYHAL_TRIGGER_TCPWM0_TR_OUT027 = 415, //!< tcpwm[0].tr_out0[27] 461 _CYHAL_TRIGGER_TCPWM0_TR_OUT028 = 416, //!< tcpwm[0].tr_out0[28] 462 _CYHAL_TRIGGER_TCPWM0_TR_OUT029 = 417, //!< tcpwm[0].tr_out0[29] 463 _CYHAL_TRIGGER_TCPWM0_TR_OUT030 = 418, //!< tcpwm[0].tr_out0[30] 464 _CYHAL_TRIGGER_TCPWM0_TR_OUT031 = 419, //!< tcpwm[0].tr_out0[31] 465 _CYHAL_TRIGGER_TCPWM0_TR_OUT032 = 420, //!< tcpwm[0].tr_out0[32] 466 _CYHAL_TRIGGER_TCPWM0_TR_OUT033 = 421, //!< tcpwm[0].tr_out0[33] 467 _CYHAL_TRIGGER_TCPWM0_TR_OUT034 = 422, //!< tcpwm[0].tr_out0[34] 468 _CYHAL_TRIGGER_TCPWM0_TR_OUT035 = 423, //!< tcpwm[0].tr_out0[35] 469 _CYHAL_TRIGGER_TCPWM0_TR_OUT036 = 424, //!< tcpwm[0].tr_out0[36] 470 _CYHAL_TRIGGER_TCPWM0_TR_OUT037 = 425, //!< tcpwm[0].tr_out0[37] 471 _CYHAL_TRIGGER_TCPWM0_TR_OUT038 = 426, //!< tcpwm[0].tr_out0[38] 472 _CYHAL_TRIGGER_TCPWM0_TR_OUT039 = 427, //!< tcpwm[0].tr_out0[39] 473 _CYHAL_TRIGGER_TCPWM0_TR_OUT040 = 428, //!< tcpwm[0].tr_out0[40] 474 _CYHAL_TRIGGER_TCPWM0_TR_OUT041 = 429, //!< tcpwm[0].tr_out0[41] 475 _CYHAL_TRIGGER_TCPWM0_TR_OUT042 = 430, //!< tcpwm[0].tr_out0[42] 476 _CYHAL_TRIGGER_TCPWM0_TR_OUT043 = 431, //!< tcpwm[0].tr_out0[43] 477 _CYHAL_TRIGGER_TCPWM0_TR_OUT044 = 432, //!< tcpwm[0].tr_out0[44] 478 _CYHAL_TRIGGER_TCPWM0_TR_OUT045 = 433, //!< tcpwm[0].tr_out0[45] 479 _CYHAL_TRIGGER_TCPWM0_TR_OUT046 = 434, //!< tcpwm[0].tr_out0[46] 480 _CYHAL_TRIGGER_TCPWM0_TR_OUT047 = 435, //!< tcpwm[0].tr_out0[47] 481 _CYHAL_TRIGGER_TCPWM0_TR_OUT048 = 436, //!< tcpwm[0].tr_out0[48] 482 _CYHAL_TRIGGER_TCPWM0_TR_OUT049 = 437, //!< tcpwm[0].tr_out0[49] 483 _CYHAL_TRIGGER_TCPWM0_TR_OUT050 = 438, //!< tcpwm[0].tr_out0[50] 484 _CYHAL_TRIGGER_TCPWM0_TR_OUT051 = 439, //!< tcpwm[0].tr_out0[51] 485 _CYHAL_TRIGGER_TCPWM0_TR_OUT052 = 440, //!< tcpwm[0].tr_out0[52] 486 _CYHAL_TRIGGER_TCPWM0_TR_OUT053 = 441, //!< tcpwm[0].tr_out0[53] 487 _CYHAL_TRIGGER_TCPWM0_TR_OUT054 = 442, //!< tcpwm[0].tr_out0[54] 488 _CYHAL_TRIGGER_TCPWM0_TR_OUT055 = 443, //!< tcpwm[0].tr_out0[55] 489 _CYHAL_TRIGGER_TCPWM0_TR_OUT056 = 444, //!< tcpwm[0].tr_out0[56] 490 _CYHAL_TRIGGER_TCPWM0_TR_OUT057 = 445, //!< tcpwm[0].tr_out0[57] 491 _CYHAL_TRIGGER_TCPWM0_TR_OUT058 = 446, //!< tcpwm[0].tr_out0[58] 492 _CYHAL_TRIGGER_TCPWM0_TR_OUT059 = 447, //!< tcpwm[0].tr_out0[59] 493 _CYHAL_TRIGGER_TCPWM0_TR_OUT060 = 448, //!< tcpwm[0].tr_out0[60] 494 _CYHAL_TRIGGER_TCPWM0_TR_OUT061 = 449, //!< tcpwm[0].tr_out0[61] 495 _CYHAL_TRIGGER_TCPWM0_TR_OUT062 = 450, //!< tcpwm[0].tr_out0[62] 496 _CYHAL_TRIGGER_TCPWM0_TR_OUT0256 = 451, //!< tcpwm[0].tr_out0[256] 497 _CYHAL_TRIGGER_TCPWM0_TR_OUT0257 = 452, //!< tcpwm[0].tr_out0[257] 498 _CYHAL_TRIGGER_TCPWM0_TR_OUT0258 = 453, //!< tcpwm[0].tr_out0[258] 499 _CYHAL_TRIGGER_TCPWM0_TR_OUT0259 = 454, //!< tcpwm[0].tr_out0[259] 500 _CYHAL_TRIGGER_TCPWM0_TR_OUT0260 = 455, //!< tcpwm[0].tr_out0[260] 501 _CYHAL_TRIGGER_TCPWM0_TR_OUT0261 = 456, //!< tcpwm[0].tr_out0[261] 502 _CYHAL_TRIGGER_TCPWM0_TR_OUT0262 = 457, //!< tcpwm[0].tr_out0[262] 503 _CYHAL_TRIGGER_TCPWM0_TR_OUT0263 = 458, //!< tcpwm[0].tr_out0[263] 504 _CYHAL_TRIGGER_TCPWM0_TR_OUT0264 = 459, //!< tcpwm[0].tr_out0[264] 505 _CYHAL_TRIGGER_TCPWM0_TR_OUT0265 = 460, //!< tcpwm[0].tr_out0[265] 506 _CYHAL_TRIGGER_TCPWM0_TR_OUT0266 = 461, //!< tcpwm[0].tr_out0[266] 507 _CYHAL_TRIGGER_TCPWM0_TR_OUT0267 = 462, //!< tcpwm[0].tr_out0[267] 508 _CYHAL_TRIGGER_TCPWM0_TR_OUT0512 = 463, //!< tcpwm[0].tr_out0[512] 509 _CYHAL_TRIGGER_TCPWM0_TR_OUT0513 = 464, //!< tcpwm[0].tr_out0[513] 510 _CYHAL_TRIGGER_TCPWM0_TR_OUT0514 = 465, //!< tcpwm[0].tr_out0[514] 511 _CYHAL_TRIGGER_TCPWM0_TR_OUT0515 = 466, //!< tcpwm[0].tr_out0[515] 512 _CYHAL_TRIGGER_TCPWM0_TR_OUT0516 = 467, //!< tcpwm[0].tr_out0[516] 513 _CYHAL_TRIGGER_TCPWM0_TR_OUT0517 = 468, //!< tcpwm[0].tr_out0[517] 514 _CYHAL_TRIGGER_TCPWM0_TR_OUT0518 = 469, //!< tcpwm[0].tr_out0[518] 515 _CYHAL_TRIGGER_TCPWM0_TR_OUT0519 = 470, //!< tcpwm[0].tr_out0[519] 516 _CYHAL_TRIGGER_TCPWM0_TR_OUT10 = 471, //!< tcpwm[0].tr_out1[0] 517 _CYHAL_TRIGGER_TCPWM0_TR_OUT11 = 472, //!< tcpwm[0].tr_out1[1] 518 _CYHAL_TRIGGER_TCPWM0_TR_OUT12 = 473, //!< tcpwm[0].tr_out1[2] 519 _CYHAL_TRIGGER_TCPWM0_TR_OUT13 = 474, //!< tcpwm[0].tr_out1[3] 520 _CYHAL_TRIGGER_TCPWM0_TR_OUT14 = 475, //!< tcpwm[0].tr_out1[4] 521 _CYHAL_TRIGGER_TCPWM0_TR_OUT15 = 476, //!< tcpwm[0].tr_out1[5] 522 _CYHAL_TRIGGER_TCPWM0_TR_OUT16 = 477, //!< tcpwm[0].tr_out1[6] 523 _CYHAL_TRIGGER_TCPWM0_TR_OUT17 = 478, //!< tcpwm[0].tr_out1[7] 524 _CYHAL_TRIGGER_TCPWM0_TR_OUT18 = 479, //!< tcpwm[0].tr_out1[8] 525 _CYHAL_TRIGGER_TCPWM0_TR_OUT19 = 480, //!< tcpwm[0].tr_out1[9] 526 _CYHAL_TRIGGER_TCPWM0_TR_OUT110 = 481, //!< tcpwm[0].tr_out1[10] 527 _CYHAL_TRIGGER_TCPWM0_TR_OUT111 = 482, //!< tcpwm[0].tr_out1[11] 528 _CYHAL_TRIGGER_TCPWM0_TR_OUT112 = 483, //!< tcpwm[0].tr_out1[12] 529 _CYHAL_TRIGGER_TCPWM0_TR_OUT113 = 484, //!< tcpwm[0].tr_out1[13] 530 _CYHAL_TRIGGER_TCPWM0_TR_OUT114 = 485, //!< tcpwm[0].tr_out1[14] 531 _CYHAL_TRIGGER_TCPWM0_TR_OUT115 = 486, //!< tcpwm[0].tr_out1[15] 532 _CYHAL_TRIGGER_TCPWM0_TR_OUT116 = 487, //!< tcpwm[0].tr_out1[16] 533 _CYHAL_TRIGGER_TCPWM0_TR_OUT117 = 488, //!< tcpwm[0].tr_out1[17] 534 _CYHAL_TRIGGER_TCPWM0_TR_OUT118 = 489, //!< tcpwm[0].tr_out1[18] 535 _CYHAL_TRIGGER_TCPWM0_TR_OUT119 = 490, //!< tcpwm[0].tr_out1[19] 536 _CYHAL_TRIGGER_TCPWM0_TR_OUT120 = 491, //!< tcpwm[0].tr_out1[20] 537 _CYHAL_TRIGGER_TCPWM0_TR_OUT121 = 492, //!< tcpwm[0].tr_out1[21] 538 _CYHAL_TRIGGER_TCPWM0_TR_OUT122 = 493, //!< tcpwm[0].tr_out1[22] 539 _CYHAL_TRIGGER_TCPWM0_TR_OUT123 = 494, //!< tcpwm[0].tr_out1[23] 540 _CYHAL_TRIGGER_TCPWM0_TR_OUT124 = 495, //!< tcpwm[0].tr_out1[24] 541 _CYHAL_TRIGGER_TCPWM0_TR_OUT125 = 496, //!< tcpwm[0].tr_out1[25] 542 _CYHAL_TRIGGER_TCPWM0_TR_OUT126 = 497, //!< tcpwm[0].tr_out1[26] 543 _CYHAL_TRIGGER_TCPWM0_TR_OUT127 = 498, //!< tcpwm[0].tr_out1[27] 544 _CYHAL_TRIGGER_TCPWM0_TR_OUT128 = 499, //!< tcpwm[0].tr_out1[28] 545 _CYHAL_TRIGGER_TCPWM0_TR_OUT129 = 500, //!< tcpwm[0].tr_out1[29] 546 _CYHAL_TRIGGER_TCPWM0_TR_OUT130 = 501, //!< tcpwm[0].tr_out1[30] 547 _CYHAL_TRIGGER_TCPWM0_TR_OUT131 = 502, //!< tcpwm[0].tr_out1[31] 548 _CYHAL_TRIGGER_TCPWM0_TR_OUT132 = 503, //!< tcpwm[0].tr_out1[32] 549 _CYHAL_TRIGGER_TCPWM0_TR_OUT133 = 504, //!< tcpwm[0].tr_out1[33] 550 _CYHAL_TRIGGER_TCPWM0_TR_OUT134 = 505, //!< tcpwm[0].tr_out1[34] 551 _CYHAL_TRIGGER_TCPWM0_TR_OUT135 = 506, //!< tcpwm[0].tr_out1[35] 552 _CYHAL_TRIGGER_TCPWM0_TR_OUT136 = 507, //!< tcpwm[0].tr_out1[36] 553 _CYHAL_TRIGGER_TCPWM0_TR_OUT137 = 508, //!< tcpwm[0].tr_out1[37] 554 _CYHAL_TRIGGER_TCPWM0_TR_OUT138 = 509, //!< tcpwm[0].tr_out1[38] 555 _CYHAL_TRIGGER_TCPWM0_TR_OUT139 = 510, //!< tcpwm[0].tr_out1[39] 556 _CYHAL_TRIGGER_TCPWM0_TR_OUT140 = 511, //!< tcpwm[0].tr_out1[40] 557 _CYHAL_TRIGGER_TCPWM0_TR_OUT141 = 512, //!< tcpwm[0].tr_out1[41] 558 _CYHAL_TRIGGER_TCPWM0_TR_OUT142 = 513, //!< tcpwm[0].tr_out1[42] 559 _CYHAL_TRIGGER_TCPWM0_TR_OUT143 = 514, //!< tcpwm[0].tr_out1[43] 560 _CYHAL_TRIGGER_TCPWM0_TR_OUT144 = 515, //!< tcpwm[0].tr_out1[44] 561 _CYHAL_TRIGGER_TCPWM0_TR_OUT145 = 516, //!< tcpwm[0].tr_out1[45] 562 _CYHAL_TRIGGER_TCPWM0_TR_OUT146 = 517, //!< tcpwm[0].tr_out1[46] 563 _CYHAL_TRIGGER_TCPWM0_TR_OUT147 = 518, //!< tcpwm[0].tr_out1[47] 564 _CYHAL_TRIGGER_TCPWM0_TR_OUT148 = 519, //!< tcpwm[0].tr_out1[48] 565 _CYHAL_TRIGGER_TCPWM0_TR_OUT149 = 520, //!< tcpwm[0].tr_out1[49] 566 _CYHAL_TRIGGER_TCPWM0_TR_OUT150 = 521, //!< tcpwm[0].tr_out1[50] 567 _CYHAL_TRIGGER_TCPWM0_TR_OUT151 = 522, //!< tcpwm[0].tr_out1[51] 568 _CYHAL_TRIGGER_TCPWM0_TR_OUT152 = 523, //!< tcpwm[0].tr_out1[52] 569 _CYHAL_TRIGGER_TCPWM0_TR_OUT153 = 524, //!< tcpwm[0].tr_out1[53] 570 _CYHAL_TRIGGER_TCPWM0_TR_OUT154 = 525, //!< tcpwm[0].tr_out1[54] 571 _CYHAL_TRIGGER_TCPWM0_TR_OUT155 = 526, //!< tcpwm[0].tr_out1[55] 572 _CYHAL_TRIGGER_TCPWM0_TR_OUT156 = 527, //!< tcpwm[0].tr_out1[56] 573 _CYHAL_TRIGGER_TCPWM0_TR_OUT157 = 528, //!< tcpwm[0].tr_out1[57] 574 _CYHAL_TRIGGER_TCPWM0_TR_OUT158 = 529, //!< tcpwm[0].tr_out1[58] 575 _CYHAL_TRIGGER_TCPWM0_TR_OUT159 = 530, //!< tcpwm[0].tr_out1[59] 576 _CYHAL_TRIGGER_TCPWM0_TR_OUT160 = 531, //!< tcpwm[0].tr_out1[60] 577 _CYHAL_TRIGGER_TCPWM0_TR_OUT161 = 532, //!< tcpwm[0].tr_out1[61] 578 _CYHAL_TRIGGER_TCPWM0_TR_OUT162 = 533, //!< tcpwm[0].tr_out1[62] 579 _CYHAL_TRIGGER_TCPWM0_TR_OUT1256 = 534, //!< tcpwm[0].tr_out1[256] 580 _CYHAL_TRIGGER_TCPWM0_TR_OUT1257 = 535, //!< tcpwm[0].tr_out1[257] 581 _CYHAL_TRIGGER_TCPWM0_TR_OUT1258 = 536, //!< tcpwm[0].tr_out1[258] 582 _CYHAL_TRIGGER_TCPWM0_TR_OUT1259 = 537, //!< tcpwm[0].tr_out1[259] 583 _CYHAL_TRIGGER_TCPWM0_TR_OUT1260 = 538, //!< tcpwm[0].tr_out1[260] 584 _CYHAL_TRIGGER_TCPWM0_TR_OUT1261 = 539, //!< tcpwm[0].tr_out1[261] 585 _CYHAL_TRIGGER_TCPWM0_TR_OUT1262 = 540, //!< tcpwm[0].tr_out1[262] 586 _CYHAL_TRIGGER_TCPWM0_TR_OUT1263 = 541, //!< tcpwm[0].tr_out1[263] 587 _CYHAL_TRIGGER_TCPWM0_TR_OUT1264 = 542, //!< tcpwm[0].tr_out1[264] 588 _CYHAL_TRIGGER_TCPWM0_TR_OUT1265 = 543, //!< tcpwm[0].tr_out1[265] 589 _CYHAL_TRIGGER_TCPWM0_TR_OUT1266 = 544, //!< tcpwm[0].tr_out1[266] 590 _CYHAL_TRIGGER_TCPWM0_TR_OUT1267 = 545, //!< tcpwm[0].tr_out1[267] 591 _CYHAL_TRIGGER_TCPWM0_TR_OUT1512 = 546, //!< tcpwm[0].tr_out1[512] 592 _CYHAL_TRIGGER_TCPWM0_TR_OUT1513 = 547, //!< tcpwm[0].tr_out1[513] 593 _CYHAL_TRIGGER_TCPWM0_TR_OUT1514 = 548, //!< tcpwm[0].tr_out1[514] 594 _CYHAL_TRIGGER_TCPWM0_TR_OUT1515 = 549, //!< tcpwm[0].tr_out1[515] 595 _CYHAL_TRIGGER_TCPWM0_TR_OUT1516 = 550, //!< tcpwm[0].tr_out1[516] 596 _CYHAL_TRIGGER_TCPWM0_TR_OUT1517 = 551, //!< tcpwm[0].tr_out1[517] 597 _CYHAL_TRIGGER_TCPWM0_TR_OUT1518 = 552, //!< tcpwm[0].tr_out1[518] 598 _CYHAL_TRIGGER_TCPWM0_TR_OUT1519 = 553, //!< tcpwm[0].tr_out1[519] 599 _CYHAL_TRIGGER_TR_GROUP9_OUTPUT0 = 554, //!< tr_group[9].output[0] 600 _CYHAL_TRIGGER_TR_GROUP9_OUTPUT1 = 555, //!< tr_group[9].output[1] 601 _CYHAL_TRIGGER_TR_GROUP9_OUTPUT2 = 556, //!< tr_group[9].output[2] 602 _CYHAL_TRIGGER_TR_GROUP9_OUTPUT3 = 557, //!< tr_group[9].output[3] 603 _CYHAL_TRIGGER_TR_GROUP9_OUTPUT4 = 558, //!< tr_group[9].output[4] 604 _CYHAL_TRIGGER_TR_GROUP10_OUTPUT0 = 559, //!< tr_group[10].output[0] 605 _CYHAL_TRIGGER_TR_GROUP10_OUTPUT1 = 560, //!< tr_group[10].output[1] 606 _CYHAL_TRIGGER_TR_GROUP10_OUTPUT2 = 561, //!< tr_group[10].output[2] 607 _CYHAL_TRIGGER_TR_GROUP10_OUTPUT3 = 562, //!< tr_group[10].output[3] 608 _CYHAL_TRIGGER_TR_GROUP10_OUTPUT4 = 563, //!< tr_group[10].output[4] 609 } _cyhal_trigger_source_tviibe4m_t; 610 611 /** Typedef for internal device family specific trigger source to generic trigger source */ 612 typedef _cyhal_trigger_source_tviibe4m_t cyhal_internal_source_t; 613 614 /** @brief Get a public source signal type (cyhal_trigger_source_tviibe4m_t) given an internal source signal and signal type */ 615 #define _CYHAL_TRIGGER_CREATE_SOURCE(src, type) ((src) << 1 | (type)) 616 /** @brief Get an internal source signal (_cyhal_trigger_source_tviibe4m_t) given a public source signal. */ 617 #define _CYHAL_TRIGGER_GET_SOURCE_SIGNAL(src) ((cyhal_internal_source_t)((src) >> 1)) 618 /** @brief Get the signal type (cyhal_signal_type_t) given a public source signal. */ 619 #define _CYHAL_TRIGGER_GET_SOURCE_TYPE(src) ((cyhal_signal_type_t)((src) & 1)) 620 /** \endcond */ 621 622 /** @brief Name of each input trigger. */ 623 typedef enum 624 { 625 CYHAL_TRIGGER_CPUSS_ZERO_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_ZERO, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.zero 626 CYHAL_TRIGGER_CPUSS_ZERO_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_ZERO, CYHAL_SIGNAL_TYPE_LEVEL), //!< cpuss.zero 627 CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ0, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[0].tr_dbg_dma_req[0] 628 CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ1, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[0].tr_dbg_dma_req[1] 629 CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ2, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[0].tr_dbg_dma_req[2] 630 CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ3, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[0].tr_dbg_dma_req[3] 631 CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_REQ0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_REQ0, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[1].tr_dbg_dma_req[0] 632 CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_REQ1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_REQ1, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[1].tr_dbg_dma_req[1] 633 CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_REQ2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_REQ2, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[1].tr_dbg_dma_req[2] 634 CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_REQ3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_REQ3, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[1].tr_dbg_dma_req[3] 635 CYHAL_TRIGGER_CANFD0_TR_FIFO00 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_FIFO00, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[0].tr_fifo0[0] 636 CYHAL_TRIGGER_CANFD0_TR_FIFO01 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_FIFO01, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[0].tr_fifo0[1] 637 CYHAL_TRIGGER_CANFD0_TR_FIFO02 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_FIFO02, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[0].tr_fifo0[2] 638 CYHAL_TRIGGER_CANFD0_TR_FIFO03 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_FIFO03, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[0].tr_fifo0[3] 639 CYHAL_TRIGGER_CANFD1_TR_FIFO00 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD1_TR_FIFO00, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[1].tr_fifo0[0] 640 CYHAL_TRIGGER_CANFD1_TR_FIFO01 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD1_TR_FIFO01, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[1].tr_fifo0[1] 641 CYHAL_TRIGGER_CANFD1_TR_FIFO02 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD1_TR_FIFO02, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[1].tr_fifo0[2] 642 CYHAL_TRIGGER_CANFD1_TR_FIFO03 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD1_TR_FIFO03, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[1].tr_fifo0[3] 643 CYHAL_TRIGGER_CANFD0_TR_FIFO10 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_FIFO10, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[0].tr_fifo1[0] 644 CYHAL_TRIGGER_CANFD0_TR_FIFO11 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_FIFO11, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[0].tr_fifo1[1] 645 CYHAL_TRIGGER_CANFD0_TR_FIFO12 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_FIFO12, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[0].tr_fifo1[2] 646 CYHAL_TRIGGER_CANFD0_TR_FIFO13 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_FIFO13, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[0].tr_fifo1[3] 647 CYHAL_TRIGGER_CANFD1_TR_FIFO10 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD1_TR_FIFO10, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[1].tr_fifo1[0] 648 CYHAL_TRIGGER_CANFD1_TR_FIFO11 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD1_TR_FIFO11, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[1].tr_fifo1[1] 649 CYHAL_TRIGGER_CANFD1_TR_FIFO12 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD1_TR_FIFO12, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[1].tr_fifo1[2] 650 CYHAL_TRIGGER_CANFD1_TR_FIFO13 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD1_TR_FIFO13, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[1].tr_fifo1[3] 651 CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< canfd[0].tr_tmp_rtp_out[0] 652 CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< canfd[0].tr_tmp_rtp_out[1] 653 CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT2, CYHAL_SIGNAL_TYPE_EDGE), //!< canfd[0].tr_tmp_rtp_out[2] 654 CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT3, CYHAL_SIGNAL_TYPE_EDGE), //!< canfd[0].tr_tmp_rtp_out[3] 655 CYHAL_TRIGGER_CANFD1_TR_TMP_RTP_OUT0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD1_TR_TMP_RTP_OUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< canfd[1].tr_tmp_rtp_out[0] 656 CYHAL_TRIGGER_CANFD1_TR_TMP_RTP_OUT1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD1_TR_TMP_RTP_OUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< canfd[1].tr_tmp_rtp_out[1] 657 CYHAL_TRIGGER_CANFD1_TR_TMP_RTP_OUT2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD1_TR_TMP_RTP_OUT2, CYHAL_SIGNAL_TYPE_EDGE), //!< canfd[1].tr_tmp_rtp_out[2] 658 CYHAL_TRIGGER_CANFD1_TR_TMP_RTP_OUT3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD1_TR_TMP_RTP_OUT3, CYHAL_SIGNAL_TYPE_EDGE), //!< canfd[1].tr_tmp_rtp_out[3] 659 CYHAL_TRIGGER_CPUSS_CTI_TR_OUT0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_CTI_TR_OUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.cti_tr_out[0] 660 CYHAL_TRIGGER_CPUSS_CTI_TR_OUT1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_CTI_TR_OUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.cti_tr_out[1] 661 CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dmac_tr_out[0] 662 CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dmac_tr_out[1] 663 CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT2, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dmac_tr_out[2] 664 CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT3, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dmac_tr_out[3] 665 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[0] 666 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[1] 667 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT2, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[2] 668 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT3, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[3] 669 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT4 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT4, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[4] 670 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT5 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT5, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[5] 671 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT6 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT6, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[6] 672 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT7 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT7, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[7] 673 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT8 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT8, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[8] 674 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT9 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT9, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[9] 675 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT10 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT10, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[10] 676 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT11 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT11, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[11] 677 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT12 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT12, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[12] 678 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT13 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT13, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[13] 679 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT14 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT14, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[14] 680 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT15 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT15, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[15] 681 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT16 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT16, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[16] 682 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT17 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT17, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[17] 683 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT18 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT18, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[18] 684 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT19 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT19, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[19] 685 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT20 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT20, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[20] 686 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT21 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT21, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[21] 687 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT22 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT22, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[22] 688 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT23 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT23, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[23] 689 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT24 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT24, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[24] 690 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT25 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT25, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[25] 691 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT26 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT26, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[26] 692 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT27 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT27, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[27] 693 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT28 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT28, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[28] 694 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT29 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT29, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[29] 695 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT30 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT30, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[30] 696 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT31 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT31, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[31] 697 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT32 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT32, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[32] 698 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT33 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT33, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[33] 699 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT34 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT34, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[34] 700 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT35 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT35, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[35] 701 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT36 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT36, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[36] 702 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT37 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT37, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[37] 703 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT38 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT38, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[38] 704 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT39 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT39, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[39] 705 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT40 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT40, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[40] 706 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT41 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT41, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[41] 707 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT42 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT42, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[42] 708 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT43 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT43, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[43] 709 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT44 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT44, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[44] 710 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT45 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT45, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[45] 711 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT46 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT46, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[46] 712 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT47 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT47, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[47] 713 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT48 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT48, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[48] 714 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT49 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT49, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[49] 715 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT50 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT50, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[50] 716 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT51 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT51, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[51] 717 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT52 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT52, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[52] 718 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT53 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT53, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[53] 719 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT54 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT54, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[54] 720 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT55 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT55, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[55] 721 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT56 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT56, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[56] 722 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT57 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT57, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[57] 723 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT58 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT58, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[58] 724 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT59 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT59, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[59] 725 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT60 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT60, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[60] 726 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT61 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT61, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[61] 727 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT62 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT62, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[62] 728 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT63 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT63, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[63] 729 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT64 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT64, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[64] 730 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT65 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT65, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[65] 731 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT66 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT66, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[66] 732 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT67 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT67, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[67] 733 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT68 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT68, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[68] 734 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT69 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT69, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[69] 735 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT70 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT70, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[70] 736 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT71 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT71, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[71] 737 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT72 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT72, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[72] 738 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT73 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT73, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[73] 739 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT74 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT74, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[74] 740 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT75 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT75, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[75] 741 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT76 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT76, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[76] 742 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT77 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT77, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[77] 743 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT78 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT78, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[78] 744 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT79 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT79, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[79] 745 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT80 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT80, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[80] 746 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT81 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT81, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[81] 747 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT82 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT82, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[82] 748 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT83 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT83, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[83] 749 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT84 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT84, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[84] 750 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT85 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT85, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[85] 751 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT86 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT86, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[86] 752 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT87 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT87, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[87] 753 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT88 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT88, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[88] 754 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT89 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT89, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[89] 755 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT90 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT90, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[90] 756 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT91 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT91, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[91] 757 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[0] 758 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[1] 759 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT2, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[2] 760 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT3, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[3] 761 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT4 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT4, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[4] 762 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT5 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT5, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[5] 763 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT6 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT6, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[6] 764 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT7 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT7, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[7] 765 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT8 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT8, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[8] 766 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT9 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT9, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[9] 767 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT10 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT10, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[10] 768 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT11 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT11, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[11] 769 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT12 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT12, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[12] 770 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT13 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT13, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[13] 771 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT14 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT14, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[14] 772 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT15 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT15, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[15] 773 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT16 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT16, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[16] 774 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT17 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT17, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[17] 775 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT18 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT18, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[18] 776 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT19 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT19, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[19] 777 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT20 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT20, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[20] 778 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT21 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT21, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[21] 779 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT22 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT22, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[22] 780 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT23 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT23, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[23] 781 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT24 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT24, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[24] 782 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT25 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT25, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[25] 783 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT26 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT26, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[26] 784 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT27 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT27, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[27] 785 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT28 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT28, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[28] 786 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT29 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT29, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[29] 787 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT30 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT30, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[30] 788 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT31 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT31, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[31] 789 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT32 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT32, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[32] 790 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT33 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT33, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[33] 791 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT34 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT34, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[34] 792 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT35 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT35, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[35] 793 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT36 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT36, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[36] 794 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT37 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT37, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[37] 795 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT38 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT38, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[38] 796 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT39 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT39, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[39] 797 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT40 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT40, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[40] 798 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT41 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT41, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[41] 799 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT42 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT42, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[42] 800 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT43 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT43, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[43] 801 CYHAL_TRIGGER_CPUSS_TR_FAULT0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_TR_FAULT0, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.tr_fault[0] 802 CYHAL_TRIGGER_CPUSS_TR_FAULT1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_TR_FAULT1, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.tr_fault[1] 803 CYHAL_TRIGGER_CPUSS_TR_FAULT2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_TR_FAULT2, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.tr_fault[2] 804 CYHAL_TRIGGER_CPUSS_TR_FAULT3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_TR_FAULT3, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.tr_fault[3] 805 CYHAL_TRIGGER_CXPI0_TR_RX_REQ0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CXPI0_TR_RX_REQ0, CYHAL_SIGNAL_TYPE_LEVEL), //!< cxpi[0].tr_rx_req[0] 806 CYHAL_TRIGGER_CXPI0_TR_RX_REQ1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CXPI0_TR_RX_REQ1, CYHAL_SIGNAL_TYPE_LEVEL), //!< cxpi[0].tr_rx_req[1] 807 CYHAL_TRIGGER_CXPI0_TR_RX_REQ2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CXPI0_TR_RX_REQ2, CYHAL_SIGNAL_TYPE_LEVEL), //!< cxpi[0].tr_rx_req[2] 808 CYHAL_TRIGGER_CXPI0_TR_RX_REQ3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CXPI0_TR_RX_REQ3, CYHAL_SIGNAL_TYPE_LEVEL), //!< cxpi[0].tr_rx_req[3] 809 CYHAL_TRIGGER_CXPI0_TR_TX_REQ0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CXPI0_TR_TX_REQ0, CYHAL_SIGNAL_TYPE_LEVEL), //!< cxpi[0].tr_tx_req[0] 810 CYHAL_TRIGGER_CXPI0_TR_TX_REQ1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CXPI0_TR_TX_REQ1, CYHAL_SIGNAL_TYPE_LEVEL), //!< cxpi[0].tr_tx_req[1] 811 CYHAL_TRIGGER_CXPI0_TR_TX_REQ2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CXPI0_TR_TX_REQ2, CYHAL_SIGNAL_TYPE_LEVEL), //!< cxpi[0].tr_tx_req[2] 812 CYHAL_TRIGGER_CXPI0_TR_TX_REQ3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CXPI0_TR_TX_REQ3, CYHAL_SIGNAL_TYPE_LEVEL), //!< cxpi[0].tr_tx_req[3] 813 CYHAL_TRIGGER_EVTGEN0_TR_OUT0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< evtgen[0].tr_out[0] 814 CYHAL_TRIGGER_EVTGEN0_TR_OUT0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT0, CYHAL_SIGNAL_TYPE_LEVEL), //!< evtgen[0].tr_out[0] 815 CYHAL_TRIGGER_EVTGEN0_TR_OUT1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< evtgen[0].tr_out[1] 816 CYHAL_TRIGGER_EVTGEN0_TR_OUT1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT1, CYHAL_SIGNAL_TYPE_LEVEL), //!< evtgen[0].tr_out[1] 817 CYHAL_TRIGGER_EVTGEN0_TR_OUT2_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT2, CYHAL_SIGNAL_TYPE_EDGE), //!< evtgen[0].tr_out[2] 818 CYHAL_TRIGGER_EVTGEN0_TR_OUT2_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT2, CYHAL_SIGNAL_TYPE_LEVEL), //!< evtgen[0].tr_out[2] 819 CYHAL_TRIGGER_EVTGEN0_TR_OUT3_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT3, CYHAL_SIGNAL_TYPE_EDGE), //!< evtgen[0].tr_out[3] 820 CYHAL_TRIGGER_EVTGEN0_TR_OUT3_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT3, CYHAL_SIGNAL_TYPE_LEVEL), //!< evtgen[0].tr_out[3] 821 CYHAL_TRIGGER_EVTGEN0_TR_OUT4_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT4, CYHAL_SIGNAL_TYPE_EDGE), //!< evtgen[0].tr_out[4] 822 CYHAL_TRIGGER_EVTGEN0_TR_OUT4_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT4, CYHAL_SIGNAL_TYPE_LEVEL), //!< evtgen[0].tr_out[4] 823 CYHAL_TRIGGER_EVTGEN0_TR_OUT5_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT5, CYHAL_SIGNAL_TYPE_EDGE), //!< evtgen[0].tr_out[5] 824 CYHAL_TRIGGER_EVTGEN0_TR_OUT5_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT5, CYHAL_SIGNAL_TYPE_LEVEL), //!< evtgen[0].tr_out[5] 825 CYHAL_TRIGGER_EVTGEN0_TR_OUT6_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT6, CYHAL_SIGNAL_TYPE_EDGE), //!< evtgen[0].tr_out[6] 826 CYHAL_TRIGGER_EVTGEN0_TR_OUT6_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT6, CYHAL_SIGNAL_TYPE_LEVEL), //!< evtgen[0].tr_out[6] 827 CYHAL_TRIGGER_EVTGEN0_TR_OUT7_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT7, CYHAL_SIGNAL_TYPE_EDGE), //!< evtgen[0].tr_out[7] 828 CYHAL_TRIGGER_EVTGEN0_TR_OUT7_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT7, CYHAL_SIGNAL_TYPE_LEVEL), //!< evtgen[0].tr_out[7] 829 CYHAL_TRIGGER_EVTGEN0_TR_OUT8_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT8, CYHAL_SIGNAL_TYPE_EDGE), //!< evtgen[0].tr_out[8] 830 CYHAL_TRIGGER_EVTGEN0_TR_OUT8_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT8, CYHAL_SIGNAL_TYPE_LEVEL), //!< evtgen[0].tr_out[8] 831 CYHAL_TRIGGER_EVTGEN0_TR_OUT9_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT9, CYHAL_SIGNAL_TYPE_EDGE), //!< evtgen[0].tr_out[9] 832 CYHAL_TRIGGER_EVTGEN0_TR_OUT9_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT9, CYHAL_SIGNAL_TYPE_LEVEL), //!< evtgen[0].tr_out[9] 833 CYHAL_TRIGGER_EVTGEN0_TR_OUT10_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT10, CYHAL_SIGNAL_TYPE_EDGE), //!< evtgen[0].tr_out[10] 834 CYHAL_TRIGGER_EVTGEN0_TR_OUT10_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT10, CYHAL_SIGNAL_TYPE_LEVEL), //!< evtgen[0].tr_out[10] 835 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE0, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[0] 836 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE0, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[0] 837 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE1, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[1] 838 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE1, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[1] 839 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE2_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE2, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[2] 840 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE2_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE2, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[2] 841 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE3_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE3, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[3] 842 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE3_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE3, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[3] 843 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE4_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE4, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[4] 844 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE4_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE4, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[4] 845 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE5_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE5, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[5] 846 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE5_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE5, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[5] 847 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE6_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE6, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[6] 848 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE6_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE6, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[6] 849 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE7_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE7, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[7] 850 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE7_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE7, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[7] 851 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE8_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE8, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[8] 852 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE8_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE8, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[8] 853 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE9_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE9, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[9] 854 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE9_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE9, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[9] 855 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE10_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE10, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[10] 856 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE10_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE10, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[10] 857 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE11_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE11, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[11] 858 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE11_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE11, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[11] 859 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE12_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE12, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[12] 860 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE12_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE12, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[12] 861 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE13_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE13, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[13] 862 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE13_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE13, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[13] 863 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE14_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE14, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[14] 864 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE14_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE14, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[14] 865 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE15_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE15, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[15] 866 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE15_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE15, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[15] 867 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE16_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE16, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[16] 868 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE16_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE16, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[16] 869 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE17_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE17, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[17] 870 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE17_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE17, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[17] 871 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE18_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE18, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[18] 872 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE18_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE18, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[18] 873 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE19_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE19, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[19] 874 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE19_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE19, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[19] 875 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE20_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE20, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[20] 876 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE20_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE20, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[20] 877 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE21_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE21, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[21] 878 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE21_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE21, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[21] 879 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE22_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE22, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[22] 880 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE22_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE22, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[22] 881 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE23_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE23, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[23] 882 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE23_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE23, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[23] 883 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE32_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE32, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[32] 884 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE32_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE32, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[32] 885 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE33_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE33, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[33] 886 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE33_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE33, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[33] 887 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE34_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE34, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[34] 888 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE34_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE34, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[34] 889 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE35_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE35, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[35] 890 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE35_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE35, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[35] 891 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE36_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE36, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[36] 892 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE36_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE36, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[36] 893 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE37_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE37, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[37] 894 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE37_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE37, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[37] 895 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE38_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE38, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[38] 896 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE38_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE38, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[38] 897 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE39_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE39, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[39] 898 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE39_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE39, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[39] 899 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE40_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE40, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[40] 900 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE40_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE40, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[40] 901 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE41_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE41, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[41] 902 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE41_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE41, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[41] 903 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE42_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE42, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[42] 904 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE42_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE42, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[42] 905 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE43_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE43, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[43] 906 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE43_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE43, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[43] 907 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE44_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE44, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[44] 908 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE44_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE44, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[44] 909 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE45_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE45, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[45] 910 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE45_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE45, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[45] 911 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE46_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE46, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[46] 912 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE46_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE46, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[46] 913 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE47_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE47, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[47] 914 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE47_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE47, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[47] 915 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE48_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE48, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[48] 916 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE48_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE48, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[48] 917 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE49_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE49, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[49] 918 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE49_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE49, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[49] 919 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE50_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE50, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[50] 920 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE50_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE50, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[50] 921 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE51_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE51, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[51] 922 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE51_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE51, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[51] 923 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE52_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE52, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[52] 924 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE52_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE52, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[52] 925 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE53_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE53, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[53] 926 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE53_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE53, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[53] 927 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE54_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE54, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[54] 928 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE54_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE54, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[54] 929 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE55_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE55, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[55] 930 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE55_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE55, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[55] 931 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE56_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE56, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[56] 932 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE56_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE56, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[56] 933 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE57_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE57, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[57] 934 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE57_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE57, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[57] 935 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE58_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE58, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[58] 936 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE58_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE58, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[58] 937 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE59_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE59, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[59] 938 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE59_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE59, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[59] 939 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE60_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE60, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[60] 940 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE60_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE60, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[60] 941 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE61_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE61, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[61] 942 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE61_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE61, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[61] 943 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE62_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE62, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[62] 944 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE62_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE62, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[62] 945 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE63_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE63, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[63] 946 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE63_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE63, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[63] 947 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE64_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE64, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[64] 948 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE64_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE64, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[64] 949 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE65_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE65, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[65] 950 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE65_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE65, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[65] 951 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE66_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE66, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[66] 952 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE66_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE66, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[66] 953 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE67_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE67, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[67] 954 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE67_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE67, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[67] 955 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE68_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE68, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[68] 956 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE68_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE68, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[68] 957 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE69_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE69, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[69] 958 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE69_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE69, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[69] 959 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE70_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE70, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[70] 960 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE70_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE70, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[70] 961 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE71_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE71, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[71] 962 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE71_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE71, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[71] 963 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO0, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[0] 964 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO1, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[1] 965 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO2, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[2] 966 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO3, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[3] 967 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO4 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO4, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[4] 968 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO5 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO5, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[5] 969 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO6 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO6, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[6] 970 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO7 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO7, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[7] 971 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO8 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO8, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[8] 972 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO9 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO9, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[9] 973 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO10 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO10, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[10] 974 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO11 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO11, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[11] 975 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO12 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO12, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[12] 976 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO13 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO13, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[13] 977 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO14 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO14, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[14] 978 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO15 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO15, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[15] 979 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO16 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO16, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[16] 980 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO17 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO17, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[17] 981 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO18 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO18, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[18] 982 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO19 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO19, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[19] 983 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO20 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO20, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[20] 984 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO21 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO21, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[21] 985 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO22 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO22, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[22] 986 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO23 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO23, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[23] 987 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO32 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO32, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[32] 988 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO33 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO33, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[33] 989 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO34 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO34, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[34] 990 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO35 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO35, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[35] 991 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO36 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO36, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[36] 992 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO37 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO37, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[37] 993 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO38 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO38, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[38] 994 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO39 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO39, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[39] 995 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO40 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO40, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[40] 996 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO41 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO41, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[41] 997 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO42 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO42, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[42] 998 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO43 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO43, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[43] 999 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO44 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO44, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[44] 1000 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO45 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO45, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[45] 1001 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO46 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO46, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[46] 1002 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO47 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO47, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[47] 1003 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO48 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO48, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[48] 1004 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO49 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO49, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[49] 1005 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO50 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO50, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[50] 1006 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO51 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO51, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[51] 1007 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO52 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO52, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[52] 1008 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO53 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO53, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[53] 1009 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO54 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO54, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[54] 1010 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO55 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO55, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[55] 1011 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO56 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO56, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[56] 1012 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO57 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO57, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[57] 1013 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO58 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO58, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[58] 1014 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO59 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO59, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[59] 1015 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO60 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO60, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[60] 1016 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO61 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO61, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[61] 1017 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO62 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO62, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[62] 1018 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO63 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO63, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[63] 1019 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO64 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO64, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[64] 1020 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO65 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO65, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[65] 1021 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO66 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO66, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[66] 1022 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO67 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO67, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[67] 1023 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO68 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO68, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[68] 1024 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO69 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO69, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[69] 1025 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO70 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO70, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[70] 1026 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO71 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO71, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[71] 1027 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_gen_out[0] 1028 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT0, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_gen_out[0] 1029 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_gen_out[1] 1030 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT1, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_gen_out[1] 1031 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT2_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT2, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_gen_out[2] 1032 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT2_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT2, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_gen_out[2] 1033 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT3_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT3, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_gen_out[3] 1034 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT3_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT3, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_gen_out[3] 1035 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT4_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT4, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_gen_out[4] 1036 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT4_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT4, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_gen_out[4] 1037 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT5_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT5, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_gen_out[5] 1038 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT5_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT5, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_gen_out[5] 1039 CYHAL_TRIGGER_PERI_TR_IO_INPUT0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[0] 1040 CYHAL_TRIGGER_PERI_TR_IO_INPUT0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT0, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[0] 1041 CYHAL_TRIGGER_PERI_TR_IO_INPUT1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[1] 1042 CYHAL_TRIGGER_PERI_TR_IO_INPUT1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT1, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[1] 1043 CYHAL_TRIGGER_PERI_TR_IO_INPUT2_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT2, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[2] 1044 CYHAL_TRIGGER_PERI_TR_IO_INPUT2_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT2, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[2] 1045 CYHAL_TRIGGER_PERI_TR_IO_INPUT3_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT3, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[3] 1046 CYHAL_TRIGGER_PERI_TR_IO_INPUT3_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT3, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[3] 1047 CYHAL_TRIGGER_PERI_TR_IO_INPUT4_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT4, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[4] 1048 CYHAL_TRIGGER_PERI_TR_IO_INPUT4_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT4, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[4] 1049 CYHAL_TRIGGER_PERI_TR_IO_INPUT5_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT5, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[5] 1050 CYHAL_TRIGGER_PERI_TR_IO_INPUT5_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT5, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[5] 1051 CYHAL_TRIGGER_PERI_TR_IO_INPUT6_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT6, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[6] 1052 CYHAL_TRIGGER_PERI_TR_IO_INPUT6_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT6, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[6] 1053 CYHAL_TRIGGER_PERI_TR_IO_INPUT7_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT7, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[7] 1054 CYHAL_TRIGGER_PERI_TR_IO_INPUT7_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT7, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[7] 1055 CYHAL_TRIGGER_PERI_TR_IO_INPUT8_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT8, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[8] 1056 CYHAL_TRIGGER_PERI_TR_IO_INPUT8_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT8, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[8] 1057 CYHAL_TRIGGER_PERI_TR_IO_INPUT9_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT9, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[9] 1058 CYHAL_TRIGGER_PERI_TR_IO_INPUT9_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT9, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[9] 1059 CYHAL_TRIGGER_PERI_TR_IO_INPUT10_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT10, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[10] 1060 CYHAL_TRIGGER_PERI_TR_IO_INPUT10_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT10, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[10] 1061 CYHAL_TRIGGER_PERI_TR_IO_INPUT11_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT11, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[11] 1062 CYHAL_TRIGGER_PERI_TR_IO_INPUT11_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT11, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[11] 1063 CYHAL_TRIGGER_PERI_TR_IO_INPUT12_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT12, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[12] 1064 CYHAL_TRIGGER_PERI_TR_IO_INPUT12_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT12, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[12] 1065 CYHAL_TRIGGER_PERI_TR_IO_INPUT13_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT13, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[13] 1066 CYHAL_TRIGGER_PERI_TR_IO_INPUT13_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT13, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[13] 1067 CYHAL_TRIGGER_PERI_TR_IO_INPUT14_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT14, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[14] 1068 CYHAL_TRIGGER_PERI_TR_IO_INPUT14_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT14, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[14] 1069 CYHAL_TRIGGER_PERI_TR_IO_INPUT15_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT15, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[15] 1070 CYHAL_TRIGGER_PERI_TR_IO_INPUT15_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT15, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[15] 1071 CYHAL_TRIGGER_PERI_TR_IO_INPUT16_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT16, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[16] 1072 CYHAL_TRIGGER_PERI_TR_IO_INPUT16_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT16, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[16] 1073 CYHAL_TRIGGER_PERI_TR_IO_INPUT17_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT17, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[17] 1074 CYHAL_TRIGGER_PERI_TR_IO_INPUT17_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT17, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[17] 1075 CYHAL_TRIGGER_PERI_TR_IO_INPUT18_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT18, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[18] 1076 CYHAL_TRIGGER_PERI_TR_IO_INPUT18_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT18, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[18] 1077 CYHAL_TRIGGER_PERI_TR_IO_INPUT19_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT19, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[19] 1078 CYHAL_TRIGGER_PERI_TR_IO_INPUT19_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT19, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[19] 1079 CYHAL_TRIGGER_PERI_TR_IO_INPUT20_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT20, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[20] 1080 CYHAL_TRIGGER_PERI_TR_IO_INPUT20_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT20, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[20] 1081 CYHAL_TRIGGER_PERI_TR_IO_INPUT21_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT21, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[21] 1082 CYHAL_TRIGGER_PERI_TR_IO_INPUT21_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT21, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[21] 1083 CYHAL_TRIGGER_PERI_TR_IO_INPUT22_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT22, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[22] 1084 CYHAL_TRIGGER_PERI_TR_IO_INPUT22_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT22, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[22] 1085 CYHAL_TRIGGER_PERI_TR_IO_INPUT23_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT23, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[23] 1086 CYHAL_TRIGGER_PERI_TR_IO_INPUT23_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT23, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[23] 1087 CYHAL_TRIGGER_PERI_TR_IO_INPUT24_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT24, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[24] 1088 CYHAL_TRIGGER_PERI_TR_IO_INPUT24_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT24, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[24] 1089 CYHAL_TRIGGER_PERI_TR_IO_INPUT25_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT25, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[25] 1090 CYHAL_TRIGGER_PERI_TR_IO_INPUT25_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT25, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[25] 1091 CYHAL_TRIGGER_PERI_TR_IO_INPUT26_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT26, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[26] 1092 CYHAL_TRIGGER_PERI_TR_IO_INPUT26_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT26, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[26] 1093 CYHAL_TRIGGER_PERI_TR_IO_INPUT27_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT27, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[27] 1094 CYHAL_TRIGGER_PERI_TR_IO_INPUT27_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT27, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[27] 1095 CYHAL_TRIGGER_PERI_TR_IO_INPUT28_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT28, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[28] 1096 CYHAL_TRIGGER_PERI_TR_IO_INPUT28_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT28, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[28] 1097 CYHAL_TRIGGER_PERI_TR_IO_INPUT29_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT29, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[29] 1098 CYHAL_TRIGGER_PERI_TR_IO_INPUT29_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT29, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[29] 1099 CYHAL_TRIGGER_PERI_TR_IO_INPUT30_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT30, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[30] 1100 CYHAL_TRIGGER_PERI_TR_IO_INPUT30_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT30, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[30] 1101 CYHAL_TRIGGER_PERI_TR_IO_INPUT31_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT31, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[31] 1102 CYHAL_TRIGGER_PERI_TR_IO_INPUT31_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT31, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[31] 1103 CYHAL_TRIGGER_SCB0_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB0_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[0].tr_i2c_scl_filtered 1104 CYHAL_TRIGGER_SCB1_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB1_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[1].tr_i2c_scl_filtered 1105 CYHAL_TRIGGER_SCB2_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB2_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[2].tr_i2c_scl_filtered 1106 CYHAL_TRIGGER_SCB3_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB3_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[3].tr_i2c_scl_filtered 1107 CYHAL_TRIGGER_SCB4_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB4_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[4].tr_i2c_scl_filtered 1108 CYHAL_TRIGGER_SCB5_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB5_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[5].tr_i2c_scl_filtered 1109 CYHAL_TRIGGER_SCB6_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB6_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[6].tr_i2c_scl_filtered 1110 CYHAL_TRIGGER_SCB7_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB7_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[7].tr_i2c_scl_filtered 1111 CYHAL_TRIGGER_SCB0_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB0_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[0].tr_rx_req 1112 CYHAL_TRIGGER_SCB1_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB1_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[1].tr_rx_req 1113 CYHAL_TRIGGER_SCB2_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB2_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[2].tr_rx_req 1114 CYHAL_TRIGGER_SCB3_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB3_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[3].tr_rx_req 1115 CYHAL_TRIGGER_SCB4_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB4_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[4].tr_rx_req 1116 CYHAL_TRIGGER_SCB5_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB5_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[5].tr_rx_req 1117 CYHAL_TRIGGER_SCB6_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB6_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[6].tr_rx_req 1118 CYHAL_TRIGGER_SCB7_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB7_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[7].tr_rx_req 1119 CYHAL_TRIGGER_SCB0_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB0_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[0].tr_tx_req 1120 CYHAL_TRIGGER_SCB1_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB1_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[1].tr_tx_req 1121 CYHAL_TRIGGER_SCB2_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB2_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[2].tr_tx_req 1122 CYHAL_TRIGGER_SCB3_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB3_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[3].tr_tx_req 1123 CYHAL_TRIGGER_SCB4_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB4_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[4].tr_tx_req 1124 CYHAL_TRIGGER_SCB5_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB5_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[5].tr_tx_req 1125 CYHAL_TRIGGER_SCB6_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB6_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[6].tr_tx_req 1126 CYHAL_TRIGGER_SCB7_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB7_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[7].tr_tx_req 1127 CYHAL_TRIGGER_TCPWM0_TR_OUT00_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT00, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[0] 1128 CYHAL_TRIGGER_TCPWM0_TR_OUT00_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT00, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[0] 1129 CYHAL_TRIGGER_TCPWM0_TR_OUT01_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT01, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[1] 1130 CYHAL_TRIGGER_TCPWM0_TR_OUT01_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT01, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[1] 1131 CYHAL_TRIGGER_TCPWM0_TR_OUT02_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT02, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[2] 1132 CYHAL_TRIGGER_TCPWM0_TR_OUT02_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT02, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[2] 1133 CYHAL_TRIGGER_TCPWM0_TR_OUT03_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT03, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[3] 1134 CYHAL_TRIGGER_TCPWM0_TR_OUT03_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT03, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[3] 1135 CYHAL_TRIGGER_TCPWM0_TR_OUT04_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT04, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[4] 1136 CYHAL_TRIGGER_TCPWM0_TR_OUT04_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT04, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[4] 1137 CYHAL_TRIGGER_TCPWM0_TR_OUT05_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT05, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[5] 1138 CYHAL_TRIGGER_TCPWM0_TR_OUT05_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT05, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[5] 1139 CYHAL_TRIGGER_TCPWM0_TR_OUT06_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT06, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[6] 1140 CYHAL_TRIGGER_TCPWM0_TR_OUT06_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT06, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[6] 1141 CYHAL_TRIGGER_TCPWM0_TR_OUT07_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT07, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[7] 1142 CYHAL_TRIGGER_TCPWM0_TR_OUT07_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT07, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[7] 1143 CYHAL_TRIGGER_TCPWM0_TR_OUT08_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT08, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[8] 1144 CYHAL_TRIGGER_TCPWM0_TR_OUT08_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT08, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[8] 1145 CYHAL_TRIGGER_TCPWM0_TR_OUT09_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT09, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[9] 1146 CYHAL_TRIGGER_TCPWM0_TR_OUT09_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT09, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[9] 1147 CYHAL_TRIGGER_TCPWM0_TR_OUT010_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT010, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[10] 1148 CYHAL_TRIGGER_TCPWM0_TR_OUT010_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT010, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[10] 1149 CYHAL_TRIGGER_TCPWM0_TR_OUT011_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT011, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[11] 1150 CYHAL_TRIGGER_TCPWM0_TR_OUT011_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT011, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[11] 1151 CYHAL_TRIGGER_TCPWM0_TR_OUT012_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT012, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[12] 1152 CYHAL_TRIGGER_TCPWM0_TR_OUT012_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT012, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[12] 1153 CYHAL_TRIGGER_TCPWM0_TR_OUT013_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT013, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[13] 1154 CYHAL_TRIGGER_TCPWM0_TR_OUT013_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT013, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[13] 1155 CYHAL_TRIGGER_TCPWM0_TR_OUT014_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT014, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[14] 1156 CYHAL_TRIGGER_TCPWM0_TR_OUT014_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT014, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[14] 1157 CYHAL_TRIGGER_TCPWM0_TR_OUT015_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT015, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[15] 1158 CYHAL_TRIGGER_TCPWM0_TR_OUT015_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT015, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[15] 1159 CYHAL_TRIGGER_TCPWM0_TR_OUT016_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT016, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[16] 1160 CYHAL_TRIGGER_TCPWM0_TR_OUT016_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT016, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[16] 1161 CYHAL_TRIGGER_TCPWM0_TR_OUT017_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT017, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[17] 1162 CYHAL_TRIGGER_TCPWM0_TR_OUT017_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT017, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[17] 1163 CYHAL_TRIGGER_TCPWM0_TR_OUT018_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT018, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[18] 1164 CYHAL_TRIGGER_TCPWM0_TR_OUT018_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT018, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[18] 1165 CYHAL_TRIGGER_TCPWM0_TR_OUT019_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT019, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[19] 1166 CYHAL_TRIGGER_TCPWM0_TR_OUT019_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT019, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[19] 1167 CYHAL_TRIGGER_TCPWM0_TR_OUT020_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT020, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[20] 1168 CYHAL_TRIGGER_TCPWM0_TR_OUT020_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT020, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[20] 1169 CYHAL_TRIGGER_TCPWM0_TR_OUT021_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT021, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[21] 1170 CYHAL_TRIGGER_TCPWM0_TR_OUT021_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT021, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[21] 1171 CYHAL_TRIGGER_TCPWM0_TR_OUT022_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT022, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[22] 1172 CYHAL_TRIGGER_TCPWM0_TR_OUT022_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT022, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[22] 1173 CYHAL_TRIGGER_TCPWM0_TR_OUT023_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT023, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[23] 1174 CYHAL_TRIGGER_TCPWM0_TR_OUT023_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT023, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[23] 1175 CYHAL_TRIGGER_TCPWM0_TR_OUT024_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT024, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[24] 1176 CYHAL_TRIGGER_TCPWM0_TR_OUT024_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT024, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[24] 1177 CYHAL_TRIGGER_TCPWM0_TR_OUT025_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT025, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[25] 1178 CYHAL_TRIGGER_TCPWM0_TR_OUT025_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT025, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[25] 1179 CYHAL_TRIGGER_TCPWM0_TR_OUT026_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT026, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[26] 1180 CYHAL_TRIGGER_TCPWM0_TR_OUT026_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT026, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[26] 1181 CYHAL_TRIGGER_TCPWM0_TR_OUT027_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT027, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[27] 1182 CYHAL_TRIGGER_TCPWM0_TR_OUT027_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT027, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[27] 1183 CYHAL_TRIGGER_TCPWM0_TR_OUT028_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT028, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[28] 1184 CYHAL_TRIGGER_TCPWM0_TR_OUT028_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT028, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[28] 1185 CYHAL_TRIGGER_TCPWM0_TR_OUT029_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT029, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[29] 1186 CYHAL_TRIGGER_TCPWM0_TR_OUT029_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT029, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[29] 1187 CYHAL_TRIGGER_TCPWM0_TR_OUT030_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT030, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[30] 1188 CYHAL_TRIGGER_TCPWM0_TR_OUT030_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT030, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[30] 1189 CYHAL_TRIGGER_TCPWM0_TR_OUT031_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT031, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[31] 1190 CYHAL_TRIGGER_TCPWM0_TR_OUT031_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT031, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[31] 1191 CYHAL_TRIGGER_TCPWM0_TR_OUT032_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT032, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[32] 1192 CYHAL_TRIGGER_TCPWM0_TR_OUT032_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT032, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[32] 1193 CYHAL_TRIGGER_TCPWM0_TR_OUT033_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT033, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[33] 1194 CYHAL_TRIGGER_TCPWM0_TR_OUT033_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT033, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[33] 1195 CYHAL_TRIGGER_TCPWM0_TR_OUT034_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT034, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[34] 1196 CYHAL_TRIGGER_TCPWM0_TR_OUT034_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT034, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[34] 1197 CYHAL_TRIGGER_TCPWM0_TR_OUT035_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT035, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[35] 1198 CYHAL_TRIGGER_TCPWM0_TR_OUT035_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT035, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[35] 1199 CYHAL_TRIGGER_TCPWM0_TR_OUT036_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT036, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[36] 1200 CYHAL_TRIGGER_TCPWM0_TR_OUT036_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT036, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[36] 1201 CYHAL_TRIGGER_TCPWM0_TR_OUT037_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT037, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[37] 1202 CYHAL_TRIGGER_TCPWM0_TR_OUT037_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT037, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[37] 1203 CYHAL_TRIGGER_TCPWM0_TR_OUT038_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT038, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[38] 1204 CYHAL_TRIGGER_TCPWM0_TR_OUT038_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT038, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[38] 1205 CYHAL_TRIGGER_TCPWM0_TR_OUT039_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT039, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[39] 1206 CYHAL_TRIGGER_TCPWM0_TR_OUT039_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT039, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[39] 1207 CYHAL_TRIGGER_TCPWM0_TR_OUT040_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT040, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[40] 1208 CYHAL_TRIGGER_TCPWM0_TR_OUT040_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT040, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[40] 1209 CYHAL_TRIGGER_TCPWM0_TR_OUT041_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT041, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[41] 1210 CYHAL_TRIGGER_TCPWM0_TR_OUT041_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT041, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[41] 1211 CYHAL_TRIGGER_TCPWM0_TR_OUT042_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT042, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[42] 1212 CYHAL_TRIGGER_TCPWM0_TR_OUT042_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT042, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[42] 1213 CYHAL_TRIGGER_TCPWM0_TR_OUT043_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT043, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[43] 1214 CYHAL_TRIGGER_TCPWM0_TR_OUT043_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT043, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[43] 1215 CYHAL_TRIGGER_TCPWM0_TR_OUT044_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT044, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[44] 1216 CYHAL_TRIGGER_TCPWM0_TR_OUT044_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT044, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[44] 1217 CYHAL_TRIGGER_TCPWM0_TR_OUT045_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT045, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[45] 1218 CYHAL_TRIGGER_TCPWM0_TR_OUT045_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT045, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[45] 1219 CYHAL_TRIGGER_TCPWM0_TR_OUT046_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT046, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[46] 1220 CYHAL_TRIGGER_TCPWM0_TR_OUT046_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT046, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[46] 1221 CYHAL_TRIGGER_TCPWM0_TR_OUT047_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT047, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[47] 1222 CYHAL_TRIGGER_TCPWM0_TR_OUT047_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT047, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[47] 1223 CYHAL_TRIGGER_TCPWM0_TR_OUT048_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT048, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[48] 1224 CYHAL_TRIGGER_TCPWM0_TR_OUT048_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT048, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[48] 1225 CYHAL_TRIGGER_TCPWM0_TR_OUT049_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT049, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[49] 1226 CYHAL_TRIGGER_TCPWM0_TR_OUT049_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT049, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[49] 1227 CYHAL_TRIGGER_TCPWM0_TR_OUT050_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT050, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[50] 1228 CYHAL_TRIGGER_TCPWM0_TR_OUT050_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT050, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[50] 1229 CYHAL_TRIGGER_TCPWM0_TR_OUT051_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT051, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[51] 1230 CYHAL_TRIGGER_TCPWM0_TR_OUT051_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT051, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[51] 1231 CYHAL_TRIGGER_TCPWM0_TR_OUT052_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT052, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[52] 1232 CYHAL_TRIGGER_TCPWM0_TR_OUT052_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT052, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[52] 1233 CYHAL_TRIGGER_TCPWM0_TR_OUT053_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT053, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[53] 1234 CYHAL_TRIGGER_TCPWM0_TR_OUT053_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT053, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[53] 1235 CYHAL_TRIGGER_TCPWM0_TR_OUT054_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT054, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[54] 1236 CYHAL_TRIGGER_TCPWM0_TR_OUT054_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT054, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[54] 1237 CYHAL_TRIGGER_TCPWM0_TR_OUT055_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT055, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[55] 1238 CYHAL_TRIGGER_TCPWM0_TR_OUT055_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT055, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[55] 1239 CYHAL_TRIGGER_TCPWM0_TR_OUT056_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT056, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[56] 1240 CYHAL_TRIGGER_TCPWM0_TR_OUT056_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT056, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[56] 1241 CYHAL_TRIGGER_TCPWM0_TR_OUT057_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT057, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[57] 1242 CYHAL_TRIGGER_TCPWM0_TR_OUT057_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT057, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[57] 1243 CYHAL_TRIGGER_TCPWM0_TR_OUT058_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT058, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[58] 1244 CYHAL_TRIGGER_TCPWM0_TR_OUT058_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT058, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[58] 1245 CYHAL_TRIGGER_TCPWM0_TR_OUT059_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT059, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[59] 1246 CYHAL_TRIGGER_TCPWM0_TR_OUT059_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT059, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[59] 1247 CYHAL_TRIGGER_TCPWM0_TR_OUT060_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT060, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[60] 1248 CYHAL_TRIGGER_TCPWM0_TR_OUT060_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT060, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[60] 1249 CYHAL_TRIGGER_TCPWM0_TR_OUT061_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT061, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[61] 1250 CYHAL_TRIGGER_TCPWM0_TR_OUT061_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT061, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[61] 1251 CYHAL_TRIGGER_TCPWM0_TR_OUT062_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT062, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[62] 1252 CYHAL_TRIGGER_TCPWM0_TR_OUT062_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT062, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[62] 1253 CYHAL_TRIGGER_TCPWM0_TR_OUT0256_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0256, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[256] 1254 CYHAL_TRIGGER_TCPWM0_TR_OUT0256_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0256, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[256] 1255 CYHAL_TRIGGER_TCPWM0_TR_OUT0257_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0257, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[257] 1256 CYHAL_TRIGGER_TCPWM0_TR_OUT0257_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0257, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[257] 1257 CYHAL_TRIGGER_TCPWM0_TR_OUT0258_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0258, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[258] 1258 CYHAL_TRIGGER_TCPWM0_TR_OUT0258_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0258, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[258] 1259 CYHAL_TRIGGER_TCPWM0_TR_OUT0259_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0259, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[259] 1260 CYHAL_TRIGGER_TCPWM0_TR_OUT0259_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0259, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[259] 1261 CYHAL_TRIGGER_TCPWM0_TR_OUT0260_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0260, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[260] 1262 CYHAL_TRIGGER_TCPWM0_TR_OUT0260_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0260, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[260] 1263 CYHAL_TRIGGER_TCPWM0_TR_OUT0261_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0261, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[261] 1264 CYHAL_TRIGGER_TCPWM0_TR_OUT0261_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0261, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[261] 1265 CYHAL_TRIGGER_TCPWM0_TR_OUT0262_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0262, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[262] 1266 CYHAL_TRIGGER_TCPWM0_TR_OUT0262_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0262, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[262] 1267 CYHAL_TRIGGER_TCPWM0_TR_OUT0263_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0263, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[263] 1268 CYHAL_TRIGGER_TCPWM0_TR_OUT0263_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0263, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[263] 1269 CYHAL_TRIGGER_TCPWM0_TR_OUT0264_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0264, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[264] 1270 CYHAL_TRIGGER_TCPWM0_TR_OUT0264_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0264, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[264] 1271 CYHAL_TRIGGER_TCPWM0_TR_OUT0265_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0265, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[265] 1272 CYHAL_TRIGGER_TCPWM0_TR_OUT0265_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0265, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[265] 1273 CYHAL_TRIGGER_TCPWM0_TR_OUT0266_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0266, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[266] 1274 CYHAL_TRIGGER_TCPWM0_TR_OUT0266_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0266, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[266] 1275 CYHAL_TRIGGER_TCPWM0_TR_OUT0267_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0267, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[267] 1276 CYHAL_TRIGGER_TCPWM0_TR_OUT0267_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0267, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[267] 1277 CYHAL_TRIGGER_TCPWM0_TR_OUT0512_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0512, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[512] 1278 CYHAL_TRIGGER_TCPWM0_TR_OUT0512_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0512, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[512] 1279 CYHAL_TRIGGER_TCPWM0_TR_OUT0513_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0513, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[513] 1280 CYHAL_TRIGGER_TCPWM0_TR_OUT0513_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0513, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[513] 1281 CYHAL_TRIGGER_TCPWM0_TR_OUT0514_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0514, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[514] 1282 CYHAL_TRIGGER_TCPWM0_TR_OUT0514_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0514, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[514] 1283 CYHAL_TRIGGER_TCPWM0_TR_OUT0515_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0515, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[515] 1284 CYHAL_TRIGGER_TCPWM0_TR_OUT0515_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0515, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[515] 1285 CYHAL_TRIGGER_TCPWM0_TR_OUT0516_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0516, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[516] 1286 CYHAL_TRIGGER_TCPWM0_TR_OUT0516_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0516, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[516] 1287 CYHAL_TRIGGER_TCPWM0_TR_OUT0517_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0517, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[517] 1288 CYHAL_TRIGGER_TCPWM0_TR_OUT0517_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0517, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[517] 1289 CYHAL_TRIGGER_TCPWM0_TR_OUT0518_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0518, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[518] 1290 CYHAL_TRIGGER_TCPWM0_TR_OUT0518_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0518, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[518] 1291 CYHAL_TRIGGER_TCPWM0_TR_OUT0519_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0519, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[519] 1292 CYHAL_TRIGGER_TCPWM0_TR_OUT0519_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0519, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[519] 1293 CYHAL_TRIGGER_TCPWM0_TR_OUT10_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT10, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[0] 1294 CYHAL_TRIGGER_TCPWM0_TR_OUT10_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT10, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[0] 1295 CYHAL_TRIGGER_TCPWM0_TR_OUT11_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT11, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[1] 1296 CYHAL_TRIGGER_TCPWM0_TR_OUT11_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT11, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[1] 1297 CYHAL_TRIGGER_TCPWM0_TR_OUT12_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT12, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[2] 1298 CYHAL_TRIGGER_TCPWM0_TR_OUT12_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT12, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[2] 1299 CYHAL_TRIGGER_TCPWM0_TR_OUT13_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT13, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[3] 1300 CYHAL_TRIGGER_TCPWM0_TR_OUT13_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT13, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[3] 1301 CYHAL_TRIGGER_TCPWM0_TR_OUT14_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT14, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[4] 1302 CYHAL_TRIGGER_TCPWM0_TR_OUT14_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT14, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[4] 1303 CYHAL_TRIGGER_TCPWM0_TR_OUT15_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT15, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[5] 1304 CYHAL_TRIGGER_TCPWM0_TR_OUT15_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT15, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[5] 1305 CYHAL_TRIGGER_TCPWM0_TR_OUT16_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT16, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[6] 1306 CYHAL_TRIGGER_TCPWM0_TR_OUT16_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT16, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[6] 1307 CYHAL_TRIGGER_TCPWM0_TR_OUT17_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT17, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[7] 1308 CYHAL_TRIGGER_TCPWM0_TR_OUT17_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT17, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[7] 1309 CYHAL_TRIGGER_TCPWM0_TR_OUT18_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT18, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[8] 1310 CYHAL_TRIGGER_TCPWM0_TR_OUT18_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT18, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[8] 1311 CYHAL_TRIGGER_TCPWM0_TR_OUT19_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT19, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[9] 1312 CYHAL_TRIGGER_TCPWM0_TR_OUT19_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT19, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[9] 1313 CYHAL_TRIGGER_TCPWM0_TR_OUT110_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT110, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[10] 1314 CYHAL_TRIGGER_TCPWM0_TR_OUT110_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT110, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[10] 1315 CYHAL_TRIGGER_TCPWM0_TR_OUT111_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT111, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[11] 1316 CYHAL_TRIGGER_TCPWM0_TR_OUT111_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT111, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[11] 1317 CYHAL_TRIGGER_TCPWM0_TR_OUT112_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT112, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[12] 1318 CYHAL_TRIGGER_TCPWM0_TR_OUT112_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT112, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[12] 1319 CYHAL_TRIGGER_TCPWM0_TR_OUT113_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT113, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[13] 1320 CYHAL_TRIGGER_TCPWM0_TR_OUT113_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT113, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[13] 1321 CYHAL_TRIGGER_TCPWM0_TR_OUT114_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT114, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[14] 1322 CYHAL_TRIGGER_TCPWM0_TR_OUT114_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT114, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[14] 1323 CYHAL_TRIGGER_TCPWM0_TR_OUT115_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT115, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[15] 1324 CYHAL_TRIGGER_TCPWM0_TR_OUT115_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT115, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[15] 1325 CYHAL_TRIGGER_TCPWM0_TR_OUT116_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT116, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[16] 1326 CYHAL_TRIGGER_TCPWM0_TR_OUT116_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT116, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[16] 1327 CYHAL_TRIGGER_TCPWM0_TR_OUT117_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT117, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[17] 1328 CYHAL_TRIGGER_TCPWM0_TR_OUT117_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT117, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[17] 1329 CYHAL_TRIGGER_TCPWM0_TR_OUT118_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT118, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[18] 1330 CYHAL_TRIGGER_TCPWM0_TR_OUT118_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT118, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[18] 1331 CYHAL_TRIGGER_TCPWM0_TR_OUT119_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT119, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[19] 1332 CYHAL_TRIGGER_TCPWM0_TR_OUT119_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT119, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[19] 1333 CYHAL_TRIGGER_TCPWM0_TR_OUT120_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT120, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[20] 1334 CYHAL_TRIGGER_TCPWM0_TR_OUT120_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT120, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[20] 1335 CYHAL_TRIGGER_TCPWM0_TR_OUT121_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT121, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[21] 1336 CYHAL_TRIGGER_TCPWM0_TR_OUT121_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT121, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[21] 1337 CYHAL_TRIGGER_TCPWM0_TR_OUT122_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT122, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[22] 1338 CYHAL_TRIGGER_TCPWM0_TR_OUT122_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT122, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[22] 1339 CYHAL_TRIGGER_TCPWM0_TR_OUT123_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT123, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[23] 1340 CYHAL_TRIGGER_TCPWM0_TR_OUT123_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT123, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[23] 1341 CYHAL_TRIGGER_TCPWM0_TR_OUT124_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT124, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[24] 1342 CYHAL_TRIGGER_TCPWM0_TR_OUT124_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT124, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[24] 1343 CYHAL_TRIGGER_TCPWM0_TR_OUT125_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT125, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[25] 1344 CYHAL_TRIGGER_TCPWM0_TR_OUT125_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT125, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[25] 1345 CYHAL_TRIGGER_TCPWM0_TR_OUT126_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT126, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[26] 1346 CYHAL_TRIGGER_TCPWM0_TR_OUT126_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT126, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[26] 1347 CYHAL_TRIGGER_TCPWM0_TR_OUT127_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT127, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[27] 1348 CYHAL_TRIGGER_TCPWM0_TR_OUT127_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT127, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[27] 1349 CYHAL_TRIGGER_TCPWM0_TR_OUT128_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT128, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[28] 1350 CYHAL_TRIGGER_TCPWM0_TR_OUT128_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT128, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[28] 1351 CYHAL_TRIGGER_TCPWM0_TR_OUT129_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT129, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[29] 1352 CYHAL_TRIGGER_TCPWM0_TR_OUT129_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT129, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[29] 1353 CYHAL_TRIGGER_TCPWM0_TR_OUT130_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT130, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[30] 1354 CYHAL_TRIGGER_TCPWM0_TR_OUT130_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT130, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[30] 1355 CYHAL_TRIGGER_TCPWM0_TR_OUT131_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT131, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[31] 1356 CYHAL_TRIGGER_TCPWM0_TR_OUT131_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT131, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[31] 1357 CYHAL_TRIGGER_TCPWM0_TR_OUT132_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT132, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[32] 1358 CYHAL_TRIGGER_TCPWM0_TR_OUT132_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT132, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[32] 1359 CYHAL_TRIGGER_TCPWM0_TR_OUT133_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT133, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[33] 1360 CYHAL_TRIGGER_TCPWM0_TR_OUT133_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT133, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[33] 1361 CYHAL_TRIGGER_TCPWM0_TR_OUT134_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT134, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[34] 1362 CYHAL_TRIGGER_TCPWM0_TR_OUT134_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT134, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[34] 1363 CYHAL_TRIGGER_TCPWM0_TR_OUT135_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT135, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[35] 1364 CYHAL_TRIGGER_TCPWM0_TR_OUT135_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT135, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[35] 1365 CYHAL_TRIGGER_TCPWM0_TR_OUT136_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT136, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[36] 1366 CYHAL_TRIGGER_TCPWM0_TR_OUT136_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT136, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[36] 1367 CYHAL_TRIGGER_TCPWM0_TR_OUT137_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT137, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[37] 1368 CYHAL_TRIGGER_TCPWM0_TR_OUT137_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT137, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[37] 1369 CYHAL_TRIGGER_TCPWM0_TR_OUT138_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT138, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[38] 1370 CYHAL_TRIGGER_TCPWM0_TR_OUT138_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT138, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[38] 1371 CYHAL_TRIGGER_TCPWM0_TR_OUT139_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT139, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[39] 1372 CYHAL_TRIGGER_TCPWM0_TR_OUT139_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT139, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[39] 1373 CYHAL_TRIGGER_TCPWM0_TR_OUT140_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT140, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[40] 1374 CYHAL_TRIGGER_TCPWM0_TR_OUT140_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT140, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[40] 1375 CYHAL_TRIGGER_TCPWM0_TR_OUT141_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT141, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[41] 1376 CYHAL_TRIGGER_TCPWM0_TR_OUT141_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT141, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[41] 1377 CYHAL_TRIGGER_TCPWM0_TR_OUT142_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT142, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[42] 1378 CYHAL_TRIGGER_TCPWM0_TR_OUT142_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT142, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[42] 1379 CYHAL_TRIGGER_TCPWM0_TR_OUT143_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT143, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[43] 1380 CYHAL_TRIGGER_TCPWM0_TR_OUT143_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT143, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[43] 1381 CYHAL_TRIGGER_TCPWM0_TR_OUT144_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT144, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[44] 1382 CYHAL_TRIGGER_TCPWM0_TR_OUT144_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT144, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[44] 1383 CYHAL_TRIGGER_TCPWM0_TR_OUT145_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT145, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[45] 1384 CYHAL_TRIGGER_TCPWM0_TR_OUT145_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT145, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[45] 1385 CYHAL_TRIGGER_TCPWM0_TR_OUT146_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT146, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[46] 1386 CYHAL_TRIGGER_TCPWM0_TR_OUT146_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT146, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[46] 1387 CYHAL_TRIGGER_TCPWM0_TR_OUT147_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT147, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[47] 1388 CYHAL_TRIGGER_TCPWM0_TR_OUT147_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT147, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[47] 1389 CYHAL_TRIGGER_TCPWM0_TR_OUT148_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT148, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[48] 1390 CYHAL_TRIGGER_TCPWM0_TR_OUT148_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT148, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[48] 1391 CYHAL_TRIGGER_TCPWM0_TR_OUT149_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT149, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[49] 1392 CYHAL_TRIGGER_TCPWM0_TR_OUT149_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT149, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[49] 1393 CYHAL_TRIGGER_TCPWM0_TR_OUT150_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT150, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[50] 1394 CYHAL_TRIGGER_TCPWM0_TR_OUT150_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT150, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[50] 1395 CYHAL_TRIGGER_TCPWM0_TR_OUT151_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT151, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[51] 1396 CYHAL_TRIGGER_TCPWM0_TR_OUT151_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT151, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[51] 1397 CYHAL_TRIGGER_TCPWM0_TR_OUT152_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT152, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[52] 1398 CYHAL_TRIGGER_TCPWM0_TR_OUT152_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT152, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[52] 1399 CYHAL_TRIGGER_TCPWM0_TR_OUT153_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT153, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[53] 1400 CYHAL_TRIGGER_TCPWM0_TR_OUT153_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT153, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[53] 1401 CYHAL_TRIGGER_TCPWM0_TR_OUT154_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT154, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[54] 1402 CYHAL_TRIGGER_TCPWM0_TR_OUT154_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT154, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[54] 1403 CYHAL_TRIGGER_TCPWM0_TR_OUT155_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT155, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[55] 1404 CYHAL_TRIGGER_TCPWM0_TR_OUT155_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT155, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[55] 1405 CYHAL_TRIGGER_TCPWM0_TR_OUT156_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT156, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[56] 1406 CYHAL_TRIGGER_TCPWM0_TR_OUT156_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT156, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[56] 1407 CYHAL_TRIGGER_TCPWM0_TR_OUT157_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT157, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[57] 1408 CYHAL_TRIGGER_TCPWM0_TR_OUT157_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT157, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[57] 1409 CYHAL_TRIGGER_TCPWM0_TR_OUT158_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT158, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[58] 1410 CYHAL_TRIGGER_TCPWM0_TR_OUT158_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT158, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[58] 1411 CYHAL_TRIGGER_TCPWM0_TR_OUT159_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT159, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[59] 1412 CYHAL_TRIGGER_TCPWM0_TR_OUT159_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT159, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[59] 1413 CYHAL_TRIGGER_TCPWM0_TR_OUT160_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT160, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[60] 1414 CYHAL_TRIGGER_TCPWM0_TR_OUT160_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT160, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[60] 1415 CYHAL_TRIGGER_TCPWM0_TR_OUT161_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT161, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[61] 1416 CYHAL_TRIGGER_TCPWM0_TR_OUT161_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT161, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[61] 1417 CYHAL_TRIGGER_TCPWM0_TR_OUT162_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT162, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[62] 1418 CYHAL_TRIGGER_TCPWM0_TR_OUT162_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT162, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[62] 1419 CYHAL_TRIGGER_TCPWM0_TR_OUT1256_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1256, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[256] 1420 CYHAL_TRIGGER_TCPWM0_TR_OUT1256_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1256, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[256] 1421 CYHAL_TRIGGER_TCPWM0_TR_OUT1257_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1257, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[257] 1422 CYHAL_TRIGGER_TCPWM0_TR_OUT1257_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1257, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[257] 1423 CYHAL_TRIGGER_TCPWM0_TR_OUT1258_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1258, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[258] 1424 CYHAL_TRIGGER_TCPWM0_TR_OUT1258_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1258, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[258] 1425 CYHAL_TRIGGER_TCPWM0_TR_OUT1259_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1259, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[259] 1426 CYHAL_TRIGGER_TCPWM0_TR_OUT1259_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1259, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[259] 1427 CYHAL_TRIGGER_TCPWM0_TR_OUT1260_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1260, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[260] 1428 CYHAL_TRIGGER_TCPWM0_TR_OUT1260_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1260, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[260] 1429 CYHAL_TRIGGER_TCPWM0_TR_OUT1261_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1261, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[261] 1430 CYHAL_TRIGGER_TCPWM0_TR_OUT1261_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1261, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[261] 1431 CYHAL_TRIGGER_TCPWM0_TR_OUT1262_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1262, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[262] 1432 CYHAL_TRIGGER_TCPWM0_TR_OUT1262_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1262, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[262] 1433 CYHAL_TRIGGER_TCPWM0_TR_OUT1263_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1263, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[263] 1434 CYHAL_TRIGGER_TCPWM0_TR_OUT1263_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1263, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[263] 1435 CYHAL_TRIGGER_TCPWM0_TR_OUT1264_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1264, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[264] 1436 CYHAL_TRIGGER_TCPWM0_TR_OUT1264_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1264, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[264] 1437 CYHAL_TRIGGER_TCPWM0_TR_OUT1265_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1265, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[265] 1438 CYHAL_TRIGGER_TCPWM0_TR_OUT1265_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1265, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[265] 1439 CYHAL_TRIGGER_TCPWM0_TR_OUT1266_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1266, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[266] 1440 CYHAL_TRIGGER_TCPWM0_TR_OUT1266_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1266, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[266] 1441 CYHAL_TRIGGER_TCPWM0_TR_OUT1267_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1267, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[267] 1442 CYHAL_TRIGGER_TCPWM0_TR_OUT1267_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1267, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[267] 1443 CYHAL_TRIGGER_TCPWM0_TR_OUT1512_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1512, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[512] 1444 CYHAL_TRIGGER_TCPWM0_TR_OUT1512_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1512, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[512] 1445 CYHAL_TRIGGER_TCPWM0_TR_OUT1513_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1513, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[513] 1446 CYHAL_TRIGGER_TCPWM0_TR_OUT1513_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1513, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[513] 1447 CYHAL_TRIGGER_TCPWM0_TR_OUT1514_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1514, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[514] 1448 CYHAL_TRIGGER_TCPWM0_TR_OUT1514_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1514, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[514] 1449 CYHAL_TRIGGER_TCPWM0_TR_OUT1515_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1515, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[515] 1450 CYHAL_TRIGGER_TCPWM0_TR_OUT1515_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1515, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[515] 1451 CYHAL_TRIGGER_TCPWM0_TR_OUT1516_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1516, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[516] 1452 CYHAL_TRIGGER_TCPWM0_TR_OUT1516_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1516, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[516] 1453 CYHAL_TRIGGER_TCPWM0_TR_OUT1517_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1517, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[517] 1454 CYHAL_TRIGGER_TCPWM0_TR_OUT1517_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1517, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[517] 1455 CYHAL_TRIGGER_TCPWM0_TR_OUT1518_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1518, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[518] 1456 CYHAL_TRIGGER_TCPWM0_TR_OUT1518_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1518, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[518] 1457 CYHAL_TRIGGER_TCPWM0_TR_OUT1519_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1519, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[519] 1458 CYHAL_TRIGGER_TCPWM0_TR_OUT1519_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1519, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[519] 1459 CYHAL_TRIGGER_TR_GROUP9_OUTPUT0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP9_OUTPUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[9].output[0] 1460 CYHAL_TRIGGER_TR_GROUP9_OUTPUT0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP9_OUTPUT0, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[9].output[0] 1461 CYHAL_TRIGGER_TR_GROUP9_OUTPUT1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP9_OUTPUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[9].output[1] 1462 CYHAL_TRIGGER_TR_GROUP9_OUTPUT1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP9_OUTPUT1, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[9].output[1] 1463 CYHAL_TRIGGER_TR_GROUP9_OUTPUT2_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP9_OUTPUT2, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[9].output[2] 1464 CYHAL_TRIGGER_TR_GROUP9_OUTPUT2_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP9_OUTPUT2, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[9].output[2] 1465 CYHAL_TRIGGER_TR_GROUP9_OUTPUT3_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP9_OUTPUT3, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[9].output[3] 1466 CYHAL_TRIGGER_TR_GROUP9_OUTPUT3_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP9_OUTPUT3, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[9].output[3] 1467 CYHAL_TRIGGER_TR_GROUP9_OUTPUT4_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP9_OUTPUT4, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[9].output[4] 1468 CYHAL_TRIGGER_TR_GROUP9_OUTPUT4_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP9_OUTPUT4, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[9].output[4] 1469 CYHAL_TRIGGER_TR_GROUP10_OUTPUT0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[10].output[0] 1470 CYHAL_TRIGGER_TR_GROUP10_OUTPUT0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT0, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[10].output[0] 1471 CYHAL_TRIGGER_TR_GROUP10_OUTPUT1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[10].output[1] 1472 CYHAL_TRIGGER_TR_GROUP10_OUTPUT1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT1, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[10].output[1] 1473 CYHAL_TRIGGER_TR_GROUP10_OUTPUT2_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT2, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[10].output[2] 1474 CYHAL_TRIGGER_TR_GROUP10_OUTPUT2_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT2, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[10].output[2] 1475 CYHAL_TRIGGER_TR_GROUP10_OUTPUT3_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT3, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[10].output[3] 1476 CYHAL_TRIGGER_TR_GROUP10_OUTPUT3_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT3, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[10].output[3] 1477 CYHAL_TRIGGER_TR_GROUP10_OUTPUT4_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT4, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[10].output[4] 1478 CYHAL_TRIGGER_TR_GROUP10_OUTPUT4_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT4, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[10].output[4] 1479 } cyhal_trigger_source_tviibe4m_t; 1480 1481 /** Typedef from device family specific trigger source to generic trigger source */ 1482 typedef cyhal_trigger_source_tviibe4m_t cyhal_source_t; 1483 1484 /** Deprecated defines for signals that can be either level or edge. */ 1485 #define CYHAL_TRIGGER_CPUSS_ZERO (CYHAL_TRIGGER_CPUSS_ZERO_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1486 #define CYHAL_TRIGGER_EVTGEN0_TR_OUT0 (CYHAL_TRIGGER_EVTGEN0_TR_OUT0_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1487 #define CYHAL_TRIGGER_EVTGEN0_TR_OUT1 (CYHAL_TRIGGER_EVTGEN0_TR_OUT1_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1488 #define CYHAL_TRIGGER_EVTGEN0_TR_OUT2 (CYHAL_TRIGGER_EVTGEN0_TR_OUT2_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1489 #define CYHAL_TRIGGER_EVTGEN0_TR_OUT3 (CYHAL_TRIGGER_EVTGEN0_TR_OUT3_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1490 #define CYHAL_TRIGGER_EVTGEN0_TR_OUT4 (CYHAL_TRIGGER_EVTGEN0_TR_OUT4_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1491 #define CYHAL_TRIGGER_EVTGEN0_TR_OUT5 (CYHAL_TRIGGER_EVTGEN0_TR_OUT5_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1492 #define CYHAL_TRIGGER_EVTGEN0_TR_OUT6 (CYHAL_TRIGGER_EVTGEN0_TR_OUT6_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1493 #define CYHAL_TRIGGER_EVTGEN0_TR_OUT7 (CYHAL_TRIGGER_EVTGEN0_TR_OUT7_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1494 #define CYHAL_TRIGGER_EVTGEN0_TR_OUT8 (CYHAL_TRIGGER_EVTGEN0_TR_OUT8_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1495 #define CYHAL_TRIGGER_EVTGEN0_TR_OUT9 (CYHAL_TRIGGER_EVTGEN0_TR_OUT9_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1496 #define CYHAL_TRIGGER_EVTGEN0_TR_OUT10 (CYHAL_TRIGGER_EVTGEN0_TR_OUT10_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1497 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE0 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE0_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1498 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE1 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE1_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1499 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE2 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE2_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1500 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE3 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE3_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1501 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE4 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE4_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1502 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE5 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE5_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1503 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE6 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE6_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1504 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE7 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE7_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1505 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE8 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE8_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1506 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE9 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE9_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1507 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE10 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE10_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1508 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE11 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE11_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1509 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE12 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE12_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1510 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE13 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE13_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1511 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE14 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE14_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1512 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE15 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE15_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1513 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE16 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE16_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1514 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE17 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE17_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1515 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE18 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE18_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1516 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE19 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE19_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1517 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE20 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE20_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1518 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE21 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE21_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1519 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE22 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE22_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1520 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE23 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE23_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1521 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE32 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE32_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1522 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE33 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE33_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1523 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE34 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE34_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1524 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE35 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE35_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1525 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE36 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE36_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1526 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE37 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE37_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1527 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE38 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE38_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1528 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE39 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE39_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1529 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE40 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE40_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1530 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE41 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE41_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1531 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE42 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE42_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1532 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE43 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE43_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1533 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE44 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE44_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1534 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE45 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE45_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1535 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE46 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE46_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1536 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE47 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE47_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1537 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE48 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE48_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1538 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE49 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE49_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1539 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE50 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE50_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1540 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE51 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE51_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1541 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE52 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE52_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1542 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE53 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE53_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1543 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE54 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE54_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1544 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE55 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE55_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1545 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE56 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE56_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1546 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE57 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE57_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1547 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE58 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE58_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1548 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE59 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE59_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1549 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE60 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE60_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1550 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE61 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE61_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1551 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE62 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE62_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1552 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE63 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE63_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1553 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE64 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE64_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1554 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE65 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE65_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1555 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE66 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE66_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1556 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE67 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE67_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1557 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE68 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE68_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1558 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE69 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE69_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1559 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE70 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE70_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1560 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE71 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE71_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1561 #define CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT0 (CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT0_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1562 #define CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT1 (CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT1_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1563 #define CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT2 (CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT2_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1564 #define CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT3 (CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT3_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1565 #define CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT4 (CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT4_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1566 #define CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT5 (CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT5_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1567 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT0 (CYHAL_TRIGGER_PERI_TR_IO_INPUT0_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1568 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT1 (CYHAL_TRIGGER_PERI_TR_IO_INPUT1_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1569 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT2 (CYHAL_TRIGGER_PERI_TR_IO_INPUT2_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1570 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT3 (CYHAL_TRIGGER_PERI_TR_IO_INPUT3_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1571 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT4 (CYHAL_TRIGGER_PERI_TR_IO_INPUT4_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1572 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT5 (CYHAL_TRIGGER_PERI_TR_IO_INPUT5_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1573 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT6 (CYHAL_TRIGGER_PERI_TR_IO_INPUT6_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1574 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT7 (CYHAL_TRIGGER_PERI_TR_IO_INPUT7_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1575 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT8 (CYHAL_TRIGGER_PERI_TR_IO_INPUT8_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1576 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT9 (CYHAL_TRIGGER_PERI_TR_IO_INPUT9_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1577 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT10 (CYHAL_TRIGGER_PERI_TR_IO_INPUT10_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1578 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT11 (CYHAL_TRIGGER_PERI_TR_IO_INPUT11_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1579 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT12 (CYHAL_TRIGGER_PERI_TR_IO_INPUT12_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1580 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT13 (CYHAL_TRIGGER_PERI_TR_IO_INPUT13_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1581 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT14 (CYHAL_TRIGGER_PERI_TR_IO_INPUT14_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1582 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT15 (CYHAL_TRIGGER_PERI_TR_IO_INPUT15_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1583 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT16 (CYHAL_TRIGGER_PERI_TR_IO_INPUT16_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1584 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT17 (CYHAL_TRIGGER_PERI_TR_IO_INPUT17_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1585 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT18 (CYHAL_TRIGGER_PERI_TR_IO_INPUT18_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1586 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT19 (CYHAL_TRIGGER_PERI_TR_IO_INPUT19_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1587 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT20 (CYHAL_TRIGGER_PERI_TR_IO_INPUT20_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1588 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT21 (CYHAL_TRIGGER_PERI_TR_IO_INPUT21_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1589 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT22 (CYHAL_TRIGGER_PERI_TR_IO_INPUT22_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1590 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT23 (CYHAL_TRIGGER_PERI_TR_IO_INPUT23_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1591 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT24 (CYHAL_TRIGGER_PERI_TR_IO_INPUT24_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1592 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT25 (CYHAL_TRIGGER_PERI_TR_IO_INPUT25_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1593 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT26 (CYHAL_TRIGGER_PERI_TR_IO_INPUT26_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1594 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT27 (CYHAL_TRIGGER_PERI_TR_IO_INPUT27_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1595 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT28 (CYHAL_TRIGGER_PERI_TR_IO_INPUT28_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1596 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT29 (CYHAL_TRIGGER_PERI_TR_IO_INPUT29_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1597 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT30 (CYHAL_TRIGGER_PERI_TR_IO_INPUT30_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1598 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT31 (CYHAL_TRIGGER_PERI_TR_IO_INPUT31_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1599 #define CYHAL_TRIGGER_TCPWM0_TR_OUT00 (CYHAL_TRIGGER_TCPWM0_TR_OUT00_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1600 #define CYHAL_TRIGGER_TCPWM0_TR_OUT01 (CYHAL_TRIGGER_TCPWM0_TR_OUT01_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1601 #define CYHAL_TRIGGER_TCPWM0_TR_OUT02 (CYHAL_TRIGGER_TCPWM0_TR_OUT02_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1602 #define CYHAL_TRIGGER_TCPWM0_TR_OUT03 (CYHAL_TRIGGER_TCPWM0_TR_OUT03_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1603 #define CYHAL_TRIGGER_TCPWM0_TR_OUT04 (CYHAL_TRIGGER_TCPWM0_TR_OUT04_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1604 #define CYHAL_TRIGGER_TCPWM0_TR_OUT05 (CYHAL_TRIGGER_TCPWM0_TR_OUT05_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1605 #define CYHAL_TRIGGER_TCPWM0_TR_OUT06 (CYHAL_TRIGGER_TCPWM0_TR_OUT06_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1606 #define CYHAL_TRIGGER_TCPWM0_TR_OUT07 (CYHAL_TRIGGER_TCPWM0_TR_OUT07_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1607 #define CYHAL_TRIGGER_TCPWM0_TR_OUT08 (CYHAL_TRIGGER_TCPWM0_TR_OUT08_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1608 #define CYHAL_TRIGGER_TCPWM0_TR_OUT09 (CYHAL_TRIGGER_TCPWM0_TR_OUT09_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1609 #define CYHAL_TRIGGER_TCPWM0_TR_OUT010 (CYHAL_TRIGGER_TCPWM0_TR_OUT010_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1610 #define CYHAL_TRIGGER_TCPWM0_TR_OUT011 (CYHAL_TRIGGER_TCPWM0_TR_OUT011_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1611 #define CYHAL_TRIGGER_TCPWM0_TR_OUT012 (CYHAL_TRIGGER_TCPWM0_TR_OUT012_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1612 #define CYHAL_TRIGGER_TCPWM0_TR_OUT013 (CYHAL_TRIGGER_TCPWM0_TR_OUT013_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1613 #define CYHAL_TRIGGER_TCPWM0_TR_OUT014 (CYHAL_TRIGGER_TCPWM0_TR_OUT014_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1614 #define CYHAL_TRIGGER_TCPWM0_TR_OUT015 (CYHAL_TRIGGER_TCPWM0_TR_OUT015_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1615 #define CYHAL_TRIGGER_TCPWM0_TR_OUT016 (CYHAL_TRIGGER_TCPWM0_TR_OUT016_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1616 #define CYHAL_TRIGGER_TCPWM0_TR_OUT017 (CYHAL_TRIGGER_TCPWM0_TR_OUT017_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1617 #define CYHAL_TRIGGER_TCPWM0_TR_OUT018 (CYHAL_TRIGGER_TCPWM0_TR_OUT018_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1618 #define CYHAL_TRIGGER_TCPWM0_TR_OUT019 (CYHAL_TRIGGER_TCPWM0_TR_OUT019_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1619 #define CYHAL_TRIGGER_TCPWM0_TR_OUT020 (CYHAL_TRIGGER_TCPWM0_TR_OUT020_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1620 #define CYHAL_TRIGGER_TCPWM0_TR_OUT021 (CYHAL_TRIGGER_TCPWM0_TR_OUT021_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1621 #define CYHAL_TRIGGER_TCPWM0_TR_OUT022 (CYHAL_TRIGGER_TCPWM0_TR_OUT022_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1622 #define CYHAL_TRIGGER_TCPWM0_TR_OUT023 (CYHAL_TRIGGER_TCPWM0_TR_OUT023_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1623 #define CYHAL_TRIGGER_TCPWM0_TR_OUT024 (CYHAL_TRIGGER_TCPWM0_TR_OUT024_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1624 #define CYHAL_TRIGGER_TCPWM0_TR_OUT025 (CYHAL_TRIGGER_TCPWM0_TR_OUT025_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1625 #define CYHAL_TRIGGER_TCPWM0_TR_OUT026 (CYHAL_TRIGGER_TCPWM0_TR_OUT026_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1626 #define CYHAL_TRIGGER_TCPWM0_TR_OUT027 (CYHAL_TRIGGER_TCPWM0_TR_OUT027_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1627 #define CYHAL_TRIGGER_TCPWM0_TR_OUT028 (CYHAL_TRIGGER_TCPWM0_TR_OUT028_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1628 #define CYHAL_TRIGGER_TCPWM0_TR_OUT029 (CYHAL_TRIGGER_TCPWM0_TR_OUT029_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1629 #define CYHAL_TRIGGER_TCPWM0_TR_OUT030 (CYHAL_TRIGGER_TCPWM0_TR_OUT030_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1630 #define CYHAL_TRIGGER_TCPWM0_TR_OUT031 (CYHAL_TRIGGER_TCPWM0_TR_OUT031_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1631 #define CYHAL_TRIGGER_TCPWM0_TR_OUT032 (CYHAL_TRIGGER_TCPWM0_TR_OUT032_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1632 #define CYHAL_TRIGGER_TCPWM0_TR_OUT033 (CYHAL_TRIGGER_TCPWM0_TR_OUT033_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1633 #define CYHAL_TRIGGER_TCPWM0_TR_OUT034 (CYHAL_TRIGGER_TCPWM0_TR_OUT034_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1634 #define CYHAL_TRIGGER_TCPWM0_TR_OUT035 (CYHAL_TRIGGER_TCPWM0_TR_OUT035_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1635 #define CYHAL_TRIGGER_TCPWM0_TR_OUT036 (CYHAL_TRIGGER_TCPWM0_TR_OUT036_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1636 #define CYHAL_TRIGGER_TCPWM0_TR_OUT037 (CYHAL_TRIGGER_TCPWM0_TR_OUT037_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1637 #define CYHAL_TRIGGER_TCPWM0_TR_OUT038 (CYHAL_TRIGGER_TCPWM0_TR_OUT038_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1638 #define CYHAL_TRIGGER_TCPWM0_TR_OUT039 (CYHAL_TRIGGER_TCPWM0_TR_OUT039_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1639 #define CYHAL_TRIGGER_TCPWM0_TR_OUT040 (CYHAL_TRIGGER_TCPWM0_TR_OUT040_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1640 #define CYHAL_TRIGGER_TCPWM0_TR_OUT041 (CYHAL_TRIGGER_TCPWM0_TR_OUT041_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1641 #define CYHAL_TRIGGER_TCPWM0_TR_OUT042 (CYHAL_TRIGGER_TCPWM0_TR_OUT042_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1642 #define CYHAL_TRIGGER_TCPWM0_TR_OUT043 (CYHAL_TRIGGER_TCPWM0_TR_OUT043_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1643 #define CYHAL_TRIGGER_TCPWM0_TR_OUT044 (CYHAL_TRIGGER_TCPWM0_TR_OUT044_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1644 #define CYHAL_TRIGGER_TCPWM0_TR_OUT045 (CYHAL_TRIGGER_TCPWM0_TR_OUT045_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1645 #define CYHAL_TRIGGER_TCPWM0_TR_OUT046 (CYHAL_TRIGGER_TCPWM0_TR_OUT046_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1646 #define CYHAL_TRIGGER_TCPWM0_TR_OUT047 (CYHAL_TRIGGER_TCPWM0_TR_OUT047_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1647 #define CYHAL_TRIGGER_TCPWM0_TR_OUT048 (CYHAL_TRIGGER_TCPWM0_TR_OUT048_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1648 #define CYHAL_TRIGGER_TCPWM0_TR_OUT049 (CYHAL_TRIGGER_TCPWM0_TR_OUT049_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1649 #define CYHAL_TRIGGER_TCPWM0_TR_OUT050 (CYHAL_TRIGGER_TCPWM0_TR_OUT050_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1650 #define CYHAL_TRIGGER_TCPWM0_TR_OUT051 (CYHAL_TRIGGER_TCPWM0_TR_OUT051_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1651 #define CYHAL_TRIGGER_TCPWM0_TR_OUT052 (CYHAL_TRIGGER_TCPWM0_TR_OUT052_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1652 #define CYHAL_TRIGGER_TCPWM0_TR_OUT053 (CYHAL_TRIGGER_TCPWM0_TR_OUT053_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1653 #define CYHAL_TRIGGER_TCPWM0_TR_OUT054 (CYHAL_TRIGGER_TCPWM0_TR_OUT054_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1654 #define CYHAL_TRIGGER_TCPWM0_TR_OUT055 (CYHAL_TRIGGER_TCPWM0_TR_OUT055_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1655 #define CYHAL_TRIGGER_TCPWM0_TR_OUT056 (CYHAL_TRIGGER_TCPWM0_TR_OUT056_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1656 #define CYHAL_TRIGGER_TCPWM0_TR_OUT057 (CYHAL_TRIGGER_TCPWM0_TR_OUT057_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1657 #define CYHAL_TRIGGER_TCPWM0_TR_OUT058 (CYHAL_TRIGGER_TCPWM0_TR_OUT058_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1658 #define CYHAL_TRIGGER_TCPWM0_TR_OUT059 (CYHAL_TRIGGER_TCPWM0_TR_OUT059_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1659 #define CYHAL_TRIGGER_TCPWM0_TR_OUT060 (CYHAL_TRIGGER_TCPWM0_TR_OUT060_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1660 #define CYHAL_TRIGGER_TCPWM0_TR_OUT061 (CYHAL_TRIGGER_TCPWM0_TR_OUT061_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1661 #define CYHAL_TRIGGER_TCPWM0_TR_OUT062 (CYHAL_TRIGGER_TCPWM0_TR_OUT062_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1662 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0256 (CYHAL_TRIGGER_TCPWM0_TR_OUT0256_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1663 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0257 (CYHAL_TRIGGER_TCPWM0_TR_OUT0257_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1664 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0258 (CYHAL_TRIGGER_TCPWM0_TR_OUT0258_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1665 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0259 (CYHAL_TRIGGER_TCPWM0_TR_OUT0259_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1666 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0260 (CYHAL_TRIGGER_TCPWM0_TR_OUT0260_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1667 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0261 (CYHAL_TRIGGER_TCPWM0_TR_OUT0261_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1668 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0262 (CYHAL_TRIGGER_TCPWM0_TR_OUT0262_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1669 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0263 (CYHAL_TRIGGER_TCPWM0_TR_OUT0263_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1670 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0264 (CYHAL_TRIGGER_TCPWM0_TR_OUT0264_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1671 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0265 (CYHAL_TRIGGER_TCPWM0_TR_OUT0265_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1672 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0266 (CYHAL_TRIGGER_TCPWM0_TR_OUT0266_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1673 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0267 (CYHAL_TRIGGER_TCPWM0_TR_OUT0267_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1674 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0512 (CYHAL_TRIGGER_TCPWM0_TR_OUT0512_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1675 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0513 (CYHAL_TRIGGER_TCPWM0_TR_OUT0513_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1676 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0514 (CYHAL_TRIGGER_TCPWM0_TR_OUT0514_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1677 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0515 (CYHAL_TRIGGER_TCPWM0_TR_OUT0515_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1678 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0516 (CYHAL_TRIGGER_TCPWM0_TR_OUT0516_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1679 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0517 (CYHAL_TRIGGER_TCPWM0_TR_OUT0517_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1680 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0518 (CYHAL_TRIGGER_TCPWM0_TR_OUT0518_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1681 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0519 (CYHAL_TRIGGER_TCPWM0_TR_OUT0519_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1682 #define CYHAL_TRIGGER_TCPWM0_TR_OUT10 (CYHAL_TRIGGER_TCPWM0_TR_OUT10_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1683 #define CYHAL_TRIGGER_TCPWM0_TR_OUT11 (CYHAL_TRIGGER_TCPWM0_TR_OUT11_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1684 #define CYHAL_TRIGGER_TCPWM0_TR_OUT12 (CYHAL_TRIGGER_TCPWM0_TR_OUT12_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1685 #define CYHAL_TRIGGER_TCPWM0_TR_OUT13 (CYHAL_TRIGGER_TCPWM0_TR_OUT13_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1686 #define CYHAL_TRIGGER_TCPWM0_TR_OUT14 (CYHAL_TRIGGER_TCPWM0_TR_OUT14_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1687 #define CYHAL_TRIGGER_TCPWM0_TR_OUT15 (CYHAL_TRIGGER_TCPWM0_TR_OUT15_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1688 #define CYHAL_TRIGGER_TCPWM0_TR_OUT16 (CYHAL_TRIGGER_TCPWM0_TR_OUT16_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1689 #define CYHAL_TRIGGER_TCPWM0_TR_OUT17 (CYHAL_TRIGGER_TCPWM0_TR_OUT17_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1690 #define CYHAL_TRIGGER_TCPWM0_TR_OUT18 (CYHAL_TRIGGER_TCPWM0_TR_OUT18_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1691 #define CYHAL_TRIGGER_TCPWM0_TR_OUT19 (CYHAL_TRIGGER_TCPWM0_TR_OUT19_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1692 #define CYHAL_TRIGGER_TCPWM0_TR_OUT110 (CYHAL_TRIGGER_TCPWM0_TR_OUT110_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1693 #define CYHAL_TRIGGER_TCPWM0_TR_OUT111 (CYHAL_TRIGGER_TCPWM0_TR_OUT111_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1694 #define CYHAL_TRIGGER_TCPWM0_TR_OUT112 (CYHAL_TRIGGER_TCPWM0_TR_OUT112_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1695 #define CYHAL_TRIGGER_TCPWM0_TR_OUT113 (CYHAL_TRIGGER_TCPWM0_TR_OUT113_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1696 #define CYHAL_TRIGGER_TCPWM0_TR_OUT114 (CYHAL_TRIGGER_TCPWM0_TR_OUT114_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1697 #define CYHAL_TRIGGER_TCPWM0_TR_OUT115 (CYHAL_TRIGGER_TCPWM0_TR_OUT115_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1698 #define CYHAL_TRIGGER_TCPWM0_TR_OUT116 (CYHAL_TRIGGER_TCPWM0_TR_OUT116_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1699 #define CYHAL_TRIGGER_TCPWM0_TR_OUT117 (CYHAL_TRIGGER_TCPWM0_TR_OUT117_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1700 #define CYHAL_TRIGGER_TCPWM0_TR_OUT118 (CYHAL_TRIGGER_TCPWM0_TR_OUT118_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1701 #define CYHAL_TRIGGER_TCPWM0_TR_OUT119 (CYHAL_TRIGGER_TCPWM0_TR_OUT119_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1702 #define CYHAL_TRIGGER_TCPWM0_TR_OUT120 (CYHAL_TRIGGER_TCPWM0_TR_OUT120_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1703 #define CYHAL_TRIGGER_TCPWM0_TR_OUT121 (CYHAL_TRIGGER_TCPWM0_TR_OUT121_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1704 #define CYHAL_TRIGGER_TCPWM0_TR_OUT122 (CYHAL_TRIGGER_TCPWM0_TR_OUT122_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1705 #define CYHAL_TRIGGER_TCPWM0_TR_OUT123 (CYHAL_TRIGGER_TCPWM0_TR_OUT123_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1706 #define CYHAL_TRIGGER_TCPWM0_TR_OUT124 (CYHAL_TRIGGER_TCPWM0_TR_OUT124_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1707 #define CYHAL_TRIGGER_TCPWM0_TR_OUT125 (CYHAL_TRIGGER_TCPWM0_TR_OUT125_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1708 #define CYHAL_TRIGGER_TCPWM0_TR_OUT126 (CYHAL_TRIGGER_TCPWM0_TR_OUT126_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1709 #define CYHAL_TRIGGER_TCPWM0_TR_OUT127 (CYHAL_TRIGGER_TCPWM0_TR_OUT127_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1710 #define CYHAL_TRIGGER_TCPWM0_TR_OUT128 (CYHAL_TRIGGER_TCPWM0_TR_OUT128_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1711 #define CYHAL_TRIGGER_TCPWM0_TR_OUT129 (CYHAL_TRIGGER_TCPWM0_TR_OUT129_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1712 #define CYHAL_TRIGGER_TCPWM0_TR_OUT130 (CYHAL_TRIGGER_TCPWM0_TR_OUT130_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1713 #define CYHAL_TRIGGER_TCPWM0_TR_OUT131 (CYHAL_TRIGGER_TCPWM0_TR_OUT131_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1714 #define CYHAL_TRIGGER_TCPWM0_TR_OUT132 (CYHAL_TRIGGER_TCPWM0_TR_OUT132_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1715 #define CYHAL_TRIGGER_TCPWM0_TR_OUT133 (CYHAL_TRIGGER_TCPWM0_TR_OUT133_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1716 #define CYHAL_TRIGGER_TCPWM0_TR_OUT134 (CYHAL_TRIGGER_TCPWM0_TR_OUT134_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1717 #define CYHAL_TRIGGER_TCPWM0_TR_OUT135 (CYHAL_TRIGGER_TCPWM0_TR_OUT135_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1718 #define CYHAL_TRIGGER_TCPWM0_TR_OUT136 (CYHAL_TRIGGER_TCPWM0_TR_OUT136_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1719 #define CYHAL_TRIGGER_TCPWM0_TR_OUT137 (CYHAL_TRIGGER_TCPWM0_TR_OUT137_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1720 #define CYHAL_TRIGGER_TCPWM0_TR_OUT138 (CYHAL_TRIGGER_TCPWM0_TR_OUT138_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1721 #define CYHAL_TRIGGER_TCPWM0_TR_OUT139 (CYHAL_TRIGGER_TCPWM0_TR_OUT139_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1722 #define CYHAL_TRIGGER_TCPWM0_TR_OUT140 (CYHAL_TRIGGER_TCPWM0_TR_OUT140_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1723 #define CYHAL_TRIGGER_TCPWM0_TR_OUT141 (CYHAL_TRIGGER_TCPWM0_TR_OUT141_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1724 #define CYHAL_TRIGGER_TCPWM0_TR_OUT142 (CYHAL_TRIGGER_TCPWM0_TR_OUT142_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1725 #define CYHAL_TRIGGER_TCPWM0_TR_OUT143 (CYHAL_TRIGGER_TCPWM0_TR_OUT143_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1726 #define CYHAL_TRIGGER_TCPWM0_TR_OUT144 (CYHAL_TRIGGER_TCPWM0_TR_OUT144_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1727 #define CYHAL_TRIGGER_TCPWM0_TR_OUT145 (CYHAL_TRIGGER_TCPWM0_TR_OUT145_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1728 #define CYHAL_TRIGGER_TCPWM0_TR_OUT146 (CYHAL_TRIGGER_TCPWM0_TR_OUT146_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1729 #define CYHAL_TRIGGER_TCPWM0_TR_OUT147 (CYHAL_TRIGGER_TCPWM0_TR_OUT147_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1730 #define CYHAL_TRIGGER_TCPWM0_TR_OUT148 (CYHAL_TRIGGER_TCPWM0_TR_OUT148_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1731 #define CYHAL_TRIGGER_TCPWM0_TR_OUT149 (CYHAL_TRIGGER_TCPWM0_TR_OUT149_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1732 #define CYHAL_TRIGGER_TCPWM0_TR_OUT150 (CYHAL_TRIGGER_TCPWM0_TR_OUT150_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1733 #define CYHAL_TRIGGER_TCPWM0_TR_OUT151 (CYHAL_TRIGGER_TCPWM0_TR_OUT151_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1734 #define CYHAL_TRIGGER_TCPWM0_TR_OUT152 (CYHAL_TRIGGER_TCPWM0_TR_OUT152_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1735 #define CYHAL_TRIGGER_TCPWM0_TR_OUT153 (CYHAL_TRIGGER_TCPWM0_TR_OUT153_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1736 #define CYHAL_TRIGGER_TCPWM0_TR_OUT154 (CYHAL_TRIGGER_TCPWM0_TR_OUT154_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1737 #define CYHAL_TRIGGER_TCPWM0_TR_OUT155 (CYHAL_TRIGGER_TCPWM0_TR_OUT155_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1738 #define CYHAL_TRIGGER_TCPWM0_TR_OUT156 (CYHAL_TRIGGER_TCPWM0_TR_OUT156_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1739 #define CYHAL_TRIGGER_TCPWM0_TR_OUT157 (CYHAL_TRIGGER_TCPWM0_TR_OUT157_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1740 #define CYHAL_TRIGGER_TCPWM0_TR_OUT158 (CYHAL_TRIGGER_TCPWM0_TR_OUT158_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1741 #define CYHAL_TRIGGER_TCPWM0_TR_OUT159 (CYHAL_TRIGGER_TCPWM0_TR_OUT159_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1742 #define CYHAL_TRIGGER_TCPWM0_TR_OUT160 (CYHAL_TRIGGER_TCPWM0_TR_OUT160_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1743 #define CYHAL_TRIGGER_TCPWM0_TR_OUT161 (CYHAL_TRIGGER_TCPWM0_TR_OUT161_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1744 #define CYHAL_TRIGGER_TCPWM0_TR_OUT162 (CYHAL_TRIGGER_TCPWM0_TR_OUT162_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1745 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1256 (CYHAL_TRIGGER_TCPWM0_TR_OUT1256_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1746 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1257 (CYHAL_TRIGGER_TCPWM0_TR_OUT1257_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1747 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1258 (CYHAL_TRIGGER_TCPWM0_TR_OUT1258_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1748 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1259 (CYHAL_TRIGGER_TCPWM0_TR_OUT1259_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1749 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1260 (CYHAL_TRIGGER_TCPWM0_TR_OUT1260_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1750 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1261 (CYHAL_TRIGGER_TCPWM0_TR_OUT1261_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1751 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1262 (CYHAL_TRIGGER_TCPWM0_TR_OUT1262_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1752 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1263 (CYHAL_TRIGGER_TCPWM0_TR_OUT1263_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1753 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1264 (CYHAL_TRIGGER_TCPWM0_TR_OUT1264_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1754 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1265 (CYHAL_TRIGGER_TCPWM0_TR_OUT1265_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1755 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1266 (CYHAL_TRIGGER_TCPWM0_TR_OUT1266_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1756 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1267 (CYHAL_TRIGGER_TCPWM0_TR_OUT1267_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1757 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1512 (CYHAL_TRIGGER_TCPWM0_TR_OUT1512_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1758 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1513 (CYHAL_TRIGGER_TCPWM0_TR_OUT1513_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1759 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1514 (CYHAL_TRIGGER_TCPWM0_TR_OUT1514_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1760 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1515 (CYHAL_TRIGGER_TCPWM0_TR_OUT1515_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1761 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1516 (CYHAL_TRIGGER_TCPWM0_TR_OUT1516_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1762 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1517 (CYHAL_TRIGGER_TCPWM0_TR_OUT1517_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1763 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1518 (CYHAL_TRIGGER_TCPWM0_TR_OUT1518_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1764 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1519 (CYHAL_TRIGGER_TCPWM0_TR_OUT1519_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1765 #define CYHAL_TRIGGER_TR_GROUP9_OUTPUT0 (CYHAL_TRIGGER_TR_GROUP9_OUTPUT0_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1766 #define CYHAL_TRIGGER_TR_GROUP9_OUTPUT1 (CYHAL_TRIGGER_TR_GROUP9_OUTPUT1_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1767 #define CYHAL_TRIGGER_TR_GROUP9_OUTPUT2 (CYHAL_TRIGGER_TR_GROUP9_OUTPUT2_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1768 #define CYHAL_TRIGGER_TR_GROUP9_OUTPUT3 (CYHAL_TRIGGER_TR_GROUP9_OUTPUT3_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1769 #define CYHAL_TRIGGER_TR_GROUP9_OUTPUT4 (CYHAL_TRIGGER_TR_GROUP9_OUTPUT4_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1770 #define CYHAL_TRIGGER_TR_GROUP10_OUTPUT0 (CYHAL_TRIGGER_TR_GROUP10_OUTPUT0_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1771 #define CYHAL_TRIGGER_TR_GROUP10_OUTPUT1 (CYHAL_TRIGGER_TR_GROUP10_OUTPUT1_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1772 #define CYHAL_TRIGGER_TR_GROUP10_OUTPUT2 (CYHAL_TRIGGER_TR_GROUP10_OUTPUT2_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1773 #define CYHAL_TRIGGER_TR_GROUP10_OUTPUT3 (CYHAL_TRIGGER_TR_GROUP10_OUTPUT3_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1774 #define CYHAL_TRIGGER_TR_GROUP10_OUTPUT4 (CYHAL_TRIGGER_TR_GROUP10_OUTPUT4_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1775 1776 /** @brief Name of each output trigger. */ 1777 typedef enum 1778 { 1779 CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_ACK0 = 0, //!< CAN DW0 triggers (from DW back to CAN) - canfd[0].tr_dbg_dma_ack[0] 1780 CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_ACK1 = 1, //!< CAN DW0 triggers (from DW back to CAN) - canfd[0].tr_dbg_dma_ack[1] 1781 CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_ACK2 = 2, //!< CAN DW0 triggers (from DW back to CAN) - canfd[0].tr_dbg_dma_ack[2] 1782 CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_ACK3 = 3, //!< CAN DW0 triggers (from DW back to CAN) - canfd[0].tr_dbg_dma_ack[3] 1783 CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_ACK0 = 4, //!< CAN DW1 triggers (from DW back to CAN) - canfd[1].tr_dbg_dma_ack[0] 1784 CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_ACK1 = 5, //!< CAN DW1 triggers (from DW back to CAN) - canfd[1].tr_dbg_dma_ack[1] 1785 CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_ACK2 = 6, //!< CAN DW1 triggers (from DW back to CAN) - canfd[1].tr_dbg_dma_ack[2] 1786 CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_ACK3 = 7, //!< CAN DW1 triggers (from DW back to CAN) - canfd[1].tr_dbg_dma_ack[3] 1787 CYHAL_TRIGGER_CANFD0_TR_EVT_SWT_IN0 = 8, //!< CAN TT Sync - canfd[0].tr_evt_swt_in[0] 1788 CYHAL_TRIGGER_CANFD0_TR_EVT_SWT_IN1 = 9, //!< CAN TT Sync - canfd[0].tr_evt_swt_in[1] 1789 CYHAL_TRIGGER_CANFD0_TR_EVT_SWT_IN2 = 10, //!< CAN TT Sync - canfd[0].tr_evt_swt_in[2] 1790 CYHAL_TRIGGER_CANFD0_TR_EVT_SWT_IN3 = 11, //!< CAN TT Sync - canfd[0].tr_evt_swt_in[3] 1791 CYHAL_TRIGGER_CANFD1_TR_EVT_SWT_IN0 = 12, //!< CAN TT Sync - canfd[1].tr_evt_swt_in[0] 1792 CYHAL_TRIGGER_CANFD1_TR_EVT_SWT_IN1 = 13, //!< CAN TT Sync - canfd[1].tr_evt_swt_in[1] 1793 CYHAL_TRIGGER_CANFD1_TR_EVT_SWT_IN2 = 14, //!< CAN TT Sync - canfd[1].tr_evt_swt_in[2] 1794 CYHAL_TRIGGER_CANFD1_TR_EVT_SWT_IN3 = 15, //!< CAN TT Sync - canfd[1].tr_evt_swt_in[3] 1795 CYHAL_TRIGGER_CPUSS_CTI_TR_IN0 = 16, //!< Debug Multiplexer - cpuss.cti_tr_in[0] 1796 CYHAL_TRIGGER_CPUSS_CTI_TR_IN1 = 17, //!< Debug Multiplexer - cpuss.cti_tr_in[1] 1797 CYHAL_TRIGGER_CPUSS_DMAC_TR_IN0 = 18, //!< M-DMA trigger multiplexer - cpuss.dmac_tr_in[0] 1798 CYHAL_TRIGGER_CPUSS_DMAC_TR_IN1 = 19, //!< M-DMA trigger multiplexer - cpuss.dmac_tr_in[1] 1799 CYHAL_TRIGGER_CPUSS_DMAC_TR_IN2 = 20, //!< M-DMA trigger multiplexer - cpuss.dmac_tr_in[2] 1800 CYHAL_TRIGGER_CPUSS_DMAC_TR_IN3 = 21, //!< M-DMA trigger multiplexer - cpuss.dmac_tr_in[3] 1801 CYHAL_TRIGGER_CPUSS_DW0_TR_IN0 = 22, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[0] 1802 CYHAL_TRIGGER_CPUSS_DW0_TR_IN1 = 23, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[1] 1803 CYHAL_TRIGGER_CPUSS_DW0_TR_IN2 = 24, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[2] 1804 CYHAL_TRIGGER_CPUSS_DW0_TR_IN3 = 25, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[3] 1805 CYHAL_TRIGGER_CPUSS_DW0_TR_IN4 = 26, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[4] 1806 CYHAL_TRIGGER_CPUSS_DW0_TR_IN5 = 27, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[5] 1807 CYHAL_TRIGGER_CPUSS_DW0_TR_IN6 = 28, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[6] 1808 CYHAL_TRIGGER_CPUSS_DW0_TR_IN7 = 29, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[7] 1809 CYHAL_TRIGGER_CPUSS_DW0_TR_IN8 = 30, //!< TCPWM to P-DMA0 trigger mux - cpuss.dw0_tr_in[8] 1810 CYHAL_TRIGGER_CPUSS_DW0_TR_IN9 = 31, //!< TCPWM to P-DMA0 trigger mux - cpuss.dw0_tr_in[9] 1811 CYHAL_TRIGGER_CPUSS_DW0_TR_IN10 = 32, //!< TCPWM to P-DMA0 trigger mux - cpuss.dw0_tr_in[10] 1812 CYHAL_TRIGGER_CPUSS_DW0_TR_IN11 = 33, //!< TCPWM to P-DMA0 trigger mux - cpuss.dw0_tr_in[11] 1813 CYHAL_TRIGGER_CPUSS_DW0_TR_IN12 = 34, //!< TCPWM to P-DMA0 trigger mux - cpuss.dw0_tr_in[12] 1814 CYHAL_TRIGGER_CPUSS_DW0_TR_IN13 = 35, //!< TCPWM to P-DMA0 trigger mux - cpuss.dw0_tr_in[13] 1815 CYHAL_TRIGGER_CPUSS_DW0_TR_IN14 = 36, //!< TCPWM to P-DMA0 trigger mux - cpuss.dw0_tr_in[14] 1816 CYHAL_TRIGGER_CPUSS_DW0_TR_IN15 = 37, //!< TCPWM to P-DMA0 trigger mux - cpuss.dw0_tr_in[15] 1817 CYHAL_TRIGGER_CPUSS_DW0_TR_IN16 = 38, //!< CAN DW0 Triggers - cpuss.dw0_tr_in[16] 1818 CYHAL_TRIGGER_CPUSS_DW0_TR_IN17 = 39, //!< CAN DW0 Triggers - cpuss.dw0_tr_in[17] 1819 CYHAL_TRIGGER_CPUSS_DW0_TR_IN18 = 40, //!< CAN DW0 Triggers - cpuss.dw0_tr_in[18] 1820 CYHAL_TRIGGER_CPUSS_DW0_TR_IN19 = 41, //!< CAN DW0 Triggers - cpuss.dw0_tr_in[19] 1821 CYHAL_TRIGGER_CPUSS_DW0_TR_IN20 = 42, //!< CAN DW0 Triggers - cpuss.dw0_tr_in[20] 1822 CYHAL_TRIGGER_CPUSS_DW0_TR_IN21 = 43, //!< CAN DW0 Triggers - cpuss.dw0_tr_in[21] 1823 CYHAL_TRIGGER_CPUSS_DW0_TR_IN22 = 44, //!< CAN DW0 Triggers - cpuss.dw0_tr_in[22] 1824 CYHAL_TRIGGER_CPUSS_DW0_TR_IN23 = 45, //!< CAN DW0 Triggers - cpuss.dw0_tr_in[23] 1825 CYHAL_TRIGGER_CPUSS_DW0_TR_IN24 = 46, //!< CAN DW0 Triggers - cpuss.dw0_tr_in[24] 1826 CYHAL_TRIGGER_CPUSS_DW0_TR_IN25 = 47, //!< CAN DW0 Triggers - cpuss.dw0_tr_in[25] 1827 CYHAL_TRIGGER_CPUSS_DW0_TR_IN26 = 48, //!< CAN DW0 Triggers - cpuss.dw0_tr_in[26] 1828 CYHAL_TRIGGER_CPUSS_DW0_TR_IN27 = 49, //!< CAN DW0 Triggers - cpuss.dw0_tr_in[27] 1829 CYHAL_TRIGGER_CPUSS_DW0_TR_IN28 = 50, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[28] 1830 CYHAL_TRIGGER_CPUSS_DW0_TR_IN29 = 51, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[29] 1831 CYHAL_TRIGGER_CPUSS_DW0_TR_IN30 = 52, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[30] 1832 CYHAL_TRIGGER_CPUSS_DW0_TR_IN31 = 53, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[31] 1833 CYHAL_TRIGGER_CPUSS_DW0_TR_IN32 = 54, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[32] 1834 CYHAL_TRIGGER_CPUSS_DW0_TR_IN33 = 55, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[33] 1835 CYHAL_TRIGGER_CPUSS_DW0_TR_IN34 = 56, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[34] 1836 CYHAL_TRIGGER_CPUSS_DW0_TR_IN35 = 57, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[35] 1837 CYHAL_TRIGGER_CPUSS_DW0_TR_IN36 = 58, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[36] 1838 CYHAL_TRIGGER_CPUSS_DW0_TR_IN37 = 59, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[37] 1839 CYHAL_TRIGGER_CPUSS_DW0_TR_IN38 = 60, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[38] 1840 CYHAL_TRIGGER_CPUSS_DW0_TR_IN39 = 61, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[39] 1841 CYHAL_TRIGGER_CPUSS_DW0_TR_IN40 = 62, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[40] 1842 CYHAL_TRIGGER_CPUSS_DW0_TR_IN41 = 63, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[41] 1843 CYHAL_TRIGGER_CPUSS_DW0_TR_IN42 = 64, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[42] 1844 CYHAL_TRIGGER_CPUSS_DW0_TR_IN43 = 65, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[43] 1845 CYHAL_TRIGGER_CPUSS_DW0_TR_IN44 = 66, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[44] 1846 CYHAL_TRIGGER_CPUSS_DW0_TR_IN45 = 67, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[45] 1847 CYHAL_TRIGGER_CPUSS_DW0_TR_IN46 = 68, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[46] 1848 CYHAL_TRIGGER_CPUSS_DW0_TR_IN47 = 69, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[47] 1849 CYHAL_TRIGGER_CPUSS_DW0_TR_IN48 = 70, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[48] 1850 CYHAL_TRIGGER_CPUSS_DW0_TR_IN49 = 71, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[49] 1851 CYHAL_TRIGGER_CPUSS_DW0_TR_IN50 = 72, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[50] 1852 CYHAL_TRIGGER_CPUSS_DW0_TR_IN51 = 73, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[51] 1853 CYHAL_TRIGGER_CPUSS_DW0_TR_IN52 = 74, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[52] 1854 CYHAL_TRIGGER_CPUSS_DW0_TR_IN53 = 75, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[53] 1855 CYHAL_TRIGGER_CPUSS_DW0_TR_IN54 = 76, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[54] 1856 CYHAL_TRIGGER_CPUSS_DW0_TR_IN55 = 77, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[55] 1857 CYHAL_TRIGGER_CPUSS_DW0_TR_IN56 = 78, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[56] 1858 CYHAL_TRIGGER_CPUSS_DW0_TR_IN57 = 79, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[57] 1859 CYHAL_TRIGGER_CPUSS_DW0_TR_IN58 = 80, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[58] 1860 CYHAL_TRIGGER_CPUSS_DW0_TR_IN59 = 81, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[59] 1861 CYHAL_TRIGGER_CPUSS_DW0_TR_IN60 = 82, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[60] 1862 CYHAL_TRIGGER_CPUSS_DW0_TR_IN61 = 83, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[61] 1863 CYHAL_TRIGGER_CPUSS_DW0_TR_IN62 = 84, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[62] 1864 CYHAL_TRIGGER_CPUSS_DW0_TR_IN63 = 85, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[63] 1865 CYHAL_TRIGGER_CPUSS_DW0_TR_IN64 = 86, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[64] 1866 CYHAL_TRIGGER_CPUSS_DW0_TR_IN65 = 87, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[65] 1867 CYHAL_TRIGGER_CPUSS_DW0_TR_IN66 = 88, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[66] 1868 CYHAL_TRIGGER_CPUSS_DW0_TR_IN67 = 89, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[67] 1869 CYHAL_TRIGGER_CPUSS_DW0_TR_IN68 = 90, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[68] 1870 CYHAL_TRIGGER_CPUSS_DW0_TR_IN69 = 91, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[69] 1871 CYHAL_TRIGGER_CPUSS_DW0_TR_IN70 = 92, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[70] 1872 CYHAL_TRIGGER_CPUSS_DW0_TR_IN71 = 93, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[71] 1873 CYHAL_TRIGGER_CPUSS_DW0_TR_IN72 = 94, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[72] 1874 CYHAL_TRIGGER_CPUSS_DW0_TR_IN73 = 95, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[73] 1875 CYHAL_TRIGGER_CPUSS_DW0_TR_IN74 = 96, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[74] 1876 CYHAL_TRIGGER_CPUSS_DW0_TR_IN75 = 97, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[75] 1877 CYHAL_TRIGGER_CPUSS_DW0_TR_IN76 = 98, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[76] 1878 CYHAL_TRIGGER_CPUSS_DW0_TR_IN77 = 99, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[77] 1879 CYHAL_TRIGGER_CPUSS_DW0_TR_IN78 = 100, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[78] 1880 CYHAL_TRIGGER_CPUSS_DW0_TR_IN79 = 101, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[79] 1881 CYHAL_TRIGGER_CPUSS_DW0_TR_IN80 = 102, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[80] 1882 CYHAL_TRIGGER_CPUSS_DW0_TR_IN81 = 103, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[81] 1883 CYHAL_TRIGGER_CPUSS_DW0_TR_IN82 = 104, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[82] 1884 CYHAL_TRIGGER_CPUSS_DW0_TR_IN83 = 105, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[83] 1885 CYHAL_TRIGGER_CPUSS_DW0_TR_IN84 = 106, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[84] 1886 CYHAL_TRIGGER_CPUSS_DW0_TR_IN85 = 107, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[85] 1887 CYHAL_TRIGGER_CPUSS_DW0_TR_IN86 = 108, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[86] 1888 CYHAL_TRIGGER_CPUSS_DW0_TR_IN87 = 109, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[87] 1889 CYHAL_TRIGGER_CPUSS_DW0_TR_IN88 = 110, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[88] 1890 CYHAL_TRIGGER_CPUSS_DW0_TR_IN89 = 111, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[89] 1891 CYHAL_TRIGGER_CPUSS_DW0_TR_IN90 = 112, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[90] 1892 CYHAL_TRIGGER_CPUSS_DW0_TR_IN91 = 113, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[91] 1893 CYHAL_TRIGGER_CPUSS_DW1_TR_IN0 = 114, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[0] 1894 CYHAL_TRIGGER_CPUSS_DW1_TR_IN1 = 115, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[1] 1895 CYHAL_TRIGGER_CPUSS_DW1_TR_IN2 = 116, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[2] 1896 CYHAL_TRIGGER_CPUSS_DW1_TR_IN3 = 117, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[3] 1897 CYHAL_TRIGGER_CPUSS_DW1_TR_IN4 = 118, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[4] 1898 CYHAL_TRIGGER_CPUSS_DW1_TR_IN5 = 119, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[5] 1899 CYHAL_TRIGGER_CPUSS_DW1_TR_IN6 = 120, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[6] 1900 CYHAL_TRIGGER_CPUSS_DW1_TR_IN7 = 121, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[7] 1901 CYHAL_TRIGGER_CPUSS_DW1_TR_IN8 = 122, //!< SCB DW Triggers - cpuss.dw1_tr_in[8] 1902 CYHAL_TRIGGER_CPUSS_DW1_TR_IN9 = 123, //!< SCB DW Triggers - cpuss.dw1_tr_in[9] 1903 CYHAL_TRIGGER_CPUSS_DW1_TR_IN10 = 124, //!< SCB DW Triggers - cpuss.dw1_tr_in[10] 1904 CYHAL_TRIGGER_CPUSS_DW1_TR_IN11 = 125, //!< SCB DW Triggers - cpuss.dw1_tr_in[11] 1905 CYHAL_TRIGGER_CPUSS_DW1_TR_IN12 = 126, //!< SCB DW Triggers - cpuss.dw1_tr_in[12] 1906 CYHAL_TRIGGER_CPUSS_DW1_TR_IN13 = 127, //!< SCB DW Triggers - cpuss.dw1_tr_in[13] 1907 CYHAL_TRIGGER_CPUSS_DW1_TR_IN14 = 128, //!< SCB DW Triggers - cpuss.dw1_tr_in[14] 1908 CYHAL_TRIGGER_CPUSS_DW1_TR_IN15 = 129, //!< SCB DW Triggers - cpuss.dw1_tr_in[15] 1909 CYHAL_TRIGGER_CPUSS_DW1_TR_IN16 = 130, //!< SCB DW Triggers - cpuss.dw1_tr_in[16] 1910 CYHAL_TRIGGER_CPUSS_DW1_TR_IN17 = 131, //!< SCB DW Triggers - cpuss.dw1_tr_in[17] 1911 CYHAL_TRIGGER_CPUSS_DW1_TR_IN18 = 132, //!< SCB DW Triggers - cpuss.dw1_tr_in[18] 1912 CYHAL_TRIGGER_CPUSS_DW1_TR_IN19 = 133, //!< SCB DW Triggers - cpuss.dw1_tr_in[19] 1913 CYHAL_TRIGGER_CPUSS_DW1_TR_IN20 = 134, //!< SCB DW Triggers - cpuss.dw1_tr_in[20] 1914 CYHAL_TRIGGER_CPUSS_DW1_TR_IN21 = 135, //!< SCB DW Triggers - cpuss.dw1_tr_in[21] 1915 CYHAL_TRIGGER_CPUSS_DW1_TR_IN22 = 136, //!< SCB DW Triggers - cpuss.dw1_tr_in[22] 1916 CYHAL_TRIGGER_CPUSS_DW1_TR_IN23 = 137, //!< SCB DW Triggers - cpuss.dw1_tr_in[23] 1917 CYHAL_TRIGGER_CPUSS_DW1_TR_IN24 = 138, //!< CAN DW1 triggers - cpuss.dw1_tr_in[24] 1918 CYHAL_TRIGGER_CPUSS_DW1_TR_IN25 = 139, //!< CAN DW1 triggers - cpuss.dw1_tr_in[25] 1919 CYHAL_TRIGGER_CPUSS_DW1_TR_IN26 = 140, //!< CAN DW1 triggers - cpuss.dw1_tr_in[26] 1920 CYHAL_TRIGGER_CPUSS_DW1_TR_IN27 = 141, //!< CAN DW1 triggers - cpuss.dw1_tr_in[27] 1921 CYHAL_TRIGGER_CPUSS_DW1_TR_IN28 = 142, //!< CAN DW1 triggers - cpuss.dw1_tr_in[28] 1922 CYHAL_TRIGGER_CPUSS_DW1_TR_IN29 = 143, //!< CAN DW1 triggers - cpuss.dw1_tr_in[29] 1923 CYHAL_TRIGGER_CPUSS_DW1_TR_IN30 = 144, //!< CAN DW1 triggers - cpuss.dw1_tr_in[30] 1924 CYHAL_TRIGGER_CPUSS_DW1_TR_IN31 = 145, //!< CAN DW1 triggers - cpuss.dw1_tr_in[31] 1925 CYHAL_TRIGGER_CPUSS_DW1_TR_IN32 = 146, //!< CAN DW1 triggers - cpuss.dw1_tr_in[32] 1926 CYHAL_TRIGGER_CPUSS_DW1_TR_IN33 = 147, //!< CAN DW1 triggers - cpuss.dw1_tr_in[33] 1927 CYHAL_TRIGGER_CPUSS_DW1_TR_IN34 = 148, //!< CAN DW1 triggers - cpuss.dw1_tr_in[34] 1928 CYHAL_TRIGGER_CPUSS_DW1_TR_IN35 = 149, //!< CAN DW1 triggers - cpuss.dw1_tr_in[35] 1929 CYHAL_TRIGGER_CPUSS_DW1_TR_IN36 = 150, //!< CXPI DW Triggers - cpuss.dw1_tr_in[36] 1930 CYHAL_TRIGGER_CPUSS_DW1_TR_IN37 = 151, //!< CXPI DW Triggers - cpuss.dw1_tr_in[37] 1931 CYHAL_TRIGGER_CPUSS_DW1_TR_IN38 = 152, //!< CXPI DW Triggers - cpuss.dw1_tr_in[38] 1932 CYHAL_TRIGGER_CPUSS_DW1_TR_IN39 = 153, //!< CXPI DW Triggers - cpuss.dw1_tr_in[39] 1933 CYHAL_TRIGGER_CPUSS_DW1_TR_IN40 = 154, //!< CXPI DW Triggers - cpuss.dw1_tr_in[40] 1934 CYHAL_TRIGGER_CPUSS_DW1_TR_IN41 = 155, //!< CXPI DW Triggers - cpuss.dw1_tr_in[41] 1935 CYHAL_TRIGGER_CPUSS_DW1_TR_IN42 = 156, //!< CXPI DW Triggers - cpuss.dw1_tr_in[42] 1936 CYHAL_TRIGGER_CPUSS_DW1_TR_IN43 = 157, //!< CXPI DW Triggers - cpuss.dw1_tr_in[43] 1937 CYHAL_TRIGGER_CXPI0_TR_CMD_TX_HEADER0 = 158, //!< EVTGEN CXPI triggers - cxpi[0].tr_cmd_tx_header[0] 1938 CYHAL_TRIGGER_CXPI0_TR_CMD_TX_HEADER1 = 159, //!< EVTGEN CXPI triggers - cxpi[0].tr_cmd_tx_header[1] 1939 CYHAL_TRIGGER_CXPI0_TR_CMD_TX_HEADER2 = 160, //!< EVTGEN CXPI triggers - cxpi[0].tr_cmd_tx_header[2] 1940 CYHAL_TRIGGER_CXPI0_TR_CMD_TX_HEADER3 = 161, //!< EVTGEN CXPI triggers - cxpi[0].tr_cmd_tx_header[3] 1941 CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER0 = 162, //!< TCPWM to LIN - lin[0].tr_cmd_tx_header[0] 1942 CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER1 = 163, //!< TCPWM to LIN - lin[0].tr_cmd_tx_header[1] 1943 CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER2 = 164, //!< TCPWM to LIN - lin[0].tr_cmd_tx_header[2] 1944 CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER3 = 165, //!< TCPWM to LIN - lin[0].tr_cmd_tx_header[3] 1945 CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER4 = 166, //!< TCPWM to LIN - lin[0].tr_cmd_tx_header[4] 1946 CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER5 = 167, //!< TCPWM to LIN - lin[0].tr_cmd_tx_header[5] 1947 CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER6 = 168, //!< TCPWM to LIN - lin[0].tr_cmd_tx_header[6] 1948 CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER7 = 169, //!< TCPWM to LIN - lin[0].tr_cmd_tx_header[7] 1949 CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER8 = 170, //!< TCPWM to LIN - lin[0].tr_cmd_tx_header[8] 1950 CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER9 = 171, //!< TCPWM to LIN - lin[0].tr_cmd_tx_header[9] 1951 CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER10 = 172, //!< TCPWM to LIN - lin[0].tr_cmd_tx_header[10] 1952 CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER11 = 173, //!< TCPWM to LIN - lin[0].tr_cmd_tx_header[11] 1953 CYHAL_TRIGGER_PASS0_TR_DEBUG_FREEZE = 174, //!< Debug Multiplexer - pass[0].tr_debug_freeze 1954 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN0 = 175, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[0] 1955 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN1 = 176, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[1] 1956 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN2 = 177, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[2] 1957 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN3 = 178, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[3] 1958 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN4 = 179, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[4] 1959 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN5 = 180, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[5] 1960 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN6 = 181, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[6] 1961 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN7 = 182, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[7] 1962 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN8 = 183, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[8] 1963 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN9 = 184, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[9] 1964 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN10 = 185, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[10] 1965 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN11 = 186, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[11] 1966 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN12 = 187, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[12] 1967 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN13 = 188, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[13] 1968 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN14 = 189, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[14] 1969 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN15 = 190, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[15] 1970 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN16 = 191, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[16] 1971 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN17 = 192, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[17] 1972 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN18 = 193, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[18] 1973 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN19 = 194, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[19] 1974 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN20 = 195, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[20] 1975 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN21 = 196, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[21] 1976 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN22 = 197, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[22] 1977 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN23 = 198, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[23] 1978 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN32 = 199, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[32] 1979 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN33 = 200, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[33] 1980 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN34 = 201, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[34] 1981 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN35 = 202, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[35] 1982 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN36 = 203, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[36] 1983 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN37 = 204, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[37] 1984 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN38 = 205, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[38] 1985 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN39 = 206, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[39] 1986 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN40 = 207, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[40] 1987 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN41 = 208, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[41] 1988 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN42 = 209, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[42] 1989 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN43 = 210, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[43] 1990 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN44 = 211, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[44] 1991 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN45 = 212, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[45] 1992 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN46 = 213, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[46] 1993 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN47 = 214, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[47] 1994 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN48 = 215, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[48] 1995 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN49 = 216, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[49] 1996 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN50 = 217, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[50] 1997 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN51 = 218, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[51] 1998 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN52 = 219, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[52] 1999 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN53 = 220, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[53] 2000 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN54 = 221, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[54] 2001 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN55 = 222, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[55] 2002 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN56 = 223, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[56] 2003 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN57 = 224, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[57] 2004 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN58 = 225, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[58] 2005 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN59 = 226, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[59] 2006 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN60 = 227, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[60] 2007 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN61 = 228, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[61] 2008 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN62 = 229, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[62] 2009 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN63 = 230, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[63] 2010 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN64 = 231, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[64] 2011 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN65 = 232, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[65] 2012 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN66 = 233, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[66] 2013 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN67 = 234, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[67] 2014 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN68 = 235, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[68] 2015 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN69 = 236, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[69] 2016 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN70 = 237, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[70] 2017 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN71 = 238, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[71] 2018 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN0 = 239, //!< PASS trigger multiplexer - pass[0].tr_sar_gen_in[0] 2019 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN1 = 240, //!< PASS trigger multiplexer - pass[0].tr_sar_gen_in[1] 2020 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN2 = 241, //!< PASS trigger multiplexer - pass[0].tr_sar_gen_in[2] 2021 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN3 = 242, //!< PASS trigger multiplexer - pass[0].tr_sar_gen_in[3] 2022 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN4 = 243, //!< PASS trigger multiplexer - pass[0].tr_sar_gen_in[4] 2023 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN5 = 244, //!< PASS trigger multiplexer - pass[0].tr_sar_gen_in[5] 2024 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN6 = 245, //!< PASS trigger multiplexer - pass[0].tr_sar_gen_in[6] 2025 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN7 = 246, //!< PASS trigger multiplexer - pass[0].tr_sar_gen_in[7] 2026 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN8 = 247, //!< PASS trigger multiplexer - pass[0].tr_sar_gen_in[8] 2027 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN9 = 248, //!< PASS trigger multiplexer - pass[0].tr_sar_gen_in[9] 2028 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN10 = 249, //!< PASS trigger multiplexer - pass[0].tr_sar_gen_in[10] 2029 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN11 = 250, //!< PASS trigger multiplexer - pass[0].tr_sar_gen_in[11] 2030 CYHAL_TRIGGER_PERI_TR_DBG_FREEZE = 251, //!< Debug Multiplexer - peri.tr_dbg_freeze 2031 CYHAL_TRIGGER_PERI_TR_IO_OUTPUT0 = 252, //!< Debug Multiplexer - peri.tr_io_output[0] 2032 CYHAL_TRIGGER_PERI_TR_IO_OUTPUT1 = 253, //!< Debug Multiplexer - peri.tr_io_output[1] 2033 CYHAL_TRIGGER_SRSS_TR_DEBUG_FREEZE_MCWDT0 = 254, //!< Debug Multiplexer - srss.tr_debug_freeze_mcwdt[0] 2034 CYHAL_TRIGGER_SRSS_TR_DEBUG_FREEZE_MCWDT1 = 255, //!< Debug Multiplexer - srss.tr_debug_freeze_mcwdt[1] 2035 CYHAL_TRIGGER_SRSS_TR_DEBUG_FREEZE_WDT = 256, //!< Debug Multiplexer - srss.tr_debug_freeze_wdt 2036 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN0 = 257, //!< TCPWM loopback mux - tcpwm[0].tr_all_cnt_in[0] 2037 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN1 = 258, //!< TCPWM loopback mux - tcpwm[0].tr_all_cnt_in[1] 2038 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN2 = 259, //!< TCPWM loopback mux - tcpwm[0].tr_all_cnt_in[2] 2039 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN3 = 260, //!< TCPWM loopback mux - tcpwm[0].tr_all_cnt_in[3] 2040 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN4 = 261, //!< TCPWM loopback mux - tcpwm[0].tr_all_cnt_in[4] 2041 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN5 = 262, //!< TCPWM loopback mux - tcpwm[0].tr_all_cnt_in[5] 2042 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN6 = 263, //!< TCPWM loopback mux - tcpwm[0].tr_all_cnt_in[6] 2043 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN7 = 264, //!< TCPWM loopback mux - tcpwm[0].tr_all_cnt_in[7] 2044 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN8 = 265, //!< TCPWM loopback mux - tcpwm[0].tr_all_cnt_in[8] 2045 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN9 = 266, //!< TCPWM loopback mux - tcpwm[0].tr_all_cnt_in[9] 2046 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN10 = 267, //!< TCPWM loopback mux - tcpwm[0].tr_all_cnt_in[10] 2047 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN11 = 268, //!< TCPWM loopback mux - tcpwm[0].tr_all_cnt_in[11] 2048 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN12 = 269, //!< TCPWM loopback mux - tcpwm[0].tr_all_cnt_in[12] 2049 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN13 = 270, //!< TCPWM loopback mux - tcpwm[0].tr_all_cnt_in[13] 2050 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN14 = 271, //!< TCPWM loopback mux - tcpwm[0].tr_all_cnt_in[14] 2051 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN15 = 272, //!< TCPWM loopback mux - tcpwm[0].tr_all_cnt_in[15] 2052 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN16 = 273, //!< TCPWM Trigger Multiplexer - tcpwm[0].tr_all_cnt_in[16] 2053 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN17 = 274, //!< TCPWM Trigger Multiplexer - tcpwm[0].tr_all_cnt_in[17] 2054 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN18 = 275, //!< TCPWM Trigger Multiplexer - tcpwm[0].tr_all_cnt_in[18] 2055 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN19 = 276, //!< TCPWM Trigger Multiplexer - tcpwm[0].tr_all_cnt_in[19] 2056 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN20 = 277, //!< TCPWM Trigger Multiplexer - tcpwm[0].tr_all_cnt_in[20] 2057 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN21 = 278, //!< TCPWM Trigger Multiplexer - tcpwm[0].tr_all_cnt_in[21] 2058 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN22 = 279, //!< TCPWM Trigger Multiplexer - tcpwm[0].tr_all_cnt_in[22] 2059 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN23 = 280, //!< TCPWM Trigger Multiplexer - tcpwm[0].tr_all_cnt_in[23] 2060 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN24 = 281, //!< TCPWM Trigger Multiplexer - tcpwm[0].tr_all_cnt_in[24] 2061 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN25 = 282, //!< TCPWM Trigger Multiplexer - tcpwm[0].tr_all_cnt_in[25] 2062 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN26 = 283, //!< TCPWM Trigger Multiplexer - tcpwm[0].tr_all_cnt_in[26] 2063 CYHAL_TRIGGER_TCPWM0_TR_DEBUG_FREEZE = 284, //!< Debug Multiplexer - tcpwm[0].tr_debug_freeze 2064 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN2 = 285, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[2] 2065 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN5 = 286, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[5] 2066 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN8 = 287, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[8] 2067 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN11 = 288, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[11] 2068 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN14 = 289, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[14] 2069 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN17 = 290, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[17] 2070 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN20 = 291, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[20] 2071 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN23 = 292, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[23] 2072 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN26 = 293, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[26] 2073 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN29 = 294, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[29] 2074 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN32 = 295, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[32] 2075 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN35 = 296, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[35] 2076 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN38 = 297, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[38] 2077 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN41 = 298, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[41] 2078 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN44 = 299, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[44] 2079 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN47 = 300, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[47] 2080 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN50 = 301, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[50] 2081 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN53 = 302, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[53] 2082 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN56 = 303, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[56] 2083 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN59 = 304, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[59] 2084 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN62 = 305, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[62] 2085 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN65 = 306, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[65] 2086 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN68 = 307, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[68] 2087 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN71 = 308, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[71] 2088 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN74 = 309, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[74] 2089 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN77 = 310, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[77] 2090 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN80 = 311, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[80] 2091 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN83 = 312, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[83] 2092 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN86 = 313, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[86] 2093 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN89 = 314, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[89] 2094 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN92 = 315, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[92] 2095 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN95 = 316, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[95] 2096 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN98 = 317, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[98] 2097 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN101 = 318, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[101] 2098 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN104 = 319, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[104] 2099 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN107 = 320, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[107] 2100 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN110 = 321, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[110] 2101 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN113 = 322, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[113] 2102 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN116 = 323, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[116] 2103 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN119 = 324, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[119] 2104 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN122 = 325, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[122] 2105 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN125 = 326, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[125] 2106 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN128 = 327, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[128] 2107 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN131 = 328, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[131] 2108 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN134 = 329, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[134] 2109 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN137 = 330, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[137] 2110 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN140 = 331, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[140] 2111 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN143 = 332, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[143] 2112 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN146 = 333, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[146] 2113 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN149 = 334, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[149] 2114 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN152 = 335, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[152] 2115 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN155 = 336, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[155] 2116 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN770 = 337, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[770] 2117 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN773 = 338, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[773] 2118 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN776 = 339, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[776] 2119 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN779 = 340, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[779] 2120 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN782 = 341, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[782] 2121 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN785 = 342, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[785] 2122 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN788 = 343, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[788] 2123 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN791 = 344, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[791] 2124 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN794 = 345, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[794] 2125 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN797 = 346, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[797] 2126 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN800 = 347, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[800] 2127 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN803 = 348, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[803] 2128 CYHAL_TRIGGER_TR_GROUP8_INPUT1 = 349, //!< Debug Reduction #1 - tr_group[8].input[1] 2129 CYHAL_TRIGGER_TR_GROUP8_INPUT2 = 350, //!< Debug Reduction #1 - tr_group[8].input[2] 2130 CYHAL_TRIGGER_TR_GROUP8_INPUT3 = 351, //!< Debug Reduction #1 - tr_group[8].input[3] 2131 CYHAL_TRIGGER_TR_GROUP8_INPUT4 = 352, //!< Debug Reduction #1 - tr_group[8].input[4] 2132 CYHAL_TRIGGER_TR_GROUP8_INPUT5 = 353, //!< Debug Reduction #1 - tr_group[8].input[5] 2133 CYHAL_TRIGGER_TR_GROUP8_INPUT6 = 354, //!< Debug Reduction #2 - tr_group[8].input[6] 2134 CYHAL_TRIGGER_TR_GROUP8_INPUT7 = 355, //!< Debug Reduction #2 - tr_group[8].input[7] 2135 CYHAL_TRIGGER_TR_GROUP8_INPUT8 = 356, //!< Debug Reduction #2 - tr_group[8].input[8] 2136 CYHAL_TRIGGER_TR_GROUP8_INPUT9 = 357, //!< Debug Reduction #2 - tr_group[8].input[9] 2137 CYHAL_TRIGGER_TR_GROUP8_INPUT10 = 358, //!< Debug Reduction #2 - tr_group[8].input[10] 2138 } cyhal_trigger_dest_tviibe4m_t; 2139 2140 /** Typedef from device family specific trigger dest to generic trigger dest */ 2141 typedef cyhal_trigger_dest_tviibe4m_t cyhal_dest_t; 2142 2143 /** \cond INTERNAL */ 2144 /** Table of number of inputs to each mux. */ 2145 extern const uint16_t cyhal_sources_per_mux[22]; 2146 2147 /** Table indicating whether mux is 1to1. */ 2148 extern const bool cyhal_is_mux_1to1[22]; 2149 2150 /** Table pointing to each mux source table. The index of each source in the table is its mux input index. */ 2151 extern const _cyhal_trigger_source_tviibe4m_t* cyhal_mux_to_sources [22]; 2152 2153 /** Maps each cyhal_destination_t to a mux index. 2154 * If bit 8 of the mux index is set, this denotes that the trigger is a 2155 * one to one trigger. 2156 */ 2157 extern const uint8_t cyhal_dest_to_mux[359]; 2158 2159 /* Maps each cyhal_destination_t to a specific output in its mux */ 2160 extern const uint8_t cyhal_mux_dest_index[359]; 2161 /** \endcond */ 2162 2163 #if defined(__cplusplus) 2164 } 2165 #endif /* __cplusplus */ 2166 /** \} group_hal_impl_triggers_tviibe4m */ 2167 #endif /* _CYHAL_TRIGGERS_TVIIBE4M_H_ */ 2168 2169 2170 /* [] END OF FILE */ 2171
