1 /***************************************************************************//** 2 * \file cyhal_triggers_tviibe1m.h 3 * 4 * \brief 5 * TVIIBE1M family HAL triggers header 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYHAL_TRIGGERS_TVIIBE1M_H_ 28 #define _CYHAL_TRIGGERS_TVIIBE1M_H_ 29 30 /** 31 * \addtogroup group_hal_impl_triggers_tviibe1m TVIIBE1M 32 * \ingroup group_hal_impl_triggers 33 * \{ 34 * Trigger connections for tviibe1m 35 */ 36 37 #if defined(__cplusplus) 38 extern "C" { 39 #endif /* __cplusplus */ 40 41 /** \cond INTERNAL */ 42 /** @brief Name of each input trigger. */ 43 typedef enum 44 { 45 _CYHAL_TRIGGER_CPUSS_ZERO = 0, //!< cpuss.zero 46 _CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ0 = 1, //!< canfd[0].tr_dbg_dma_req[0] 47 _CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ1 = 2, //!< canfd[0].tr_dbg_dma_req[1] 48 _CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ2 = 3, //!< canfd[0].tr_dbg_dma_req[2] 49 _CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_REQ0 = 4, //!< canfd[1].tr_dbg_dma_req[0] 50 _CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_REQ1 = 5, //!< canfd[1].tr_dbg_dma_req[1] 51 _CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_REQ2 = 6, //!< canfd[1].tr_dbg_dma_req[2] 52 _CYHAL_TRIGGER_CANFD0_TR_FIFO00 = 7, //!< canfd[0].tr_fifo0[0] 53 _CYHAL_TRIGGER_CANFD0_TR_FIFO01 = 8, //!< canfd[0].tr_fifo0[1] 54 _CYHAL_TRIGGER_CANFD0_TR_FIFO02 = 9, //!< canfd[0].tr_fifo0[2] 55 _CYHAL_TRIGGER_CANFD1_TR_FIFO00 = 10, //!< canfd[1].tr_fifo0[0] 56 _CYHAL_TRIGGER_CANFD1_TR_FIFO01 = 11, //!< canfd[1].tr_fifo0[1] 57 _CYHAL_TRIGGER_CANFD1_TR_FIFO02 = 12, //!< canfd[1].tr_fifo0[2] 58 _CYHAL_TRIGGER_CANFD0_TR_FIFO10 = 13, //!< canfd[0].tr_fifo1[0] 59 _CYHAL_TRIGGER_CANFD0_TR_FIFO11 = 14, //!< canfd[0].tr_fifo1[1] 60 _CYHAL_TRIGGER_CANFD0_TR_FIFO12 = 15, //!< canfd[0].tr_fifo1[2] 61 _CYHAL_TRIGGER_CANFD1_TR_FIFO10 = 16, //!< canfd[1].tr_fifo1[0] 62 _CYHAL_TRIGGER_CANFD1_TR_FIFO11 = 17, //!< canfd[1].tr_fifo1[1] 63 _CYHAL_TRIGGER_CANFD1_TR_FIFO12 = 18, //!< canfd[1].tr_fifo1[2] 64 _CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT0 = 19, //!< canfd[0].tr_tmp_rtp_out[0] 65 _CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT1 = 20, //!< canfd[0].tr_tmp_rtp_out[1] 66 _CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT2 = 21, //!< canfd[0].tr_tmp_rtp_out[2] 67 _CYHAL_TRIGGER_CANFD1_TR_TMP_RTP_OUT0 = 22, //!< canfd[1].tr_tmp_rtp_out[0] 68 _CYHAL_TRIGGER_CANFD1_TR_TMP_RTP_OUT1 = 23, //!< canfd[1].tr_tmp_rtp_out[1] 69 _CYHAL_TRIGGER_CANFD1_TR_TMP_RTP_OUT2 = 24, //!< canfd[1].tr_tmp_rtp_out[2] 70 _CYHAL_TRIGGER_CPUSS_CTI_TR_OUT0 = 25, //!< cpuss.cti_tr_out[0] 71 _CYHAL_TRIGGER_CPUSS_CTI_TR_OUT1 = 26, //!< cpuss.cti_tr_out[1] 72 _CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT0 = 27, //!< cpuss.dmac_tr_out[0] 73 _CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT1 = 28, //!< cpuss.dmac_tr_out[1] 74 _CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT2 = 29, //!< cpuss.dmac_tr_out[2] 75 _CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT3 = 30, //!< cpuss.dmac_tr_out[3] 76 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT0 = 31, //!< cpuss.dw0_tr_out[0] 77 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT1 = 32, //!< cpuss.dw0_tr_out[1] 78 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT2 = 33, //!< cpuss.dw0_tr_out[2] 79 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT3 = 34, //!< cpuss.dw0_tr_out[3] 80 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT4 = 35, //!< cpuss.dw0_tr_out[4] 81 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT5 = 36, //!< cpuss.dw0_tr_out[5] 82 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT6 = 37, //!< cpuss.dw0_tr_out[6] 83 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT7 = 38, //!< cpuss.dw0_tr_out[7] 84 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT8 = 39, //!< cpuss.dw0_tr_out[8] 85 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT9 = 40, //!< cpuss.dw0_tr_out[9] 86 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT10 = 41, //!< cpuss.dw0_tr_out[10] 87 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT11 = 42, //!< cpuss.dw0_tr_out[11] 88 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT12 = 43, //!< cpuss.dw0_tr_out[12] 89 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT13 = 44, //!< cpuss.dw0_tr_out[13] 90 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT14 = 45, //!< cpuss.dw0_tr_out[14] 91 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT15 = 46, //!< cpuss.dw0_tr_out[15] 92 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT16 = 47, //!< cpuss.dw0_tr_out[16] 93 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT17 = 48, //!< cpuss.dw0_tr_out[17] 94 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT18 = 49, //!< cpuss.dw0_tr_out[18] 95 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT19 = 50, //!< cpuss.dw0_tr_out[19] 96 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT20 = 51, //!< cpuss.dw0_tr_out[20] 97 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT21 = 52, //!< cpuss.dw0_tr_out[21] 98 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT22 = 53, //!< cpuss.dw0_tr_out[22] 99 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT23 = 54, //!< cpuss.dw0_tr_out[23] 100 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT24 = 55, //!< cpuss.dw0_tr_out[24] 101 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT25 = 56, //!< cpuss.dw0_tr_out[25] 102 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT26 = 57, //!< cpuss.dw0_tr_out[26] 103 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT27 = 58, //!< cpuss.dw0_tr_out[27] 104 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT28 = 59, //!< cpuss.dw0_tr_out[28] 105 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT29 = 60, //!< cpuss.dw0_tr_out[29] 106 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT30 = 61, //!< cpuss.dw0_tr_out[30] 107 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT31 = 62, //!< cpuss.dw0_tr_out[31] 108 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT32 = 63, //!< cpuss.dw0_tr_out[32] 109 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT33 = 64, //!< cpuss.dw0_tr_out[33] 110 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT34 = 65, //!< cpuss.dw0_tr_out[34] 111 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT35 = 66, //!< cpuss.dw0_tr_out[35] 112 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT36 = 67, //!< cpuss.dw0_tr_out[36] 113 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT37 = 68, //!< cpuss.dw0_tr_out[37] 114 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT38 = 69, //!< cpuss.dw0_tr_out[38] 115 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT39 = 70, //!< cpuss.dw0_tr_out[39] 116 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT40 = 71, //!< cpuss.dw0_tr_out[40] 117 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT41 = 72, //!< cpuss.dw0_tr_out[41] 118 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT42 = 73, //!< cpuss.dw0_tr_out[42] 119 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT43 = 74, //!< cpuss.dw0_tr_out[43] 120 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT44 = 75, //!< cpuss.dw0_tr_out[44] 121 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT45 = 76, //!< cpuss.dw0_tr_out[45] 122 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT46 = 77, //!< cpuss.dw0_tr_out[46] 123 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT47 = 78, //!< cpuss.dw0_tr_out[47] 124 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT48 = 79, //!< cpuss.dw0_tr_out[48] 125 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT49 = 80, //!< cpuss.dw0_tr_out[49] 126 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT50 = 81, //!< cpuss.dw0_tr_out[50] 127 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT51 = 82, //!< cpuss.dw0_tr_out[51] 128 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT52 = 83, //!< cpuss.dw0_tr_out[52] 129 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT53 = 84, //!< cpuss.dw0_tr_out[53] 130 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT54 = 85, //!< cpuss.dw0_tr_out[54] 131 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT55 = 86, //!< cpuss.dw0_tr_out[55] 132 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT56 = 87, //!< cpuss.dw0_tr_out[56] 133 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT57 = 88, //!< cpuss.dw0_tr_out[57] 134 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT58 = 89, //!< cpuss.dw0_tr_out[58] 135 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT59 = 90, //!< cpuss.dw0_tr_out[59] 136 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT60 = 91, //!< cpuss.dw0_tr_out[60] 137 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT61 = 92, //!< cpuss.dw0_tr_out[61] 138 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT62 = 93, //!< cpuss.dw0_tr_out[62] 139 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT63 = 94, //!< cpuss.dw0_tr_out[63] 140 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT64 = 95, //!< cpuss.dw0_tr_out[64] 141 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT65 = 96, //!< cpuss.dw0_tr_out[65] 142 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT66 = 97, //!< cpuss.dw0_tr_out[66] 143 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT67 = 98, //!< cpuss.dw0_tr_out[67] 144 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT68 = 99, //!< cpuss.dw0_tr_out[68] 145 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT69 = 100, //!< cpuss.dw0_tr_out[69] 146 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT70 = 101, //!< cpuss.dw0_tr_out[70] 147 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT71 = 102, //!< cpuss.dw0_tr_out[71] 148 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT72 = 103, //!< cpuss.dw0_tr_out[72] 149 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT73 = 104, //!< cpuss.dw0_tr_out[73] 150 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT74 = 105, //!< cpuss.dw0_tr_out[74] 151 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT75 = 106, //!< cpuss.dw0_tr_out[75] 152 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT76 = 107, //!< cpuss.dw0_tr_out[76] 153 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT77 = 108, //!< cpuss.dw0_tr_out[77] 154 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT78 = 109, //!< cpuss.dw0_tr_out[78] 155 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT79 = 110, //!< cpuss.dw0_tr_out[79] 156 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT80 = 111, //!< cpuss.dw0_tr_out[80] 157 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT81 = 112, //!< cpuss.dw0_tr_out[81] 158 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT82 = 113, //!< cpuss.dw0_tr_out[82] 159 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT83 = 114, //!< cpuss.dw0_tr_out[83] 160 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT84 = 115, //!< cpuss.dw0_tr_out[84] 161 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT85 = 116, //!< cpuss.dw0_tr_out[85] 162 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT86 = 117, //!< cpuss.dw0_tr_out[86] 163 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT87 = 118, //!< cpuss.dw0_tr_out[87] 164 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT88 = 119, //!< cpuss.dw0_tr_out[88] 165 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT0 = 120, //!< cpuss.dw1_tr_out[0] 166 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT1 = 121, //!< cpuss.dw1_tr_out[1] 167 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT2 = 122, //!< cpuss.dw1_tr_out[2] 168 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT3 = 123, //!< cpuss.dw1_tr_out[3] 169 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT4 = 124, //!< cpuss.dw1_tr_out[4] 170 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT5 = 125, //!< cpuss.dw1_tr_out[5] 171 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT6 = 126, //!< cpuss.dw1_tr_out[6] 172 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT7 = 127, //!< cpuss.dw1_tr_out[7] 173 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT8 = 128, //!< cpuss.dw1_tr_out[8] 174 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT9 = 129, //!< cpuss.dw1_tr_out[9] 175 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT10 = 130, //!< cpuss.dw1_tr_out[10] 176 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT11 = 131, //!< cpuss.dw1_tr_out[11] 177 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT12 = 132, //!< cpuss.dw1_tr_out[12] 178 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT13 = 133, //!< cpuss.dw1_tr_out[13] 179 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT14 = 134, //!< cpuss.dw1_tr_out[14] 180 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT15 = 135, //!< cpuss.dw1_tr_out[15] 181 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT16 = 136, //!< cpuss.dw1_tr_out[16] 182 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT17 = 137, //!< cpuss.dw1_tr_out[17] 183 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT18 = 138, //!< cpuss.dw1_tr_out[18] 184 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT19 = 139, //!< cpuss.dw1_tr_out[19] 185 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT20 = 140, //!< cpuss.dw1_tr_out[20] 186 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT21 = 141, //!< cpuss.dw1_tr_out[21] 187 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT22 = 142, //!< cpuss.dw1_tr_out[22] 188 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT23 = 143, //!< cpuss.dw1_tr_out[23] 189 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT24 = 144, //!< cpuss.dw1_tr_out[24] 190 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT25 = 145, //!< cpuss.dw1_tr_out[25] 191 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT26 = 146, //!< cpuss.dw1_tr_out[26] 192 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT27 = 147, //!< cpuss.dw1_tr_out[27] 193 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT28 = 148, //!< cpuss.dw1_tr_out[28] 194 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT29 = 149, //!< cpuss.dw1_tr_out[29] 195 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT30 = 150, //!< cpuss.dw1_tr_out[30] 196 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT31 = 151, //!< cpuss.dw1_tr_out[31] 197 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT32 = 152, //!< cpuss.dw1_tr_out[32] 198 _CYHAL_TRIGGER_CPUSS_TR_FAULT0 = 153, //!< cpuss.tr_fault[0] 199 _CYHAL_TRIGGER_CPUSS_TR_FAULT1 = 154, //!< cpuss.tr_fault[1] 200 _CYHAL_TRIGGER_CPUSS_TR_FAULT2 = 155, //!< cpuss.tr_fault[2] 201 _CYHAL_TRIGGER_CPUSS_TR_FAULT3 = 156, //!< cpuss.tr_fault[3] 202 _CYHAL_TRIGGER_EVTGEN0_TR_OUT0 = 157, //!< evtgen[0].tr_out[0] 203 _CYHAL_TRIGGER_EVTGEN0_TR_OUT1 = 158, //!< evtgen[0].tr_out[1] 204 _CYHAL_TRIGGER_EVTGEN0_TR_OUT2 = 159, //!< evtgen[0].tr_out[2] 205 _CYHAL_TRIGGER_EVTGEN0_TR_OUT3 = 160, //!< evtgen[0].tr_out[3] 206 _CYHAL_TRIGGER_EVTGEN0_TR_OUT4 = 161, //!< evtgen[0].tr_out[4] 207 _CYHAL_TRIGGER_EVTGEN0_TR_OUT5 = 162, //!< evtgen[0].tr_out[5] 208 _CYHAL_TRIGGER_EVTGEN0_TR_OUT6 = 163, //!< evtgen[0].tr_out[6] 209 _CYHAL_TRIGGER_EVTGEN0_TR_OUT7 = 164, //!< evtgen[0].tr_out[7] 210 _CYHAL_TRIGGER_EVTGEN0_TR_OUT8 = 165, //!< evtgen[0].tr_out[8] 211 _CYHAL_TRIGGER_EVTGEN0_TR_OUT9 = 166, //!< evtgen[0].tr_out[9] 212 _CYHAL_TRIGGER_EVTGEN0_TR_OUT10 = 167, //!< evtgen[0].tr_out[10] 213 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE0 = 168, //!< pass[0].tr_sar_ch_done[0] 214 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE1 = 169, //!< pass[0].tr_sar_ch_done[1] 215 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE2 = 170, //!< pass[0].tr_sar_ch_done[2] 216 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE3 = 171, //!< pass[0].tr_sar_ch_done[3] 217 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE4 = 172, //!< pass[0].tr_sar_ch_done[4] 218 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE5 = 173, //!< pass[0].tr_sar_ch_done[5] 219 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE6 = 174, //!< pass[0].tr_sar_ch_done[6] 220 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE7 = 175, //!< pass[0].tr_sar_ch_done[7] 221 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE8 = 176, //!< pass[0].tr_sar_ch_done[8] 222 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE9 = 177, //!< pass[0].tr_sar_ch_done[9] 223 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE10 = 178, //!< pass[0].tr_sar_ch_done[10] 224 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE11 = 179, //!< pass[0].tr_sar_ch_done[11] 225 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE12 = 180, //!< pass[0].tr_sar_ch_done[12] 226 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE13 = 181, //!< pass[0].tr_sar_ch_done[13] 227 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE14 = 182, //!< pass[0].tr_sar_ch_done[14] 228 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE15 = 183, //!< pass[0].tr_sar_ch_done[15] 229 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE16 = 184, //!< pass[0].tr_sar_ch_done[16] 230 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE17 = 185, //!< pass[0].tr_sar_ch_done[17] 231 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE18 = 186, //!< pass[0].tr_sar_ch_done[18] 232 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE19 = 187, //!< pass[0].tr_sar_ch_done[19] 233 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE20 = 188, //!< pass[0].tr_sar_ch_done[20] 234 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE21 = 189, //!< pass[0].tr_sar_ch_done[21] 235 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE22 = 190, //!< pass[0].tr_sar_ch_done[22] 236 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE23 = 191, //!< pass[0].tr_sar_ch_done[23] 237 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE32 = 192, //!< pass[0].tr_sar_ch_done[32] 238 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE33 = 193, //!< pass[0].tr_sar_ch_done[33] 239 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE34 = 194, //!< pass[0].tr_sar_ch_done[34] 240 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE35 = 195, //!< pass[0].tr_sar_ch_done[35] 241 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE36 = 196, //!< pass[0].tr_sar_ch_done[36] 242 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE37 = 197, //!< pass[0].tr_sar_ch_done[37] 243 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE38 = 198, //!< pass[0].tr_sar_ch_done[38] 244 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE39 = 199, //!< pass[0].tr_sar_ch_done[39] 245 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE40 = 200, //!< pass[0].tr_sar_ch_done[40] 246 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE41 = 201, //!< pass[0].tr_sar_ch_done[41] 247 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE42 = 202, //!< pass[0].tr_sar_ch_done[42] 248 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE43 = 203, //!< pass[0].tr_sar_ch_done[43] 249 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE44 = 204, //!< pass[0].tr_sar_ch_done[44] 250 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE45 = 205, //!< pass[0].tr_sar_ch_done[45] 251 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE46 = 206, //!< pass[0].tr_sar_ch_done[46] 252 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE47 = 207, //!< pass[0].tr_sar_ch_done[47] 253 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE48 = 208, //!< pass[0].tr_sar_ch_done[48] 254 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE49 = 209, //!< pass[0].tr_sar_ch_done[49] 255 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE50 = 210, //!< pass[0].tr_sar_ch_done[50] 256 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE51 = 211, //!< pass[0].tr_sar_ch_done[51] 257 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE52 = 212, //!< pass[0].tr_sar_ch_done[52] 258 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE53 = 213, //!< pass[0].tr_sar_ch_done[53] 259 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE54 = 214, //!< pass[0].tr_sar_ch_done[54] 260 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE55 = 215, //!< pass[0].tr_sar_ch_done[55] 261 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE56 = 216, //!< pass[0].tr_sar_ch_done[56] 262 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE57 = 217, //!< pass[0].tr_sar_ch_done[57] 263 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE58 = 218, //!< pass[0].tr_sar_ch_done[58] 264 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE59 = 219, //!< pass[0].tr_sar_ch_done[59] 265 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE60 = 220, //!< pass[0].tr_sar_ch_done[60] 266 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE61 = 221, //!< pass[0].tr_sar_ch_done[61] 267 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE62 = 222, //!< pass[0].tr_sar_ch_done[62] 268 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE63 = 223, //!< pass[0].tr_sar_ch_done[63] 269 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE64 = 224, //!< pass[0].tr_sar_ch_done[64] 270 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE65 = 225, //!< pass[0].tr_sar_ch_done[65] 271 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE66 = 226, //!< pass[0].tr_sar_ch_done[66] 272 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE67 = 227, //!< pass[0].tr_sar_ch_done[67] 273 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE68 = 228, //!< pass[0].tr_sar_ch_done[68] 274 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE69 = 229, //!< pass[0].tr_sar_ch_done[69] 275 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE70 = 230, //!< pass[0].tr_sar_ch_done[70] 276 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE71 = 231, //!< pass[0].tr_sar_ch_done[71] 277 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO0 = 232, //!< pass[0].tr_sar_ch_rangevio[0] 278 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO1 = 233, //!< pass[0].tr_sar_ch_rangevio[1] 279 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO2 = 234, //!< pass[0].tr_sar_ch_rangevio[2] 280 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO3 = 235, //!< pass[0].tr_sar_ch_rangevio[3] 281 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO4 = 236, //!< pass[0].tr_sar_ch_rangevio[4] 282 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO5 = 237, //!< pass[0].tr_sar_ch_rangevio[5] 283 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO6 = 238, //!< pass[0].tr_sar_ch_rangevio[6] 284 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO7 = 239, //!< pass[0].tr_sar_ch_rangevio[7] 285 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO8 = 240, //!< pass[0].tr_sar_ch_rangevio[8] 286 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO9 = 241, //!< pass[0].tr_sar_ch_rangevio[9] 287 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO10 = 242, //!< pass[0].tr_sar_ch_rangevio[10] 288 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO11 = 243, //!< pass[0].tr_sar_ch_rangevio[11] 289 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO12 = 244, //!< pass[0].tr_sar_ch_rangevio[12] 290 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO13 = 245, //!< pass[0].tr_sar_ch_rangevio[13] 291 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO14 = 246, //!< pass[0].tr_sar_ch_rangevio[14] 292 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO15 = 247, //!< pass[0].tr_sar_ch_rangevio[15] 293 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO16 = 248, //!< pass[0].tr_sar_ch_rangevio[16] 294 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO17 = 249, //!< pass[0].tr_sar_ch_rangevio[17] 295 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO18 = 250, //!< pass[0].tr_sar_ch_rangevio[18] 296 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO19 = 251, //!< pass[0].tr_sar_ch_rangevio[19] 297 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO20 = 252, //!< pass[0].tr_sar_ch_rangevio[20] 298 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO21 = 253, //!< pass[0].tr_sar_ch_rangevio[21] 299 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO22 = 254, //!< pass[0].tr_sar_ch_rangevio[22] 300 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO23 = 255, //!< pass[0].tr_sar_ch_rangevio[23] 301 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO32 = 256, //!< pass[0].tr_sar_ch_rangevio[32] 302 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO33 = 257, //!< pass[0].tr_sar_ch_rangevio[33] 303 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO34 = 258, //!< pass[0].tr_sar_ch_rangevio[34] 304 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO35 = 259, //!< pass[0].tr_sar_ch_rangevio[35] 305 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO36 = 260, //!< pass[0].tr_sar_ch_rangevio[36] 306 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO37 = 261, //!< pass[0].tr_sar_ch_rangevio[37] 307 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO38 = 262, //!< pass[0].tr_sar_ch_rangevio[38] 308 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO39 = 263, //!< pass[0].tr_sar_ch_rangevio[39] 309 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO40 = 264, //!< pass[0].tr_sar_ch_rangevio[40] 310 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO41 = 265, //!< pass[0].tr_sar_ch_rangevio[41] 311 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO42 = 266, //!< pass[0].tr_sar_ch_rangevio[42] 312 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO43 = 267, //!< pass[0].tr_sar_ch_rangevio[43] 313 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO44 = 268, //!< pass[0].tr_sar_ch_rangevio[44] 314 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO45 = 269, //!< pass[0].tr_sar_ch_rangevio[45] 315 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO46 = 270, //!< pass[0].tr_sar_ch_rangevio[46] 316 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO47 = 271, //!< pass[0].tr_sar_ch_rangevio[47] 317 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO48 = 272, //!< pass[0].tr_sar_ch_rangevio[48] 318 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO49 = 273, //!< pass[0].tr_sar_ch_rangevio[49] 319 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO50 = 274, //!< pass[0].tr_sar_ch_rangevio[50] 320 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO51 = 275, //!< pass[0].tr_sar_ch_rangevio[51] 321 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO52 = 276, //!< pass[0].tr_sar_ch_rangevio[52] 322 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO53 = 277, //!< pass[0].tr_sar_ch_rangevio[53] 323 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO54 = 278, //!< pass[0].tr_sar_ch_rangevio[54] 324 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO55 = 279, //!< pass[0].tr_sar_ch_rangevio[55] 325 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO56 = 280, //!< pass[0].tr_sar_ch_rangevio[56] 326 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO57 = 281, //!< pass[0].tr_sar_ch_rangevio[57] 327 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO58 = 282, //!< pass[0].tr_sar_ch_rangevio[58] 328 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO59 = 283, //!< pass[0].tr_sar_ch_rangevio[59] 329 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO60 = 284, //!< pass[0].tr_sar_ch_rangevio[60] 330 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO61 = 285, //!< pass[0].tr_sar_ch_rangevio[61] 331 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO62 = 286, //!< pass[0].tr_sar_ch_rangevio[62] 332 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO63 = 287, //!< pass[0].tr_sar_ch_rangevio[63] 333 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO64 = 288, //!< pass[0].tr_sar_ch_rangevio[64] 334 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO65 = 289, //!< pass[0].tr_sar_ch_rangevio[65] 335 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO66 = 290, //!< pass[0].tr_sar_ch_rangevio[66] 336 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO67 = 291, //!< pass[0].tr_sar_ch_rangevio[67] 337 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO68 = 292, //!< pass[0].tr_sar_ch_rangevio[68] 338 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO69 = 293, //!< pass[0].tr_sar_ch_rangevio[69] 339 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO70 = 294, //!< pass[0].tr_sar_ch_rangevio[70] 340 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO71 = 295, //!< pass[0].tr_sar_ch_rangevio[71] 341 _CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT0 = 296, //!< pass[0].tr_sar_gen_out[0] 342 _CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT1 = 297, //!< pass[0].tr_sar_gen_out[1] 343 _CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT2 = 298, //!< pass[0].tr_sar_gen_out[2] 344 _CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT3 = 299, //!< pass[0].tr_sar_gen_out[3] 345 _CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT4 = 300, //!< pass[0].tr_sar_gen_out[4] 346 _CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT5 = 301, //!< pass[0].tr_sar_gen_out[5] 347 _CYHAL_TRIGGER_PERI_TR_IO_INPUT0 = 302, //!< peri.tr_io_input[0] 348 _CYHAL_TRIGGER_PERI_TR_IO_INPUT1 = 303, //!< peri.tr_io_input[1] 349 _CYHAL_TRIGGER_PERI_TR_IO_INPUT2 = 304, //!< peri.tr_io_input[2] 350 _CYHAL_TRIGGER_PERI_TR_IO_INPUT3 = 305, //!< peri.tr_io_input[3] 351 _CYHAL_TRIGGER_PERI_TR_IO_INPUT4 = 306, //!< peri.tr_io_input[4] 352 _CYHAL_TRIGGER_PERI_TR_IO_INPUT5 = 307, //!< peri.tr_io_input[5] 353 _CYHAL_TRIGGER_PERI_TR_IO_INPUT6 = 308, //!< peri.tr_io_input[6] 354 _CYHAL_TRIGGER_PERI_TR_IO_INPUT7 = 309, //!< peri.tr_io_input[7] 355 _CYHAL_TRIGGER_PERI_TR_IO_INPUT8 = 310, //!< peri.tr_io_input[8] 356 _CYHAL_TRIGGER_PERI_TR_IO_INPUT9 = 311, //!< peri.tr_io_input[9] 357 _CYHAL_TRIGGER_PERI_TR_IO_INPUT10 = 312, //!< peri.tr_io_input[10] 358 _CYHAL_TRIGGER_PERI_TR_IO_INPUT11 = 313, //!< peri.tr_io_input[11] 359 _CYHAL_TRIGGER_PERI_TR_IO_INPUT12 = 314, //!< peri.tr_io_input[12] 360 _CYHAL_TRIGGER_PERI_TR_IO_INPUT13 = 315, //!< peri.tr_io_input[13] 361 _CYHAL_TRIGGER_PERI_TR_IO_INPUT14 = 316, //!< peri.tr_io_input[14] 362 _CYHAL_TRIGGER_PERI_TR_IO_INPUT15 = 317, //!< peri.tr_io_input[15] 363 _CYHAL_TRIGGER_PERI_TR_IO_INPUT16 = 318, //!< peri.tr_io_input[16] 364 _CYHAL_TRIGGER_PERI_TR_IO_INPUT17 = 319, //!< peri.tr_io_input[17] 365 _CYHAL_TRIGGER_PERI_TR_IO_INPUT18 = 320, //!< peri.tr_io_input[18] 366 _CYHAL_TRIGGER_PERI_TR_IO_INPUT19 = 321, //!< peri.tr_io_input[19] 367 _CYHAL_TRIGGER_PERI_TR_IO_INPUT20 = 322, //!< peri.tr_io_input[20] 368 _CYHAL_TRIGGER_PERI_TR_IO_INPUT21 = 323, //!< peri.tr_io_input[21] 369 _CYHAL_TRIGGER_PERI_TR_IO_INPUT22 = 324, //!< peri.tr_io_input[22] 370 _CYHAL_TRIGGER_PERI_TR_IO_INPUT23 = 325, //!< peri.tr_io_input[23] 371 _CYHAL_TRIGGER_PERI_TR_IO_INPUT24 = 326, //!< peri.tr_io_input[24] 372 _CYHAL_TRIGGER_PERI_TR_IO_INPUT25 = 327, //!< peri.tr_io_input[25] 373 _CYHAL_TRIGGER_PERI_TR_IO_INPUT26 = 328, //!< peri.tr_io_input[26] 374 _CYHAL_TRIGGER_PERI_TR_IO_INPUT27 = 329, //!< peri.tr_io_input[27] 375 _CYHAL_TRIGGER_PERI_TR_IO_INPUT28 = 330, //!< peri.tr_io_input[28] 376 _CYHAL_TRIGGER_PERI_TR_IO_INPUT29 = 331, //!< peri.tr_io_input[29] 377 _CYHAL_TRIGGER_PERI_TR_IO_INPUT30 = 332, //!< peri.tr_io_input[30] 378 _CYHAL_TRIGGER_PERI_TR_IO_INPUT31 = 333, //!< peri.tr_io_input[31] 379 _CYHAL_TRIGGER_SCB0_TR_I2C_SCL_FILTERED = 334, //!< scb[0].tr_i2c_scl_filtered 380 _CYHAL_TRIGGER_SCB1_TR_I2C_SCL_FILTERED = 335, //!< scb[1].tr_i2c_scl_filtered 381 _CYHAL_TRIGGER_SCB2_TR_I2C_SCL_FILTERED = 336, //!< scb[2].tr_i2c_scl_filtered 382 _CYHAL_TRIGGER_SCB3_TR_I2C_SCL_FILTERED = 337, //!< scb[3].tr_i2c_scl_filtered 383 _CYHAL_TRIGGER_SCB4_TR_I2C_SCL_FILTERED = 338, //!< scb[4].tr_i2c_scl_filtered 384 _CYHAL_TRIGGER_SCB5_TR_I2C_SCL_FILTERED = 339, //!< scb[5].tr_i2c_scl_filtered 385 _CYHAL_TRIGGER_SCB6_TR_I2C_SCL_FILTERED = 340, //!< scb[6].tr_i2c_scl_filtered 386 _CYHAL_TRIGGER_SCB7_TR_I2C_SCL_FILTERED = 341, //!< scb[7].tr_i2c_scl_filtered 387 _CYHAL_TRIGGER_SCB0_TR_RX_REQ = 342, //!< scb[0].tr_rx_req 388 _CYHAL_TRIGGER_SCB1_TR_RX_REQ = 343, //!< scb[1].tr_rx_req 389 _CYHAL_TRIGGER_SCB2_TR_RX_REQ = 344, //!< scb[2].tr_rx_req 390 _CYHAL_TRIGGER_SCB3_TR_RX_REQ = 345, //!< scb[3].tr_rx_req 391 _CYHAL_TRIGGER_SCB4_TR_RX_REQ = 346, //!< scb[4].tr_rx_req 392 _CYHAL_TRIGGER_SCB5_TR_RX_REQ = 347, //!< scb[5].tr_rx_req 393 _CYHAL_TRIGGER_SCB6_TR_RX_REQ = 348, //!< scb[6].tr_rx_req 394 _CYHAL_TRIGGER_SCB7_TR_RX_REQ = 349, //!< scb[7].tr_rx_req 395 _CYHAL_TRIGGER_SCB0_TR_TX_REQ = 350, //!< scb[0].tr_tx_req 396 _CYHAL_TRIGGER_SCB1_TR_TX_REQ = 351, //!< scb[1].tr_tx_req 397 _CYHAL_TRIGGER_SCB2_TR_TX_REQ = 352, //!< scb[2].tr_tx_req 398 _CYHAL_TRIGGER_SCB3_TR_TX_REQ = 353, //!< scb[3].tr_tx_req 399 _CYHAL_TRIGGER_SCB4_TR_TX_REQ = 354, //!< scb[4].tr_tx_req 400 _CYHAL_TRIGGER_SCB5_TR_TX_REQ = 355, //!< scb[5].tr_tx_req 401 _CYHAL_TRIGGER_SCB6_TR_TX_REQ = 356, //!< scb[6].tr_tx_req 402 _CYHAL_TRIGGER_SCB7_TR_TX_REQ = 357, //!< scb[7].tr_tx_req 403 _CYHAL_TRIGGER_TCPWM0_TR_OUT00 = 358, //!< tcpwm[0].tr_out0[0] 404 _CYHAL_TRIGGER_TCPWM0_TR_OUT01 = 359, //!< tcpwm[0].tr_out0[1] 405 _CYHAL_TRIGGER_TCPWM0_TR_OUT02 = 360, //!< tcpwm[0].tr_out0[2] 406 _CYHAL_TRIGGER_TCPWM0_TR_OUT03 = 361, //!< tcpwm[0].tr_out0[3] 407 _CYHAL_TRIGGER_TCPWM0_TR_OUT04 = 362, //!< tcpwm[0].tr_out0[4] 408 _CYHAL_TRIGGER_TCPWM0_TR_OUT05 = 363, //!< tcpwm[0].tr_out0[5] 409 _CYHAL_TRIGGER_TCPWM0_TR_OUT06 = 364, //!< tcpwm[0].tr_out0[6] 410 _CYHAL_TRIGGER_TCPWM0_TR_OUT07 = 365, //!< tcpwm[0].tr_out0[7] 411 _CYHAL_TRIGGER_TCPWM0_TR_OUT08 = 366, //!< tcpwm[0].tr_out0[8] 412 _CYHAL_TRIGGER_TCPWM0_TR_OUT09 = 367, //!< tcpwm[0].tr_out0[9] 413 _CYHAL_TRIGGER_TCPWM0_TR_OUT010 = 368, //!< tcpwm[0].tr_out0[10] 414 _CYHAL_TRIGGER_TCPWM0_TR_OUT011 = 369, //!< tcpwm[0].tr_out0[11] 415 _CYHAL_TRIGGER_TCPWM0_TR_OUT012 = 370, //!< tcpwm[0].tr_out0[12] 416 _CYHAL_TRIGGER_TCPWM0_TR_OUT013 = 371, //!< tcpwm[0].tr_out0[13] 417 _CYHAL_TRIGGER_TCPWM0_TR_OUT014 = 372, //!< tcpwm[0].tr_out0[14] 418 _CYHAL_TRIGGER_TCPWM0_TR_OUT015 = 373, //!< tcpwm[0].tr_out0[15] 419 _CYHAL_TRIGGER_TCPWM0_TR_OUT016 = 374, //!< tcpwm[0].tr_out0[16] 420 _CYHAL_TRIGGER_TCPWM0_TR_OUT017 = 375, //!< tcpwm[0].tr_out0[17] 421 _CYHAL_TRIGGER_TCPWM0_TR_OUT018 = 376, //!< tcpwm[0].tr_out0[18] 422 _CYHAL_TRIGGER_TCPWM0_TR_OUT019 = 377, //!< tcpwm[0].tr_out0[19] 423 _CYHAL_TRIGGER_TCPWM0_TR_OUT020 = 378, //!< tcpwm[0].tr_out0[20] 424 _CYHAL_TRIGGER_TCPWM0_TR_OUT021 = 379, //!< tcpwm[0].tr_out0[21] 425 _CYHAL_TRIGGER_TCPWM0_TR_OUT022 = 380, //!< tcpwm[0].tr_out0[22] 426 _CYHAL_TRIGGER_TCPWM0_TR_OUT023 = 381, //!< tcpwm[0].tr_out0[23] 427 _CYHAL_TRIGGER_TCPWM0_TR_OUT024 = 382, //!< tcpwm[0].tr_out0[24] 428 _CYHAL_TRIGGER_TCPWM0_TR_OUT025 = 383, //!< tcpwm[0].tr_out0[25] 429 _CYHAL_TRIGGER_TCPWM0_TR_OUT026 = 384, //!< tcpwm[0].tr_out0[26] 430 _CYHAL_TRIGGER_TCPWM0_TR_OUT027 = 385, //!< tcpwm[0].tr_out0[27] 431 _CYHAL_TRIGGER_TCPWM0_TR_OUT028 = 386, //!< tcpwm[0].tr_out0[28] 432 _CYHAL_TRIGGER_TCPWM0_TR_OUT029 = 387, //!< tcpwm[0].tr_out0[29] 433 _CYHAL_TRIGGER_TCPWM0_TR_OUT030 = 388, //!< tcpwm[0].tr_out0[30] 434 _CYHAL_TRIGGER_TCPWM0_TR_OUT031 = 389, //!< tcpwm[0].tr_out0[31] 435 _CYHAL_TRIGGER_TCPWM0_TR_OUT032 = 390, //!< tcpwm[0].tr_out0[32] 436 _CYHAL_TRIGGER_TCPWM0_TR_OUT033 = 391, //!< tcpwm[0].tr_out0[33] 437 _CYHAL_TRIGGER_TCPWM0_TR_OUT034 = 392, //!< tcpwm[0].tr_out0[34] 438 _CYHAL_TRIGGER_TCPWM0_TR_OUT035 = 393, //!< tcpwm[0].tr_out0[35] 439 _CYHAL_TRIGGER_TCPWM0_TR_OUT036 = 394, //!< tcpwm[0].tr_out0[36] 440 _CYHAL_TRIGGER_TCPWM0_TR_OUT037 = 395, //!< tcpwm[0].tr_out0[37] 441 _CYHAL_TRIGGER_TCPWM0_TR_OUT038 = 396, //!< tcpwm[0].tr_out0[38] 442 _CYHAL_TRIGGER_TCPWM0_TR_OUT039 = 397, //!< tcpwm[0].tr_out0[39] 443 _CYHAL_TRIGGER_TCPWM0_TR_OUT040 = 398, //!< tcpwm[0].tr_out0[40] 444 _CYHAL_TRIGGER_TCPWM0_TR_OUT041 = 399, //!< tcpwm[0].tr_out0[41] 445 _CYHAL_TRIGGER_TCPWM0_TR_OUT042 = 400, //!< tcpwm[0].tr_out0[42] 446 _CYHAL_TRIGGER_TCPWM0_TR_OUT043 = 401, //!< tcpwm[0].tr_out0[43] 447 _CYHAL_TRIGGER_TCPWM0_TR_OUT044 = 402, //!< tcpwm[0].tr_out0[44] 448 _CYHAL_TRIGGER_TCPWM0_TR_OUT045 = 403, //!< tcpwm[0].tr_out0[45] 449 _CYHAL_TRIGGER_TCPWM0_TR_OUT046 = 404, //!< tcpwm[0].tr_out0[46] 450 _CYHAL_TRIGGER_TCPWM0_TR_OUT047 = 405, //!< tcpwm[0].tr_out0[47] 451 _CYHAL_TRIGGER_TCPWM0_TR_OUT048 = 406, //!< tcpwm[0].tr_out0[48] 452 _CYHAL_TRIGGER_TCPWM0_TR_OUT049 = 407, //!< tcpwm[0].tr_out0[49] 453 _CYHAL_TRIGGER_TCPWM0_TR_OUT050 = 408, //!< tcpwm[0].tr_out0[50] 454 _CYHAL_TRIGGER_TCPWM0_TR_OUT051 = 409, //!< tcpwm[0].tr_out0[51] 455 _CYHAL_TRIGGER_TCPWM0_TR_OUT052 = 410, //!< tcpwm[0].tr_out0[52] 456 _CYHAL_TRIGGER_TCPWM0_TR_OUT053 = 411, //!< tcpwm[0].tr_out0[53] 457 _CYHAL_TRIGGER_TCPWM0_TR_OUT054 = 412, //!< tcpwm[0].tr_out0[54] 458 _CYHAL_TRIGGER_TCPWM0_TR_OUT055 = 413, //!< tcpwm[0].tr_out0[55] 459 _CYHAL_TRIGGER_TCPWM0_TR_OUT056 = 414, //!< tcpwm[0].tr_out0[56] 460 _CYHAL_TRIGGER_TCPWM0_TR_OUT057 = 415, //!< tcpwm[0].tr_out0[57] 461 _CYHAL_TRIGGER_TCPWM0_TR_OUT058 = 416, //!< tcpwm[0].tr_out0[58] 462 _CYHAL_TRIGGER_TCPWM0_TR_OUT059 = 417, //!< tcpwm[0].tr_out0[59] 463 _CYHAL_TRIGGER_TCPWM0_TR_OUT060 = 418, //!< tcpwm[0].tr_out0[60] 464 _CYHAL_TRIGGER_TCPWM0_TR_OUT061 = 419, //!< tcpwm[0].tr_out0[61] 465 _CYHAL_TRIGGER_TCPWM0_TR_OUT062 = 420, //!< tcpwm[0].tr_out0[62] 466 _CYHAL_TRIGGER_TCPWM0_TR_OUT0256 = 421, //!< tcpwm[0].tr_out0[256] 467 _CYHAL_TRIGGER_TCPWM0_TR_OUT0257 = 422, //!< tcpwm[0].tr_out0[257] 468 _CYHAL_TRIGGER_TCPWM0_TR_OUT0258 = 423, //!< tcpwm[0].tr_out0[258] 469 _CYHAL_TRIGGER_TCPWM0_TR_OUT0259 = 424, //!< tcpwm[0].tr_out0[259] 470 _CYHAL_TRIGGER_TCPWM0_TR_OUT0260 = 425, //!< tcpwm[0].tr_out0[260] 471 _CYHAL_TRIGGER_TCPWM0_TR_OUT0261 = 426, //!< tcpwm[0].tr_out0[261] 472 _CYHAL_TRIGGER_TCPWM0_TR_OUT0262 = 427, //!< tcpwm[0].tr_out0[262] 473 _CYHAL_TRIGGER_TCPWM0_TR_OUT0263 = 428, //!< tcpwm[0].tr_out0[263] 474 _CYHAL_TRIGGER_TCPWM0_TR_OUT0264 = 429, //!< tcpwm[0].tr_out0[264] 475 _CYHAL_TRIGGER_TCPWM0_TR_OUT0265 = 430, //!< tcpwm[0].tr_out0[265] 476 _CYHAL_TRIGGER_TCPWM0_TR_OUT0266 = 431, //!< tcpwm[0].tr_out0[266] 477 _CYHAL_TRIGGER_TCPWM0_TR_OUT0267 = 432, //!< tcpwm[0].tr_out0[267] 478 _CYHAL_TRIGGER_TCPWM0_TR_OUT0512 = 433, //!< tcpwm[0].tr_out0[512] 479 _CYHAL_TRIGGER_TCPWM0_TR_OUT0513 = 434, //!< tcpwm[0].tr_out0[513] 480 _CYHAL_TRIGGER_TCPWM0_TR_OUT0514 = 435, //!< tcpwm[0].tr_out0[514] 481 _CYHAL_TRIGGER_TCPWM0_TR_OUT0515 = 436, //!< tcpwm[0].tr_out0[515] 482 _CYHAL_TRIGGER_TCPWM0_TR_OUT10 = 437, //!< tcpwm[0].tr_out1[0] 483 _CYHAL_TRIGGER_TCPWM0_TR_OUT11 = 438, //!< tcpwm[0].tr_out1[1] 484 _CYHAL_TRIGGER_TCPWM0_TR_OUT12 = 439, //!< tcpwm[0].tr_out1[2] 485 _CYHAL_TRIGGER_TCPWM0_TR_OUT13 = 440, //!< tcpwm[0].tr_out1[3] 486 _CYHAL_TRIGGER_TCPWM0_TR_OUT14 = 441, //!< tcpwm[0].tr_out1[4] 487 _CYHAL_TRIGGER_TCPWM0_TR_OUT15 = 442, //!< tcpwm[0].tr_out1[5] 488 _CYHAL_TRIGGER_TCPWM0_TR_OUT16 = 443, //!< tcpwm[0].tr_out1[6] 489 _CYHAL_TRIGGER_TCPWM0_TR_OUT17 = 444, //!< tcpwm[0].tr_out1[7] 490 _CYHAL_TRIGGER_TCPWM0_TR_OUT18 = 445, //!< tcpwm[0].tr_out1[8] 491 _CYHAL_TRIGGER_TCPWM0_TR_OUT19 = 446, //!< tcpwm[0].tr_out1[9] 492 _CYHAL_TRIGGER_TCPWM0_TR_OUT110 = 447, //!< tcpwm[0].tr_out1[10] 493 _CYHAL_TRIGGER_TCPWM0_TR_OUT111 = 448, //!< tcpwm[0].tr_out1[11] 494 _CYHAL_TRIGGER_TCPWM0_TR_OUT112 = 449, //!< tcpwm[0].tr_out1[12] 495 _CYHAL_TRIGGER_TCPWM0_TR_OUT113 = 450, //!< tcpwm[0].tr_out1[13] 496 _CYHAL_TRIGGER_TCPWM0_TR_OUT114 = 451, //!< tcpwm[0].tr_out1[14] 497 _CYHAL_TRIGGER_TCPWM0_TR_OUT115 = 452, //!< tcpwm[0].tr_out1[15] 498 _CYHAL_TRIGGER_TCPWM0_TR_OUT116 = 453, //!< tcpwm[0].tr_out1[16] 499 _CYHAL_TRIGGER_TCPWM0_TR_OUT117 = 454, //!< tcpwm[0].tr_out1[17] 500 _CYHAL_TRIGGER_TCPWM0_TR_OUT118 = 455, //!< tcpwm[0].tr_out1[18] 501 _CYHAL_TRIGGER_TCPWM0_TR_OUT119 = 456, //!< tcpwm[0].tr_out1[19] 502 _CYHAL_TRIGGER_TCPWM0_TR_OUT120 = 457, //!< tcpwm[0].tr_out1[20] 503 _CYHAL_TRIGGER_TCPWM0_TR_OUT121 = 458, //!< tcpwm[0].tr_out1[21] 504 _CYHAL_TRIGGER_TCPWM0_TR_OUT122 = 459, //!< tcpwm[0].tr_out1[22] 505 _CYHAL_TRIGGER_TCPWM0_TR_OUT123 = 460, //!< tcpwm[0].tr_out1[23] 506 _CYHAL_TRIGGER_TCPWM0_TR_OUT124 = 461, //!< tcpwm[0].tr_out1[24] 507 _CYHAL_TRIGGER_TCPWM0_TR_OUT125 = 462, //!< tcpwm[0].tr_out1[25] 508 _CYHAL_TRIGGER_TCPWM0_TR_OUT126 = 463, //!< tcpwm[0].tr_out1[26] 509 _CYHAL_TRIGGER_TCPWM0_TR_OUT127 = 464, //!< tcpwm[0].tr_out1[27] 510 _CYHAL_TRIGGER_TCPWM0_TR_OUT128 = 465, //!< tcpwm[0].tr_out1[28] 511 _CYHAL_TRIGGER_TCPWM0_TR_OUT129 = 466, //!< tcpwm[0].tr_out1[29] 512 _CYHAL_TRIGGER_TCPWM0_TR_OUT130 = 467, //!< tcpwm[0].tr_out1[30] 513 _CYHAL_TRIGGER_TCPWM0_TR_OUT131 = 468, //!< tcpwm[0].tr_out1[31] 514 _CYHAL_TRIGGER_TCPWM0_TR_OUT132 = 469, //!< tcpwm[0].tr_out1[32] 515 _CYHAL_TRIGGER_TCPWM0_TR_OUT133 = 470, //!< tcpwm[0].tr_out1[33] 516 _CYHAL_TRIGGER_TCPWM0_TR_OUT134 = 471, //!< tcpwm[0].tr_out1[34] 517 _CYHAL_TRIGGER_TCPWM0_TR_OUT135 = 472, //!< tcpwm[0].tr_out1[35] 518 _CYHAL_TRIGGER_TCPWM0_TR_OUT136 = 473, //!< tcpwm[0].tr_out1[36] 519 _CYHAL_TRIGGER_TCPWM0_TR_OUT137 = 474, //!< tcpwm[0].tr_out1[37] 520 _CYHAL_TRIGGER_TCPWM0_TR_OUT138 = 475, //!< tcpwm[0].tr_out1[38] 521 _CYHAL_TRIGGER_TCPWM0_TR_OUT139 = 476, //!< tcpwm[0].tr_out1[39] 522 _CYHAL_TRIGGER_TCPWM0_TR_OUT140 = 477, //!< tcpwm[0].tr_out1[40] 523 _CYHAL_TRIGGER_TCPWM0_TR_OUT141 = 478, //!< tcpwm[0].tr_out1[41] 524 _CYHAL_TRIGGER_TCPWM0_TR_OUT142 = 479, //!< tcpwm[0].tr_out1[42] 525 _CYHAL_TRIGGER_TCPWM0_TR_OUT143 = 480, //!< tcpwm[0].tr_out1[43] 526 _CYHAL_TRIGGER_TCPWM0_TR_OUT144 = 481, //!< tcpwm[0].tr_out1[44] 527 _CYHAL_TRIGGER_TCPWM0_TR_OUT145 = 482, //!< tcpwm[0].tr_out1[45] 528 _CYHAL_TRIGGER_TCPWM0_TR_OUT146 = 483, //!< tcpwm[0].tr_out1[46] 529 _CYHAL_TRIGGER_TCPWM0_TR_OUT147 = 484, //!< tcpwm[0].tr_out1[47] 530 _CYHAL_TRIGGER_TCPWM0_TR_OUT148 = 485, //!< tcpwm[0].tr_out1[48] 531 _CYHAL_TRIGGER_TCPWM0_TR_OUT149 = 486, //!< tcpwm[0].tr_out1[49] 532 _CYHAL_TRIGGER_TCPWM0_TR_OUT150 = 487, //!< tcpwm[0].tr_out1[50] 533 _CYHAL_TRIGGER_TCPWM0_TR_OUT151 = 488, //!< tcpwm[0].tr_out1[51] 534 _CYHAL_TRIGGER_TCPWM0_TR_OUT152 = 489, //!< tcpwm[0].tr_out1[52] 535 _CYHAL_TRIGGER_TCPWM0_TR_OUT153 = 490, //!< tcpwm[0].tr_out1[53] 536 _CYHAL_TRIGGER_TCPWM0_TR_OUT154 = 491, //!< tcpwm[0].tr_out1[54] 537 _CYHAL_TRIGGER_TCPWM0_TR_OUT155 = 492, //!< tcpwm[0].tr_out1[55] 538 _CYHAL_TRIGGER_TCPWM0_TR_OUT156 = 493, //!< tcpwm[0].tr_out1[56] 539 _CYHAL_TRIGGER_TCPWM0_TR_OUT157 = 494, //!< tcpwm[0].tr_out1[57] 540 _CYHAL_TRIGGER_TCPWM0_TR_OUT158 = 495, //!< tcpwm[0].tr_out1[58] 541 _CYHAL_TRIGGER_TCPWM0_TR_OUT159 = 496, //!< tcpwm[0].tr_out1[59] 542 _CYHAL_TRIGGER_TCPWM0_TR_OUT160 = 497, //!< tcpwm[0].tr_out1[60] 543 _CYHAL_TRIGGER_TCPWM0_TR_OUT161 = 498, //!< tcpwm[0].tr_out1[61] 544 _CYHAL_TRIGGER_TCPWM0_TR_OUT162 = 499, //!< tcpwm[0].tr_out1[62] 545 _CYHAL_TRIGGER_TCPWM0_TR_OUT1256 = 500, //!< tcpwm[0].tr_out1[256] 546 _CYHAL_TRIGGER_TCPWM0_TR_OUT1257 = 501, //!< tcpwm[0].tr_out1[257] 547 _CYHAL_TRIGGER_TCPWM0_TR_OUT1258 = 502, //!< tcpwm[0].tr_out1[258] 548 _CYHAL_TRIGGER_TCPWM0_TR_OUT1259 = 503, //!< tcpwm[0].tr_out1[259] 549 _CYHAL_TRIGGER_TCPWM0_TR_OUT1260 = 504, //!< tcpwm[0].tr_out1[260] 550 _CYHAL_TRIGGER_TCPWM0_TR_OUT1261 = 505, //!< tcpwm[0].tr_out1[261] 551 _CYHAL_TRIGGER_TCPWM0_TR_OUT1262 = 506, //!< tcpwm[0].tr_out1[262] 552 _CYHAL_TRIGGER_TCPWM0_TR_OUT1263 = 507, //!< tcpwm[0].tr_out1[263] 553 _CYHAL_TRIGGER_TCPWM0_TR_OUT1264 = 508, //!< tcpwm[0].tr_out1[264] 554 _CYHAL_TRIGGER_TCPWM0_TR_OUT1265 = 509, //!< tcpwm[0].tr_out1[265] 555 _CYHAL_TRIGGER_TCPWM0_TR_OUT1266 = 510, //!< tcpwm[0].tr_out1[266] 556 _CYHAL_TRIGGER_TCPWM0_TR_OUT1267 = 511, //!< tcpwm[0].tr_out1[267] 557 _CYHAL_TRIGGER_TCPWM0_TR_OUT1512 = 512, //!< tcpwm[0].tr_out1[512] 558 _CYHAL_TRIGGER_TCPWM0_TR_OUT1513 = 513, //!< tcpwm[0].tr_out1[513] 559 _CYHAL_TRIGGER_TCPWM0_TR_OUT1514 = 514, //!< tcpwm[0].tr_out1[514] 560 _CYHAL_TRIGGER_TCPWM0_TR_OUT1515 = 515, //!< tcpwm[0].tr_out1[515] 561 _CYHAL_TRIGGER_TR_GROUP9_OUTPUT0 = 516, //!< tr_group[9].output[0] 562 _CYHAL_TRIGGER_TR_GROUP9_OUTPUT1 = 517, //!< tr_group[9].output[1] 563 _CYHAL_TRIGGER_TR_GROUP9_OUTPUT2 = 518, //!< tr_group[9].output[2] 564 _CYHAL_TRIGGER_TR_GROUP9_OUTPUT3 = 519, //!< tr_group[9].output[3] 565 _CYHAL_TRIGGER_TR_GROUP9_OUTPUT4 = 520, //!< tr_group[9].output[4] 566 _CYHAL_TRIGGER_TR_GROUP10_OUTPUT0 = 521, //!< tr_group[10].output[0] 567 _CYHAL_TRIGGER_TR_GROUP10_OUTPUT1 = 522, //!< tr_group[10].output[1] 568 _CYHAL_TRIGGER_TR_GROUP10_OUTPUT2 = 523, //!< tr_group[10].output[2] 569 _CYHAL_TRIGGER_TR_GROUP10_OUTPUT3 = 524, //!< tr_group[10].output[3] 570 _CYHAL_TRIGGER_TR_GROUP10_OUTPUT4 = 525, //!< tr_group[10].output[4] 571 } _cyhal_trigger_source_tviibe1m_t; 572 573 /** Typedef for internal device family specific trigger source to generic trigger source */ 574 typedef _cyhal_trigger_source_tviibe1m_t cyhal_internal_source_t; 575 576 /** @brief Get a public source signal type (cyhal_trigger_source_tviibe1m_t) given an internal source signal and signal type */ 577 #define _CYHAL_TRIGGER_CREATE_SOURCE(src, type) ((src) << 1 | (type)) 578 /** @brief Get an internal source signal (_cyhal_trigger_source_tviibe1m_t) given a public source signal. */ 579 #define _CYHAL_TRIGGER_GET_SOURCE_SIGNAL(src) ((cyhal_internal_source_t)((src) >> 1)) 580 /** @brief Get the signal type (cyhal_signal_type_t) given a public source signal. */ 581 #define _CYHAL_TRIGGER_GET_SOURCE_TYPE(src) ((cyhal_signal_type_t)((src) & 1)) 582 /** \endcond */ 583 584 /** @brief Name of each input trigger. */ 585 typedef enum 586 { 587 CYHAL_TRIGGER_CPUSS_ZERO_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_ZERO, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.zero 588 CYHAL_TRIGGER_CPUSS_ZERO_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_ZERO, CYHAL_SIGNAL_TYPE_LEVEL), //!< cpuss.zero 589 CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ0, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[0].tr_dbg_dma_req[0] 590 CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ1, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[0].tr_dbg_dma_req[1] 591 CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ2, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[0].tr_dbg_dma_req[2] 592 CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_REQ0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_REQ0, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[1].tr_dbg_dma_req[0] 593 CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_REQ1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_REQ1, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[1].tr_dbg_dma_req[1] 594 CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_REQ2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_REQ2, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[1].tr_dbg_dma_req[2] 595 CYHAL_TRIGGER_CANFD0_TR_FIFO00 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_FIFO00, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[0].tr_fifo0[0] 596 CYHAL_TRIGGER_CANFD0_TR_FIFO01 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_FIFO01, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[0].tr_fifo0[1] 597 CYHAL_TRIGGER_CANFD0_TR_FIFO02 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_FIFO02, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[0].tr_fifo0[2] 598 CYHAL_TRIGGER_CANFD1_TR_FIFO00 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD1_TR_FIFO00, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[1].tr_fifo0[0] 599 CYHAL_TRIGGER_CANFD1_TR_FIFO01 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD1_TR_FIFO01, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[1].tr_fifo0[1] 600 CYHAL_TRIGGER_CANFD1_TR_FIFO02 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD1_TR_FIFO02, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[1].tr_fifo0[2] 601 CYHAL_TRIGGER_CANFD0_TR_FIFO10 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_FIFO10, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[0].tr_fifo1[0] 602 CYHAL_TRIGGER_CANFD0_TR_FIFO11 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_FIFO11, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[0].tr_fifo1[1] 603 CYHAL_TRIGGER_CANFD0_TR_FIFO12 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_FIFO12, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[0].tr_fifo1[2] 604 CYHAL_TRIGGER_CANFD1_TR_FIFO10 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD1_TR_FIFO10, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[1].tr_fifo1[0] 605 CYHAL_TRIGGER_CANFD1_TR_FIFO11 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD1_TR_FIFO11, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[1].tr_fifo1[1] 606 CYHAL_TRIGGER_CANFD1_TR_FIFO12 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD1_TR_FIFO12, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[1].tr_fifo1[2] 607 CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< canfd[0].tr_tmp_rtp_out[0] 608 CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< canfd[0].tr_tmp_rtp_out[1] 609 CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT2, CYHAL_SIGNAL_TYPE_EDGE), //!< canfd[0].tr_tmp_rtp_out[2] 610 CYHAL_TRIGGER_CANFD1_TR_TMP_RTP_OUT0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD1_TR_TMP_RTP_OUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< canfd[1].tr_tmp_rtp_out[0] 611 CYHAL_TRIGGER_CANFD1_TR_TMP_RTP_OUT1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD1_TR_TMP_RTP_OUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< canfd[1].tr_tmp_rtp_out[1] 612 CYHAL_TRIGGER_CANFD1_TR_TMP_RTP_OUT2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD1_TR_TMP_RTP_OUT2, CYHAL_SIGNAL_TYPE_EDGE), //!< canfd[1].tr_tmp_rtp_out[2] 613 CYHAL_TRIGGER_CPUSS_CTI_TR_OUT0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_CTI_TR_OUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.cti_tr_out[0] 614 CYHAL_TRIGGER_CPUSS_CTI_TR_OUT1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_CTI_TR_OUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.cti_tr_out[1] 615 CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dmac_tr_out[0] 616 CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dmac_tr_out[1] 617 CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT2, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dmac_tr_out[2] 618 CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT3, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dmac_tr_out[3] 619 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[0] 620 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[1] 621 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT2, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[2] 622 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT3, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[3] 623 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT4 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT4, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[4] 624 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT5 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT5, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[5] 625 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT6 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT6, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[6] 626 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT7 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT7, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[7] 627 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT8 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT8, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[8] 628 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT9 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT9, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[9] 629 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT10 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT10, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[10] 630 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT11 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT11, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[11] 631 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT12 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT12, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[12] 632 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT13 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT13, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[13] 633 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT14 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT14, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[14] 634 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT15 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT15, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[15] 635 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT16 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT16, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[16] 636 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT17 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT17, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[17] 637 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT18 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT18, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[18] 638 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT19 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT19, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[19] 639 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT20 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT20, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[20] 640 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT21 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT21, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[21] 641 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT22 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT22, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[22] 642 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT23 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT23, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[23] 643 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT24 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT24, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[24] 644 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT25 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT25, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[25] 645 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT26 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT26, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[26] 646 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT27 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT27, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[27] 647 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT28 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT28, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[28] 648 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT29 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT29, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[29] 649 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT30 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT30, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[30] 650 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT31 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT31, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[31] 651 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT32 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT32, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[32] 652 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT33 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT33, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[33] 653 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT34 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT34, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[34] 654 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT35 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT35, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[35] 655 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT36 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT36, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[36] 656 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT37 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT37, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[37] 657 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT38 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT38, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[38] 658 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT39 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT39, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[39] 659 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT40 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT40, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[40] 660 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT41 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT41, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[41] 661 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT42 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT42, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[42] 662 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT43 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT43, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[43] 663 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT44 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT44, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[44] 664 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT45 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT45, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[45] 665 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT46 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT46, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[46] 666 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT47 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT47, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[47] 667 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT48 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT48, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[48] 668 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT49 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT49, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[49] 669 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT50 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT50, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[50] 670 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT51 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT51, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[51] 671 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT52 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT52, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[52] 672 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT53 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT53, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[53] 673 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT54 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT54, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[54] 674 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT55 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT55, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[55] 675 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT56 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT56, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[56] 676 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT57 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT57, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[57] 677 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT58 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT58, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[58] 678 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT59 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT59, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[59] 679 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT60 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT60, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[60] 680 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT61 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT61, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[61] 681 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT62 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT62, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[62] 682 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT63 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT63, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[63] 683 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT64 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT64, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[64] 684 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT65 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT65, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[65] 685 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT66 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT66, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[66] 686 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT67 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT67, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[67] 687 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT68 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT68, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[68] 688 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT69 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT69, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[69] 689 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT70 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT70, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[70] 690 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT71 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT71, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[71] 691 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT72 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT72, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[72] 692 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT73 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT73, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[73] 693 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT74 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT74, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[74] 694 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT75 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT75, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[75] 695 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT76 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT76, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[76] 696 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT77 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT77, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[77] 697 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT78 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT78, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[78] 698 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT79 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT79, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[79] 699 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT80 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT80, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[80] 700 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT81 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT81, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[81] 701 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT82 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT82, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[82] 702 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT83 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT83, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[83] 703 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT84 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT84, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[84] 704 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT85 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT85, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[85] 705 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT86 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT86, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[86] 706 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT87 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT87, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[87] 707 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT88 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT88, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[88] 708 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[0] 709 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[1] 710 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT2, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[2] 711 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT3, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[3] 712 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT4 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT4, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[4] 713 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT5 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT5, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[5] 714 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT6 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT6, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[6] 715 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT7 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT7, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[7] 716 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT8 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT8, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[8] 717 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT9 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT9, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[9] 718 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT10 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT10, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[10] 719 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT11 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT11, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[11] 720 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT12 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT12, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[12] 721 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT13 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT13, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[13] 722 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT14 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT14, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[14] 723 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT15 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT15, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[15] 724 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT16 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT16, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[16] 725 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT17 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT17, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[17] 726 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT18 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT18, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[18] 727 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT19 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT19, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[19] 728 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT20 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT20, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[20] 729 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT21 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT21, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[21] 730 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT22 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT22, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[22] 731 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT23 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT23, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[23] 732 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT24 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT24, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[24] 733 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT25 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT25, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[25] 734 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT26 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT26, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[26] 735 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT27 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT27, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[27] 736 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT28 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT28, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[28] 737 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT29 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT29, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[29] 738 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT30 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT30, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[30] 739 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT31 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT31, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[31] 740 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT32 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT32, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[32] 741 CYHAL_TRIGGER_CPUSS_TR_FAULT0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_TR_FAULT0, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.tr_fault[0] 742 CYHAL_TRIGGER_CPUSS_TR_FAULT1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_TR_FAULT1, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.tr_fault[1] 743 CYHAL_TRIGGER_CPUSS_TR_FAULT2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_TR_FAULT2, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.tr_fault[2] 744 CYHAL_TRIGGER_CPUSS_TR_FAULT3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_TR_FAULT3, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.tr_fault[3] 745 CYHAL_TRIGGER_EVTGEN0_TR_OUT0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< evtgen[0].tr_out[0] 746 CYHAL_TRIGGER_EVTGEN0_TR_OUT0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT0, CYHAL_SIGNAL_TYPE_LEVEL), //!< evtgen[0].tr_out[0] 747 CYHAL_TRIGGER_EVTGEN0_TR_OUT1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< evtgen[0].tr_out[1] 748 CYHAL_TRIGGER_EVTGEN0_TR_OUT1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT1, CYHAL_SIGNAL_TYPE_LEVEL), //!< evtgen[0].tr_out[1] 749 CYHAL_TRIGGER_EVTGEN0_TR_OUT2_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT2, CYHAL_SIGNAL_TYPE_EDGE), //!< evtgen[0].tr_out[2] 750 CYHAL_TRIGGER_EVTGEN0_TR_OUT2_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT2, CYHAL_SIGNAL_TYPE_LEVEL), //!< evtgen[0].tr_out[2] 751 CYHAL_TRIGGER_EVTGEN0_TR_OUT3_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT3, CYHAL_SIGNAL_TYPE_EDGE), //!< evtgen[0].tr_out[3] 752 CYHAL_TRIGGER_EVTGEN0_TR_OUT3_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT3, CYHAL_SIGNAL_TYPE_LEVEL), //!< evtgen[0].tr_out[3] 753 CYHAL_TRIGGER_EVTGEN0_TR_OUT4_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT4, CYHAL_SIGNAL_TYPE_EDGE), //!< evtgen[0].tr_out[4] 754 CYHAL_TRIGGER_EVTGEN0_TR_OUT4_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT4, CYHAL_SIGNAL_TYPE_LEVEL), //!< evtgen[0].tr_out[4] 755 CYHAL_TRIGGER_EVTGEN0_TR_OUT5_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT5, CYHAL_SIGNAL_TYPE_EDGE), //!< evtgen[0].tr_out[5] 756 CYHAL_TRIGGER_EVTGEN0_TR_OUT5_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT5, CYHAL_SIGNAL_TYPE_LEVEL), //!< evtgen[0].tr_out[5] 757 CYHAL_TRIGGER_EVTGEN0_TR_OUT6_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT6, CYHAL_SIGNAL_TYPE_EDGE), //!< evtgen[0].tr_out[6] 758 CYHAL_TRIGGER_EVTGEN0_TR_OUT6_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT6, CYHAL_SIGNAL_TYPE_LEVEL), //!< evtgen[0].tr_out[6] 759 CYHAL_TRIGGER_EVTGEN0_TR_OUT7_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT7, CYHAL_SIGNAL_TYPE_EDGE), //!< evtgen[0].tr_out[7] 760 CYHAL_TRIGGER_EVTGEN0_TR_OUT7_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT7, CYHAL_SIGNAL_TYPE_LEVEL), //!< evtgen[0].tr_out[7] 761 CYHAL_TRIGGER_EVTGEN0_TR_OUT8_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT8, CYHAL_SIGNAL_TYPE_EDGE), //!< evtgen[0].tr_out[8] 762 CYHAL_TRIGGER_EVTGEN0_TR_OUT8_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT8, CYHAL_SIGNAL_TYPE_LEVEL), //!< evtgen[0].tr_out[8] 763 CYHAL_TRIGGER_EVTGEN0_TR_OUT9_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT9, CYHAL_SIGNAL_TYPE_EDGE), //!< evtgen[0].tr_out[9] 764 CYHAL_TRIGGER_EVTGEN0_TR_OUT9_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT9, CYHAL_SIGNAL_TYPE_LEVEL), //!< evtgen[0].tr_out[9] 765 CYHAL_TRIGGER_EVTGEN0_TR_OUT10_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT10, CYHAL_SIGNAL_TYPE_EDGE), //!< evtgen[0].tr_out[10] 766 CYHAL_TRIGGER_EVTGEN0_TR_OUT10_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT10, CYHAL_SIGNAL_TYPE_LEVEL), //!< evtgen[0].tr_out[10] 767 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE0, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[0] 768 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE0, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[0] 769 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE1, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[1] 770 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE1, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[1] 771 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE2_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE2, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[2] 772 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE2_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE2, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[2] 773 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE3_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE3, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[3] 774 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE3_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE3, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[3] 775 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE4_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE4, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[4] 776 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE4_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE4, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[4] 777 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE5_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE5, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[5] 778 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE5_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE5, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[5] 779 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE6_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE6, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[6] 780 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE6_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE6, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[6] 781 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE7_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE7, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[7] 782 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE7_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE7, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[7] 783 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE8_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE8, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[8] 784 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE8_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE8, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[8] 785 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE9_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE9, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[9] 786 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE9_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE9, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[9] 787 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE10_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE10, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[10] 788 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE10_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE10, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[10] 789 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE11_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE11, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[11] 790 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE11_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE11, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[11] 791 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE12_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE12, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[12] 792 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE12_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE12, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[12] 793 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE13_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE13, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[13] 794 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE13_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE13, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[13] 795 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE14_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE14, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[14] 796 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE14_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE14, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[14] 797 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE15_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE15, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[15] 798 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE15_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE15, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[15] 799 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE16_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE16, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[16] 800 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE16_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE16, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[16] 801 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE17_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE17, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[17] 802 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE17_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE17, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[17] 803 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE18_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE18, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[18] 804 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE18_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE18, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[18] 805 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE19_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE19, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[19] 806 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE19_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE19, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[19] 807 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE20_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE20, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[20] 808 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE20_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE20, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[20] 809 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE21_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE21, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[21] 810 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE21_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE21, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[21] 811 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE22_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE22, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[22] 812 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE22_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE22, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[22] 813 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE23_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE23, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[23] 814 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE23_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE23, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[23] 815 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE32_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE32, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[32] 816 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE32_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE32, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[32] 817 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE33_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE33, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[33] 818 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE33_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE33, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[33] 819 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE34_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE34, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[34] 820 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE34_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE34, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[34] 821 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE35_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE35, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[35] 822 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE35_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE35, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[35] 823 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE36_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE36, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[36] 824 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE36_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE36, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[36] 825 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE37_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE37, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[37] 826 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE37_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE37, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[37] 827 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE38_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE38, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[38] 828 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE38_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE38, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[38] 829 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE39_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE39, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[39] 830 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE39_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE39, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[39] 831 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE40_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE40, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[40] 832 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE40_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE40, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[40] 833 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE41_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE41, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[41] 834 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE41_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE41, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[41] 835 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE42_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE42, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[42] 836 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE42_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE42, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[42] 837 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE43_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE43, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[43] 838 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE43_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE43, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[43] 839 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE44_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE44, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[44] 840 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE44_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE44, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[44] 841 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE45_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE45, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[45] 842 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE45_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE45, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[45] 843 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE46_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE46, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[46] 844 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE46_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE46, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[46] 845 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE47_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE47, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[47] 846 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE47_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE47, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[47] 847 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE48_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE48, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[48] 848 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE48_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE48, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[48] 849 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE49_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE49, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[49] 850 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE49_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE49, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[49] 851 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE50_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE50, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[50] 852 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE50_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE50, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[50] 853 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE51_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE51, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[51] 854 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE51_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE51, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[51] 855 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE52_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE52, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[52] 856 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE52_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE52, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[52] 857 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE53_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE53, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[53] 858 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE53_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE53, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[53] 859 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE54_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE54, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[54] 860 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE54_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE54, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[54] 861 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE55_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE55, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[55] 862 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE55_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE55, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[55] 863 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE56_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE56, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[56] 864 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE56_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE56, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[56] 865 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE57_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE57, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[57] 866 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE57_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE57, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[57] 867 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE58_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE58, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[58] 868 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE58_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE58, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[58] 869 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE59_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE59, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[59] 870 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE59_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE59, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[59] 871 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE60_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE60, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[60] 872 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE60_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE60, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[60] 873 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE61_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE61, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[61] 874 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE61_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE61, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[61] 875 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE62_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE62, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[62] 876 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE62_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE62, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[62] 877 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE63_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE63, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[63] 878 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE63_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE63, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[63] 879 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE64_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE64, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[64] 880 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE64_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE64, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[64] 881 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE65_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE65, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[65] 882 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE65_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE65, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[65] 883 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE66_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE66, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[66] 884 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE66_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE66, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[66] 885 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE67_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE67, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[67] 886 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE67_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE67, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[67] 887 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE68_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE68, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[68] 888 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE68_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE68, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[68] 889 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE69_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE69, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[69] 890 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE69_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE69, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[69] 891 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE70_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE70, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[70] 892 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE70_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE70, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[70] 893 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE71_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE71, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[71] 894 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE71_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE71, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[71] 895 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO0, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[0] 896 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO1, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[1] 897 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO2, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[2] 898 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO3, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[3] 899 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO4 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO4, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[4] 900 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO5 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO5, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[5] 901 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO6 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO6, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[6] 902 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO7 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO7, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[7] 903 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO8 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO8, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[8] 904 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO9 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO9, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[9] 905 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO10 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO10, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[10] 906 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO11 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO11, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[11] 907 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO12 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO12, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[12] 908 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO13 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO13, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[13] 909 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO14 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO14, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[14] 910 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO15 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO15, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[15] 911 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO16 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO16, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[16] 912 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO17 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO17, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[17] 913 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO18 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO18, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[18] 914 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO19 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO19, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[19] 915 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO20 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO20, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[20] 916 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO21 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO21, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[21] 917 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO22 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO22, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[22] 918 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO23 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO23, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[23] 919 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO32 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO32, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[32] 920 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO33 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO33, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[33] 921 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO34 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO34, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[34] 922 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO35 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO35, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[35] 923 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO36 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO36, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[36] 924 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO37 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO37, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[37] 925 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO38 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO38, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[38] 926 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO39 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO39, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[39] 927 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO40 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO40, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[40] 928 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO41 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO41, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[41] 929 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO42 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO42, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[42] 930 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO43 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO43, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[43] 931 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO44 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO44, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[44] 932 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO45 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO45, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[45] 933 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO46 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO46, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[46] 934 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO47 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO47, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[47] 935 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO48 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO48, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[48] 936 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO49 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO49, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[49] 937 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO50 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO50, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[50] 938 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO51 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO51, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[51] 939 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO52 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO52, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[52] 940 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO53 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO53, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[53] 941 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO54 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO54, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[54] 942 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO55 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO55, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[55] 943 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO56 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO56, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[56] 944 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO57 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO57, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[57] 945 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO58 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO58, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[58] 946 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO59 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO59, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[59] 947 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO60 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO60, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[60] 948 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO61 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO61, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[61] 949 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO62 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO62, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[62] 950 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO63 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO63, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[63] 951 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO64 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO64, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[64] 952 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO65 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO65, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[65] 953 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO66 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO66, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[66] 954 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO67 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO67, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[67] 955 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO68 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO68, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[68] 956 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO69 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO69, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[69] 957 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO70 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO70, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[70] 958 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO71 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO71, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[71] 959 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_gen_out[0] 960 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT0, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_gen_out[0] 961 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_gen_out[1] 962 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT1, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_gen_out[1] 963 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT2_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT2, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_gen_out[2] 964 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT2_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT2, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_gen_out[2] 965 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT3_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT3, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_gen_out[3] 966 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT3_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT3, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_gen_out[3] 967 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT4_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT4, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_gen_out[4] 968 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT4_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT4, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_gen_out[4] 969 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT5_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT5, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_gen_out[5] 970 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT5_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT5, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_gen_out[5] 971 CYHAL_TRIGGER_PERI_TR_IO_INPUT0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[0] 972 CYHAL_TRIGGER_PERI_TR_IO_INPUT0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT0, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[0] 973 CYHAL_TRIGGER_PERI_TR_IO_INPUT1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[1] 974 CYHAL_TRIGGER_PERI_TR_IO_INPUT1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT1, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[1] 975 CYHAL_TRIGGER_PERI_TR_IO_INPUT2_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT2, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[2] 976 CYHAL_TRIGGER_PERI_TR_IO_INPUT2_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT2, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[2] 977 CYHAL_TRIGGER_PERI_TR_IO_INPUT3_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT3, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[3] 978 CYHAL_TRIGGER_PERI_TR_IO_INPUT3_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT3, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[3] 979 CYHAL_TRIGGER_PERI_TR_IO_INPUT4_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT4, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[4] 980 CYHAL_TRIGGER_PERI_TR_IO_INPUT4_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT4, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[4] 981 CYHAL_TRIGGER_PERI_TR_IO_INPUT5_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT5, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[5] 982 CYHAL_TRIGGER_PERI_TR_IO_INPUT5_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT5, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[5] 983 CYHAL_TRIGGER_PERI_TR_IO_INPUT6_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT6, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[6] 984 CYHAL_TRIGGER_PERI_TR_IO_INPUT6_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT6, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[6] 985 CYHAL_TRIGGER_PERI_TR_IO_INPUT7_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT7, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[7] 986 CYHAL_TRIGGER_PERI_TR_IO_INPUT7_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT7, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[7] 987 CYHAL_TRIGGER_PERI_TR_IO_INPUT8_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT8, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[8] 988 CYHAL_TRIGGER_PERI_TR_IO_INPUT8_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT8, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[8] 989 CYHAL_TRIGGER_PERI_TR_IO_INPUT9_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT9, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[9] 990 CYHAL_TRIGGER_PERI_TR_IO_INPUT9_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT9, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[9] 991 CYHAL_TRIGGER_PERI_TR_IO_INPUT10_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT10, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[10] 992 CYHAL_TRIGGER_PERI_TR_IO_INPUT10_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT10, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[10] 993 CYHAL_TRIGGER_PERI_TR_IO_INPUT11_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT11, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[11] 994 CYHAL_TRIGGER_PERI_TR_IO_INPUT11_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT11, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[11] 995 CYHAL_TRIGGER_PERI_TR_IO_INPUT12_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT12, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[12] 996 CYHAL_TRIGGER_PERI_TR_IO_INPUT12_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT12, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[12] 997 CYHAL_TRIGGER_PERI_TR_IO_INPUT13_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT13, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[13] 998 CYHAL_TRIGGER_PERI_TR_IO_INPUT13_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT13, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[13] 999 CYHAL_TRIGGER_PERI_TR_IO_INPUT14_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT14, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[14] 1000 CYHAL_TRIGGER_PERI_TR_IO_INPUT14_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT14, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[14] 1001 CYHAL_TRIGGER_PERI_TR_IO_INPUT15_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT15, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[15] 1002 CYHAL_TRIGGER_PERI_TR_IO_INPUT15_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT15, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[15] 1003 CYHAL_TRIGGER_PERI_TR_IO_INPUT16_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT16, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[16] 1004 CYHAL_TRIGGER_PERI_TR_IO_INPUT16_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT16, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[16] 1005 CYHAL_TRIGGER_PERI_TR_IO_INPUT17_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT17, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[17] 1006 CYHAL_TRIGGER_PERI_TR_IO_INPUT17_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT17, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[17] 1007 CYHAL_TRIGGER_PERI_TR_IO_INPUT18_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT18, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[18] 1008 CYHAL_TRIGGER_PERI_TR_IO_INPUT18_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT18, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[18] 1009 CYHAL_TRIGGER_PERI_TR_IO_INPUT19_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT19, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[19] 1010 CYHAL_TRIGGER_PERI_TR_IO_INPUT19_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT19, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[19] 1011 CYHAL_TRIGGER_PERI_TR_IO_INPUT20_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT20, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[20] 1012 CYHAL_TRIGGER_PERI_TR_IO_INPUT20_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT20, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[20] 1013 CYHAL_TRIGGER_PERI_TR_IO_INPUT21_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT21, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[21] 1014 CYHAL_TRIGGER_PERI_TR_IO_INPUT21_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT21, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[21] 1015 CYHAL_TRIGGER_PERI_TR_IO_INPUT22_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT22, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[22] 1016 CYHAL_TRIGGER_PERI_TR_IO_INPUT22_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT22, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[22] 1017 CYHAL_TRIGGER_PERI_TR_IO_INPUT23_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT23, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[23] 1018 CYHAL_TRIGGER_PERI_TR_IO_INPUT23_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT23, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[23] 1019 CYHAL_TRIGGER_PERI_TR_IO_INPUT24_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT24, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[24] 1020 CYHAL_TRIGGER_PERI_TR_IO_INPUT24_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT24, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[24] 1021 CYHAL_TRIGGER_PERI_TR_IO_INPUT25_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT25, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[25] 1022 CYHAL_TRIGGER_PERI_TR_IO_INPUT25_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT25, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[25] 1023 CYHAL_TRIGGER_PERI_TR_IO_INPUT26_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT26, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[26] 1024 CYHAL_TRIGGER_PERI_TR_IO_INPUT26_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT26, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[26] 1025 CYHAL_TRIGGER_PERI_TR_IO_INPUT27_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT27, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[27] 1026 CYHAL_TRIGGER_PERI_TR_IO_INPUT27_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT27, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[27] 1027 CYHAL_TRIGGER_PERI_TR_IO_INPUT28_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT28, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[28] 1028 CYHAL_TRIGGER_PERI_TR_IO_INPUT28_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT28, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[28] 1029 CYHAL_TRIGGER_PERI_TR_IO_INPUT29_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT29, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[29] 1030 CYHAL_TRIGGER_PERI_TR_IO_INPUT29_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT29, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[29] 1031 CYHAL_TRIGGER_PERI_TR_IO_INPUT30_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT30, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[30] 1032 CYHAL_TRIGGER_PERI_TR_IO_INPUT30_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT30, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[30] 1033 CYHAL_TRIGGER_PERI_TR_IO_INPUT31_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT31, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[31] 1034 CYHAL_TRIGGER_PERI_TR_IO_INPUT31_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT31, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[31] 1035 CYHAL_TRIGGER_SCB0_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB0_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[0].tr_i2c_scl_filtered 1036 CYHAL_TRIGGER_SCB1_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB1_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[1].tr_i2c_scl_filtered 1037 CYHAL_TRIGGER_SCB2_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB2_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[2].tr_i2c_scl_filtered 1038 CYHAL_TRIGGER_SCB3_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB3_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[3].tr_i2c_scl_filtered 1039 CYHAL_TRIGGER_SCB4_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB4_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[4].tr_i2c_scl_filtered 1040 CYHAL_TRIGGER_SCB5_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB5_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[5].tr_i2c_scl_filtered 1041 CYHAL_TRIGGER_SCB6_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB6_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[6].tr_i2c_scl_filtered 1042 CYHAL_TRIGGER_SCB7_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB7_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[7].tr_i2c_scl_filtered 1043 CYHAL_TRIGGER_SCB0_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB0_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[0].tr_rx_req 1044 CYHAL_TRIGGER_SCB1_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB1_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[1].tr_rx_req 1045 CYHAL_TRIGGER_SCB2_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB2_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[2].tr_rx_req 1046 CYHAL_TRIGGER_SCB3_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB3_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[3].tr_rx_req 1047 CYHAL_TRIGGER_SCB4_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB4_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[4].tr_rx_req 1048 CYHAL_TRIGGER_SCB5_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB5_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[5].tr_rx_req 1049 CYHAL_TRIGGER_SCB6_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB6_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[6].tr_rx_req 1050 CYHAL_TRIGGER_SCB7_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB7_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[7].tr_rx_req 1051 CYHAL_TRIGGER_SCB0_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB0_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[0].tr_tx_req 1052 CYHAL_TRIGGER_SCB1_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB1_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[1].tr_tx_req 1053 CYHAL_TRIGGER_SCB2_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB2_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[2].tr_tx_req 1054 CYHAL_TRIGGER_SCB3_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB3_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[3].tr_tx_req 1055 CYHAL_TRIGGER_SCB4_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB4_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[4].tr_tx_req 1056 CYHAL_TRIGGER_SCB5_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB5_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[5].tr_tx_req 1057 CYHAL_TRIGGER_SCB6_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB6_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[6].tr_tx_req 1058 CYHAL_TRIGGER_SCB7_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB7_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[7].tr_tx_req 1059 CYHAL_TRIGGER_TCPWM0_TR_OUT00_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT00, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[0] 1060 CYHAL_TRIGGER_TCPWM0_TR_OUT00_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT00, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[0] 1061 CYHAL_TRIGGER_TCPWM0_TR_OUT01_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT01, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[1] 1062 CYHAL_TRIGGER_TCPWM0_TR_OUT01_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT01, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[1] 1063 CYHAL_TRIGGER_TCPWM0_TR_OUT02_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT02, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[2] 1064 CYHAL_TRIGGER_TCPWM0_TR_OUT02_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT02, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[2] 1065 CYHAL_TRIGGER_TCPWM0_TR_OUT03_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT03, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[3] 1066 CYHAL_TRIGGER_TCPWM0_TR_OUT03_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT03, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[3] 1067 CYHAL_TRIGGER_TCPWM0_TR_OUT04_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT04, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[4] 1068 CYHAL_TRIGGER_TCPWM0_TR_OUT04_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT04, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[4] 1069 CYHAL_TRIGGER_TCPWM0_TR_OUT05_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT05, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[5] 1070 CYHAL_TRIGGER_TCPWM0_TR_OUT05_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT05, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[5] 1071 CYHAL_TRIGGER_TCPWM0_TR_OUT06_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT06, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[6] 1072 CYHAL_TRIGGER_TCPWM0_TR_OUT06_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT06, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[6] 1073 CYHAL_TRIGGER_TCPWM0_TR_OUT07_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT07, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[7] 1074 CYHAL_TRIGGER_TCPWM0_TR_OUT07_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT07, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[7] 1075 CYHAL_TRIGGER_TCPWM0_TR_OUT08_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT08, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[8] 1076 CYHAL_TRIGGER_TCPWM0_TR_OUT08_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT08, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[8] 1077 CYHAL_TRIGGER_TCPWM0_TR_OUT09_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT09, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[9] 1078 CYHAL_TRIGGER_TCPWM0_TR_OUT09_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT09, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[9] 1079 CYHAL_TRIGGER_TCPWM0_TR_OUT010_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT010, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[10] 1080 CYHAL_TRIGGER_TCPWM0_TR_OUT010_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT010, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[10] 1081 CYHAL_TRIGGER_TCPWM0_TR_OUT011_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT011, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[11] 1082 CYHAL_TRIGGER_TCPWM0_TR_OUT011_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT011, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[11] 1083 CYHAL_TRIGGER_TCPWM0_TR_OUT012_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT012, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[12] 1084 CYHAL_TRIGGER_TCPWM0_TR_OUT012_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT012, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[12] 1085 CYHAL_TRIGGER_TCPWM0_TR_OUT013_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT013, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[13] 1086 CYHAL_TRIGGER_TCPWM0_TR_OUT013_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT013, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[13] 1087 CYHAL_TRIGGER_TCPWM0_TR_OUT014_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT014, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[14] 1088 CYHAL_TRIGGER_TCPWM0_TR_OUT014_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT014, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[14] 1089 CYHAL_TRIGGER_TCPWM0_TR_OUT015_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT015, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[15] 1090 CYHAL_TRIGGER_TCPWM0_TR_OUT015_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT015, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[15] 1091 CYHAL_TRIGGER_TCPWM0_TR_OUT016_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT016, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[16] 1092 CYHAL_TRIGGER_TCPWM0_TR_OUT016_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT016, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[16] 1093 CYHAL_TRIGGER_TCPWM0_TR_OUT017_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT017, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[17] 1094 CYHAL_TRIGGER_TCPWM0_TR_OUT017_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT017, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[17] 1095 CYHAL_TRIGGER_TCPWM0_TR_OUT018_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT018, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[18] 1096 CYHAL_TRIGGER_TCPWM0_TR_OUT018_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT018, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[18] 1097 CYHAL_TRIGGER_TCPWM0_TR_OUT019_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT019, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[19] 1098 CYHAL_TRIGGER_TCPWM0_TR_OUT019_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT019, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[19] 1099 CYHAL_TRIGGER_TCPWM0_TR_OUT020_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT020, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[20] 1100 CYHAL_TRIGGER_TCPWM0_TR_OUT020_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT020, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[20] 1101 CYHAL_TRIGGER_TCPWM0_TR_OUT021_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT021, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[21] 1102 CYHAL_TRIGGER_TCPWM0_TR_OUT021_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT021, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[21] 1103 CYHAL_TRIGGER_TCPWM0_TR_OUT022_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT022, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[22] 1104 CYHAL_TRIGGER_TCPWM0_TR_OUT022_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT022, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[22] 1105 CYHAL_TRIGGER_TCPWM0_TR_OUT023_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT023, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[23] 1106 CYHAL_TRIGGER_TCPWM0_TR_OUT023_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT023, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[23] 1107 CYHAL_TRIGGER_TCPWM0_TR_OUT024_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT024, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[24] 1108 CYHAL_TRIGGER_TCPWM0_TR_OUT024_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT024, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[24] 1109 CYHAL_TRIGGER_TCPWM0_TR_OUT025_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT025, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[25] 1110 CYHAL_TRIGGER_TCPWM0_TR_OUT025_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT025, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[25] 1111 CYHAL_TRIGGER_TCPWM0_TR_OUT026_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT026, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[26] 1112 CYHAL_TRIGGER_TCPWM0_TR_OUT026_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT026, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[26] 1113 CYHAL_TRIGGER_TCPWM0_TR_OUT027_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT027, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[27] 1114 CYHAL_TRIGGER_TCPWM0_TR_OUT027_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT027, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[27] 1115 CYHAL_TRIGGER_TCPWM0_TR_OUT028_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT028, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[28] 1116 CYHAL_TRIGGER_TCPWM0_TR_OUT028_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT028, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[28] 1117 CYHAL_TRIGGER_TCPWM0_TR_OUT029_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT029, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[29] 1118 CYHAL_TRIGGER_TCPWM0_TR_OUT029_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT029, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[29] 1119 CYHAL_TRIGGER_TCPWM0_TR_OUT030_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT030, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[30] 1120 CYHAL_TRIGGER_TCPWM0_TR_OUT030_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT030, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[30] 1121 CYHAL_TRIGGER_TCPWM0_TR_OUT031_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT031, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[31] 1122 CYHAL_TRIGGER_TCPWM0_TR_OUT031_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT031, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[31] 1123 CYHAL_TRIGGER_TCPWM0_TR_OUT032_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT032, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[32] 1124 CYHAL_TRIGGER_TCPWM0_TR_OUT032_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT032, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[32] 1125 CYHAL_TRIGGER_TCPWM0_TR_OUT033_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT033, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[33] 1126 CYHAL_TRIGGER_TCPWM0_TR_OUT033_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT033, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[33] 1127 CYHAL_TRIGGER_TCPWM0_TR_OUT034_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT034, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[34] 1128 CYHAL_TRIGGER_TCPWM0_TR_OUT034_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT034, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[34] 1129 CYHAL_TRIGGER_TCPWM0_TR_OUT035_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT035, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[35] 1130 CYHAL_TRIGGER_TCPWM0_TR_OUT035_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT035, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[35] 1131 CYHAL_TRIGGER_TCPWM0_TR_OUT036_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT036, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[36] 1132 CYHAL_TRIGGER_TCPWM0_TR_OUT036_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT036, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[36] 1133 CYHAL_TRIGGER_TCPWM0_TR_OUT037_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT037, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[37] 1134 CYHAL_TRIGGER_TCPWM0_TR_OUT037_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT037, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[37] 1135 CYHAL_TRIGGER_TCPWM0_TR_OUT038_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT038, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[38] 1136 CYHAL_TRIGGER_TCPWM0_TR_OUT038_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT038, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[38] 1137 CYHAL_TRIGGER_TCPWM0_TR_OUT039_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT039, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[39] 1138 CYHAL_TRIGGER_TCPWM0_TR_OUT039_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT039, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[39] 1139 CYHAL_TRIGGER_TCPWM0_TR_OUT040_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT040, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[40] 1140 CYHAL_TRIGGER_TCPWM0_TR_OUT040_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT040, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[40] 1141 CYHAL_TRIGGER_TCPWM0_TR_OUT041_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT041, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[41] 1142 CYHAL_TRIGGER_TCPWM0_TR_OUT041_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT041, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[41] 1143 CYHAL_TRIGGER_TCPWM0_TR_OUT042_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT042, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[42] 1144 CYHAL_TRIGGER_TCPWM0_TR_OUT042_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT042, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[42] 1145 CYHAL_TRIGGER_TCPWM0_TR_OUT043_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT043, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[43] 1146 CYHAL_TRIGGER_TCPWM0_TR_OUT043_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT043, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[43] 1147 CYHAL_TRIGGER_TCPWM0_TR_OUT044_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT044, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[44] 1148 CYHAL_TRIGGER_TCPWM0_TR_OUT044_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT044, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[44] 1149 CYHAL_TRIGGER_TCPWM0_TR_OUT045_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT045, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[45] 1150 CYHAL_TRIGGER_TCPWM0_TR_OUT045_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT045, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[45] 1151 CYHAL_TRIGGER_TCPWM0_TR_OUT046_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT046, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[46] 1152 CYHAL_TRIGGER_TCPWM0_TR_OUT046_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT046, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[46] 1153 CYHAL_TRIGGER_TCPWM0_TR_OUT047_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT047, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[47] 1154 CYHAL_TRIGGER_TCPWM0_TR_OUT047_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT047, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[47] 1155 CYHAL_TRIGGER_TCPWM0_TR_OUT048_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT048, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[48] 1156 CYHAL_TRIGGER_TCPWM0_TR_OUT048_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT048, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[48] 1157 CYHAL_TRIGGER_TCPWM0_TR_OUT049_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT049, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[49] 1158 CYHAL_TRIGGER_TCPWM0_TR_OUT049_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT049, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[49] 1159 CYHAL_TRIGGER_TCPWM0_TR_OUT050_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT050, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[50] 1160 CYHAL_TRIGGER_TCPWM0_TR_OUT050_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT050, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[50] 1161 CYHAL_TRIGGER_TCPWM0_TR_OUT051_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT051, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[51] 1162 CYHAL_TRIGGER_TCPWM0_TR_OUT051_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT051, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[51] 1163 CYHAL_TRIGGER_TCPWM0_TR_OUT052_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT052, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[52] 1164 CYHAL_TRIGGER_TCPWM0_TR_OUT052_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT052, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[52] 1165 CYHAL_TRIGGER_TCPWM0_TR_OUT053_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT053, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[53] 1166 CYHAL_TRIGGER_TCPWM0_TR_OUT053_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT053, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[53] 1167 CYHAL_TRIGGER_TCPWM0_TR_OUT054_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT054, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[54] 1168 CYHAL_TRIGGER_TCPWM0_TR_OUT054_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT054, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[54] 1169 CYHAL_TRIGGER_TCPWM0_TR_OUT055_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT055, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[55] 1170 CYHAL_TRIGGER_TCPWM0_TR_OUT055_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT055, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[55] 1171 CYHAL_TRIGGER_TCPWM0_TR_OUT056_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT056, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[56] 1172 CYHAL_TRIGGER_TCPWM0_TR_OUT056_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT056, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[56] 1173 CYHAL_TRIGGER_TCPWM0_TR_OUT057_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT057, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[57] 1174 CYHAL_TRIGGER_TCPWM0_TR_OUT057_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT057, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[57] 1175 CYHAL_TRIGGER_TCPWM0_TR_OUT058_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT058, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[58] 1176 CYHAL_TRIGGER_TCPWM0_TR_OUT058_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT058, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[58] 1177 CYHAL_TRIGGER_TCPWM0_TR_OUT059_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT059, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[59] 1178 CYHAL_TRIGGER_TCPWM0_TR_OUT059_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT059, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[59] 1179 CYHAL_TRIGGER_TCPWM0_TR_OUT060_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT060, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[60] 1180 CYHAL_TRIGGER_TCPWM0_TR_OUT060_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT060, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[60] 1181 CYHAL_TRIGGER_TCPWM0_TR_OUT061_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT061, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[61] 1182 CYHAL_TRIGGER_TCPWM0_TR_OUT061_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT061, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[61] 1183 CYHAL_TRIGGER_TCPWM0_TR_OUT062_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT062, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[62] 1184 CYHAL_TRIGGER_TCPWM0_TR_OUT062_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT062, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[62] 1185 CYHAL_TRIGGER_TCPWM0_TR_OUT0256_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0256, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[256] 1186 CYHAL_TRIGGER_TCPWM0_TR_OUT0256_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0256, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[256] 1187 CYHAL_TRIGGER_TCPWM0_TR_OUT0257_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0257, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[257] 1188 CYHAL_TRIGGER_TCPWM0_TR_OUT0257_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0257, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[257] 1189 CYHAL_TRIGGER_TCPWM0_TR_OUT0258_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0258, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[258] 1190 CYHAL_TRIGGER_TCPWM0_TR_OUT0258_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0258, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[258] 1191 CYHAL_TRIGGER_TCPWM0_TR_OUT0259_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0259, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[259] 1192 CYHAL_TRIGGER_TCPWM0_TR_OUT0259_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0259, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[259] 1193 CYHAL_TRIGGER_TCPWM0_TR_OUT0260_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0260, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[260] 1194 CYHAL_TRIGGER_TCPWM0_TR_OUT0260_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0260, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[260] 1195 CYHAL_TRIGGER_TCPWM0_TR_OUT0261_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0261, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[261] 1196 CYHAL_TRIGGER_TCPWM0_TR_OUT0261_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0261, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[261] 1197 CYHAL_TRIGGER_TCPWM0_TR_OUT0262_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0262, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[262] 1198 CYHAL_TRIGGER_TCPWM0_TR_OUT0262_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0262, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[262] 1199 CYHAL_TRIGGER_TCPWM0_TR_OUT0263_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0263, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[263] 1200 CYHAL_TRIGGER_TCPWM0_TR_OUT0263_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0263, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[263] 1201 CYHAL_TRIGGER_TCPWM0_TR_OUT0264_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0264, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[264] 1202 CYHAL_TRIGGER_TCPWM0_TR_OUT0264_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0264, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[264] 1203 CYHAL_TRIGGER_TCPWM0_TR_OUT0265_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0265, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[265] 1204 CYHAL_TRIGGER_TCPWM0_TR_OUT0265_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0265, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[265] 1205 CYHAL_TRIGGER_TCPWM0_TR_OUT0266_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0266, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[266] 1206 CYHAL_TRIGGER_TCPWM0_TR_OUT0266_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0266, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[266] 1207 CYHAL_TRIGGER_TCPWM0_TR_OUT0267_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0267, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[267] 1208 CYHAL_TRIGGER_TCPWM0_TR_OUT0267_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0267, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[267] 1209 CYHAL_TRIGGER_TCPWM0_TR_OUT0512_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0512, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[512] 1210 CYHAL_TRIGGER_TCPWM0_TR_OUT0512_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0512, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[512] 1211 CYHAL_TRIGGER_TCPWM0_TR_OUT0513_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0513, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[513] 1212 CYHAL_TRIGGER_TCPWM0_TR_OUT0513_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0513, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[513] 1213 CYHAL_TRIGGER_TCPWM0_TR_OUT0514_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0514, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[514] 1214 CYHAL_TRIGGER_TCPWM0_TR_OUT0514_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0514, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[514] 1215 CYHAL_TRIGGER_TCPWM0_TR_OUT0515_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0515, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[515] 1216 CYHAL_TRIGGER_TCPWM0_TR_OUT0515_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0515, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[515] 1217 CYHAL_TRIGGER_TCPWM0_TR_OUT10_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT10, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[0] 1218 CYHAL_TRIGGER_TCPWM0_TR_OUT10_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT10, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[0] 1219 CYHAL_TRIGGER_TCPWM0_TR_OUT11_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT11, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[1] 1220 CYHAL_TRIGGER_TCPWM0_TR_OUT11_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT11, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[1] 1221 CYHAL_TRIGGER_TCPWM0_TR_OUT12_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT12, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[2] 1222 CYHAL_TRIGGER_TCPWM0_TR_OUT12_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT12, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[2] 1223 CYHAL_TRIGGER_TCPWM0_TR_OUT13_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT13, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[3] 1224 CYHAL_TRIGGER_TCPWM0_TR_OUT13_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT13, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[3] 1225 CYHAL_TRIGGER_TCPWM0_TR_OUT14_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT14, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[4] 1226 CYHAL_TRIGGER_TCPWM0_TR_OUT14_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT14, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[4] 1227 CYHAL_TRIGGER_TCPWM0_TR_OUT15_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT15, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[5] 1228 CYHAL_TRIGGER_TCPWM0_TR_OUT15_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT15, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[5] 1229 CYHAL_TRIGGER_TCPWM0_TR_OUT16_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT16, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[6] 1230 CYHAL_TRIGGER_TCPWM0_TR_OUT16_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT16, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[6] 1231 CYHAL_TRIGGER_TCPWM0_TR_OUT17_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT17, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[7] 1232 CYHAL_TRIGGER_TCPWM0_TR_OUT17_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT17, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[7] 1233 CYHAL_TRIGGER_TCPWM0_TR_OUT18_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT18, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[8] 1234 CYHAL_TRIGGER_TCPWM0_TR_OUT18_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT18, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[8] 1235 CYHAL_TRIGGER_TCPWM0_TR_OUT19_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT19, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[9] 1236 CYHAL_TRIGGER_TCPWM0_TR_OUT19_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT19, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[9] 1237 CYHAL_TRIGGER_TCPWM0_TR_OUT110_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT110, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[10] 1238 CYHAL_TRIGGER_TCPWM0_TR_OUT110_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT110, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[10] 1239 CYHAL_TRIGGER_TCPWM0_TR_OUT111_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT111, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[11] 1240 CYHAL_TRIGGER_TCPWM0_TR_OUT111_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT111, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[11] 1241 CYHAL_TRIGGER_TCPWM0_TR_OUT112_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT112, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[12] 1242 CYHAL_TRIGGER_TCPWM0_TR_OUT112_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT112, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[12] 1243 CYHAL_TRIGGER_TCPWM0_TR_OUT113_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT113, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[13] 1244 CYHAL_TRIGGER_TCPWM0_TR_OUT113_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT113, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[13] 1245 CYHAL_TRIGGER_TCPWM0_TR_OUT114_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT114, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[14] 1246 CYHAL_TRIGGER_TCPWM0_TR_OUT114_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT114, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[14] 1247 CYHAL_TRIGGER_TCPWM0_TR_OUT115_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT115, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[15] 1248 CYHAL_TRIGGER_TCPWM0_TR_OUT115_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT115, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[15] 1249 CYHAL_TRIGGER_TCPWM0_TR_OUT116_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT116, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[16] 1250 CYHAL_TRIGGER_TCPWM0_TR_OUT116_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT116, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[16] 1251 CYHAL_TRIGGER_TCPWM0_TR_OUT117_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT117, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[17] 1252 CYHAL_TRIGGER_TCPWM0_TR_OUT117_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT117, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[17] 1253 CYHAL_TRIGGER_TCPWM0_TR_OUT118_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT118, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[18] 1254 CYHAL_TRIGGER_TCPWM0_TR_OUT118_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT118, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[18] 1255 CYHAL_TRIGGER_TCPWM0_TR_OUT119_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT119, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[19] 1256 CYHAL_TRIGGER_TCPWM0_TR_OUT119_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT119, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[19] 1257 CYHAL_TRIGGER_TCPWM0_TR_OUT120_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT120, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[20] 1258 CYHAL_TRIGGER_TCPWM0_TR_OUT120_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT120, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[20] 1259 CYHAL_TRIGGER_TCPWM0_TR_OUT121_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT121, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[21] 1260 CYHAL_TRIGGER_TCPWM0_TR_OUT121_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT121, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[21] 1261 CYHAL_TRIGGER_TCPWM0_TR_OUT122_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT122, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[22] 1262 CYHAL_TRIGGER_TCPWM0_TR_OUT122_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT122, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[22] 1263 CYHAL_TRIGGER_TCPWM0_TR_OUT123_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT123, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[23] 1264 CYHAL_TRIGGER_TCPWM0_TR_OUT123_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT123, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[23] 1265 CYHAL_TRIGGER_TCPWM0_TR_OUT124_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT124, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[24] 1266 CYHAL_TRIGGER_TCPWM0_TR_OUT124_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT124, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[24] 1267 CYHAL_TRIGGER_TCPWM0_TR_OUT125_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT125, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[25] 1268 CYHAL_TRIGGER_TCPWM0_TR_OUT125_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT125, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[25] 1269 CYHAL_TRIGGER_TCPWM0_TR_OUT126_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT126, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[26] 1270 CYHAL_TRIGGER_TCPWM0_TR_OUT126_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT126, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[26] 1271 CYHAL_TRIGGER_TCPWM0_TR_OUT127_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT127, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[27] 1272 CYHAL_TRIGGER_TCPWM0_TR_OUT127_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT127, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[27] 1273 CYHAL_TRIGGER_TCPWM0_TR_OUT128_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT128, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[28] 1274 CYHAL_TRIGGER_TCPWM0_TR_OUT128_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT128, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[28] 1275 CYHAL_TRIGGER_TCPWM0_TR_OUT129_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT129, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[29] 1276 CYHAL_TRIGGER_TCPWM0_TR_OUT129_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT129, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[29] 1277 CYHAL_TRIGGER_TCPWM0_TR_OUT130_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT130, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[30] 1278 CYHAL_TRIGGER_TCPWM0_TR_OUT130_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT130, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[30] 1279 CYHAL_TRIGGER_TCPWM0_TR_OUT131_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT131, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[31] 1280 CYHAL_TRIGGER_TCPWM0_TR_OUT131_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT131, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[31] 1281 CYHAL_TRIGGER_TCPWM0_TR_OUT132_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT132, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[32] 1282 CYHAL_TRIGGER_TCPWM0_TR_OUT132_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT132, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[32] 1283 CYHAL_TRIGGER_TCPWM0_TR_OUT133_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT133, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[33] 1284 CYHAL_TRIGGER_TCPWM0_TR_OUT133_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT133, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[33] 1285 CYHAL_TRIGGER_TCPWM0_TR_OUT134_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT134, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[34] 1286 CYHAL_TRIGGER_TCPWM0_TR_OUT134_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT134, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[34] 1287 CYHAL_TRIGGER_TCPWM0_TR_OUT135_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT135, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[35] 1288 CYHAL_TRIGGER_TCPWM0_TR_OUT135_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT135, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[35] 1289 CYHAL_TRIGGER_TCPWM0_TR_OUT136_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT136, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[36] 1290 CYHAL_TRIGGER_TCPWM0_TR_OUT136_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT136, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[36] 1291 CYHAL_TRIGGER_TCPWM0_TR_OUT137_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT137, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[37] 1292 CYHAL_TRIGGER_TCPWM0_TR_OUT137_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT137, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[37] 1293 CYHAL_TRIGGER_TCPWM0_TR_OUT138_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT138, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[38] 1294 CYHAL_TRIGGER_TCPWM0_TR_OUT138_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT138, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[38] 1295 CYHAL_TRIGGER_TCPWM0_TR_OUT139_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT139, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[39] 1296 CYHAL_TRIGGER_TCPWM0_TR_OUT139_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT139, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[39] 1297 CYHAL_TRIGGER_TCPWM0_TR_OUT140_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT140, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[40] 1298 CYHAL_TRIGGER_TCPWM0_TR_OUT140_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT140, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[40] 1299 CYHAL_TRIGGER_TCPWM0_TR_OUT141_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT141, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[41] 1300 CYHAL_TRIGGER_TCPWM0_TR_OUT141_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT141, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[41] 1301 CYHAL_TRIGGER_TCPWM0_TR_OUT142_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT142, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[42] 1302 CYHAL_TRIGGER_TCPWM0_TR_OUT142_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT142, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[42] 1303 CYHAL_TRIGGER_TCPWM0_TR_OUT143_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT143, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[43] 1304 CYHAL_TRIGGER_TCPWM0_TR_OUT143_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT143, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[43] 1305 CYHAL_TRIGGER_TCPWM0_TR_OUT144_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT144, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[44] 1306 CYHAL_TRIGGER_TCPWM0_TR_OUT144_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT144, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[44] 1307 CYHAL_TRIGGER_TCPWM0_TR_OUT145_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT145, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[45] 1308 CYHAL_TRIGGER_TCPWM0_TR_OUT145_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT145, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[45] 1309 CYHAL_TRIGGER_TCPWM0_TR_OUT146_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT146, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[46] 1310 CYHAL_TRIGGER_TCPWM0_TR_OUT146_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT146, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[46] 1311 CYHAL_TRIGGER_TCPWM0_TR_OUT147_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT147, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[47] 1312 CYHAL_TRIGGER_TCPWM0_TR_OUT147_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT147, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[47] 1313 CYHAL_TRIGGER_TCPWM0_TR_OUT148_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT148, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[48] 1314 CYHAL_TRIGGER_TCPWM0_TR_OUT148_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT148, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[48] 1315 CYHAL_TRIGGER_TCPWM0_TR_OUT149_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT149, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[49] 1316 CYHAL_TRIGGER_TCPWM0_TR_OUT149_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT149, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[49] 1317 CYHAL_TRIGGER_TCPWM0_TR_OUT150_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT150, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[50] 1318 CYHAL_TRIGGER_TCPWM0_TR_OUT150_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT150, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[50] 1319 CYHAL_TRIGGER_TCPWM0_TR_OUT151_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT151, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[51] 1320 CYHAL_TRIGGER_TCPWM0_TR_OUT151_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT151, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[51] 1321 CYHAL_TRIGGER_TCPWM0_TR_OUT152_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT152, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[52] 1322 CYHAL_TRIGGER_TCPWM0_TR_OUT152_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT152, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[52] 1323 CYHAL_TRIGGER_TCPWM0_TR_OUT153_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT153, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[53] 1324 CYHAL_TRIGGER_TCPWM0_TR_OUT153_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT153, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[53] 1325 CYHAL_TRIGGER_TCPWM0_TR_OUT154_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT154, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[54] 1326 CYHAL_TRIGGER_TCPWM0_TR_OUT154_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT154, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[54] 1327 CYHAL_TRIGGER_TCPWM0_TR_OUT155_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT155, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[55] 1328 CYHAL_TRIGGER_TCPWM0_TR_OUT155_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT155, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[55] 1329 CYHAL_TRIGGER_TCPWM0_TR_OUT156_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT156, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[56] 1330 CYHAL_TRIGGER_TCPWM0_TR_OUT156_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT156, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[56] 1331 CYHAL_TRIGGER_TCPWM0_TR_OUT157_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT157, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[57] 1332 CYHAL_TRIGGER_TCPWM0_TR_OUT157_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT157, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[57] 1333 CYHAL_TRIGGER_TCPWM0_TR_OUT158_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT158, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[58] 1334 CYHAL_TRIGGER_TCPWM0_TR_OUT158_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT158, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[58] 1335 CYHAL_TRIGGER_TCPWM0_TR_OUT159_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT159, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[59] 1336 CYHAL_TRIGGER_TCPWM0_TR_OUT159_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT159, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[59] 1337 CYHAL_TRIGGER_TCPWM0_TR_OUT160_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT160, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[60] 1338 CYHAL_TRIGGER_TCPWM0_TR_OUT160_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT160, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[60] 1339 CYHAL_TRIGGER_TCPWM0_TR_OUT161_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT161, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[61] 1340 CYHAL_TRIGGER_TCPWM0_TR_OUT161_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT161, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[61] 1341 CYHAL_TRIGGER_TCPWM0_TR_OUT162_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT162, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[62] 1342 CYHAL_TRIGGER_TCPWM0_TR_OUT162_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT162, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[62] 1343 CYHAL_TRIGGER_TCPWM0_TR_OUT1256_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1256, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[256] 1344 CYHAL_TRIGGER_TCPWM0_TR_OUT1256_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1256, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[256] 1345 CYHAL_TRIGGER_TCPWM0_TR_OUT1257_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1257, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[257] 1346 CYHAL_TRIGGER_TCPWM0_TR_OUT1257_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1257, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[257] 1347 CYHAL_TRIGGER_TCPWM0_TR_OUT1258_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1258, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[258] 1348 CYHAL_TRIGGER_TCPWM0_TR_OUT1258_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1258, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[258] 1349 CYHAL_TRIGGER_TCPWM0_TR_OUT1259_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1259, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[259] 1350 CYHAL_TRIGGER_TCPWM0_TR_OUT1259_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1259, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[259] 1351 CYHAL_TRIGGER_TCPWM0_TR_OUT1260_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1260, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[260] 1352 CYHAL_TRIGGER_TCPWM0_TR_OUT1260_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1260, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[260] 1353 CYHAL_TRIGGER_TCPWM0_TR_OUT1261_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1261, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[261] 1354 CYHAL_TRIGGER_TCPWM0_TR_OUT1261_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1261, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[261] 1355 CYHAL_TRIGGER_TCPWM0_TR_OUT1262_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1262, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[262] 1356 CYHAL_TRIGGER_TCPWM0_TR_OUT1262_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1262, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[262] 1357 CYHAL_TRIGGER_TCPWM0_TR_OUT1263_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1263, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[263] 1358 CYHAL_TRIGGER_TCPWM0_TR_OUT1263_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1263, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[263] 1359 CYHAL_TRIGGER_TCPWM0_TR_OUT1264_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1264, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[264] 1360 CYHAL_TRIGGER_TCPWM0_TR_OUT1264_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1264, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[264] 1361 CYHAL_TRIGGER_TCPWM0_TR_OUT1265_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1265, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[265] 1362 CYHAL_TRIGGER_TCPWM0_TR_OUT1265_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1265, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[265] 1363 CYHAL_TRIGGER_TCPWM0_TR_OUT1266_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1266, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[266] 1364 CYHAL_TRIGGER_TCPWM0_TR_OUT1266_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1266, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[266] 1365 CYHAL_TRIGGER_TCPWM0_TR_OUT1267_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1267, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[267] 1366 CYHAL_TRIGGER_TCPWM0_TR_OUT1267_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1267, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[267] 1367 CYHAL_TRIGGER_TCPWM0_TR_OUT1512_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1512, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[512] 1368 CYHAL_TRIGGER_TCPWM0_TR_OUT1512_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1512, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[512] 1369 CYHAL_TRIGGER_TCPWM0_TR_OUT1513_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1513, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[513] 1370 CYHAL_TRIGGER_TCPWM0_TR_OUT1513_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1513, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[513] 1371 CYHAL_TRIGGER_TCPWM0_TR_OUT1514_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1514, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[514] 1372 CYHAL_TRIGGER_TCPWM0_TR_OUT1514_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1514, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[514] 1373 CYHAL_TRIGGER_TCPWM0_TR_OUT1515_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1515, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[515] 1374 CYHAL_TRIGGER_TCPWM0_TR_OUT1515_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1515, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[515] 1375 CYHAL_TRIGGER_TR_GROUP9_OUTPUT0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP9_OUTPUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[9].output[0] 1376 CYHAL_TRIGGER_TR_GROUP9_OUTPUT0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP9_OUTPUT0, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[9].output[0] 1377 CYHAL_TRIGGER_TR_GROUP9_OUTPUT1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP9_OUTPUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[9].output[1] 1378 CYHAL_TRIGGER_TR_GROUP9_OUTPUT1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP9_OUTPUT1, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[9].output[1] 1379 CYHAL_TRIGGER_TR_GROUP9_OUTPUT2_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP9_OUTPUT2, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[9].output[2] 1380 CYHAL_TRIGGER_TR_GROUP9_OUTPUT2_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP9_OUTPUT2, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[9].output[2] 1381 CYHAL_TRIGGER_TR_GROUP9_OUTPUT3_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP9_OUTPUT3, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[9].output[3] 1382 CYHAL_TRIGGER_TR_GROUP9_OUTPUT3_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP9_OUTPUT3, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[9].output[3] 1383 CYHAL_TRIGGER_TR_GROUP9_OUTPUT4_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP9_OUTPUT4, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[9].output[4] 1384 CYHAL_TRIGGER_TR_GROUP9_OUTPUT4_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP9_OUTPUT4, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[9].output[4] 1385 CYHAL_TRIGGER_TR_GROUP10_OUTPUT0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[10].output[0] 1386 CYHAL_TRIGGER_TR_GROUP10_OUTPUT0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT0, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[10].output[0] 1387 CYHAL_TRIGGER_TR_GROUP10_OUTPUT1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[10].output[1] 1388 CYHAL_TRIGGER_TR_GROUP10_OUTPUT1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT1, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[10].output[1] 1389 CYHAL_TRIGGER_TR_GROUP10_OUTPUT2_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT2, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[10].output[2] 1390 CYHAL_TRIGGER_TR_GROUP10_OUTPUT2_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT2, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[10].output[2] 1391 CYHAL_TRIGGER_TR_GROUP10_OUTPUT3_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT3, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[10].output[3] 1392 CYHAL_TRIGGER_TR_GROUP10_OUTPUT3_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT3, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[10].output[3] 1393 CYHAL_TRIGGER_TR_GROUP10_OUTPUT4_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT4, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[10].output[4] 1394 CYHAL_TRIGGER_TR_GROUP10_OUTPUT4_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT4, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[10].output[4] 1395 } cyhal_trigger_source_tviibe1m_t; 1396 1397 /** Typedef from device family specific trigger source to generic trigger source */ 1398 typedef cyhal_trigger_source_tviibe1m_t cyhal_source_t; 1399 1400 /** Deprecated defines for signals that can be either level or edge. */ 1401 #define CYHAL_TRIGGER_CPUSS_ZERO (CYHAL_TRIGGER_CPUSS_ZERO_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1402 #define CYHAL_TRIGGER_EVTGEN0_TR_OUT0 (CYHAL_TRIGGER_EVTGEN0_TR_OUT0_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1403 #define CYHAL_TRIGGER_EVTGEN0_TR_OUT1 (CYHAL_TRIGGER_EVTGEN0_TR_OUT1_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1404 #define CYHAL_TRIGGER_EVTGEN0_TR_OUT2 (CYHAL_TRIGGER_EVTGEN0_TR_OUT2_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1405 #define CYHAL_TRIGGER_EVTGEN0_TR_OUT3 (CYHAL_TRIGGER_EVTGEN0_TR_OUT3_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1406 #define CYHAL_TRIGGER_EVTGEN0_TR_OUT4 (CYHAL_TRIGGER_EVTGEN0_TR_OUT4_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1407 #define CYHAL_TRIGGER_EVTGEN0_TR_OUT5 (CYHAL_TRIGGER_EVTGEN0_TR_OUT5_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1408 #define CYHAL_TRIGGER_EVTGEN0_TR_OUT6 (CYHAL_TRIGGER_EVTGEN0_TR_OUT6_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1409 #define CYHAL_TRIGGER_EVTGEN0_TR_OUT7 (CYHAL_TRIGGER_EVTGEN0_TR_OUT7_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1410 #define CYHAL_TRIGGER_EVTGEN0_TR_OUT8 (CYHAL_TRIGGER_EVTGEN0_TR_OUT8_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1411 #define CYHAL_TRIGGER_EVTGEN0_TR_OUT9 (CYHAL_TRIGGER_EVTGEN0_TR_OUT9_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1412 #define CYHAL_TRIGGER_EVTGEN0_TR_OUT10 (CYHAL_TRIGGER_EVTGEN0_TR_OUT10_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1413 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE0 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE0_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1414 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE1 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE1_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1415 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE2 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE2_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1416 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE3 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE3_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1417 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE4 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE4_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1418 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE5 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE5_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1419 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE6 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE6_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1420 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE7 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE7_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1421 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE8 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE8_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1422 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE9 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE9_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1423 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE10 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE10_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1424 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE11 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE11_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1425 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE12 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE12_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1426 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE13 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE13_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1427 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE14 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE14_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1428 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE15 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE15_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1429 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE16 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE16_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1430 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE17 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE17_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1431 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE18 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE18_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1432 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE19 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE19_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1433 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE20 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE20_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1434 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE21 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE21_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1435 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE22 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE22_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1436 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE23 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE23_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1437 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE32 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE32_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1438 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE33 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE33_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1439 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE34 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE34_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1440 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE35 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE35_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1441 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE36 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE36_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1442 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE37 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE37_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1443 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE38 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE38_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1444 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE39 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE39_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1445 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE40 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE40_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1446 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE41 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE41_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1447 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE42 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE42_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1448 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE43 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE43_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1449 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE44 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE44_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1450 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE45 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE45_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1451 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE46 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE46_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1452 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE47 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE47_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1453 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE48 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE48_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1454 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE49 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE49_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1455 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE50 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE50_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1456 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE51 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE51_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1457 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE52 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE52_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1458 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE53 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE53_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1459 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE54 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE54_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1460 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE55 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE55_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1461 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE56 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE56_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1462 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE57 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE57_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1463 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE58 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE58_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1464 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE59 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE59_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1465 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE60 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE60_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1466 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE61 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE61_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1467 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE62 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE62_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1468 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE63 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE63_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1469 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE64 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE64_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1470 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE65 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE65_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1471 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE66 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE66_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1472 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE67 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE67_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1473 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE68 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE68_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1474 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE69 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE69_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1475 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE70 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE70_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1476 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE71 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE71_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1477 #define CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT0 (CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT0_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1478 #define CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT1 (CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT1_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1479 #define CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT2 (CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT2_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1480 #define CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT3 (CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT3_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1481 #define CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT4 (CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT4_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1482 #define CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT5 (CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT5_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1483 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT0 (CYHAL_TRIGGER_PERI_TR_IO_INPUT0_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1484 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT1 (CYHAL_TRIGGER_PERI_TR_IO_INPUT1_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1485 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT2 (CYHAL_TRIGGER_PERI_TR_IO_INPUT2_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1486 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT3 (CYHAL_TRIGGER_PERI_TR_IO_INPUT3_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1487 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT4 (CYHAL_TRIGGER_PERI_TR_IO_INPUT4_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1488 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT5 (CYHAL_TRIGGER_PERI_TR_IO_INPUT5_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1489 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT6 (CYHAL_TRIGGER_PERI_TR_IO_INPUT6_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1490 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT7 (CYHAL_TRIGGER_PERI_TR_IO_INPUT7_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1491 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT8 (CYHAL_TRIGGER_PERI_TR_IO_INPUT8_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1492 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT9 (CYHAL_TRIGGER_PERI_TR_IO_INPUT9_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1493 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT10 (CYHAL_TRIGGER_PERI_TR_IO_INPUT10_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1494 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT11 (CYHAL_TRIGGER_PERI_TR_IO_INPUT11_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1495 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT12 (CYHAL_TRIGGER_PERI_TR_IO_INPUT12_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1496 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT13 (CYHAL_TRIGGER_PERI_TR_IO_INPUT13_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1497 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT14 (CYHAL_TRIGGER_PERI_TR_IO_INPUT14_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1498 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT15 (CYHAL_TRIGGER_PERI_TR_IO_INPUT15_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1499 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT16 (CYHAL_TRIGGER_PERI_TR_IO_INPUT16_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1500 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT17 (CYHAL_TRIGGER_PERI_TR_IO_INPUT17_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1501 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT18 (CYHAL_TRIGGER_PERI_TR_IO_INPUT18_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1502 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT19 (CYHAL_TRIGGER_PERI_TR_IO_INPUT19_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1503 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT20 (CYHAL_TRIGGER_PERI_TR_IO_INPUT20_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1504 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT21 (CYHAL_TRIGGER_PERI_TR_IO_INPUT21_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1505 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT22 (CYHAL_TRIGGER_PERI_TR_IO_INPUT22_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1506 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT23 (CYHAL_TRIGGER_PERI_TR_IO_INPUT23_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1507 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT24 (CYHAL_TRIGGER_PERI_TR_IO_INPUT24_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1508 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT25 (CYHAL_TRIGGER_PERI_TR_IO_INPUT25_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1509 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT26 (CYHAL_TRIGGER_PERI_TR_IO_INPUT26_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1510 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT27 (CYHAL_TRIGGER_PERI_TR_IO_INPUT27_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1511 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT28 (CYHAL_TRIGGER_PERI_TR_IO_INPUT28_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1512 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT29 (CYHAL_TRIGGER_PERI_TR_IO_INPUT29_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1513 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT30 (CYHAL_TRIGGER_PERI_TR_IO_INPUT30_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1514 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT31 (CYHAL_TRIGGER_PERI_TR_IO_INPUT31_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1515 #define CYHAL_TRIGGER_TCPWM0_TR_OUT00 (CYHAL_TRIGGER_TCPWM0_TR_OUT00_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1516 #define CYHAL_TRIGGER_TCPWM0_TR_OUT01 (CYHAL_TRIGGER_TCPWM0_TR_OUT01_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1517 #define CYHAL_TRIGGER_TCPWM0_TR_OUT02 (CYHAL_TRIGGER_TCPWM0_TR_OUT02_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1518 #define CYHAL_TRIGGER_TCPWM0_TR_OUT03 (CYHAL_TRIGGER_TCPWM0_TR_OUT03_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1519 #define CYHAL_TRIGGER_TCPWM0_TR_OUT04 (CYHAL_TRIGGER_TCPWM0_TR_OUT04_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1520 #define CYHAL_TRIGGER_TCPWM0_TR_OUT05 (CYHAL_TRIGGER_TCPWM0_TR_OUT05_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1521 #define CYHAL_TRIGGER_TCPWM0_TR_OUT06 (CYHAL_TRIGGER_TCPWM0_TR_OUT06_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1522 #define CYHAL_TRIGGER_TCPWM0_TR_OUT07 (CYHAL_TRIGGER_TCPWM0_TR_OUT07_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1523 #define CYHAL_TRIGGER_TCPWM0_TR_OUT08 (CYHAL_TRIGGER_TCPWM0_TR_OUT08_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1524 #define CYHAL_TRIGGER_TCPWM0_TR_OUT09 (CYHAL_TRIGGER_TCPWM0_TR_OUT09_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1525 #define CYHAL_TRIGGER_TCPWM0_TR_OUT010 (CYHAL_TRIGGER_TCPWM0_TR_OUT010_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1526 #define CYHAL_TRIGGER_TCPWM0_TR_OUT011 (CYHAL_TRIGGER_TCPWM0_TR_OUT011_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1527 #define CYHAL_TRIGGER_TCPWM0_TR_OUT012 (CYHAL_TRIGGER_TCPWM0_TR_OUT012_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1528 #define CYHAL_TRIGGER_TCPWM0_TR_OUT013 (CYHAL_TRIGGER_TCPWM0_TR_OUT013_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1529 #define CYHAL_TRIGGER_TCPWM0_TR_OUT014 (CYHAL_TRIGGER_TCPWM0_TR_OUT014_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1530 #define CYHAL_TRIGGER_TCPWM0_TR_OUT015 (CYHAL_TRIGGER_TCPWM0_TR_OUT015_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1531 #define CYHAL_TRIGGER_TCPWM0_TR_OUT016 (CYHAL_TRIGGER_TCPWM0_TR_OUT016_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1532 #define CYHAL_TRIGGER_TCPWM0_TR_OUT017 (CYHAL_TRIGGER_TCPWM0_TR_OUT017_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1533 #define CYHAL_TRIGGER_TCPWM0_TR_OUT018 (CYHAL_TRIGGER_TCPWM0_TR_OUT018_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1534 #define CYHAL_TRIGGER_TCPWM0_TR_OUT019 (CYHAL_TRIGGER_TCPWM0_TR_OUT019_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1535 #define CYHAL_TRIGGER_TCPWM0_TR_OUT020 (CYHAL_TRIGGER_TCPWM0_TR_OUT020_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1536 #define CYHAL_TRIGGER_TCPWM0_TR_OUT021 (CYHAL_TRIGGER_TCPWM0_TR_OUT021_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1537 #define CYHAL_TRIGGER_TCPWM0_TR_OUT022 (CYHAL_TRIGGER_TCPWM0_TR_OUT022_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1538 #define CYHAL_TRIGGER_TCPWM0_TR_OUT023 (CYHAL_TRIGGER_TCPWM0_TR_OUT023_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1539 #define CYHAL_TRIGGER_TCPWM0_TR_OUT024 (CYHAL_TRIGGER_TCPWM0_TR_OUT024_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1540 #define CYHAL_TRIGGER_TCPWM0_TR_OUT025 (CYHAL_TRIGGER_TCPWM0_TR_OUT025_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1541 #define CYHAL_TRIGGER_TCPWM0_TR_OUT026 (CYHAL_TRIGGER_TCPWM0_TR_OUT026_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1542 #define CYHAL_TRIGGER_TCPWM0_TR_OUT027 (CYHAL_TRIGGER_TCPWM0_TR_OUT027_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1543 #define CYHAL_TRIGGER_TCPWM0_TR_OUT028 (CYHAL_TRIGGER_TCPWM0_TR_OUT028_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1544 #define CYHAL_TRIGGER_TCPWM0_TR_OUT029 (CYHAL_TRIGGER_TCPWM0_TR_OUT029_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1545 #define CYHAL_TRIGGER_TCPWM0_TR_OUT030 (CYHAL_TRIGGER_TCPWM0_TR_OUT030_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1546 #define CYHAL_TRIGGER_TCPWM0_TR_OUT031 (CYHAL_TRIGGER_TCPWM0_TR_OUT031_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1547 #define CYHAL_TRIGGER_TCPWM0_TR_OUT032 (CYHAL_TRIGGER_TCPWM0_TR_OUT032_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1548 #define CYHAL_TRIGGER_TCPWM0_TR_OUT033 (CYHAL_TRIGGER_TCPWM0_TR_OUT033_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1549 #define CYHAL_TRIGGER_TCPWM0_TR_OUT034 (CYHAL_TRIGGER_TCPWM0_TR_OUT034_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1550 #define CYHAL_TRIGGER_TCPWM0_TR_OUT035 (CYHAL_TRIGGER_TCPWM0_TR_OUT035_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1551 #define CYHAL_TRIGGER_TCPWM0_TR_OUT036 (CYHAL_TRIGGER_TCPWM0_TR_OUT036_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1552 #define CYHAL_TRIGGER_TCPWM0_TR_OUT037 (CYHAL_TRIGGER_TCPWM0_TR_OUT037_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1553 #define CYHAL_TRIGGER_TCPWM0_TR_OUT038 (CYHAL_TRIGGER_TCPWM0_TR_OUT038_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1554 #define CYHAL_TRIGGER_TCPWM0_TR_OUT039 (CYHAL_TRIGGER_TCPWM0_TR_OUT039_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1555 #define CYHAL_TRIGGER_TCPWM0_TR_OUT040 (CYHAL_TRIGGER_TCPWM0_TR_OUT040_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1556 #define CYHAL_TRIGGER_TCPWM0_TR_OUT041 (CYHAL_TRIGGER_TCPWM0_TR_OUT041_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1557 #define CYHAL_TRIGGER_TCPWM0_TR_OUT042 (CYHAL_TRIGGER_TCPWM0_TR_OUT042_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1558 #define CYHAL_TRIGGER_TCPWM0_TR_OUT043 (CYHAL_TRIGGER_TCPWM0_TR_OUT043_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1559 #define CYHAL_TRIGGER_TCPWM0_TR_OUT044 (CYHAL_TRIGGER_TCPWM0_TR_OUT044_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1560 #define CYHAL_TRIGGER_TCPWM0_TR_OUT045 (CYHAL_TRIGGER_TCPWM0_TR_OUT045_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1561 #define CYHAL_TRIGGER_TCPWM0_TR_OUT046 (CYHAL_TRIGGER_TCPWM0_TR_OUT046_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1562 #define CYHAL_TRIGGER_TCPWM0_TR_OUT047 (CYHAL_TRIGGER_TCPWM0_TR_OUT047_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1563 #define CYHAL_TRIGGER_TCPWM0_TR_OUT048 (CYHAL_TRIGGER_TCPWM0_TR_OUT048_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1564 #define CYHAL_TRIGGER_TCPWM0_TR_OUT049 (CYHAL_TRIGGER_TCPWM0_TR_OUT049_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1565 #define CYHAL_TRIGGER_TCPWM0_TR_OUT050 (CYHAL_TRIGGER_TCPWM0_TR_OUT050_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1566 #define CYHAL_TRIGGER_TCPWM0_TR_OUT051 (CYHAL_TRIGGER_TCPWM0_TR_OUT051_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1567 #define CYHAL_TRIGGER_TCPWM0_TR_OUT052 (CYHAL_TRIGGER_TCPWM0_TR_OUT052_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1568 #define CYHAL_TRIGGER_TCPWM0_TR_OUT053 (CYHAL_TRIGGER_TCPWM0_TR_OUT053_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1569 #define CYHAL_TRIGGER_TCPWM0_TR_OUT054 (CYHAL_TRIGGER_TCPWM0_TR_OUT054_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1570 #define CYHAL_TRIGGER_TCPWM0_TR_OUT055 (CYHAL_TRIGGER_TCPWM0_TR_OUT055_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1571 #define CYHAL_TRIGGER_TCPWM0_TR_OUT056 (CYHAL_TRIGGER_TCPWM0_TR_OUT056_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1572 #define CYHAL_TRIGGER_TCPWM0_TR_OUT057 (CYHAL_TRIGGER_TCPWM0_TR_OUT057_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1573 #define CYHAL_TRIGGER_TCPWM0_TR_OUT058 (CYHAL_TRIGGER_TCPWM0_TR_OUT058_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1574 #define CYHAL_TRIGGER_TCPWM0_TR_OUT059 (CYHAL_TRIGGER_TCPWM0_TR_OUT059_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1575 #define CYHAL_TRIGGER_TCPWM0_TR_OUT060 (CYHAL_TRIGGER_TCPWM0_TR_OUT060_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1576 #define CYHAL_TRIGGER_TCPWM0_TR_OUT061 (CYHAL_TRIGGER_TCPWM0_TR_OUT061_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1577 #define CYHAL_TRIGGER_TCPWM0_TR_OUT062 (CYHAL_TRIGGER_TCPWM0_TR_OUT062_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1578 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0256 (CYHAL_TRIGGER_TCPWM0_TR_OUT0256_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1579 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0257 (CYHAL_TRIGGER_TCPWM0_TR_OUT0257_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1580 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0258 (CYHAL_TRIGGER_TCPWM0_TR_OUT0258_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1581 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0259 (CYHAL_TRIGGER_TCPWM0_TR_OUT0259_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1582 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0260 (CYHAL_TRIGGER_TCPWM0_TR_OUT0260_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1583 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0261 (CYHAL_TRIGGER_TCPWM0_TR_OUT0261_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1584 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0262 (CYHAL_TRIGGER_TCPWM0_TR_OUT0262_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1585 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0263 (CYHAL_TRIGGER_TCPWM0_TR_OUT0263_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1586 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0264 (CYHAL_TRIGGER_TCPWM0_TR_OUT0264_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1587 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0265 (CYHAL_TRIGGER_TCPWM0_TR_OUT0265_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1588 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0266 (CYHAL_TRIGGER_TCPWM0_TR_OUT0266_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1589 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0267 (CYHAL_TRIGGER_TCPWM0_TR_OUT0267_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1590 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0512 (CYHAL_TRIGGER_TCPWM0_TR_OUT0512_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1591 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0513 (CYHAL_TRIGGER_TCPWM0_TR_OUT0513_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1592 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0514 (CYHAL_TRIGGER_TCPWM0_TR_OUT0514_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1593 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0515 (CYHAL_TRIGGER_TCPWM0_TR_OUT0515_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1594 #define CYHAL_TRIGGER_TCPWM0_TR_OUT10 (CYHAL_TRIGGER_TCPWM0_TR_OUT10_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1595 #define CYHAL_TRIGGER_TCPWM0_TR_OUT11 (CYHAL_TRIGGER_TCPWM0_TR_OUT11_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1596 #define CYHAL_TRIGGER_TCPWM0_TR_OUT12 (CYHAL_TRIGGER_TCPWM0_TR_OUT12_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1597 #define CYHAL_TRIGGER_TCPWM0_TR_OUT13 (CYHAL_TRIGGER_TCPWM0_TR_OUT13_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1598 #define CYHAL_TRIGGER_TCPWM0_TR_OUT14 (CYHAL_TRIGGER_TCPWM0_TR_OUT14_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1599 #define CYHAL_TRIGGER_TCPWM0_TR_OUT15 (CYHAL_TRIGGER_TCPWM0_TR_OUT15_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1600 #define CYHAL_TRIGGER_TCPWM0_TR_OUT16 (CYHAL_TRIGGER_TCPWM0_TR_OUT16_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1601 #define CYHAL_TRIGGER_TCPWM0_TR_OUT17 (CYHAL_TRIGGER_TCPWM0_TR_OUT17_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1602 #define CYHAL_TRIGGER_TCPWM0_TR_OUT18 (CYHAL_TRIGGER_TCPWM0_TR_OUT18_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1603 #define CYHAL_TRIGGER_TCPWM0_TR_OUT19 (CYHAL_TRIGGER_TCPWM0_TR_OUT19_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1604 #define CYHAL_TRIGGER_TCPWM0_TR_OUT110 (CYHAL_TRIGGER_TCPWM0_TR_OUT110_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1605 #define CYHAL_TRIGGER_TCPWM0_TR_OUT111 (CYHAL_TRIGGER_TCPWM0_TR_OUT111_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1606 #define CYHAL_TRIGGER_TCPWM0_TR_OUT112 (CYHAL_TRIGGER_TCPWM0_TR_OUT112_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1607 #define CYHAL_TRIGGER_TCPWM0_TR_OUT113 (CYHAL_TRIGGER_TCPWM0_TR_OUT113_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1608 #define CYHAL_TRIGGER_TCPWM0_TR_OUT114 (CYHAL_TRIGGER_TCPWM0_TR_OUT114_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1609 #define CYHAL_TRIGGER_TCPWM0_TR_OUT115 (CYHAL_TRIGGER_TCPWM0_TR_OUT115_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1610 #define CYHAL_TRIGGER_TCPWM0_TR_OUT116 (CYHAL_TRIGGER_TCPWM0_TR_OUT116_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1611 #define CYHAL_TRIGGER_TCPWM0_TR_OUT117 (CYHAL_TRIGGER_TCPWM0_TR_OUT117_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1612 #define CYHAL_TRIGGER_TCPWM0_TR_OUT118 (CYHAL_TRIGGER_TCPWM0_TR_OUT118_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1613 #define CYHAL_TRIGGER_TCPWM0_TR_OUT119 (CYHAL_TRIGGER_TCPWM0_TR_OUT119_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1614 #define CYHAL_TRIGGER_TCPWM0_TR_OUT120 (CYHAL_TRIGGER_TCPWM0_TR_OUT120_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1615 #define CYHAL_TRIGGER_TCPWM0_TR_OUT121 (CYHAL_TRIGGER_TCPWM0_TR_OUT121_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1616 #define CYHAL_TRIGGER_TCPWM0_TR_OUT122 (CYHAL_TRIGGER_TCPWM0_TR_OUT122_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1617 #define CYHAL_TRIGGER_TCPWM0_TR_OUT123 (CYHAL_TRIGGER_TCPWM0_TR_OUT123_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1618 #define CYHAL_TRIGGER_TCPWM0_TR_OUT124 (CYHAL_TRIGGER_TCPWM0_TR_OUT124_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1619 #define CYHAL_TRIGGER_TCPWM0_TR_OUT125 (CYHAL_TRIGGER_TCPWM0_TR_OUT125_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1620 #define CYHAL_TRIGGER_TCPWM0_TR_OUT126 (CYHAL_TRIGGER_TCPWM0_TR_OUT126_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1621 #define CYHAL_TRIGGER_TCPWM0_TR_OUT127 (CYHAL_TRIGGER_TCPWM0_TR_OUT127_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1622 #define CYHAL_TRIGGER_TCPWM0_TR_OUT128 (CYHAL_TRIGGER_TCPWM0_TR_OUT128_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1623 #define CYHAL_TRIGGER_TCPWM0_TR_OUT129 (CYHAL_TRIGGER_TCPWM0_TR_OUT129_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1624 #define CYHAL_TRIGGER_TCPWM0_TR_OUT130 (CYHAL_TRIGGER_TCPWM0_TR_OUT130_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1625 #define CYHAL_TRIGGER_TCPWM0_TR_OUT131 (CYHAL_TRIGGER_TCPWM0_TR_OUT131_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1626 #define CYHAL_TRIGGER_TCPWM0_TR_OUT132 (CYHAL_TRIGGER_TCPWM0_TR_OUT132_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1627 #define CYHAL_TRIGGER_TCPWM0_TR_OUT133 (CYHAL_TRIGGER_TCPWM0_TR_OUT133_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1628 #define CYHAL_TRIGGER_TCPWM0_TR_OUT134 (CYHAL_TRIGGER_TCPWM0_TR_OUT134_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1629 #define CYHAL_TRIGGER_TCPWM0_TR_OUT135 (CYHAL_TRIGGER_TCPWM0_TR_OUT135_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1630 #define CYHAL_TRIGGER_TCPWM0_TR_OUT136 (CYHAL_TRIGGER_TCPWM0_TR_OUT136_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1631 #define CYHAL_TRIGGER_TCPWM0_TR_OUT137 (CYHAL_TRIGGER_TCPWM0_TR_OUT137_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1632 #define CYHAL_TRIGGER_TCPWM0_TR_OUT138 (CYHAL_TRIGGER_TCPWM0_TR_OUT138_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1633 #define CYHAL_TRIGGER_TCPWM0_TR_OUT139 (CYHAL_TRIGGER_TCPWM0_TR_OUT139_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1634 #define CYHAL_TRIGGER_TCPWM0_TR_OUT140 (CYHAL_TRIGGER_TCPWM0_TR_OUT140_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1635 #define CYHAL_TRIGGER_TCPWM0_TR_OUT141 (CYHAL_TRIGGER_TCPWM0_TR_OUT141_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1636 #define CYHAL_TRIGGER_TCPWM0_TR_OUT142 (CYHAL_TRIGGER_TCPWM0_TR_OUT142_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1637 #define CYHAL_TRIGGER_TCPWM0_TR_OUT143 (CYHAL_TRIGGER_TCPWM0_TR_OUT143_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1638 #define CYHAL_TRIGGER_TCPWM0_TR_OUT144 (CYHAL_TRIGGER_TCPWM0_TR_OUT144_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1639 #define CYHAL_TRIGGER_TCPWM0_TR_OUT145 (CYHAL_TRIGGER_TCPWM0_TR_OUT145_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1640 #define CYHAL_TRIGGER_TCPWM0_TR_OUT146 (CYHAL_TRIGGER_TCPWM0_TR_OUT146_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1641 #define CYHAL_TRIGGER_TCPWM0_TR_OUT147 (CYHAL_TRIGGER_TCPWM0_TR_OUT147_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1642 #define CYHAL_TRIGGER_TCPWM0_TR_OUT148 (CYHAL_TRIGGER_TCPWM0_TR_OUT148_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1643 #define CYHAL_TRIGGER_TCPWM0_TR_OUT149 (CYHAL_TRIGGER_TCPWM0_TR_OUT149_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1644 #define CYHAL_TRIGGER_TCPWM0_TR_OUT150 (CYHAL_TRIGGER_TCPWM0_TR_OUT150_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1645 #define CYHAL_TRIGGER_TCPWM0_TR_OUT151 (CYHAL_TRIGGER_TCPWM0_TR_OUT151_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1646 #define CYHAL_TRIGGER_TCPWM0_TR_OUT152 (CYHAL_TRIGGER_TCPWM0_TR_OUT152_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1647 #define CYHAL_TRIGGER_TCPWM0_TR_OUT153 (CYHAL_TRIGGER_TCPWM0_TR_OUT153_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1648 #define CYHAL_TRIGGER_TCPWM0_TR_OUT154 (CYHAL_TRIGGER_TCPWM0_TR_OUT154_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1649 #define CYHAL_TRIGGER_TCPWM0_TR_OUT155 (CYHAL_TRIGGER_TCPWM0_TR_OUT155_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1650 #define CYHAL_TRIGGER_TCPWM0_TR_OUT156 (CYHAL_TRIGGER_TCPWM0_TR_OUT156_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1651 #define CYHAL_TRIGGER_TCPWM0_TR_OUT157 (CYHAL_TRIGGER_TCPWM0_TR_OUT157_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1652 #define CYHAL_TRIGGER_TCPWM0_TR_OUT158 (CYHAL_TRIGGER_TCPWM0_TR_OUT158_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1653 #define CYHAL_TRIGGER_TCPWM0_TR_OUT159 (CYHAL_TRIGGER_TCPWM0_TR_OUT159_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1654 #define CYHAL_TRIGGER_TCPWM0_TR_OUT160 (CYHAL_TRIGGER_TCPWM0_TR_OUT160_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1655 #define CYHAL_TRIGGER_TCPWM0_TR_OUT161 (CYHAL_TRIGGER_TCPWM0_TR_OUT161_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1656 #define CYHAL_TRIGGER_TCPWM0_TR_OUT162 (CYHAL_TRIGGER_TCPWM0_TR_OUT162_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1657 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1256 (CYHAL_TRIGGER_TCPWM0_TR_OUT1256_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1658 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1257 (CYHAL_TRIGGER_TCPWM0_TR_OUT1257_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1659 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1258 (CYHAL_TRIGGER_TCPWM0_TR_OUT1258_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1660 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1259 (CYHAL_TRIGGER_TCPWM0_TR_OUT1259_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1661 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1260 (CYHAL_TRIGGER_TCPWM0_TR_OUT1260_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1662 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1261 (CYHAL_TRIGGER_TCPWM0_TR_OUT1261_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1663 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1262 (CYHAL_TRIGGER_TCPWM0_TR_OUT1262_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1664 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1263 (CYHAL_TRIGGER_TCPWM0_TR_OUT1263_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1665 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1264 (CYHAL_TRIGGER_TCPWM0_TR_OUT1264_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1666 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1265 (CYHAL_TRIGGER_TCPWM0_TR_OUT1265_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1667 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1266 (CYHAL_TRIGGER_TCPWM0_TR_OUT1266_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1668 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1267 (CYHAL_TRIGGER_TCPWM0_TR_OUT1267_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1669 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1512 (CYHAL_TRIGGER_TCPWM0_TR_OUT1512_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1670 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1513 (CYHAL_TRIGGER_TCPWM0_TR_OUT1513_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1671 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1514 (CYHAL_TRIGGER_TCPWM0_TR_OUT1514_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1672 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1515 (CYHAL_TRIGGER_TCPWM0_TR_OUT1515_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1673 #define CYHAL_TRIGGER_TR_GROUP9_OUTPUT0 (CYHAL_TRIGGER_TR_GROUP9_OUTPUT0_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1674 #define CYHAL_TRIGGER_TR_GROUP9_OUTPUT1 (CYHAL_TRIGGER_TR_GROUP9_OUTPUT1_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1675 #define CYHAL_TRIGGER_TR_GROUP9_OUTPUT2 (CYHAL_TRIGGER_TR_GROUP9_OUTPUT2_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1676 #define CYHAL_TRIGGER_TR_GROUP9_OUTPUT3 (CYHAL_TRIGGER_TR_GROUP9_OUTPUT3_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1677 #define CYHAL_TRIGGER_TR_GROUP9_OUTPUT4 (CYHAL_TRIGGER_TR_GROUP9_OUTPUT4_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1678 #define CYHAL_TRIGGER_TR_GROUP10_OUTPUT0 (CYHAL_TRIGGER_TR_GROUP10_OUTPUT0_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1679 #define CYHAL_TRIGGER_TR_GROUP10_OUTPUT1 (CYHAL_TRIGGER_TR_GROUP10_OUTPUT1_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1680 #define CYHAL_TRIGGER_TR_GROUP10_OUTPUT2 (CYHAL_TRIGGER_TR_GROUP10_OUTPUT2_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1681 #define CYHAL_TRIGGER_TR_GROUP10_OUTPUT3 (CYHAL_TRIGGER_TR_GROUP10_OUTPUT3_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1682 #define CYHAL_TRIGGER_TR_GROUP10_OUTPUT4 (CYHAL_TRIGGER_TR_GROUP10_OUTPUT4_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 1683 1684 /** @brief Name of each output trigger. */ 1685 typedef enum 1686 { 1687 CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_ACK0 = 0, //!< CAN DW0 triggers (from DW back to CAN) - canfd[0].tr_dbg_dma_ack[0] 1688 CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_ACK1 = 1, //!< CAN DW0 triggers (from DW back to CAN) - canfd[0].tr_dbg_dma_ack[1] 1689 CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_ACK2 = 2, //!< CAN DW0 triggers (from DW back to CAN) - canfd[0].tr_dbg_dma_ack[2] 1690 CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_ACK0 = 3, //!< CAN DW1 triggers (from DW back to CAN) - canfd[1].tr_dbg_dma_ack[0] 1691 CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_ACK1 = 4, //!< CAN DW1 triggers (from DW back to CAN) - canfd[1].tr_dbg_dma_ack[1] 1692 CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_ACK2 = 5, //!< CAN DW1 triggers (from DW back to CAN) - canfd[1].tr_dbg_dma_ack[2] 1693 CYHAL_TRIGGER_CANFD0_TR_EVT_SWT_IN0 = 6, //!< CAN TT Sync - canfd[0].tr_evt_swt_in[0] 1694 CYHAL_TRIGGER_CANFD0_TR_EVT_SWT_IN1 = 7, //!< CAN TT Sync - canfd[0].tr_evt_swt_in[1] 1695 CYHAL_TRIGGER_CANFD0_TR_EVT_SWT_IN2 = 8, //!< CAN TT Sync - canfd[0].tr_evt_swt_in[2] 1696 CYHAL_TRIGGER_CANFD1_TR_EVT_SWT_IN0 = 9, //!< CAN TT Sync - canfd[1].tr_evt_swt_in[0] 1697 CYHAL_TRIGGER_CANFD1_TR_EVT_SWT_IN1 = 10, //!< CAN TT Sync - canfd[1].tr_evt_swt_in[1] 1698 CYHAL_TRIGGER_CANFD1_TR_EVT_SWT_IN2 = 11, //!< CAN TT Sync - canfd[1].tr_evt_swt_in[2] 1699 CYHAL_TRIGGER_CPUSS_CTI_TR_IN0 = 12, //!< Debug Multiplexer - cpuss.cti_tr_in[0] 1700 CYHAL_TRIGGER_CPUSS_CTI_TR_IN1 = 13, //!< Debug Multiplexer - cpuss.cti_tr_in[1] 1701 CYHAL_TRIGGER_CPUSS_DMAC_TR_IN0 = 14, //!< M-DMA trigger multiplexer - cpuss.dmac_tr_in[0] 1702 CYHAL_TRIGGER_CPUSS_DMAC_TR_IN1 = 15, //!< M-DMA trigger multiplexer - cpuss.dmac_tr_in[1] 1703 CYHAL_TRIGGER_CPUSS_DMAC_TR_IN2 = 16, //!< M-DMA trigger multiplexer - cpuss.dmac_tr_in[2] 1704 CYHAL_TRIGGER_CPUSS_DMAC_TR_IN3 = 17, //!< M-DMA trigger multiplexer - cpuss.dmac_tr_in[3] 1705 CYHAL_TRIGGER_CPUSS_DW0_TR_IN0 = 18, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[0] 1706 CYHAL_TRIGGER_CPUSS_DW0_TR_IN1 = 19, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[1] 1707 CYHAL_TRIGGER_CPUSS_DW0_TR_IN2 = 20, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[2] 1708 CYHAL_TRIGGER_CPUSS_DW0_TR_IN3 = 21, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[3] 1709 CYHAL_TRIGGER_CPUSS_DW0_TR_IN4 = 22, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[4] 1710 CYHAL_TRIGGER_CPUSS_DW0_TR_IN5 = 23, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[5] 1711 CYHAL_TRIGGER_CPUSS_DW0_TR_IN6 = 24, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[6] 1712 CYHAL_TRIGGER_CPUSS_DW0_TR_IN7 = 25, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[7] 1713 CYHAL_TRIGGER_CPUSS_DW0_TR_IN8 = 26, //!< TCPWM to P-DMA0 trigger mux - cpuss.dw0_tr_in[8] 1714 CYHAL_TRIGGER_CPUSS_DW0_TR_IN9 = 27, //!< TCPWM to P-DMA0 trigger mux - cpuss.dw0_tr_in[9] 1715 CYHAL_TRIGGER_CPUSS_DW0_TR_IN10 = 28, //!< TCPWM to P-DMA0 trigger mux - cpuss.dw0_tr_in[10] 1716 CYHAL_TRIGGER_CPUSS_DW0_TR_IN11 = 29, //!< TCPWM to P-DMA0 trigger mux - cpuss.dw0_tr_in[11] 1717 CYHAL_TRIGGER_CPUSS_DW0_TR_IN12 = 30, //!< TCPWM to P-DMA0 trigger mux - cpuss.dw0_tr_in[12] 1718 CYHAL_TRIGGER_CPUSS_DW0_TR_IN13 = 31, //!< TCPWM to P-DMA0 trigger mux - cpuss.dw0_tr_in[13] 1719 CYHAL_TRIGGER_CPUSS_DW0_TR_IN14 = 32, //!< TCPWM to P-DMA0 trigger mux - cpuss.dw0_tr_in[14] 1720 CYHAL_TRIGGER_CPUSS_DW0_TR_IN15 = 33, //!< TCPWM to P-DMA0 trigger mux - cpuss.dw0_tr_in[15] 1721 CYHAL_TRIGGER_CPUSS_DW0_TR_IN16 = 34, //!< CAN DW0 Triggers - cpuss.dw0_tr_in[16] 1722 CYHAL_TRIGGER_CPUSS_DW0_TR_IN17 = 35, //!< CAN DW0 Triggers - cpuss.dw0_tr_in[17] 1723 CYHAL_TRIGGER_CPUSS_DW0_TR_IN18 = 36, //!< CAN DW0 Triggers - cpuss.dw0_tr_in[18] 1724 CYHAL_TRIGGER_CPUSS_DW0_TR_IN19 = 37, //!< CAN DW0 Triggers - cpuss.dw0_tr_in[19] 1725 CYHAL_TRIGGER_CPUSS_DW0_TR_IN20 = 38, //!< CAN DW0 Triggers - cpuss.dw0_tr_in[20] 1726 CYHAL_TRIGGER_CPUSS_DW0_TR_IN21 = 39, //!< CAN DW0 Triggers - cpuss.dw0_tr_in[21] 1727 CYHAL_TRIGGER_CPUSS_DW0_TR_IN22 = 40, //!< CAN DW0 Triggers - cpuss.dw0_tr_in[22] 1728 CYHAL_TRIGGER_CPUSS_DW0_TR_IN23 = 41, //!< CAN DW0 Triggers - cpuss.dw0_tr_in[23] 1729 CYHAL_TRIGGER_CPUSS_DW0_TR_IN24 = 42, //!< CAN DW0 Triggers - cpuss.dw0_tr_in[24] 1730 CYHAL_TRIGGER_CPUSS_DW0_TR_IN25 = 43, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[25] 1731 CYHAL_TRIGGER_CPUSS_DW0_TR_IN26 = 44, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[26] 1732 CYHAL_TRIGGER_CPUSS_DW0_TR_IN27 = 45, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[27] 1733 CYHAL_TRIGGER_CPUSS_DW0_TR_IN28 = 46, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[28] 1734 CYHAL_TRIGGER_CPUSS_DW0_TR_IN29 = 47, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[29] 1735 CYHAL_TRIGGER_CPUSS_DW0_TR_IN30 = 48, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[30] 1736 CYHAL_TRIGGER_CPUSS_DW0_TR_IN31 = 49, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[31] 1737 CYHAL_TRIGGER_CPUSS_DW0_TR_IN32 = 50, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[32] 1738 CYHAL_TRIGGER_CPUSS_DW0_TR_IN33 = 51, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[33] 1739 CYHAL_TRIGGER_CPUSS_DW0_TR_IN34 = 52, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[34] 1740 CYHAL_TRIGGER_CPUSS_DW0_TR_IN35 = 53, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[35] 1741 CYHAL_TRIGGER_CPUSS_DW0_TR_IN36 = 54, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[36] 1742 CYHAL_TRIGGER_CPUSS_DW0_TR_IN37 = 55, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[37] 1743 CYHAL_TRIGGER_CPUSS_DW0_TR_IN38 = 56, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[38] 1744 CYHAL_TRIGGER_CPUSS_DW0_TR_IN39 = 57, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[39] 1745 CYHAL_TRIGGER_CPUSS_DW0_TR_IN40 = 58, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[40] 1746 CYHAL_TRIGGER_CPUSS_DW0_TR_IN41 = 59, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[41] 1747 CYHAL_TRIGGER_CPUSS_DW0_TR_IN42 = 60, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[42] 1748 CYHAL_TRIGGER_CPUSS_DW0_TR_IN43 = 61, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[43] 1749 CYHAL_TRIGGER_CPUSS_DW0_TR_IN44 = 62, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[44] 1750 CYHAL_TRIGGER_CPUSS_DW0_TR_IN45 = 63, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[45] 1751 CYHAL_TRIGGER_CPUSS_DW0_TR_IN46 = 64, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[46] 1752 CYHAL_TRIGGER_CPUSS_DW0_TR_IN47 = 65, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[47] 1753 CYHAL_TRIGGER_CPUSS_DW0_TR_IN48 = 66, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[48] 1754 CYHAL_TRIGGER_CPUSS_DW0_TR_IN49 = 67, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[49] 1755 CYHAL_TRIGGER_CPUSS_DW0_TR_IN50 = 68, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[50] 1756 CYHAL_TRIGGER_CPUSS_DW0_TR_IN51 = 69, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[51] 1757 CYHAL_TRIGGER_CPUSS_DW0_TR_IN52 = 70, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[52] 1758 CYHAL_TRIGGER_CPUSS_DW0_TR_IN53 = 71, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[53] 1759 CYHAL_TRIGGER_CPUSS_DW0_TR_IN54 = 72, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[54] 1760 CYHAL_TRIGGER_CPUSS_DW0_TR_IN55 = 73, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[55] 1761 CYHAL_TRIGGER_CPUSS_DW0_TR_IN56 = 74, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[56] 1762 CYHAL_TRIGGER_CPUSS_DW0_TR_IN57 = 75, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[57] 1763 CYHAL_TRIGGER_CPUSS_DW0_TR_IN58 = 76, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[58] 1764 CYHAL_TRIGGER_CPUSS_DW0_TR_IN59 = 77, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[59] 1765 CYHAL_TRIGGER_CPUSS_DW0_TR_IN60 = 78, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[60] 1766 CYHAL_TRIGGER_CPUSS_DW0_TR_IN61 = 79, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[61] 1767 CYHAL_TRIGGER_CPUSS_DW0_TR_IN62 = 80, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[62] 1768 CYHAL_TRIGGER_CPUSS_DW0_TR_IN63 = 81, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[63] 1769 CYHAL_TRIGGER_CPUSS_DW0_TR_IN64 = 82, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[64] 1770 CYHAL_TRIGGER_CPUSS_DW0_TR_IN65 = 83, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[65] 1771 CYHAL_TRIGGER_CPUSS_DW0_TR_IN66 = 84, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[66] 1772 CYHAL_TRIGGER_CPUSS_DW0_TR_IN67 = 85, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[67] 1773 CYHAL_TRIGGER_CPUSS_DW0_TR_IN68 = 86, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[68] 1774 CYHAL_TRIGGER_CPUSS_DW0_TR_IN69 = 87, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[69] 1775 CYHAL_TRIGGER_CPUSS_DW0_TR_IN70 = 88, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[70] 1776 CYHAL_TRIGGER_CPUSS_DW0_TR_IN71 = 89, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[71] 1777 CYHAL_TRIGGER_CPUSS_DW0_TR_IN72 = 90, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[72] 1778 CYHAL_TRIGGER_CPUSS_DW0_TR_IN73 = 91, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[73] 1779 CYHAL_TRIGGER_CPUSS_DW0_TR_IN74 = 92, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[74] 1780 CYHAL_TRIGGER_CPUSS_DW0_TR_IN75 = 93, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[75] 1781 CYHAL_TRIGGER_CPUSS_DW0_TR_IN76 = 94, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[76] 1782 CYHAL_TRIGGER_CPUSS_DW0_TR_IN77 = 95, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[77] 1783 CYHAL_TRIGGER_CPUSS_DW0_TR_IN78 = 96, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[78] 1784 CYHAL_TRIGGER_CPUSS_DW0_TR_IN79 = 97, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[79] 1785 CYHAL_TRIGGER_CPUSS_DW0_TR_IN80 = 98, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[80] 1786 CYHAL_TRIGGER_CPUSS_DW0_TR_IN81 = 99, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[81] 1787 CYHAL_TRIGGER_CPUSS_DW0_TR_IN82 = 100, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[82] 1788 CYHAL_TRIGGER_CPUSS_DW0_TR_IN83 = 101, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[83] 1789 CYHAL_TRIGGER_CPUSS_DW0_TR_IN84 = 102, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[84] 1790 CYHAL_TRIGGER_CPUSS_DW0_TR_IN85 = 103, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[85] 1791 CYHAL_TRIGGER_CPUSS_DW0_TR_IN86 = 104, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[86] 1792 CYHAL_TRIGGER_CPUSS_DW0_TR_IN87 = 105, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[87] 1793 CYHAL_TRIGGER_CPUSS_DW0_TR_IN88 = 106, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[88] 1794 CYHAL_TRIGGER_CPUSS_DW1_TR_IN0 = 107, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[0] 1795 CYHAL_TRIGGER_CPUSS_DW1_TR_IN1 = 108, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[1] 1796 CYHAL_TRIGGER_CPUSS_DW1_TR_IN2 = 109, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[2] 1797 CYHAL_TRIGGER_CPUSS_DW1_TR_IN3 = 110, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[3] 1798 CYHAL_TRIGGER_CPUSS_DW1_TR_IN4 = 111, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[4] 1799 CYHAL_TRIGGER_CPUSS_DW1_TR_IN5 = 112, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[5] 1800 CYHAL_TRIGGER_CPUSS_DW1_TR_IN6 = 113, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[6] 1801 CYHAL_TRIGGER_CPUSS_DW1_TR_IN7 = 114, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[7] 1802 CYHAL_TRIGGER_CPUSS_DW1_TR_IN8 = 115, //!< SCB DW Triggers - cpuss.dw1_tr_in[8] 1803 CYHAL_TRIGGER_CPUSS_DW1_TR_IN9 = 116, //!< SCB DW Triggers - cpuss.dw1_tr_in[9] 1804 CYHAL_TRIGGER_CPUSS_DW1_TR_IN10 = 117, //!< SCB DW Triggers - cpuss.dw1_tr_in[10] 1805 CYHAL_TRIGGER_CPUSS_DW1_TR_IN11 = 118, //!< SCB DW Triggers - cpuss.dw1_tr_in[11] 1806 CYHAL_TRIGGER_CPUSS_DW1_TR_IN12 = 119, //!< SCB DW Triggers - cpuss.dw1_tr_in[12] 1807 CYHAL_TRIGGER_CPUSS_DW1_TR_IN13 = 120, //!< SCB DW Triggers - cpuss.dw1_tr_in[13] 1808 CYHAL_TRIGGER_CPUSS_DW1_TR_IN14 = 121, //!< SCB DW Triggers - cpuss.dw1_tr_in[14] 1809 CYHAL_TRIGGER_CPUSS_DW1_TR_IN15 = 122, //!< SCB DW Triggers - cpuss.dw1_tr_in[15] 1810 CYHAL_TRIGGER_CPUSS_DW1_TR_IN16 = 123, //!< SCB DW Triggers - cpuss.dw1_tr_in[16] 1811 CYHAL_TRIGGER_CPUSS_DW1_TR_IN17 = 124, //!< SCB DW Triggers - cpuss.dw1_tr_in[17] 1812 CYHAL_TRIGGER_CPUSS_DW1_TR_IN18 = 125, //!< SCB DW Triggers - cpuss.dw1_tr_in[18] 1813 CYHAL_TRIGGER_CPUSS_DW1_TR_IN19 = 126, //!< SCB DW Triggers - cpuss.dw1_tr_in[19] 1814 CYHAL_TRIGGER_CPUSS_DW1_TR_IN20 = 127, //!< SCB DW Triggers - cpuss.dw1_tr_in[20] 1815 CYHAL_TRIGGER_CPUSS_DW1_TR_IN21 = 128, //!< SCB DW Triggers - cpuss.dw1_tr_in[21] 1816 CYHAL_TRIGGER_CPUSS_DW1_TR_IN22 = 129, //!< SCB DW Triggers - cpuss.dw1_tr_in[22] 1817 CYHAL_TRIGGER_CPUSS_DW1_TR_IN23 = 130, //!< SCB DW Triggers - cpuss.dw1_tr_in[23] 1818 CYHAL_TRIGGER_CPUSS_DW1_TR_IN24 = 131, //!< CAN DW1 triggers - cpuss.dw1_tr_in[24] 1819 CYHAL_TRIGGER_CPUSS_DW1_TR_IN25 = 132, //!< CAN DW1 triggers - cpuss.dw1_tr_in[25] 1820 CYHAL_TRIGGER_CPUSS_DW1_TR_IN26 = 133, //!< CAN DW1 triggers - cpuss.dw1_tr_in[26] 1821 CYHAL_TRIGGER_CPUSS_DW1_TR_IN27 = 134, //!< CAN DW1 triggers - cpuss.dw1_tr_in[27] 1822 CYHAL_TRIGGER_CPUSS_DW1_TR_IN28 = 135, //!< CAN DW1 triggers - cpuss.dw1_tr_in[28] 1823 CYHAL_TRIGGER_CPUSS_DW1_TR_IN29 = 136, //!< CAN DW1 triggers - cpuss.dw1_tr_in[29] 1824 CYHAL_TRIGGER_CPUSS_DW1_TR_IN30 = 137, //!< CAN DW1 triggers - cpuss.dw1_tr_in[30] 1825 CYHAL_TRIGGER_CPUSS_DW1_TR_IN31 = 138, //!< CAN DW1 triggers - cpuss.dw1_tr_in[31] 1826 CYHAL_TRIGGER_CPUSS_DW1_TR_IN32 = 139, //!< CAN DW1 triggers - cpuss.dw1_tr_in[32] 1827 CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER0 = 140, //!< TCPWM to LIN - lin[0].tr_cmd_tx_header[0] 1828 CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER1 = 141, //!< TCPWM to LIN - lin[0].tr_cmd_tx_header[1] 1829 CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER2 = 142, //!< TCPWM to LIN - lin[0].tr_cmd_tx_header[2] 1830 CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER3 = 143, //!< TCPWM to LIN - lin[0].tr_cmd_tx_header[3] 1831 CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER4 = 144, //!< TCPWM to LIN - lin[0].tr_cmd_tx_header[4] 1832 CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER5 = 145, //!< TCPWM to LIN - lin[0].tr_cmd_tx_header[5] 1833 CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER6 = 146, //!< TCPWM to LIN - lin[0].tr_cmd_tx_header[6] 1834 CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER7 = 147, //!< TCPWM to LIN - lin[0].tr_cmd_tx_header[7] 1835 CYHAL_TRIGGER_PASS0_TR_DEBUG_FREEZE = 148, //!< Debug Multiplexer - pass[0].tr_debug_freeze 1836 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN0 = 149, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[0] 1837 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN1 = 150, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[1] 1838 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN2 = 151, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[2] 1839 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN3 = 152, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[3] 1840 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN4 = 153, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[4] 1841 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN5 = 154, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[5] 1842 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN6 = 155, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[6] 1843 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN7 = 156, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[7] 1844 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN8 = 157, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[8] 1845 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN9 = 158, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[9] 1846 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN10 = 159, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[10] 1847 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN11 = 160, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[11] 1848 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN12 = 161, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[12] 1849 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN13 = 162, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[13] 1850 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN14 = 163, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[14] 1851 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN15 = 164, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[15] 1852 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN16 = 165, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[16] 1853 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN17 = 166, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[17] 1854 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN18 = 167, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[18] 1855 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN19 = 168, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[19] 1856 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN20 = 169, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[20] 1857 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN21 = 170, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[21] 1858 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN22 = 171, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[22] 1859 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN23 = 172, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[23] 1860 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN32 = 173, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[32] 1861 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN33 = 174, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[33] 1862 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN34 = 175, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[34] 1863 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN35 = 176, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[35] 1864 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN36 = 177, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[36] 1865 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN37 = 178, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[37] 1866 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN38 = 179, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[38] 1867 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN39 = 180, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[39] 1868 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN40 = 181, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[40] 1869 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN41 = 182, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[41] 1870 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN42 = 183, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[42] 1871 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN43 = 184, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[43] 1872 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN44 = 185, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[44] 1873 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN45 = 186, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[45] 1874 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN46 = 187, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[46] 1875 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN47 = 188, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[47] 1876 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN48 = 189, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[48] 1877 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN49 = 190, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[49] 1878 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN50 = 191, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[50] 1879 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN51 = 192, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[51] 1880 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN52 = 193, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[52] 1881 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN53 = 194, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[53] 1882 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN54 = 195, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[54] 1883 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN55 = 196, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[55] 1884 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN56 = 197, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[56] 1885 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN57 = 198, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[57] 1886 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN58 = 199, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[58] 1887 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN59 = 200, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[59] 1888 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN60 = 201, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[60] 1889 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN61 = 202, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[61] 1890 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN62 = 203, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[62] 1891 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN63 = 204, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[63] 1892 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN64 = 205, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[64] 1893 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN65 = 206, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[65] 1894 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN66 = 207, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[66] 1895 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN67 = 208, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[67] 1896 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN68 = 209, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[68] 1897 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN69 = 210, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[69] 1898 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN70 = 211, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[70] 1899 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN71 = 212, //!< PWM Group 0 to PASS direct connect - pass[0].tr_sar_ch_in[71] 1900 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN0 = 213, //!< PASS trigger multiplexer - pass[0].tr_sar_gen_in[0] 1901 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN1 = 214, //!< PASS trigger multiplexer - pass[0].tr_sar_gen_in[1] 1902 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN2 = 215, //!< PASS trigger multiplexer - pass[0].tr_sar_gen_in[2] 1903 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN3 = 216, //!< PASS trigger multiplexer - pass[0].tr_sar_gen_in[3] 1904 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN4 = 217, //!< PASS trigger multiplexer - pass[0].tr_sar_gen_in[4] 1905 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN5 = 218, //!< PASS trigger multiplexer - pass[0].tr_sar_gen_in[5] 1906 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN6 = 219, //!< PASS trigger multiplexer - pass[0].tr_sar_gen_in[6] 1907 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN7 = 220, //!< PASS trigger multiplexer - pass[0].tr_sar_gen_in[7] 1908 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN8 = 221, //!< PASS trigger multiplexer - pass[0].tr_sar_gen_in[8] 1909 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN9 = 222, //!< PASS trigger multiplexer - pass[0].tr_sar_gen_in[9] 1910 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN10 = 223, //!< PASS trigger multiplexer - pass[0].tr_sar_gen_in[10] 1911 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN11 = 224, //!< PASS trigger multiplexer - pass[0].tr_sar_gen_in[11] 1912 CYHAL_TRIGGER_PERI_TR_DBG_FREEZE = 225, //!< Debug Multiplexer - peri.tr_dbg_freeze 1913 CYHAL_TRIGGER_PERI_TR_IO_OUTPUT0 = 226, //!< Debug Multiplexer - peri.tr_io_output[0] 1914 CYHAL_TRIGGER_PERI_TR_IO_OUTPUT1 = 227, //!< Debug Multiplexer - peri.tr_io_output[1] 1915 CYHAL_TRIGGER_SRSS_TR_DEBUG_FREEZE_MCWDT0 = 228, //!< Debug Multiplexer - srss.tr_debug_freeze_mcwdt[0] 1916 CYHAL_TRIGGER_SRSS_TR_DEBUG_FREEZE_MCWDT1 = 229, //!< Debug Multiplexer - srss.tr_debug_freeze_mcwdt[1] 1917 CYHAL_TRIGGER_SRSS_TR_DEBUG_FREEZE_WDT = 230, //!< Debug Multiplexer - srss.tr_debug_freeze_wdt 1918 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN0 = 231, //!< TCPWM loopback mux - tcpwm[0].tr_all_cnt_in[0] 1919 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN1 = 232, //!< TCPWM loopback mux - tcpwm[0].tr_all_cnt_in[1] 1920 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN2 = 233, //!< TCPWM loopback mux - tcpwm[0].tr_all_cnt_in[2] 1921 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN3 = 234, //!< TCPWM loopback mux - tcpwm[0].tr_all_cnt_in[3] 1922 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN4 = 235, //!< TCPWM loopback mux - tcpwm[0].tr_all_cnt_in[4] 1923 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN5 = 236, //!< TCPWM loopback mux - tcpwm[0].tr_all_cnt_in[5] 1924 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN6 = 237, //!< TCPWM loopback mux - tcpwm[0].tr_all_cnt_in[6] 1925 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN7 = 238, //!< TCPWM loopback mux - tcpwm[0].tr_all_cnt_in[7] 1926 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN8 = 239, //!< TCPWM loopback mux - tcpwm[0].tr_all_cnt_in[8] 1927 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN9 = 240, //!< TCPWM loopback mux - tcpwm[0].tr_all_cnt_in[9] 1928 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN10 = 241, //!< TCPWM loopback mux - tcpwm[0].tr_all_cnt_in[10] 1929 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN11 = 242, //!< TCPWM loopback mux - tcpwm[0].tr_all_cnt_in[11] 1930 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN12 = 243, //!< TCPWM loopback mux - tcpwm[0].tr_all_cnt_in[12] 1931 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN13 = 244, //!< TCPWM loopback mux - tcpwm[0].tr_all_cnt_in[13] 1932 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN14 = 245, //!< TCPWM loopback mux - tcpwm[0].tr_all_cnt_in[14] 1933 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN15 = 246, //!< TCPWM loopback mux - tcpwm[0].tr_all_cnt_in[15] 1934 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN16 = 247, //!< TCPWM Trigger Multiplexer - tcpwm[0].tr_all_cnt_in[16] 1935 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN17 = 248, //!< TCPWM Trigger Multiplexer - tcpwm[0].tr_all_cnt_in[17] 1936 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN18 = 249, //!< TCPWM Trigger Multiplexer - tcpwm[0].tr_all_cnt_in[18] 1937 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN19 = 250, //!< TCPWM Trigger Multiplexer - tcpwm[0].tr_all_cnt_in[19] 1938 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN20 = 251, //!< TCPWM Trigger Multiplexer - tcpwm[0].tr_all_cnt_in[20] 1939 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN21 = 252, //!< TCPWM Trigger Multiplexer - tcpwm[0].tr_all_cnt_in[21] 1940 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN22 = 253, //!< TCPWM Trigger Multiplexer - tcpwm[0].tr_all_cnt_in[22] 1941 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN23 = 254, //!< TCPWM Trigger Multiplexer - tcpwm[0].tr_all_cnt_in[23] 1942 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN24 = 255, //!< TCPWM Trigger Multiplexer - tcpwm[0].tr_all_cnt_in[24] 1943 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN25 = 256, //!< TCPWM Trigger Multiplexer - tcpwm[0].tr_all_cnt_in[25] 1944 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN26 = 257, //!< TCPWM Trigger Multiplexer - tcpwm[0].tr_all_cnt_in[26] 1945 CYHAL_TRIGGER_TCPWM0_TR_DEBUG_FREEZE = 258, //!< Debug Multiplexer - tcpwm[0].tr_debug_freeze 1946 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN2 = 259, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[2] 1947 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN5 = 260, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[5] 1948 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN8 = 261, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[8] 1949 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN11 = 262, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[11] 1950 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN14 = 263, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[14] 1951 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN17 = 264, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[17] 1952 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN20 = 265, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[20] 1953 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN23 = 266, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[23] 1954 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN26 = 267, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[26] 1955 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN29 = 268, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[29] 1956 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN32 = 269, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[32] 1957 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN35 = 270, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[35] 1958 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN38 = 271, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[38] 1959 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN41 = 272, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[41] 1960 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN44 = 273, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[44] 1961 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN47 = 274, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[47] 1962 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN50 = 275, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[50] 1963 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN53 = 276, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[53] 1964 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN56 = 277, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[56] 1965 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN59 = 278, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[59] 1966 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN62 = 279, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[62] 1967 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN65 = 280, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[65] 1968 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN68 = 281, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[68] 1969 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN71 = 282, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[71] 1970 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN74 = 283, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[74] 1971 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN77 = 284, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[77] 1972 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN80 = 285, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[80] 1973 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN83 = 286, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[83] 1974 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN86 = 287, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[86] 1975 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN89 = 288, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[89] 1976 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN92 = 289, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[92] 1977 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN95 = 290, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[95] 1978 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN98 = 291, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[98] 1979 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN101 = 292, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[101] 1980 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN104 = 293, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[104] 1981 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN107 = 294, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[107] 1982 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN110 = 295, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[110] 1983 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN113 = 296, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[113] 1984 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN116 = 297, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[116] 1985 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN119 = 298, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[119] 1986 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN122 = 299, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[122] 1987 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN125 = 300, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[125] 1988 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN128 = 301, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[128] 1989 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN131 = 302, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[131] 1990 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN134 = 303, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[134] 1991 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN137 = 304, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[137] 1992 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN140 = 305, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[140] 1993 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN143 = 306, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[143] 1994 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN146 = 307, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[146] 1995 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN149 = 308, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[149] 1996 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN152 = 309, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[152] 1997 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN155 = 310, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[155] 1998 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN770 = 311, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[770] 1999 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN773 = 312, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[773] 2000 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN776 = 313, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[776] 2001 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN779 = 314, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[779] 2002 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN782 = 315, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[782] 2003 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN785 = 316, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[785] 2004 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN788 = 317, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[788] 2005 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN791 = 318, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[791] 2006 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN794 = 319, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[794] 2007 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN797 = 320, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[797] 2008 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN800 = 321, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[800] 2009 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN803 = 322, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[803] 2010 CYHAL_TRIGGER_TR_GROUP8_INPUT1 = 323, //!< Debug Reduction #1 - tr_group[8].input[1] 2011 CYHAL_TRIGGER_TR_GROUP8_INPUT2 = 324, //!< Debug Reduction #1 - tr_group[8].input[2] 2012 CYHAL_TRIGGER_TR_GROUP8_INPUT3 = 325, //!< Debug Reduction #1 - tr_group[8].input[3] 2013 CYHAL_TRIGGER_TR_GROUP8_INPUT4 = 326, //!< Debug Reduction #1 - tr_group[8].input[4] 2014 CYHAL_TRIGGER_TR_GROUP8_INPUT5 = 327, //!< Debug Reduction #1 - tr_group[8].input[5] 2015 CYHAL_TRIGGER_TR_GROUP8_INPUT6 = 328, //!< Debug Reduction #2 - tr_group[8].input[6] 2016 CYHAL_TRIGGER_TR_GROUP8_INPUT7 = 329, //!< Debug Reduction #2 - tr_group[8].input[7] 2017 CYHAL_TRIGGER_TR_GROUP8_INPUT8 = 330, //!< Debug Reduction #2 - tr_group[8].input[8] 2018 CYHAL_TRIGGER_TR_GROUP8_INPUT9 = 331, //!< Debug Reduction #2 - tr_group[8].input[9] 2019 CYHAL_TRIGGER_TR_GROUP8_INPUT10 = 332, //!< Debug Reduction #2 - tr_group[8].input[10] 2020 } cyhal_trigger_dest_tviibe1m_t; 2021 2022 /** Typedef from device family specific trigger dest to generic trigger dest */ 2023 typedef cyhal_trigger_dest_tviibe1m_t cyhal_dest_t; 2024 2025 /** \cond INTERNAL */ 2026 /** Table of number of inputs to each mux. */ 2027 extern const uint16_t cyhal_sources_per_mux[20]; 2028 2029 /** Table indicating whether mux is 1to1. */ 2030 extern const bool cyhal_is_mux_1to1[20]; 2031 2032 /** Table pointing to each mux source table. The index of each source in the table is its mux input index. */ 2033 extern const _cyhal_trigger_source_tviibe1m_t* cyhal_mux_to_sources [20]; 2034 2035 /** Maps each cyhal_destination_t to a mux index. 2036 * If bit 8 of the mux index is set, this denotes that the trigger is a 2037 * one to one trigger. 2038 */ 2039 extern const uint8_t cyhal_dest_to_mux[333]; 2040 2041 /* Maps each cyhal_destination_t to a specific output in its mux */ 2042 extern const uint8_t cyhal_mux_dest_index[333]; 2043 /** \endcond */ 2044 2045 #if defined(__cplusplus) 2046 } 2047 #endif /* __cplusplus */ 2048 /** \} group_hal_impl_triggers_tviibe1m */ 2049 #endif /* _CYHAL_TRIGGERS_TVIIBE1M_H_ */ 2050 2051 2052 /* [] END OF FILE */ 2053
