1 /*
2 * Copyright (c) 2001-2019, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <stdint.h>
8 #include <stdlib.h>
9 #include <stdio.h>
10 #include <stdbool.h>
11 #include <string.h>
12
13 #include "test_proj.h"
14 #include "test_proj_defs.h"
15 #include "test_pal_time.h"
16 #include "test_pal_log.h"
17
18 #include "dx_id_registers.h"
19
Test_ProjCheckLcs(uint32_t nextLcs)20 uint32_t Test_ProjCheckLcs(uint32_t nextLcs)
21 {
22 uint32_t regVal = 0;
23
24 /* poll NVM register to be assure that the NVM boot is finished (and LCS and the keys are valid) */
25 WAIT_NVM_IDLE();
26
27 /* Read the LCS register */
28 regVal = TEST_READ_TEE_CC_REG(CC_REG_OFFSET(HOST_RGF, LCS_REG));
29 regVal = CC_REG_FLD_GET(0, LCS_REG, LCS_REG, regVal);
30
31 /* Verify lcs */
32 if(regVal != nextLcs) {
33 TEST_PRINTF_ERROR("actual LCS %d != expected LCS %d", regVal, nextLcs);
34 return TEST_COMPARE_ERR;
35 }
36
37 return TEST_OK;
38 }
39
40
Test_ProjCheckLcsAndError(uint32_t nextLcs)41 uint32_t Test_ProjCheckLcsAndError(uint32_t nextLcs)
42 {
43 uint32_t regVal = 0;
44
45 /* poll NVM register to be assure that the NVM boot is finished (and LCS and the keys are valid) */
46 WAIT_NVM_IDLE();
47
48 /* Read the LCS register */
49 regVal = TEST_READ_TEE_CC_REG(CC_REG_OFFSET(HOST_RGF, LCS_REG));
50 regVal = CC_REG_FLD_GET(0, LCS_REG, LCS_REG, regVal);
51
52 /* Verify lcs */
53 if(regVal != nextLcs) {
54 TEST_PRINTF_ERROR("actual LCS %d != expected LCS %d", regVal, nextLcs);
55 return TEST_COMPARE_ERR;
56 }
57
58 if ((CC_REG_FLD_GET(0, LCS_REG, ERROR_KDR_ZERO_CNT, regVal) != 0) ||
59 (CC_REG_FLD_GET(0, LCS_REG, ERROR_KPICV_ZERO_CNT, regVal) != 0) ||
60 (CC_REG_FLD_GET(0, LCS_REG, ERROR_KCEICV_ZERO_CNT, regVal) != 0) ||
61 (CC_REG_FLD_GET(0, LCS_REG, ERROR_PROV_ZERO_CNT, regVal) != 0) ||
62 (CC_REG_FLD_GET(0, LCS_REG, ERROR_KCE_ZERO_CNT, regVal) != 0)) {
63 TEST_PRINTF_ERROR("regVal 0x%x indicates error for LCS %d", regVal, nextLcs);
64 return TEST_HW_FAIL_ERR;
65 }
66
67 return TEST_OK;
68 }
69
70
Test_ProjGetLcs(uint32_t * lcs)71 uint32_t Test_ProjGetLcs(uint32_t *lcs)
72 {
73 uint32_t regVal = 0;
74
75 /* poll NVM register to be assure that the NVM boot is finished (and LCS and the keys are valid) */
76 WAIT_NVM_IDLE();
77
78 /* Read the LCS register */
79 regVal = TEST_READ_TEE_CC_REG(CC_REG_OFFSET(HOST_RGF, LCS_REG));
80 regVal = CC_REG_FLD_GET(0, LCS_REG, LCS_REG, regVal);
81
82 *lcs = regVal;
83
84 return TEST_OK;
85 }
86 /* Global Reset of CC and AO and env regs */
Test_ProjPerformPowerOnReset(void)87 void Test_ProjPerformPowerOnReset(void)
88 {
89 TEST_WRITE_TEE_ENV_REG(DX_ENV_CC_POR_N_ADDR_REG_OFFSET , 0x1UL);
90 Test_PalDelay(1000);
91
92 /* poll NVM register to assure that the NVM boot is finished (and LCS and the keys are valid) */
93 WAIT_NVM_IDLE();
94
95 #ifdef BIG__ENDIAN
96 /* Set DMA endianess to big */
97 TEST_WRITE_TEE_CC_REG(CC_REG_OFFSET(HOST_RGF, HOST_ENDIAN) , 0xCCUL);
98 #else /* LITTLE__ENDIAN */
99 TEST_WRITE_TEE_CC_REG(CC_REG_OFFSET(HOST_RGF, HOST_ENDIAN) , 0x00UL);
100 #endif
101
102 /* turn off the DFA since Cerberus doesn't support it */
103 TURN_DFA_OFF();
104 return;
105
106 }
107
108
109 /* Reset both CC and AO regs */
Test_ProjPerformColdReset(void)110 void Test_ProjPerformColdReset(void)
111 {
112 TEST_WRITE_TEE_ENV_REG(DX_ENV_CC_COLD_RST_REG_OFFSET , 0x1UL);
113 Test_PalDelay(1000);
114
115 #ifdef BIG__ENDIAN
116 /* Set DMA endianess to big */
117 TEST_WRITE_TEE_CC_REG(CC_REG_OFFSET(HOST_RGF, HOST_ENDIAN) , 0xCCUL);
118 #else /* LITTLE__ENDIAN */
119 TEST_WRITE_TEE_CC_REG(CC_REG_OFFSET(HOST_RGF, HOST_ENDIAN) , 0x00UL);
120 #endif
121 /* turn off the DFA since Cerberus doesn't support it */
122 TURN_DFA_OFF();
123 return;
124 }
125
126
127 /* Reset only CC regs */
Test_ProjPerformWarmReset(void)128 void Test_ProjPerformWarmReset(void)
129 {
130 TEST_WRITE_TEE_ENV_REG(DX_ENV_CC_RST_N_REG_OFFSET , 0x1UL);
131 Test_PalDelay(1000);
132
133 #ifdef BIG__ENDIAN
134 /* Set DMA endianess to big */
135 TEST_WRITE_TEE_CC_REG(CC_REG_OFFSET(HOST_RGF, HOST_ENDIAN) , 0xCCUL);
136 #else /* LITTLE__ENDIAN */
137 TEST_WRITE_TEE_CC_REG(CC_REG_OFFSET(HOST_RGF, HOST_ENDIAN) , 0x00UL);
138 #endif
139 return;
140
141 }
142
Test_ProjVerifyPIDReg(void)143 uint32_t Test_ProjVerifyPIDReg(void)
144 {
145 uint32_t i = 0;
146 uint32_t pidReg = 0;
147 uint32_t pidValTable[TEST_PID_SIZE_WORDS][2] = {
148 {DX_PERIPHERAL_ID_0_REG_OFFSET, TEST_PID_0_VAL},
149 {DX_PERIPHERAL_ID_1_REG_OFFSET, TEST_PID_1_VAL},
150 {DX_PERIPHERAL_ID_2_REG_OFFSET, TEST_PID_2_VAL},
151 {DX_PERIPHERAL_ID_3_REG_OFFSET, TEST_PID_3_VAL},
152 {DX_PERIPHERAL_ID_4_REG_OFFSET, TEST_PID_4_VAL},
153 };
154
155
156 /* verify peripheral ID (PIDR) */
157 for (i=0; i<TEST_PID_SIZE_WORDS; i++) {
158 pidReg = TEST_READ_TEE_CC_REG(pidValTable[i][0]);
159 if (pidReg != pidValTable[i][1]) {
160 TEST_PRINTF_ERROR("ERROR: verify peripheral ID (PIDR) "
161 "%d value=0x%08x expected 0x%08x\n", i,
162 pidReg, pidValTable[i][1]);
163 return 1;
164 }
165 }
166 return 0;
167 }
168 /******************************************************************************/
Test_ProjVerifyCIDReg(void)169 uint32_t Test_ProjVerifyCIDReg(void)
170 {
171 uint32_t i =0;
172 uint32_t cidReg = 0;
173
174 uint32_t cidValTable[TEST_CID_SIZE_WORDS][2] = {
175 {DX_COMPONENT_ID_0_REG_OFFSET, TEST_CID_0_VAL},
176 {DX_COMPONENT_ID_1_REG_OFFSET, TEST_CID_1_VAL},
177 {DX_COMPONENT_ID_2_REG_OFFSET, TEST_CID_2_VAL},
178 {DX_COMPONENT_ID_3_REG_OFFSET, TEST_CID_3_VAL},
179 };
180
181 /* verify component ID (CIDR) */
182 for (i=0; i<TEST_CID_SIZE_WORDS; i++) {
183 cidReg = TEST_READ_TEE_CC_REG(cidValTable[i][0]);
184 if (cidReg != cidValTable[i][1]) {
185 TEST_PRINTF_ERROR("ERROR: verify component ID (CIDR) "
186 "%d value=0x%08x expected 0x%08x", i,
187 cidReg, cidValTable[i][1]);
188 return 1;
189 }
190 }
191 return 0;
192 }
193
194
