1<?xml version="1.0" encoding="utf-8"?> 2 3 4<!--**************************************************************************** 5* \file tdm.cypersonality 6* \version 1.1 7* 8* \brief 9* TDM personality description file. It Supports CAT1B family of devices. 10* 11* 12******************************************************************************** 13* \copyright 14* Copyright (c) (2022), Cypress Semiconductor Corporation (an Infineon company) or 15* an affiliate of Cypress Semiconductor Corporation. 16* SPDX-License-Identifier: Apache-2.0 17* 18* Licensed under the Apache License, Version 2.0 (the "License"); 19* you may not use this file except in compliance with the License. 20* You may obtain a copy of the License at 21* 22* http://www.apache.org/licenses/LICENSE-2.0 23* 24* Unless required by applicable law or agreed to in writing, software 25* distributed under the License is distributed on an "AS IS" BASIS, 26* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 27* See the License for the specific language governing permissions and 28* limitations under the License. 29*****************************************************************************--> 30 31<Personality id="tdm" name="TDM" version="1.1" xmlns="http://cypress.com/xsd/cyhwpersonality_v7"> 32 <Dependencies> 33 <IpBlock name="mxtdm" /> 34 <Resource name="tdm" /> 35 </Dependencies> 36 <ExposedMembers /> 37 <Parameters> 38 <!-- PDL documentation --> 39 <ParamDoc id="pdlDoc" name="Configuration Help" group="Overview" default="file:///`${cy_libs_path()}`/docs/pdl_api_reference_manual/html/group__group__tdm.html" linkText="Open TDM Documentation" visible="true" desc="Opens the Peripheral Driver Library Documentation" /> 40 41 <!-- TX --> 42 <ParamBool id="txEnabled" name="Enable" group="TX" default="true" visible="true" editable="true" desc="Enables the transmitter" /> 43 <ParamChoice id="txMode" name="Mode" group="TX" default="CY_TDM_DEVICE_MASTER" visible="`${txEnabled}`" editable="true" desc="Sets mode to master or slave"> 44 <Entry name="Slave" value="CY_TDM_DEVICE_SLAVE" visible="true" /> 45 <Entry name="Master" value="CY_TDM_DEVICE_MASTER" visible="true" /> 46 </ParamChoice> 47 48 <ParamChoice id="txclockselect" name="Clock Select" group="TX" default="CY_TDM_SEL_SRSS_CLK0" visible="`${txEnabled}`" editable="true" desc="Set interface source clock: SRSS[0], SRSS[1], SRSS[2], SRSS[3], MCLK_IN"> 49 <Entry name="Interface Clock 0" value="CY_TDM_SEL_SRSS_CLK0" visible="true" /> 50 <Entry name="Interface Clock 1" value="CY_TDM_SEL_SRSS_CLK1" visible="false" /> 51 <Entry name="Interface Clock 2" value="CY_TDM_SEL_SRSS_CLK2" visible="false" /> 52 <Entry name="Interface Clock 3" value="CY_TDM_SEL_SRSS_CLK3" visible="false" /> 53 <Entry name="Interface Clock MCLK" value="CY_TDM_SEL_MCLK_IN" visible="true" /> 54 </ParamChoice> 55 <ParamRange id="txclockDiv" name="Clock Divider" group="TX" default="16" min="1" max="256" resolution="1" visible="`${txEnabled}`" editable="true" desc="Sets the input Clock Divider. Set to an even value ({2, 4, 6, ..., 256}), to ensure a 50/50% duty cycle clock." /> 56 57 <ParamChoice id="txInterfaceMode" name="Interface Mode" group="TX" default="true" visible="false" editable="false" desc="Set interface transfer mode: I2S mode, TDM mode"> 58 <Entry name="I2S mode" value="true" visible="true" /> 59 <Entry name="TDM mode" value="false" visible="true" /> 60 </ParamChoice> 61 62 <ParamChoice id="txAlignment" name="Alignment Format" group="TX" default="CY_TDM_LEFT_DELAYED" visible="`${txEnabled}`" editable="true" desc="Set Alignment format: CY_TDM_LEFT_DELAYED, CY_TDM_LEFT, CY_TDM_RIGHT_DELAYED, CY_TDM_RIGHT"> 63 <Entry name="Left-aligned delayed" value="CY_TDM_LEFT_DELAYED" visible="true" /> 64 <Entry name="Left-aligned" value="CY_TDM_LEFT" visible="true" /> 65 <Entry name="Right-aligned delayed" value="CY_TDM_RIGHT_DELAYED" visible="true" /> 66 <Entry name="Right-aligned" value="CY_TDM_RIGHT" visible="true" /> 67 </ParamChoice> 68 69 <ParamChoice id="txsyncformat" name="Frame Sync" group="TX" default="CY_TDM_BIT_PERIOD" visible="`${txEnabled}`" editable="true" desc="Set interface transfer mode: CY_TDM_BIT_PERIOD, CY_TDM_CH_PERIOD"> 70 <Entry name="Single Bit" value="CY_TDM_BIT_PERIOD" visible="true" /> 71 <Entry name="Channel Length" value="CY_TDM_CH_PERIOD" visible="true" /> 72 </ParamChoice> 73 74 <ParamRange id="txChannels" name="Channels" group="TX" default="2" min="1" max="8" resolution="1" visible="`${txEnabled}`" editable="true" desc="Number of channels per frame (2 is the only valid value for Left Justified and I2S modes)" /> 75 76 <ParamChoice id="txChannelsEnabled" name="Channels Enabled" group="TX" default="0x3" visible="`${!txInterfaceMode && txEnabled}`" editable="true" desc="Set channels enabled (Total 8 Channels can be enabled)"> 77 <Entry name="1" value="0x1" visible="true" /> 78 <Entry name="2" value="0x3" visible="true" /> 79 <Entry name="3" value="0x7" visible="true" /> 80 <Entry name="4" value="0xF" visible="true" /> 81 <Entry name="5" value="0x1F" visible="true" /> 82 <Entry name="6" value="0x3F" visible="true" /> 83 <Entry name="7" value="0x7F" visible="true" /> 84 <Entry name="8" value="0xFF" visible="true" /> 85 </ParamChoice> 86 87 <ParamChoice id="txChannelLength" name="Channel Size" group="TX" default="16" visible="`${!txInterfaceMode && txEnabled}`" editable="true" desc="Set channel length in bits (32 bit is the only valid value for TDM modes)"> 88 <Entry name="8" value="8" visible="true" /> 89 <Entry name="16" value="16" visible="true" /> 90 <Entry name="18" value="18" visible="true" /> 91 <Entry name="20" value="20" visible="true" /> 92 <Entry name="24" value="24" visible="true" /> 93 <Entry name="32" value="32" visible="true" /> 94 </ParamChoice> 95 <ParamChoice id="txWordLength" name="Word Size" group="TX" default="16" visible="`${!txInterfaceMode && txEnabled}`" editable="true" desc="Set word length (in bits)"> 96 <Entry name="8" value="8" visible="true" /> 97 <Entry name="16" value="16" visible="true" /> 98 <Entry name="18" value="18" visible="true" /> 99 <Entry name="20" value="20" visible="true" /> 100 <Entry name="24" value="24" visible="true" /> 101 <Entry name="32" value="32" visible="true" /> 102 </ParamChoice> 103 104 <ParamChoice id="txsignalInput" name="Signal Input" group="TX" default="0" visible="false" editable="true" desc="Controls routing to the TX slave signalling inputs (FSYNC/SCK):'0': TX slave signaling independent from RX signaling: '1': TX slave signalling inputs driven by RX Slave: '2': TX slave signalling inputs driven by RX Master:"> 105 <Entry name="0" value="0" visible="true" /> 106 <Entry name="1" value="1" visible="true" /> 107 <Entry name="2" value="2" visible="true" /> 108 </ParamChoice> 109 110 <ParamChoice id="txsyncFormatPolarity" name="Sync Format Polarity" group="TX" default="CY_TDM_SIGN" visible="`${txEnabled}`" editable="true" desc="Channel synchronization polarity"> 111 <Entry name="Normal" value="CY_TDM_SIGN" visible="true" /> 112 <Entry name="Inverted" value="CY_TDM_SIGN_INVERTED" visible="true" /> 113 </ParamChoice> 114 <ParamChoice id="txSckoPolarity" name="Output Serial Clock Polarity" group="TX" default="CY_TDM_CLK" visible="`${txEnabled}`" editable="true" desc="Polarity of the output SCK signal (available only in master mode)"> 115 <Entry name="Normal" value="CY_TDM_CLK" visible="true" /> 116 <Entry name="Inverted" value="CY_TDM_CLK_INVERTED" visible="true" /> 117 </ParamChoice> 118 <ParamRange id="txFifoTriggerLevel" name="FIFO Trigger Level" group="TX" default="0" min="0" max="255" resolution="1" visible="`${txEnabled}`" editable="true" desc="Set FIFO level to trigger an event (interrupt or DMA request)." /> 119 <ParamBool id="txDmaTrigger" name="DMA Trigger" group="TX" default="false" visible="`${txEnabled}`" editable="true" desc="Enables DMA trigger" /> 120 121 <!-- RX --> 122 <ParamBool id="rxEnabled" name="Enable" group="RX" default="true" visible="true" editable="true" desc="Enables the receiver" /> 123 <ParamChoice id="rxMode" name="Mode" group="RX" default="CY_TDM_DEVICE_SLAVE" visible="`${rxEnabled}`" editable="true" desc="Sets mode to master or slave"> 124 <Entry name="Slave" value="CY_TDM_DEVICE_SLAVE" visible="true" /> 125 <Entry name="Master" value="CY_TDM_DEVICE_MASTER" visible="true" /> 126 </ParamChoice> 127 128 <ParamChoice id="rxclockselect" name="Clock Select" group="RX" default="CY_TDM_SEL_SRSS_CLK0" visible="`${rxEnabled}`" editable="true" desc="Set interface source clock: SRSS[0], SRSS[1], SRSS[2], SRSS[3], MCLK_IN"> 129 <Entry name="Interface Clock 0" value="CY_TDM_SEL_SRSS_CLK0" visible="true" /> 130 <Entry name="Interface Clock 1" value="CY_TDM_SEL_SRSS_CLK1" visible="false" /> 131 <Entry name="Interface Clock 2" value="CY_TDM_SEL_SRSS_CLK2" visible="false" /> 132 <Entry name="Interface Clock 3" value="CY_TDM_SEL_SRSS_CLK3" visible="false" /> 133 <Entry name="Interface Clock MCLK" value="CY_TDM_SEL_MCLK_IN" visible="true" /> 134 </ParamChoice> 135 <ParamRange id="rxclockDiv" name="Clock Divider" group="RX" default="16" min="1" max="256" resolution="1" visible="`${rxEnabled}`" editable="true" desc="Sets the input Clock Divider. Set to an even value ({2, 4, 6, ..., 256}), to ensure a 50/50% duty cycle clock." /> 136 137 <ParamChoice id="rxInterfaceMode" name="Interface Mode" group="RX" default="true" visible="false" editable="false" desc="Set interface transfer mode: I2S mode, TDM mode"> 138 <Entry name="I2S mode" value="true" visible="true" /> 139 <Entry name="TDM mode" value="false" visible="true" /> 140 </ParamChoice> 141 142 <ParamChoice id="rxAlignment" name="Alignment Format" group="RX" default="CY_TDM_LEFT_DELAYED" visible="`${rxEnabled}`" editable="true" desc="Set Alignment format: CY_TDM_LEFT_DELAYED, CY_TDM_LEFT, CY_TDM_RIGHT_DELAYED, CY_TDM_RIGHT"> 143 <Entry name="Left-aligned delayed" value="CY_TDM_LEFT_DELAYED" visible="true" /> 144 <Entry name="Left-aligned" value="CY_TDM_LEFT" visible="true" /> 145 <Entry name="Right-aligned delayed" value="CY_TDM_RIGHT_DELAYED" visible="true" /> 146 <Entry name="Right-aligned" value="CY_TDM_RIGHT" visible="true" /> 147 </ParamChoice> 148 149 <ParamChoice id="rxsyncformat" name="Frame Sync" group="RX" default="CY_TDM_BIT_PERIOD" visible="`${rxEnabled}`" editable="true" desc="Set interface transfer mode: CY_TDM_BIT_PERIOD, CY_TDM_CH_PERIOD"> 150 <Entry name="Single Bit" value="CY_TDM_BIT_PERIOD" visible="true" /> 151 <Entry name="Channel Length" value="CY_TDM_CH_PERIOD" visible="true" /> 152 </ParamChoice> 153 154 <ParamRange id="rxChannels" name="Channels" group="RX" default="2" min="1" max="8" resolution="1" visible="`${rxEnabled}`" editable="true" desc="Number of channels per frame (2 is the only valid value for Left Justified and I2S modes)" /> 155 156 <ParamChoice id="rxChannelsEnabled" name="Channels Enabled" group="RX" default="0x3" visible="`${!rxInterfaceMode && rxEnabled}`" editable="true" desc="Set channels enabled (Total 8 Channels can be enabled)"> 157 <Entry name="1" value="0x1" visible="true" /> 158 <Entry name="2" value="0x3" visible="true" /> 159 <Entry name="3" value="0x7" visible="true" /> 160 <Entry name="4" value="0xF" visible="true" /> 161 <Entry name="5" value="0x1F" visible="true" /> 162 <Entry name="6" value="0x3F" visible="true" /> 163 <Entry name="7" value="0x7F" visible="true" /> 164 <Entry name="8" value="0xFF" visible="true" /> 165 </ParamChoice> 166 167 <ParamChoice id="rxChannelLength" name="Channel Size" group="RX" default="16" visible="`${!rxInterfaceMode && rxEnabled}`" editable="true" desc="Set channel length in bits (32 bit is the only valid value for TDM modes)"> 168 <Entry name="8" value="8" visible="true" /> 169 <Entry name="16" value="16" visible="true" /> 170 <Entry name="18" value="18" visible="true" /> 171 <Entry name="20" value="20" visible="true" /> 172 <Entry name="24" value="24" visible="true" /> 173 <Entry name="32" value="32" visible="true" /> 174 </ParamChoice> 175 <ParamChoice id="rxWordLength" name="Word Size" group="RX" default="16" visible="`${!rxInterfaceMode && rxEnabled}`" editable="true" desc="Set word length (in bits)"> 176 <Entry name="8" value="8" visible="true" /> 177 <Entry name="16" value="16" visible="true" /> 178 <Entry name="18" value="18" visible="true" /> 179 <Entry name="20" value="20" visible="true" /> 180 <Entry name="24" value="24" visible="true" /> 181 <Entry name="32" value="32" visible="true" /> 182 </ParamChoice> 183 184 <ParamChoice id="rxsignalInput" name="Signal Input" group="RX" default="0" visible="false" editable="true" desc="Controls routing to the RX slave signalling inputs (FSYNC/SCK):'0': RX slave signaling independent from TX signaling: '1': RX slave signalling inputs driven by TX Slave: '2': RX slave signalling inputs driven by TX Master:"> 185 <Entry name="0" value="0" visible="true" /> 186 <Entry name="1" value="1" visible="true" /> 187 <Entry name="2" value="2" visible="true" /> 188 </ParamChoice> 189 190 <ParamChoice id="rxsignExtended" name="Word Extension" group="RX" default="CY_ZERO_EXTEND" visible="`${rxEnabled}`" editable="true" desc="Set Word Extension mode: ZERO EXTEND, SIGN EXTEND"> 191 <Entry name="ZERO EXTEND" value="CY_ZERO_EXTEND" visible="true" /> 192 <Entry name="SIGN EXTEND" value="CY_SIGN_EXTEND" visible="true" /> 193 </ParamChoice> 194 195 <ParamChoice id="rxlateSample" name="Sample On" group="RX" default="false" visible="`${rxEnabled}`" editable="true" desc="Sample PCM bit value on rising edge or falling edge of receiver."> 196 <Entry name="Sample on Rising Edge" value="false" visible="true" /> 197 <Entry name="Sample on Falling Edge" value="true" visible="true" /> 198 </ParamChoice> 199 200 <ParamChoice id="rxsyncFormatPolarity" name="Sync Format Polarity" group="RX" default="CY_TDM_SIGN" visible="`${rxEnabled}`" editable="true" desc="Channel synchronization polarity"> 201 <Entry name="Normal" value="CY_TDM_SIGN" visible="true" /> 202 <Entry name="Inverted" value="CY_TDM_SIGN_INVERTED" visible="true" /> 203 </ParamChoice> 204 <ParamChoice id="rxSckoPolarity" name="Output Serial Clock Polarity" group="RX" default="CY_TDM_CLK" visible="`${rxEnabled}`" editable="true" desc="Polarity of the output SCK signal (available only in master mode)"> 205 <Entry name="Normal" value="CY_TDM_CLK" visible="true" /> 206 <Entry name="Inverted" value="CY_TDM_CLK_INVERTED" visible="true" /> 207 </ParamChoice> 208 <ParamRange id="rxFifoTriggerLevel" name="FIFO Trigger Level" group="RX" default="0" min="0" max="`${255 - rxChannels}`" resolution="1" visible="`${rxEnabled}`" editable="true" desc="Set FIFO level to trigger an event (interrupt or DMA request). Should not be greater than [255 - (number of channels)]." /> 209 <ParamBool id="rxDmaTrigger" name="DMA Trigger" group="RX" default="false" visible="`${rxEnabled}`" editable="true" desc="Enables DMA trigger" /> 210 211 <!-- Connections --> 212 213 <ParamSignal port="tdm_tx_sck[0]" name="Tx Serial Clock" group="`${(txMode eq CY_TDM_DEVICE_MASTER) ? "Outputs" : "Inputs"}`" visible="`${txEnabled}`" desc="Tx serial clock (visible when Tx is enabled)." canBeEmpty="`${(txMode eq CY_TDM_DEVICE_MASTER) || !txEnabled}`" > 214 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 215 <Parameter id="DriveModes" severity="ERROR" reason=""> 216 <Fixed value="`${(txMode eq CY_TDM_DEVICE_MASTER) ? "CY_GPIO_DM_STRONG_IN_OFF" : "CY_GPIO_DM_HIGHZ"}`" /> 217 </Parameter> 218 </Constraint> 219 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 220 </ParamSignal> 221 <ParamSignal port="tdm_tx_fsync[0]" name="Tx Word Select" group="`${(txMode eq CY_TDM_DEVICE_MASTER) ? "Outputs" : "Inputs"}`" visible="`${txEnabled}`" desc="Tx word select (visible when Tx is enabled)." canBeEmpty="`${(txMode eq CY_TDM_DEVICE_MASTER) || !txEnabled}`" > 222 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 223 <Parameter id="DriveModes" severity="ERROR" reason=""> 224 <Fixed value="`${(txMode eq CY_TDM_DEVICE_MASTER) ? "CY_GPIO_DM_STRONG_IN_OFF" : "CY_GPIO_DM_HIGHZ"}`" /> 225 </Parameter> 226 </Constraint> 227 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 228 </ParamSignal> 229 <ParamSignal port="tdm_tx_sd[0]" name="Tx Serial Data" group="Outputs" visible="`${txEnabled}`" desc="Tx serial data output (visible when Tx is enabled)." canBeEmpty="true" > 230 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 231 <Parameter id="DriveModes" severity="ERROR" reason=""> 232 <Fixed value="CY_GPIO_DM_STRONG_IN_OFF" /> 233 </Parameter> 234 </Constraint> 235 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 236 </ParamSignal> 237 <ParamSignal port="tdm_rx_sck[0]" name="Rx Serial Clock" group="`${(rxMode eq CY_TDM_DEVICE_MASTER) ? "Outputs" : "Inputs"}`" visible="`${rxEnabled}`" desc="Rx serial clock (visible when Rx is enabled)." canBeEmpty="`${(rxMode eq CY_TDM_DEVICE_MASTER) || !rxEnabled}`" > 238 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 239 <Parameter id="DriveModes" severity="ERROR" reason=""> 240 <Fixed value="`${(rxMode eq CY_TDM_DEVICE_MASTER) ? "CY_GPIO_DM_STRONG_IN_OFF" : "CY_GPIO_DM_HIGHZ"}`" /> 241 </Parameter> 242 </Constraint> 243 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 244 </ParamSignal> 245 <ParamSignal port="tdm_rx_fsync[0]" name="Rx Word Select" group="`${(rxMode eq CY_TDM_DEVICE_MASTER) ? "Outputs" : "Inputs"}`" visible="`${rxEnabled}`" desc="Rx word select (visible when Rx is enabled)." canBeEmpty="`${(rxMode eq CY_TDM_DEVICE_MASTER) || !rxEnabled}`" > 246 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 247 <Parameter id="DriveModes" severity="ERROR" reason=""> 248 <Fixed value="`${(rxMode eq CY_TDM_DEVICE_MASTER) ? "CY_GPIO_DM_STRONG_IN_OFF" : "CY_GPIO_DM_HIGHZ"}`" /> 249 </Parameter> 250 </Constraint> 251 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 252 </ParamSignal> 253 <ParamSignal port="tdm_rx_sd[0]" name="Rx Serial Data" group="Inputs" visible="`${rxEnabled}`" desc="Rx serial data input (visible when Rx is enabled)." canBeEmpty="`${!rxEnabled}`" > 254 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 255 <Parameter id="DriveModes" severity="ERROR" reason=""> 256 <Fixed value="CY_GPIO_DM_HIGHZ" /> 257 </Parameter> 258 </Constraint> 259 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 260 </ParamSignal> 261 <ParamSignal port="tr_tx_req[0]" name="Tx DMA Transfer Request Signal" group="Outputs" visible="`${txDmaTrigger && txEnabled}`" desc="Tx DMA transfer request signal (Available when Tx DMA trigger is enabled)." canBeEmpty="true" > 262 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 263 <Parameter id="DriveModes" severity="ERROR" reason=""> 264 <Fixed value="CY_GPIO_DM_STRONG_IN_OFF" /> 265 </Parameter> 266 </Constraint> 267 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 268 </ParamSignal> 269 <ParamSignal port="tr_rx_req[0]" name="Rx DMA Transfer Request Signal" group="Outputs" visible="`${rxDmaTrigger && rxEnabled}`" desc="Rx DMA transfer request signal (Available when Rx DMA trigger is enabled)." canBeEmpty="true" > 270 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 271 <Parameter id="DriveModes" severity="ERROR" reason=""> 272 <Fixed value="CY_GPIO_DM_STRONG_IN_OFF" /> 273 </Parameter> 274 </Constraint> 275 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 276 </ParamSignal> 277 278 <ParamSignal port="clk_if_srss[0]" name="Interface Clock" group="Inputs" visible="true" desc="Clock Input signal for TDM interface." canBeEmpty="false" > 279 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 280 <Parameter id="DriveModes" severity="DEFAULT" reason=""> 281 <Fixed value="CY_GPIO_DM_STRONG_IN_OFF" /> 282 </Parameter> 283 </Constraint> 284 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 285 <Parameter id="DriveModes" severity="INFO" reason="The pin Drive Mode parameter does not match expected."> 286 <Fixed value="CY_GPIO_DM_STRONG_IN_OFF" /> 287 </Parameter> 288 </Constraint> 289 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 290 </ParamSignal> 291 292 <ParamString id="sourceClock" name="sourceClock" group="Internal" default="`${getBlockFromSignal("clk_if_srss[0]")}`" visible="false" editable="false" desc="Source Clock Resource" /> 293 294 <ParamBool id="inFlash" name="Store Config in Flash" group="Advanced" default="true" visible="true" editable="true" desc="Controls whether the configuration structure is stored in flash (const, true) or SRAM (not const, false)." /> 295 296 <!-- TDM instance number --> 297 <ParamString id="InstNumber" name="Instance Number" group="Internal" default="`${getInstNumber("tdm")}`" visible="false" editable="false" desc="TDM Instance number." /> 298 <ParamBool id="hasTDM1" name="hasTDM1" group="Internal" default="`${hasBlock("tdm[1]")}`" visible="false" editable="false" desc="Check whether device has more than one TDM instance" /> 299 300 <!-- Peripheral clock divider connection --> 301 <ParamBool id="pclkOk" name="PCLK Valid" group="Internal" default="`${hasConnection("clk_if_srss", 0) && isBlockUsed(sourceClock)}`" visible="false" editable="false" desc="Checks whether there is a PCLK connected and enabled." /> 302 <ParamString id="pclkDst" name="PCLK Destination" group="Internal" default="PCLK_TDM`${InstNumber}`_CLK_IF_SRSS0" visible="false" editable="false" desc="Generates PCLK connection define." /> 303 304 </Parameters> 305 306 <DRCs> 307 <!-- RX direction --> 308 <DRC type="ERROR" text="RX Word Length value must be less than or equal RX Channel Length." condition="`${rxEnabled && rxWordLength > rxChannelLength}`" /> 309 <DRC type="ERROR" text="I2S mode, No of Channels should not exceed 2." condition="`${rxInterfaceMode && rxChannels > 2}`" /> 310 311 <!-- TX direction --> 312 <DRC type="ERROR" text="TX Word Length value must be less than or equal TX Channel Length." condition="`${txEnabled && txWordLength > txChannelLength}`" /> 313 <DRC type="ERROR" text="I2S mode, No of Channels should not exceed 2." condition="`${txInterfaceMode && txChannels > 2}`" /> 314 315 </DRCs> 316 317 <ConfigFirmware> 318 <ConfigInclude value="cy_tdm.h" include="true" /> 319 <ConfigInclude value="cy_sysclk.h" include="`${pclkOk}`" /> 320 321 <ConfigDefine name="`${INST_NAME}`_HW" value="TDM`${InstNumber}`" public="true" include="true" /> 322 <ConfigDefine name="`${INST_NAME}`_TX_HW" value="TDM_STRUCT`${InstNumber}`_TX" public="true" include="true" /> 323 <ConfigDefine name="`${INST_NAME}`_RX_HW" value="TDM_STRUCT`${InstNumber}`_RX" public="true" include="true" /> 324 <ConfigDefine name="`${INST_NAME}`_TX_IRQ" value="tdm_`${InstNumber}`_interrupts_tx_`${InstNumber}`_IRQn" public="true" include="true" /> 325 <ConfigDefine name="`${INST_NAME}`_RX_IRQ" value="tdm_`${InstNumber}`_interrupts_rx_`${InstNumber}`_IRQn" public="true" include="true" /> 326 327 <ConfigStruct name="`${INST_NAME . "_tx_config"}`" type="cy_stc_tdm_config_tx_t" const="false" public="true" include="true" > 328 <Member name="enable" value="`${txEnabled}`" /> 329 <Member name="masterMode" value="`${txMode}`" /> 330 <Member name="wordSize" value="CY_TDM_SIZE_`${txWordLength}`" /> 331 <Member name="format" value="`${txAlignment}`" /> 332 <Member name="clkDiv" value="`${txclockDiv}`" /> 333 <Member name="clkSel" value="`${txclockselect}`" /> 334 <Member name="sckPolarity" value="`${txSckoPolarity}`" /> 335 <Member name="fsyncPolarity" value="`${txsyncFormatPolarity}`" /> 336 <Member name="fsyncFormat" value="`${txsyncformat}`" /> 337 <Member name="channelNum" value="`${txChannels}`" /> 338 <Member name="channelSize" value="`${txChannelLength}`" /> 339 <Member name="fifoTriggerLevel" value="`${txFifoTriggerLevel}`" /> 340 <Member name="chEn" value="`${txChannelsEnabled}`" /> 341 <Member name="signalInput" value="`${txsignalInput}`" /> 342 <Member name="i2sMode" value="`${txInterfaceMode}`" /> 343 344 345 </ConfigStruct> 346 347 <ConfigStruct name="`${INST_NAME . "_rx_config"}`" type="cy_stc_tdm_config_rx_t" const="false" public="true" include="true" > 348 <Member name="enable" value="`${rxEnabled}`" /> 349 <Member name="masterMode" value="`${rxMode}`" /> 350 <Member name="wordSize" value="CY_TDM_SIZE_`${rxWordLength}`" /> 351 <Member name="signExtend" value="`${rxsignExtended}`" /> 352 <Member name="format" value="`${rxAlignment}`" /> 353 <Member name="clkDiv" value="`${rxclockDiv}`" /> 354 <Member name="clkSel" value="`${rxclockselect}`" /> 355 <Member name="sckPolarity" value="`${rxSckoPolarity}`" /> 356 <Member name="fsyncPolarity" value="`${rxsyncFormatPolarity}`" /> 357 <Member name="lateSample" value="`${rxlateSample}`" /> 358 <Member name="fsyncFormat" value="`${rxsyncformat}`" /> 359 <Member name="channelNum" value="`${rxChannels}`" /> 360 <Member name="channelSize" value="`${rxChannelLength}`" /> 361 <Member name="fifoTriggerLevel" value="`${rxFifoTriggerLevel}`" /> 362 <Member name="chEn" value="`${rxChannelsEnabled}`" /> 363 <Member name="signalInput" value="`${rxsignalInput}`" /> 364 <Member name="i2sMode" value="`${rxInterfaceMode}`" /> 365 366 </ConfigStruct> 367 368 <ConfigStruct name="`${INST_NAME}`_config" type="cy_stc_tdm_config_t" const="true" public="true" include="true" > 369 <Member name="tx_config" value="&`${INST_NAME . "_tx_config"}`" /> 370 <Member name="rx_config" value="&`${INST_NAME . "_rx_config"}`" /> 371 </ConfigStruct> 372 373 <ConfigInstruction value="Cy_SysClk_PeriPclkAssignDivider(`${pclkDst}`, `${getExposedMember(sourceClock, "clockSel")}`);" include="`${pclkOk}`" /> 374 375 </ConfigFirmware> 376 377</Personality> 378
