1 /**************************************************************************//**
2 * @file
3 * @brief CMSIS system header file for EFR32MG24
4 ******************************************************************************
5 * # License
6 * <b>Copyright 2023 Silicon Laboratories, Inc. www.silabs.com</b>
7 ******************************************************************************
8 *
9 * SPDX-License-Identifier: Zlib
10 *
11 * The licensor of this software is Silicon Laboratories Inc.
12 *
13 * This software is provided 'as-is', without any express or implied
14 * warranty. In no event will the authors be held liable for any damages
15 * arising from the use of this software.
16 *
17 * Permission is granted to anyone to use this software for any purpose,
18 * including commercial applications, and to alter it and redistribute it
19 * freely, subject to the following restrictions:
20 *
21 * 1. The origin of this software must not be misrepresented; you must not
22 * claim that you wrote the original software. If you use this software
23 * in a product, an acknowledgment in the product documentation would be
24 * appreciated but is not required.
25 * 2. Altered source versions must be plainly marked as such, and must not be
26 * misrepresented as being the original software.
27 * 3. This notice may not be removed or altered from any source distribution.
28 *
29 *****************************************************************************/
30
31 #ifndef SYSTEM_EFR32MG24_H
32 #define SYSTEM_EFR32MG24_H
33
34 #ifdef __cplusplus
35 extern "C" {
36 #endif
37
38 #include <stdint.h>
39
40 /***************************************************************************//**
41 * @addtogroup Parts
42 * @{
43 ******************************************************************************/
44 /***************************************************************************//**
45 * @addtogroup EFR32MG24 EFR32MG24
46 * @{
47 ******************************************************************************/
48
49 /*******************************************************************************
50 ****************************** TYPEDEFS ***********************************
51 ******************************************************************************/
52
53 /* Interrupt vectortable entry */
54 typedef union {
55 void (*VECTOR_TABLE_Type)(void);
56 void *topOfStack;
57 } tVectorEntry;
58
59 /*******************************************************************************
60 ************************** GLOBAL VARIABLES *******************************
61 ******************************************************************************/
62
63 #if !defined(SYSTEM_NO_STATIC_MEMORY)
64 extern uint32_t SystemCoreClock; /**< System Clock Frequency (Core Clock) */
65 extern uint32_t SystemHfrcoFreq; /**< System HFRCO frequency */
66 #endif
67
68 /*Re-direction of IRQn.*/
69 #if defined (SL_TRUSTZONE_SECURE)
70 #define SMU_PRIVILEGED_IRQn SMU_S_PRIVILEGED_IRQn
71 #else
72 #define SMU_PRIVILEGED_IRQn SMU_NS_PRIVILEGED_IRQn
73 #endif /* SL_TRUSTZONE_SECURE */
74
75 /*Re-direction of IRQHandler.*/
76 #if defined (SL_TRUSTZONE_SECURE)
77 #define SMU_PRIVILEGED_IRQHandler SMU_S_PRIVILEGED_IRQHandler
78 #else
79 #define SMU_PRIVILEGED_IRQHandler SMU_NS_PRIVILEGED_IRQHandler
80 #endif /* SL_TRUSTZONE_SECURE */
81
82 /*******************************************************************************
83 ***************************** PROTOTYPES **********************************
84 ******************************************************************************/
85
86 void Reset_Handler(void); /**< Reset Handler */
87 void NMI_Handler(void); /**< NMI Handler */
88 void HardFault_Handler(void); /**< Hard Fault Handler */
89 void MemManage_Handler(void); /**< MPU Fault Handler */
90 void BusFault_Handler(void); /**< Bus Fault Handler */
91 void UsageFault_Handler(void); /**< Usage Fault Handler */
92 void SecureFault_Handler(void); /**< Secure Fault Handler */
93 void SVC_Handler(void); /**< SVCall Handler */
94 void DebugMon_Handler(void); /**< Debug Monitor Handler */
95 void PendSV_Handler(void); /**< PendSV Handler */
96 void SysTick_Handler(void); /**< SysTick Handler */
97
98 /* Part Specific Interrupts */
99 void SMU_SECURE_IRQHandler(void); /**< SMU_SECURE IRQ Handler */
100 void SMU_S_PRIVILEGED_IRQHandler(void); /**< SMU_S_PRIVILEGED IRQ Handler */
101 void SMU_NS_PRIVILEGED_IRQHandler(void); /**< SMU_NS_PRIVILEGED IRQ Handler */
102 void EMU_IRQHandler(void); /**< EMU IRQ Handler */
103 void TIMER0_IRQHandler(void); /**< TIMER0 IRQ Handler */
104 void TIMER1_IRQHandler(void); /**< TIMER1 IRQ Handler */
105 void TIMER2_IRQHandler(void); /**< TIMER2 IRQ Handler */
106 void TIMER3_IRQHandler(void); /**< TIMER3 IRQ Handler */
107 void TIMER4_IRQHandler(void); /**< TIMER4 IRQ Handler */
108 void USART0_RX_IRQHandler(void); /**< USART0_RX IRQ Handler */
109 void USART0_TX_IRQHandler(void); /**< USART0_TX IRQ Handler */
110 void EUSART0_RX_IRQHandler(void); /**< EUSART0_RX IRQ Handler */
111 void EUSART0_TX_IRQHandler(void); /**< EUSART0_TX IRQ Handler */
112 void EUSART1_RX_IRQHandler(void); /**< EUSART1_RX IRQ Handler */
113 void EUSART1_TX_IRQHandler(void); /**< EUSART1_TX IRQ Handler */
114 void MVP_IRQHandler(void); /**< MVP IRQ Handler */
115 void ICACHE0_IRQHandler(void); /**< ICACHE0 IRQ Handler */
116 void BURTC_IRQHandler(void); /**< BURTC IRQ Handler */
117 void LETIMER0_IRQHandler(void); /**< LETIMER0 IRQ Handler */
118 void SYSCFG_IRQHandler(void); /**< SYSCFG IRQ Handler */
119 void MPAHBRAM_IRQHandler(void); /**< MPAHBRAM IRQ Handler */
120 void LDMA_IRQHandler(void); /**< LDMA IRQ Handler */
121 void LFXO_IRQHandler(void); /**< LFXO IRQ Handler */
122 void LFRCO_IRQHandler(void); /**< LFRCO IRQ Handler */
123 void ULFRCO_IRQHandler(void); /**< ULFRCO IRQ Handler */
124 void GPIO_ODD_IRQHandler(void); /**< GPIO_ODD IRQ Handler */
125 void GPIO_EVEN_IRQHandler(void); /**< GPIO_EVEN IRQ Handler */
126 void I2C0_IRQHandler(void); /**< I2C0 IRQ Handler */
127 void I2C1_IRQHandler(void); /**< I2C1 IRQ Handler */
128 void EMUDG_IRQHandler(void); /**< EMUDG IRQ Handler */
129 void AGC_IRQHandler(void); /**< AGC IRQ Handler */
130 void BUFC_IRQHandler(void); /**< BUFC IRQ Handler */
131 void FRC_PRI_IRQHandler(void); /**< FRC_PRI IRQ Handler */
132 void FRC_IRQHandler(void); /**< FRC IRQ Handler */
133 void MODEM_IRQHandler(void); /**< MODEM IRQ Handler */
134 void PROTIMER_IRQHandler(void); /**< PROTIMER IRQ Handler */
135 void RAC_RSM_IRQHandler(void); /**< RAC_RSM IRQ Handler */
136 void RAC_SEQ_IRQHandler(void); /**< RAC_SEQ IRQ Handler */
137 void HOSTMAILBOX_IRQHandler(void); /**< HOSTMAILBOX IRQ Handler */
138 void SYNTH_IRQHandler(void); /**< SYNTH IRQ Handler */
139 void ACMP0_IRQHandler(void); /**< ACMP0 IRQ Handler */
140 void ACMP1_IRQHandler(void); /**< ACMP1 IRQ Handler */
141 void WDOG0_IRQHandler(void); /**< WDOG0 IRQ Handler */
142 void WDOG1_IRQHandler(void); /**< WDOG1 IRQ Handler */
143 void HFXO0_IRQHandler(void); /**< HFXO0 IRQ Handler */
144 void HFRCO0_IRQHandler(void); /**< HFRCO0 IRQ Handler */
145 void HFRCOEM23_IRQHandler(void); /**< HFRCOEM23 IRQ Handler */
146 void CMU_IRQHandler(void); /**< CMU IRQ Handler */
147 void AES_IRQHandler(void); /**< AES IRQ Handler */
148 void IADC_IRQHandler(void); /**< IADC IRQ Handler */
149 void MSC_IRQHandler(void); /**< MSC IRQ Handler */
150 void DPLL0_IRQHandler(void); /**< DPLL0 IRQ Handler */
151 void EMUEFP_IRQHandler(void); /**< EMUEFP IRQ Handler */
152 void DCDC_IRQHandler(void); /**< DCDC IRQ Handler */
153 void PCNT0_IRQHandler(void); /**< PCNT0 IRQ Handler */
154 void SW0_IRQHandler(void); /**< SW0 IRQ Handler */
155 void SW1_IRQHandler(void); /**< SW1 IRQ Handler */
156 void SW2_IRQHandler(void); /**< SW2 IRQ Handler */
157 void SW3_IRQHandler(void); /**< SW3 IRQ Handler */
158 void KERNEL0_IRQHandler(void); /**< KERNEL0 IRQ Handler */
159 void KERNEL1_IRQHandler(void); /**< KERNEL1 IRQ Handler */
160 void M33CTI0_IRQHandler(void); /**< M33CTI0 IRQ Handler */
161 void M33CTI1_IRQHandler(void); /**< M33CTI1 IRQ Handler */
162 void FPUEXH_IRQHandler(void); /**< FPUEXH IRQ Handler */
163 void SETAMPERHOST_IRQHandler(void); /**< SETAMPERHOST IRQ Handler */
164 void SEMBRX_IRQHandler(void); /**< SEMBRX IRQ Handler */
165 void SEMBTX_IRQHandler(void); /**< SEMBTX IRQ Handler */
166 void SYSRTC_APP_IRQHandler(void); /**< SYSRTC_APP IRQ Handler */
167 void SYSRTC_SEQ_IRQHandler(void); /**< SYSRTC_SEQ IRQ Handler */
168 void KEYSCAN_IRQHandler(void); /**< KEYSCAN IRQ Handler */
169 void RFECA0_IRQHandler(void); /**< RFECA0 IRQ Handler */
170 void RFECA1_IRQHandler(void); /**< RFECA1 IRQ Handler */
171 void VDAC0_IRQHandler(void); /**< VDAC0 IRQ Handler */
172 void VDAC1_IRQHandler(void); /**< VDAC1 IRQ Handler */
173 void AHB2AHB0_IRQHandler(void); /**< AHB2AHB0 IRQ Handler */
174 void AHB2AHB1_IRQHandler(void); /**< AHB2AHB1 IRQ Handler */
175
176 #if (__FPU_PRESENT == 1)
177 void FPUEH_IRQHandler(void); /**< FPU IRQ Handler */
178 #endif
179
180 uint32_t SystemHCLKGet(void);
181
182 /**************************************************************************//**
183 * @brief
184 * Update CMSIS SystemCoreClock variable.
185 *
186 * @details
187 * CMSIS defines a global variable SystemCoreClock that shall hold the
188 * core frequency in Hz. If the core frequency is dynamically changed, the
189 * variable must be kept updated in order to be CMSIS compliant.
190 *
191 * Notice that only if changing the core clock frequency through the EMLIB
192 * CMU API, this variable will be kept updated. This function is only
193 * provided for CMSIS compliance and if a user modifies the the core clock
194 * outside the EMLIB CMU API.
195 *****************************************************************************/
SystemCoreClockGet(void)196 static __INLINE uint32_t SystemCoreClockGet(void)
197 {
198 return SystemHCLKGet();
199 }
200
201 /**************************************************************************//**
202 * @brief
203 * Update CMSIS SystemCoreClock variable.
204 *
205 * @details
206 * CMSIS defines a global variable SystemCoreClock that shall hold the
207 * core frequency in Hz. If the core frequency is dynamically changed, the
208 * variable must be kept updated in order to be CMSIS compliant.
209 *
210 * Notice that only if changing the core clock frequency through the EMLIB
211 * CMU API, this variable will be kept updated. This function is only
212 * provided for CMSIS compliance and if a user modifies the the core clock
213 * outside the EMLIB CMU API.
214 *****************************************************************************/
SystemCoreClockUpdate(void)215 static __INLINE void SystemCoreClockUpdate(void)
216 {
217 SystemHCLKGet();
218 }
219
220 void SystemInit(void);
221 #if !defined(SL_LEGACY_LINKER)
222 void FlashToRamCopy(uint32_t *from,
223 uint32_t *to,
224 uint32_t size);
225 #endif
226 uint32_t SystemHFRCODPLLClockGet(void);
227 void SystemHFRCODPLLClockSet(uint32_t freq);
228 uint32_t SystemSYSCLKGet(void);
229 uint32_t SystemMaxCoreClockGet(void);
230 uint32_t SystemFSRCOClockGet(void);
231 uint32_t SystemHFXOClockGet(void);
232 void SystemHFXOClockSet(uint32_t freq);
233 uint32_t SystemCLKIN0Get(void);
234 uint32_t SystemHFRCOEM23ClockGet(void);
235 uint32_t SystemLFXOClockGet(void);
236 void SystemLFXOClockSet(uint32_t freq);
237 uint32_t SystemLFRCOClockGet(void);
238 uint32_t SystemULFRCOClockGet(void);
239
240 /** @} End of group */
241 /** @} End of group Parts */
242
243 #ifdef __cplusplus
244 }
245 #endif
246 #endif /* SYSTEM_EFR32MG24_H */
247
