1 /**************************************************************************//**
2 * @file
3 * @brief CMSIS system header file for EFR32MG24
4 ******************************************************************************
5 * # License
6 * <b>Copyright 2022 Silicon Laboratories, Inc. www.silabs.com</b>
7 ******************************************************************************
8 *
9 * SPDX-License-Identifier: Zlib
10 *
11 * The licensor of this software is Silicon Laboratories Inc.
12 *
13 * This software is provided 'as-is', without any express or implied
14 * warranty. In no event will the authors be held liable for any damages
15 * arising from the use of this software.
16 *
17 * Permission is granted to anyone to use this software for any purpose,
18 * including commercial applications, and to alter it and redistribute it
19 * freely, subject to the following restrictions:
20 *
21 * 1. The origin of this software must not be misrepresented; you must not
22 * claim that you wrote the original software. If you use this software
23 * in a product, an acknowledgment in the product documentation would be
24 * appreciated but is not required.
25 * 2. Altered source versions must be plainly marked as such, and must not be
26 * misrepresented as being the original software.
27 * 3. This notice may not be removed or altered from any source distribution.
28 *
29 *****************************************************************************/
30
31 #ifndef SYSTEM_EFR32MG24_H
32 #define SYSTEM_EFR32MG24_H
33
34 #ifdef __cplusplus
35 extern "C" {
36 #endif
37
38 #include <stdint.h>
39
40 /***************************************************************************//**
41 * @addtogroup Parts
42 * @{
43 ******************************************************************************/
44 /***************************************************************************//**
45 * @addtogroup EFR32MG24 EFR32MG24
46 * @{
47 ******************************************************************************/
48
49 /*******************************************************************************
50 ****************************** TYPEDEFS ***********************************
51 ******************************************************************************/
52
53 /* Interrupt vectortable entry */
54 typedef union {
55 void (*VECTOR_TABLE_Type)(void);
56 void *topOfStack;
57 } tVectorEntry;
58
59 /*******************************************************************************
60 ************************** GLOBAL VARIABLES *******************************
61 ******************************************************************************/
62
63 #if !defined(SYSTEM_NO_STATIC_MEMORY)
64 extern uint32_t SystemCoreClock; /**< System Clock Frequency (Core Clock) */
65 extern uint32_t SystemHfrcoFreq; /**< System HFRCO frequency */
66 #endif
67
68 /*Re-direction of IRQn.*/
69 #if (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2)
70 #if defined (SL_TRUSTZONE_SECURE)
71 #define SMU_PRIVILEGED_IRQn SMU_S_PRIVILEGED_IRQn
72 #else
73 #define SMU_PRIVILEGED_IRQn SMU_NS_PRIVILEGED_IRQn
74 #endif /* SL_TRUSTZONE_SECURE */
75 #endif /* _SILICON_LABS_32B_SERIES_2_CONFIG */
76
77 /*Re-direction of IRQHandler.*/
78 #if (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2)
79 #if defined (SL_TRUSTZONE_SECURE)
80 #define SMU_PRIVILEGED_IRQHandler SMU_S_PRIVILEGED_IRQHandler
81 #else
82 #define SMU_PRIVILEGED_IRQHandler SMU_NS_PRIVILEGED_IRQHandler
83 #endif /* SL_TRUSTZONE_SECURE */
84 #endif /* _SILICON_LABS_32B_SERIES_2_CONFIG */
85
86 /*******************************************************************************
87 ***************************** PROTOTYPES **********************************
88 ******************************************************************************/
89
90 void Reset_Handler(void); /**< Reset Handler */
91 void NMI_Handler(void); /**< NMI Handler */
92 void HardFault_Handler(void); /**< Hard Fault Handler */
93 void MemManage_Handler(void); /**< MPU Fault Handler */
94 void BusFault_Handler(void); /**< Bus Fault Handler */
95 void UsageFault_Handler(void); /**< Usage Fault Handler */
96 void SecureFault_Handler(void); /**< Secure Fault Handler */
97 void SVC_Handler(void); /**< SVCall Handler */
98 void DebugMon_Handler(void); /**< Debug Monitor Handler */
99 void PendSV_Handler(void); /**< PendSV Handler */
100 void SysTick_Handler(void); /**< SysTick Handler */
101
102 /* Part Specific Interrupts */
103 void SMU_SECURE_IRQHandler(void); /**< SMU_SECURE IRQ Handler */
104 void SMU_S_PRIVILEGED_IRQHandler(void); /**< SMU_S_PRIVILEGED IRQ Handler */
105 void SMU_NS_PRIVILEGED_IRQHandler(void); /**< SMU_NS_PRIVILEGED IRQ Handler */
106 void EMU_IRQHandler(void); /**< EMU IRQ Handler */
107 void TIMER0_IRQHandler(void); /**< TIMER0 IRQ Handler */
108 void TIMER1_IRQHandler(void); /**< TIMER1 IRQ Handler */
109 void TIMER2_IRQHandler(void); /**< TIMER2 IRQ Handler */
110 void TIMER3_IRQHandler(void); /**< TIMER3 IRQ Handler */
111 void TIMER4_IRQHandler(void); /**< TIMER4 IRQ Handler */
112 void USART0_RX_IRQHandler(void); /**< USART0_RX IRQ Handler */
113 void USART0_TX_IRQHandler(void); /**< USART0_TX IRQ Handler */
114 void EUSART0_RX_IRQHandler(void); /**< EUSART0_RX IRQ Handler */
115 void EUSART0_TX_IRQHandler(void); /**< EUSART0_TX IRQ Handler */
116 void EUSART1_RX_IRQHandler(void); /**< EUSART1_RX IRQ Handler */
117 void EUSART1_TX_IRQHandler(void); /**< EUSART1_TX IRQ Handler */
118 void MVP_IRQHandler(void); /**< MVP IRQ Handler */
119 void ICACHE0_IRQHandler(void); /**< ICACHE0 IRQ Handler */
120 void BURTC_IRQHandler(void); /**< BURTC IRQ Handler */
121 void LETIMER0_IRQHandler(void); /**< LETIMER0 IRQ Handler */
122 void SYSCFG_IRQHandler(void); /**< SYSCFG IRQ Handler */
123 void MPAHBRAM_IRQHandler(void); /**< MPAHBRAM IRQ Handler */
124 void LDMA_IRQHandler(void); /**< LDMA IRQ Handler */
125 void LFXO_IRQHandler(void); /**< LFXO IRQ Handler */
126 void LFRCO_IRQHandler(void); /**< LFRCO IRQ Handler */
127 void ULFRCO_IRQHandler(void); /**< ULFRCO IRQ Handler */
128 void GPIO_ODD_IRQHandler(void); /**< GPIO_ODD IRQ Handler */
129 void GPIO_EVEN_IRQHandler(void); /**< GPIO_EVEN IRQ Handler */
130 void I2C0_IRQHandler(void); /**< I2C0 IRQ Handler */
131 void I2C1_IRQHandler(void); /**< I2C1 IRQ Handler */
132 void EMUDG_IRQHandler(void); /**< EMUDG IRQ Handler */
133 void AGC_IRQHandler(void); /**< AGC IRQ Handler */
134 void BUFC_IRQHandler(void); /**< BUFC IRQ Handler */
135 void FRC_PRI_IRQHandler(void); /**< FRC_PRI IRQ Handler */
136 void FRC_IRQHandler(void); /**< FRC IRQ Handler */
137 void MODEM_IRQHandler(void); /**< MODEM IRQ Handler */
138 void PROTIMER_IRQHandler(void); /**< PROTIMER IRQ Handler */
139 void RAC_RSM_IRQHandler(void); /**< RAC_RSM IRQ Handler */
140 void RAC_SEQ_IRQHandler(void); /**< RAC_SEQ IRQ Handler */
141 void HOSTMAILBOX_IRQHandler(void); /**< HOSTMAILBOX IRQ Handler */
142 void SYNTH_IRQHandler(void); /**< SYNTH IRQ Handler */
143 void ACMP0_IRQHandler(void); /**< ACMP0 IRQ Handler */
144 void ACMP1_IRQHandler(void); /**< ACMP1 IRQ Handler */
145 void WDOG0_IRQHandler(void); /**< WDOG0 IRQ Handler */
146 void WDOG1_IRQHandler(void); /**< WDOG1 IRQ Handler */
147 void HFXO0_IRQHandler(void); /**< HFXO0 IRQ Handler */
148 void HFRCO0_IRQHandler(void); /**< HFRCO0 IRQ Handler */
149 void HFRCOEM23_IRQHandler(void); /**< HFRCOEM23 IRQ Handler */
150 void CMU_IRQHandler(void); /**< CMU IRQ Handler */
151 void AES_IRQHandler(void); /**< AES IRQ Handler */
152 void IADC_IRQHandler(void); /**< IADC IRQ Handler */
153 void MSC_IRQHandler(void); /**< MSC IRQ Handler */
154 void DPLL0_IRQHandler(void); /**< DPLL0 IRQ Handler */
155 void EMUEFP_IRQHandler(void); /**< EMUEFP IRQ Handler */
156 void DCDC_IRQHandler(void); /**< DCDC IRQ Handler */
157 void PCNT0_IRQHandler(void); /**< PCNT0 IRQ Handler */
158 void SW0_IRQHandler(void); /**< SW0 IRQ Handler */
159 void SW1_IRQHandler(void); /**< SW1 IRQ Handler */
160 void SW2_IRQHandler(void); /**< SW2 IRQ Handler */
161 void SW3_IRQHandler(void); /**< SW3 IRQ Handler */
162 void KERNEL0_IRQHandler(void); /**< KERNEL0 IRQ Handler */
163 void KERNEL1_IRQHandler(void); /**< KERNEL1 IRQ Handler */
164 void M33CTI0_IRQHandler(void); /**< M33CTI0 IRQ Handler */
165 void M33CTI1_IRQHandler(void); /**< M33CTI1 IRQ Handler */
166 void FPUEXH_IRQHandler(void); /**< FPUEXH IRQ Handler */
167 void SETAMPERHOST_IRQHandler(void); /**< SETAMPERHOST IRQ Handler */
168 void SEMBRX_IRQHandler(void); /**< SEMBRX IRQ Handler */
169 void SEMBTX_IRQHandler(void); /**< SEMBTX IRQ Handler */
170 void SYSRTC_APP_IRQHandler(void); /**< SYSRTC_APP IRQ Handler */
171 void SYSRTC_SEQ_IRQHandler(void); /**< SYSRTC_SEQ IRQ Handler */
172 void KEYSCAN_IRQHandler(void); /**< KEYSCAN IRQ Handler */
173 void RFECA0_IRQHandler(void); /**< RFECA0 IRQ Handler */
174 void RFECA1_IRQHandler(void); /**< RFECA1 IRQ Handler */
175 void VDAC0_IRQHandler(void); /**< VDAC0 IRQ Handler */
176 void VDAC1_IRQHandler(void); /**< VDAC1 IRQ Handler */
177 void AHB2AHB0_IRQHandler(void); /**< AHB2AHB0 IRQ Handler */
178 void AHB2AHB1_IRQHandler(void); /**< AHB2AHB1 IRQ Handler */
179
180 #if (__FPU_PRESENT == 1)
181 void FPUEH_IRQHandler(void); /**< FPU IRQ Handler */
182 #endif
183
184 uint32_t SystemHCLKGet(void);
185
186 /**************************************************************************//**
187 * @brief
188 * Update CMSIS SystemCoreClock variable.
189 *
190 * @details
191 * CMSIS defines a global variable SystemCoreClock that shall hold the
192 * core frequency in Hz. If the core frequency is dynamically changed, the
193 * variable must be kept updated in order to be CMSIS compliant.
194 *
195 * Notice that only if changing the core clock frequency through the EMLIB
196 * CMU API, this variable will be kept updated. This function is only
197 * provided for CMSIS compliance and if a user modifies the the core clock
198 * outside the EMLIB CMU API.
199 *****************************************************************************/
SystemCoreClockGet(void)200 static __INLINE uint32_t SystemCoreClockGet(void)
201 {
202 return SystemHCLKGet();
203 }
204
205 /**************************************************************************//**
206 * @brief
207 * Update CMSIS SystemCoreClock variable.
208 *
209 * @details
210 * CMSIS defines a global variable SystemCoreClock that shall hold the
211 * core frequency in Hz. If the core frequency is dynamically changed, the
212 * variable must be kept updated in order to be CMSIS compliant.
213 *
214 * Notice that only if changing the core clock frequency through the EMLIB
215 * CMU API, this variable will be kept updated. This function is only
216 * provided for CMSIS compliance and if a user modifies the the core clock
217 * outside the EMLIB CMU API.
218 *****************************************************************************/
SystemCoreClockUpdate(void)219 static __INLINE void SystemCoreClockUpdate(void)
220 {
221 SystemHCLKGet();
222 }
223
224 void SystemInit(void);
225 uint32_t SystemHFRCODPLLClockGet(void);
226 void SystemHFRCODPLLClockSet(uint32_t freq);
227 uint32_t SystemSYSCLKGet(void);
228 uint32_t SystemMaxCoreClockGet(void);
229 uint32_t SystemFSRCOClockGet(void);
230 uint32_t SystemHFXOClockGet(void);
231 void SystemHFXOClockSet(uint32_t freq);
232 uint32_t SystemCLKIN0Get(void);
233 uint32_t SystemHFRCOEM23ClockGet(void);
234 uint32_t SystemLFXOClockGet(void);
235 void SystemLFXOClockSet(uint32_t freq);
236 uint32_t SystemLFRCOClockGet(void);
237 uint32_t SystemULFRCOClockGet(void);
238
239 /** @} End of group */
240 /** @} End of group Parts */
241
242 #ifdef __cplusplus
243 }
244 #endif
245 #endif /* SYSTEM_EFR32MG24_H */
246
