1 /***************************************************************************//**
2  * @file
3  * @brief CMSIS Cortex-M4 System Layer for EFM32 devices.
4  *******************************************************************************
5  * # License
6  * <b>Copyright 2022 Silicon Laboratories Inc. www.silabs.com</b>
7  *******************************************************************************
8  *
9  * SPDX-License-Identifier: Zlib
10  *
11  * The licensor of this software is Silicon Laboratories Inc.
12  *
13  * This software is provided 'as-is', without any express or implied
14  * warranty. In no event will the authors be held liable for any damages
15  * arising from the use of this software.
16  *
17  * Permission is granted to anyone to use this software for any purpose,
18  * including commercial applications, and to alter it and redistribute it
19  * freely, subject to the following restrictions:
20  *
21  * 1. The origin of this software must not be misrepresented; you must not
22  *    claim that you wrote the original software. If you use this software
23  *    in a product, an acknowledgment in the product documentation would be
24  *    appreciated but is not required.
25  * 2. Altered source versions must be plainly marked as such, and must not be
26  *    misrepresented as being the original software.
27  * 3. This notice may not be removed or altered from any source distribution.
28  *
29  ******************************************************************************/
30 
31 #ifndef SYSTEM_EFM32_H
32 #define SYSTEM_EFM32_H
33 
34 #ifdef __cplusplus
35 extern "C" {
36 #endif
37 
38 #include <stdint.h>
39 
40 /***************************************************************************//**
41  * @addtogroup Parts
42  * @{
43  ******************************************************************************/
44 /***************************************************************************//**
45  * @addtogroup EFM32GG11B EFM32GG11B
46  * @{
47  ******************************************************************************/
48 
49 /*******************************************************************************
50  ******************************   TYPEDEFS   ***********************************
51  ******************************************************************************/
52 
53 /* Interrupt vectortable entry */
54 typedef union {
55   void (*VECTOR_TABLE_Type)(void);
56   void *topOfStack;
57 } tVectorEntry;
58 
59 /*******************************************************************************
60  **************************   GLOBAL VARIABLES   *******************************
61  ******************************************************************************/
62 
63 extern uint32_t SystemCoreClock;    /**< System Clock Frequency (Core Clock) */
64 extern uint32_t SystemHfrcoFreq;    /**< System HFRCO frequency */
65 
66 /*******************************************************************************
67  *****************************   PROTOTYPES   **********************************
68  ******************************************************************************/
69 
70 void Reset_Handler(void);           /**< Reset Handler */
71 void NMI_Handler(void);             /**< NMI Handler */
72 void HardFault_Handler(void);       /**< Hard Fault Handler */
73 void MemManage_Handler(void);       /**< MPU Fault Handler */
74 void BusFault_Handler(void);        /**< Bus Fault Handler */
75 void UsageFault_Handler(void);      /**< Usage Fault Handler */
76 void SVC_Handler(void);             /**< SVCall Handler */
77 void DebugMon_Handler(void);        /**< Debug Monitor Handler */
78 void PendSV_Handler(void);          /**< PendSV Handler */
79 void SysTick_Handler(void);         /**< SysTick Handler */
80 
81 void EMU_IRQHandler(void);          /**< EMU IRQ Handler */
82 void WDOG0_IRQHandler(void);        /**< WDOG0 IRQ Handler */
83 void LDMA_IRQHandler(void);         /**< LDMA IRQ Handler */
84 void GPIO_EVEN_IRQHandler(void);    /**< GPIO_EVEN IRQ Handler */
85 void SMU_IRQHandler(void);          /**< SMU IRQ Handler */
86 void TIMER0_IRQHandler(void);       /**< TIMER0 IRQ Handler */
87 void USART0_RX_IRQHandler(void);    /**< USART0_RX IRQ Handler */
88 void USART0_TX_IRQHandler(void);    /**< USART0_TX IRQ Handler */
89 void ACMP0_IRQHandler(void);        /**< ACMP0 IRQ Handler */
90 void ADC0_IRQHandler(void);         /**< ADC0 IRQ Handler */
91 void IDAC0_IRQHandler(void);        /**<  IDAC0 IRQ Handler */
92 void I2C0_IRQHandler(void);         /**<  I2C0 IRQ Handler */
93 void I2C1_IRQHandler(void);         /**<  I2C1 IRQ Handler */
94 void GPIO_ODD_IRQHandler(void);     /**<  GPIO_ODD IRQ Handler */
95 void TIMER1_IRQHandler(void);       /**<  TIMER1 IRQ Handler */
96 void TIMER2_IRQHandler(void);       /**<  TIMER2 IRQ Handler */
97 void TIMER3_IRQHandler(void);       /**<  TIMER3 IRQ Handler */
98 void USART1_RX_IRQHandler(void);    /**<  USART1_RX IRQ Handler */
99 void USART1_TX_IRQHandler(void);    /**<  USART1_TX IRQ Handler */
100 void USART2_RX_IRQHandler(void);    /**<  USART2_RX IRQ Handler */
101 void USART2_TX_IRQHandler(void);    /**<  USART2_TX IRQ Handler */
102 void UART0_RX_IRQHandler(void);     /**<  UART0_RX IRQ Handler */
103 void UART0_TX_IRQHandler(void);     /**<  UART0_TX IRQ Handler */
104 void UART1_RX_IRQHandler(void);     /**<  UART1_RX IRQ Handler */
105 void UART1_TX_IRQHandler(void);     /**<  UART1_TX IRQ Handler */
106 void LEUART0_IRQHandler(void);      /**<  LEUART0 IRQ Handler */
107 void LEUART1_IRQHandler(void);      /**<  LEUART1 IRQ Handler */
108 void LETIMER0_IRQHandler(void);     /**<  LETIMER0 IRQ Handler */
109 void PCNT0_IRQHandler(void);        /**<  PCNT0 IRQ Handler */
110 void PCNT1_IRQHandler(void);        /**<  PCNT1 IRQ Handler */
111 void PCNT2_IRQHandler(void);        /**<  PCNT2 IRQ Handler */
112 void RTCC_IRQHandler(void);         /**<  RTCC IRQ Handler */
113 void CMU_IRQHandler(void);          /**<  CMU IRQ Handler */
114 void MSC_IRQHandler(void);          /**<  MSC IRQ Handler */
115 void CRYPTO0_IRQHandler(void);      /**<  CRYPTO0 IRQ Handler */
116 void CRYOTIMER_IRQHandler(void);    /**<  CRYOTIMER IRQ Handler */
117 void FPUEH_IRQHandler(void);        /**<  FPUEH IRQ Handler */
118 void USART3_RX_IRQHandler(void);    /**<  USART3_RX IRQ Handler */
119 void USART3_TX_IRQHandler(void);    /**<  USART3_TX IRQ Handler */
120 void USART4_RX_IRQHandler(void);    /**<  USART4_RX IRQ Handler */
121 void USART4_TX_IRQHandler(void);    /**<  USART4_TX IRQ Handler */
122 void WTIMER0_IRQHandler(void);      /**<  WTIMER0 IRQ Handler */
123 void WTIMER1_IRQHandler(void);      /**<  WTIMER1 IRQ Handler */
124 void VDAC0_IRQHandler(void);        /**<  VDAC0 IRQ Handler */
125 void CSEN_IRQHandler(void);         /**<  CSEN IRQ Handler */
126 void LESENSE_IRQHandler(void);      /**<  LESENSE IRQ Handler */
127 void EBI_IRQHandler(void);          /**<  EBI IRQ Handler */
128 void ACMP2_IRQHandler(void);        /**<  ACMP2 IRQ Handler */
129 void ADC1_IRQHandler(void);         /**<  ADC1 IRQ Handler */
130 void LCD_IRQHandler(void);          /**<  LCD IRQ Handler */
131 void SDIO_IRQHandler(void);         /**<  SDIO IRQ Handler */
132 void CAN0_IRQHandler(void);         /**<  CAN0 IRQ Handler */
133 void CAN1_IRQHandler(void);         /**<  CAN1 IRQ Handler */
134 void USB_IRQHandler(void);          /**<  USB IRQ Handler */
135 void RTC_IRQHandler(void);          /**<  RTC IRQ Handler */
136 void WDOG1_IRQHandler(void);        /**<  WDOG1 IRQ Handler */
137 void LETIMER1_IRQHandler(void);     /**<  LETIMER1 IRQ Handler */
138 void TRNG0_IRQHandler(void);        /**<  TRNG0 IRQ Handler */
139 void QSPI0_IRQHandler(void);        /**<  QSPI0 IRQ Handler */
140 void PDM_IRQHandler(void);          /**<  PDM IRQ Handler */
141 
142 uint32_t SystemCoreClockGet(void);
143 
144 /***************************************************************************//**
145  * @brief
146  *   Update CMSIS SystemCoreClock variable.
147  *
148  * @details
149  *   CMSIS defines a global variable SystemCoreClock that shall hold the
150  *   core frequency in Hz. If the core frequency is dynamically changed, the
151  *   variable must be kept updated in order to be CMSIS compliant.
152  *
153  *   Notice that only if changing the core clock frequency through the EFM32 CMU
154  *   API, this variable will be kept updated. This function is only provided
155  *   for CMSIS compliance and if a user modifies the the core clock outside
156  *   the CMU API.
157  ******************************************************************************/
SystemCoreClockUpdate(void)158 static __INLINE void SystemCoreClockUpdate(void)
159 {
160   (void)SystemCoreClockGet();
161 }
162 
163 uint32_t SystemMaxCoreClockGet(void);
164 
165 void SystemInit(void);
166 uint32_t SystemHFClockGet(void);
167 
168 uint32_t SystemHFXOClockGet(void);
169 void SystemHFXOClockSet(uint32_t freq);
170 
171 uint32_t SystemLFRCOClockGet(void);
172 uint32_t SystemULFRCOClockGet(void);
173 
174 uint32_t SystemLFXOClockGet(void);
175 void SystemLFXOClockSet(uint32_t freq);
176 
177 /** @} End of group */
178 /** @} End of group Parts */
179 
180 #ifdef __cplusplus
181 }
182 #endif
183 #endif /* SYSTEM_EFM32_H */
184