1 /* 2 * Copyright (c) 2017-2019 Arm Limited 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 /* 8 * This file is derivative of CMSIS V5.01 Device\_Template_Vendor\Vendor\Device\Include\Device.h 9 */ 10 11 #ifndef SYSTEM_CMSDK_MUSCA_B1_H 12 #define SYSTEM_CMSDK_MUSCA_B1_H 13 14 #ifdef __cplusplus 15 extern "C" { 16 #endif 17 18 /* =========================================================================================================================== */ 19 /* ================ Interrupt Number Definition ================ */ 20 /* =========================================================================================================================== */ 21 22 typedef enum IRQn { 23 /* =========================================== Core Specific Interrupt Numbers ============================================= */ 24 NonMaskableInt_IRQn = -14, /* -14 Non Maskable Interrupt */ 25 HardFault_IRQn = -13, /* -13 HardFault Interrupt */ 26 MemoryManagement_IRQn = -12, /* -12 Memory Management Interrupt */ 27 BusFault_IRQn = -11, /* -11 Bus Fault Interrupt */ 28 UsageFault_IRQn = -10, /* -10 Usage Fault Interrupt */ 29 SecureFault_IRQn = -9, /* -9 Secure Fault Interrupt */ 30 SVCall_IRQn = -5, /* -5 SV Call Interrupt */ 31 DebugMonitor_IRQn = -4, /* -4 Debug Monitor Interrupt */ 32 PendSV_IRQn = -2, /* -2 Pend SV Interrupt */ 33 SysTick_IRQn = -1, /* -1 System Tick Interrupt */ 34 35 /* ======================================== Musca Specific SSE-200 Interrupt Numbers ====================================== */ 36 NS_WATCHDOG_RESET_IRQn = 0, /* Non-Secure Watchdog Reset Request Interrupt */ 37 NS_WATCHDOG_IRQn = 1, /* Non-Secure Watchdog Interrupt */ 38 S32K_TIMER_IRQn = 2, /* S32K Timer Interrupt */ 39 TIMER0_IRQn = 3, /* CMSDK Timer 0 Interrupt */ 40 TIMER1_IRQn = 4, /* CMSDK Timer 1 Interrupt */ 41 DUALTIMER_IRQn = 5, /* CMSDK Dual Timer Interrupt */ 42 MHU0_IRQn = 6, /* Message Handling Unit 0 Interrupt */ 43 MHU1_IRQn = 7, /* Message Handling Unit 1 Interrupt */ 44 CRYPTOCELL_IRQn = 8, /* CryptoCell-312 Interrupt */ 45 S_MPC_COMBINED_IRQn = 9, /* Secure Combined MPC Interrupt */ 46 S_PPC_COMBINED_IRQn = 10, /* Secure Combined PPC Interrupt */ 47 S_MSC_COMBINED_IRQn = 11, /* Secure Combined MSC Interrupt */ 48 S_BRIDGE_ERR_IRQn = 12, /* Secure Bridge Error Combined Interrupt */ 49 I_CACHE_INV_ERR_IRQn = 13, /* Instruction Cache Invalidation Interrupt */ 50 /* Reserved = 14, Reserved */ 51 SYS_PPU_IRQn = 15, /* System PPU Interrupt */ 52 CPU0_PPU_IRQn = 16, /* CPU0 PPU Interrupt */ 53 CPU1_PPU_IRQn = 17, /* CPU1 PPU Interrupt */ 54 CPU0_DGB_PPU_IRQn = 18, /* CPU0 Debug PPU Interrupt */ 55 CPU1_DGB_PPU_IRQn = 19, /* CPU1 Debug PPU Interrupt */ 56 CRYPTOCELL_PPU_IRQn = 20, /* CryptoCell PPU Interrupt */ 57 /* Reserved = 21, Reserved */ 58 RAM0_PPU_IRQn = 22, /* RAM 0 PPU Interrupt */ 59 RAM1_PPU_IRQn = 23, /* RAM 1 PPU Interrupt */ 60 RAM2_PPU_IRQn = 24, /* RAM 2 PPU Interrupt */ 61 RAM3_PPU_IRQn = 25, /* RAM 3 PPU Interrupt */ 62 DEBUG_PPU_IRQn = 26, /* Debug PPU Interrupt */ 63 /* Reserved = 27, Reserved */ 64 CPU0_CTI_IRQn = 28, /* CPU0 CTI Interrupt */ 65 CPU1_CTI_IRQn = 29, /* CPU1 CTI Interrupt */ 66 /* Reserved = 30, Reserved */ 67 /* Reserved = 31, Reserved */ 68 /* ========================================== Musca Specific Expansion Interrupt Numbers =================================== */ 69 /* None = 32, Not used. Tied to 0 */ 70 GpTimer_IRQn = 33, /* General Purpose Timer Interrupt */ 71 I2C0_IRQn = 34, /* I2C0 Interrupt */ 72 I2C1_IRQn = 35, /* I2C1 Interrupt */ 73 I2S_IRQn = 36, /* I2S Interrupt */ 74 SPI_IRQn = 37, /* SPI Interrupt */ 75 QSPI_IRQn = 38, /* QSPI Interrupt */ 76 UART0_Rx_IRQn = 39, /* UART0 receive FIFO interrupt */ 77 UART0_Tx_IRQn = 40, /* UART0 transmit FIFO interrupt */ 78 UART0_RxTimeout_IRQn = 41, /* UART0 receive timeout interrupt */ 79 UART0_ModemStatus_IRQn = 42, /* UART0 modem status interrupt */ 80 UART0_Error_IRQn = 43, /* UART0 error interrupt */ 81 UART0_IRQn = 44, /* UART0 interrupt */ 82 UART1_Rx_IRQn = 45, /* UART1 receive FIFO interrupt */ 83 UART1_Tx_IRQn = 46, /* UART1 transmit FIFO interrupt */ 84 UART1_RxTimeout_IRQn = 47, /* UART1 receive timeout interrupt */ 85 UART1_ModemStatus_IRQn = 48, /* UART1 modem status interrupt */ 86 UART1_Error_IRQn = 49, /* UART1 error interrupt */ 87 UART1_IRQn = 50, /* UART1 interrupt */ 88 GPIO_0_IRQn = 51, /* GPIO 0 interrupt */ 89 GPIO_1_IRQn = 52, /* GPIO 1 interrupt */ 90 GPIO_2_IRQn = 53, /* GPIO 2 interrupt */ 91 GPIO_3_IRQn = 54, /* GPIO 3 interrupt */ 92 GPIO_4_IRQn = 55, /* GPIO 4 interrupt */ 93 GPIO_5_IRQn = 56, /* GPIO 5 interrupt */ 94 GPIO_6_IRQn = 57, /* GPIO 6 interrupt */ 95 GPIO_7_IRQn = 58, /* GPIO 7 interrupt */ 96 GPIO_8_IRQn = 59, /* GPIO 8 interrupt */ 97 GPIO_9_IRQn = 60, /* GPIO 9 interrupt */ 98 GPIO_10_IRQn = 61, /* GPIO 10 interrupt */ 99 GPIO_11_IRQn = 62, /* GPIO 11 interrupt */ 100 GPIO_12_IRQn = 63, /* GPIO 12 interrupt */ 101 GPIO_13_IRQn = 64, /* GPIO 13 interrupt */ 102 GPIO_14_IRQn = 65, /* GPIO 14 interrupt */ 103 GPIO_15_IRQn = 66, /* GPIO 15 interrupt */ 104 Combined_IRQn = 67, /* Combined interrupt */ 105 PVT_IRQn = 68, /* PVT sensor interrupt */ 106 /* Reserved = 69, Reserved */ 107 PWM_0_IRQn = 70, /* PWM0 interrupt */ 108 RTC_IRQn = 71, /* RTC interrupt */ 109 GpTimer0_IRQn = 72, /* General Purpose Timer0 Interrupt */ 110 GpTimer1_IRQn = 73, /* General Purpose Timer1 Interrupt */ 111 PWM_1_IRQn = 74, /* PWM1 interrupt */ 112 PWM_2_IRQn = 75, /* PWM2 interrupt */ 113 IOMUX_IRQn = 76, /* IOMUX interrupt */ 114 } IRQn_Type; 115 116 117 118 /* =========================================================================================================================== */ 119 /* ================ Processor and Core Peripheral Section ================ */ 120 /* =========================================================================================================================== */ 121 122 /* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */ 123 #define __CM33_REV 0x0000U /* Core revision r0p1 */ 124 #define __SAUREGION_PRESENT 1U /* SAU regions present */ 125 #define __MPU_PRESENT 1U /* MPU present */ 126 #define __VTOR_PRESENT 1U /* VTOR present */ 127 #define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */ 128 #define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ 129 130 /* CORE 0 doesn't have FPU or DSP */ 131 #define __FPU_PRESENT 0U /* no FPU present */ 132 #define __DSP_PRESENT 0U /* no DSP extension present */ 133 134 #ifdef __cplusplus 135 } 136 #endif 137 138 #include <core_cm33.h> /*!< ARM Cortex-M33 processor and core peripherals */ 139 140 #endif /* SYSTEM_CMSDK_MUSCA_B1_H */ 141
