1 /* 2 ** ################################################################### 3 ** Processors: RV32M1_ri5cy 4 ** RV32M1_ri5cy 5 ** 6 ** Compilers: Keil ARM C/C++ Compiler 7 ** GNU C Compiler 8 ** IAR ANSI C/C++ Compiler for ARM 9 ** MCUXpresso Compiler 10 ** 11 ** Reference manual: RV32M1 Series Reference Manual, Rev. 1 , 8/10/2018 12 ** Version: rev. 1.0, 2018-10-02 13 ** Build: b180926 14 ** 15 ** Abstract: 16 ** Provides a system configuration function and a global variable that 17 ** contains the system frequency. It configures the device and initializes 18 ** the oscillator (PLL) that is part of the microcontroller device. 19 ** 20 ** Copyright 2016 Freescale Semiconductor, Inc. 21 ** Copyright 2016-2018 NXP 22 ** All rights reserved. 23 ** 24 ** SPDX-License-Identifier: BSD-3-Clause 25 ** 26 ** http: www.nxp.com 27 ** mail: support@nxp.com 28 ** 29 ** Revisions: 30 ** - rev. 1.0 (2018-10-02) 31 ** Initial version. 32 ** 33 ** ################################################################### 34 */ 35 36 /*! 37 * @file RV32M1_ri5cy 38 * @version 1.0 39 * @date 2018-10-02 40 * @brief Device specific configuration file for RV32M1_ri5cy (header file) 41 * 42 * Provides a system configuration function and a global variable that contains 43 * the system frequency. It configures the device and initializes the oscillator 44 * (PLL) that is part of the microcontroller device. 45 */ 46 47 #ifndef _SYSTEM_RV32M1_ri5cy_H_ 48 #define _SYSTEM_RV32M1_ri5cy_H_ /**< Symbol preventing repeated inclusion */ 49 50 #ifdef __cplusplus 51 extern "C" { 52 #endif 53 54 #include <stdint.h> 55 #include <stdbool.h> 56 57 58 #ifndef DISABLE_WDOG 59 #define DISABLE_WDOG 1 60 #endif 61 62 /* Define clock source values */ 63 #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */ 64 65 /* Low power mode enable */ 66 /* SMC_PMPROT: AHSRUN=1, AVLP=1,ALLS=1,AVLLS=0x3 */ 67 #define SYSTEM_SMC_PMPROT_VALUE 0xABu /* SMC_PMPROT */ 68 #define SYSTEM_SMC_PMCTRL_VALUE 0x0u /* SMC_PMCTRL */ 69 70 #define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */ 71 72 73 74 /** 75 * @brief System clock frequency (core clock) 76 * 77 * The system clock frequency supplied to the SysTick timer and the processor 78 * core clock. This variable can be used by the user application to setup the 79 * SysTick timer or configure other parameters. It may also be used by debugger to 80 * query the frequency of the debug timer or configure the trace clock speed 81 * SystemCoreClock is initialized with a correct predefined value. 82 */ 83 extern uint32_t SystemCoreClock; 84 85 /** 86 * @brief Setup the microcontroller system. 87 * 88 * Typically this function configures the oscillator (PLL) that is part of the 89 * microcontroller device. For systems with variable clock speed it also updates 90 * the variable SystemCoreClock. SystemInit is called from startup_device file. 91 */ 92 void SystemInit (void); 93 94 /** 95 * @brief Updates the SystemCoreClock variable. 96 * 97 * It must be called whenever the core clock is changed during program 98 * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates 99 * the current core clock. 100 */ 101 void SystemCoreClockUpdate (void); 102 103 /** 104 * @brief SystemInit function hook. 105 * 106 * This weak function allows to call specific initialization code during the 107 * SystemInit() execution.This can be used when an application specific code needs 108 * to be called as close to the reset entry as possible (for example the Multicore 109 * Manager MCMGR_EarlyInit() function call). 110 * NOTE: No global r/w variables can be used in this hook function because the 111 * initialization of these variables happens after this function. 112 */ 113 void SystemInitHook (void); 114 115 /** 116 * @brief System IRQ handler which dispatches specific IRQ to corresponding registered handler. 117 * 118 * It is called from IRQ exception context and dispatches to registered handler according to 119 * MCAUSE interrupt number. 120 * 121 * @param mcause IRQ acknowledge value read from MCAUSE 122 */ 123 void SystemIrqHandler(uint32_t mcause); 124 125 /** 126 * @brief Get IRQ nesting level of current context. 127 * 128 * If the return value is 0, then the context is not ISR, otherwise the context is ISR. 129 * 130 * @return IRQ nesting level 131 */ 132 uint32_t SystemGetIRQNestingLevel (void); 133 134 /** 135 * @brief Setup systick for RTOS system. 136 * 137 * @param tickRateHz Tick number per second 138 * @param intPriority IRQ interrupt priority (the smaller, the higher priority) 139 */ 140 void SystemSetupSystick (uint32_t tickRateHz, uint32_t intPriority); 141 142 /** 143 * @brief Clear systick flag status so that next tick interrupt may occur. 144 */ 145 void SystemClearSystickFlag (void); 146 147 /** 148 * @brief Sysem is in ISR or not. 149 */ 150 bool SystemInISR(void); 151 152 #define SysTick_Handler LPIT0_IRQHandler 153 154 /** 155 * @brief Set interrupt priority in Event unit. 156 */ 157 void EVENT_SetIRQPriority(IRQn_Type IRQn, uint8_t intPriority); 158 159 /** 160 * @brief Get interrupt priority in Event unit. 161 */ 162 uint8_t EVENT_GetIRQPriority(IRQn_Type IRQn); 163 164 /** 165 * @brief Reset the system. 166 */ 167 void EVENT_SystemReset(void); 168 169 #define NVIC_SystemReset EVENT_SystemReset 170 171 /* Priority setting macro remap. */ 172 #define NVIC_SetPriority EVENT_SetIRQPriority 173 174 /* Priority getting macro remap. */ 175 #define NVIC_GetPriority EVENT_GetIRQPriority 176 177 178 #ifdef __cplusplus 179 } 180 #endif 181 182 #endif /* _SYSTEM_RV32M1_ri5cy_H_ */ 183
