1 /*
2 ** ###################################################################
3 ** Processors: MKV31F512VLH12
4 ** MKV31F512VLL12
5 **
6 ** Compilers: Freescale C/C++ for Embedded ARM
7 ** GNU C Compiler
8 ** IAR ANSI C/C++ Compiler for ARM
9 ** Keil ARM C/C++ Compiler
10 ** MCUXpresso Compiler
11 **
12 ** Reference manual: KV31P100M120SF7RM, Rev. 1, March 24, 2014
13 ** Version: rev. 1.7, 2015-02-19
14 ** Build: b181105
15 **
16 ** Abstract:
17 ** Provides a system configuration function and a global variable that
18 ** contains the system frequency. It configures the device and initializes
19 ** the oscillator (PLL) that is part of the microcontroller device.
20 **
21 ** Copyright 2016 Freescale Semiconductor, Inc.
22 ** Copyright 2016-2018 NXP
23 ** All rights reserved.
24 **
25 ** SPDX-License-Identifier: BSD-3-Clause
26 **
27 ** http: www.nxp.com
28 ** mail: support@nxp.com
29 **
30 ** Revisions:
31 ** - rev. 1.0 (2013-11-01)
32 ** Initial version.
33 ** - rev. 1.1 (2013-12-20)
34 ** Update according to reference manual rev. 0.6,
35 ** - rev. 1.2 (2014-01-13)
36 ** Update according to reference manual rev. 0.61,
37 ** - rev. 1.3 (2014-02-10)
38 ** The declaration of clock configurations has been moved to separate header file system_MKV31F51212.h
39 ** - rev. 1.4 (2014-05-06)
40 ** Update according to reference manual rev. 1.0,
41 ** Update of system and startup files.
42 ** Module access macro module_BASES replaced by module_BASE_PTRS.
43 ** - rev. 1.5 (2014-08-28)
44 ** Update of system files - default clock configuration changed.
45 ** Update of startup files - possibility to override DefaultISR added.
46 ** - rev. 1.6 (2014-10-14)
47 ** Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
48 ** - rev. 1.7 (2015-02-19)
49 ** Renamed interrupt vector LLW to LLWU.
50 **
51 ** ###################################################################
52 */
53
54 /*!
55 * @file MKV31F51212
56 * @version 1.7
57 * @date 2015-02-19
58 * @brief Device specific configuration file for MKV31F51212 (implementation
59 * file)
60 *
61 * Provides a system configuration function and a global variable that contains
62 * the system frequency. It configures the device and initializes the oscillator
63 * (PLL) that is part of the microcontroller device.
64 */
65
66 #include <stdint.h>
67 #include "fsl_device_registers.h"
68
69
70
71 /* ----------------------------------------------------------------------------
72 -- Core clock
73 ---------------------------------------------------------------------------- */
74
75 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
76
77 /* ----------------------------------------------------------------------------
78 -- SystemInit()
79 ---------------------------------------------------------------------------- */
80
SystemInit(void)81 void SystemInit (void) {
82 #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
83 SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
84 #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
85
86 #if (DISABLE_WDOG)
87 /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
88 WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
89 /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
90 WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
91 /* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
92 WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
93 WDOG_STCTRLH_WAITEN_MASK |
94 WDOG_STCTRLH_STOPEN_MASK |
95 WDOG_STCTRLH_ALLOWUPDATE_MASK |
96 WDOG_STCTRLH_CLKSRC_MASK |
97 0x0100U;
98 #endif /* (DISABLE_WDOG) */
99
100 SystemInitHook();
101 }
102
103 /* ----------------------------------------------------------------------------
104 -- SystemCoreClockUpdate()
105 ---------------------------------------------------------------------------- */
106
SystemCoreClockUpdate(void)107 void SystemCoreClockUpdate (void) {
108
109 uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
110 uint16_t Divider;
111 uint8_t tmpC7 = 0;
112
113 if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) {
114 /* Output of FLL or PLL is selected */
115 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) {
116 /* FLL is selected */
117 if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) {
118 /* External reference clock is selected */
119 switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
120 case 0x00U:
121 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
122 break;
123 case 0x02U:
124 default:
125 MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
126 break;
127 }
128 tmpC7 = MCG->C7;
129 if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((tmpC7 & MCG_C7_OSCSEL_MASK) != 0x01U)) {
130 switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
131 case 0x38U:
132 Divider = 1536U;
133 break;
134 case 0x30U:
135 Divider = 1280U;
136 break;
137 default:
138 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
139 break;
140 }
141 } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
142 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
143 }
144 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
145 } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
146 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
147 } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
148 /* Select correct multiplier to calculate the MCG output clock */
149 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
150 case 0x00U:
151 MCGOUTClock *= 640U;
152 break;
153 case 0x20U:
154 MCGOUTClock *= 1280U;
155 break;
156 case 0x40U:
157 MCGOUTClock *= 1920U;
158 break;
159 case 0x60U:
160 MCGOUTClock *= 2560U;
161 break;
162 case 0x80U:
163 MCGOUTClock *= 732U;
164 break;
165 case 0xA0U:
166 MCGOUTClock *= 1464U;
167 break;
168 case 0xC0U:
169 MCGOUTClock *= 2197U;
170 break;
171 case 0xE0U:
172 MCGOUTClock *= 2929U;
173 break;
174 default:
175 MCGOUTClock *= 640U;
176 break;
177 }
178 } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
179 /* PLL is selected */
180 Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U);
181 MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
182 Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U);
183 MCGOUTClock *= Divider; /* Calculate the MCG output clock */
184 } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
185 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) {
186 /* Internal reference clock is selected */
187 if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) {
188 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
189 } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
190 Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
191 MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
192 } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
193 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) {
194 /* External reference clock is selected */
195 switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
196 case 0x00U:
197 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
198 break;
199 case 0x02U:
200 default:
201 MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
202 break;
203 }
204 } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
205 /* Reserved value */
206 return;
207 } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
208 SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
209 }
210
211 /* ----------------------------------------------------------------------------
212 -- SystemInitHook()
213 ---------------------------------------------------------------------------- */
214
SystemInitHook(void)215 __attribute__ ((weak)) void SystemInitHook (void) {
216 /* Void implementation of the weak function. */
217 }
218
