1 /*
2 ** ###################################################################
3 ** Processors: MKV10Z128VFM7
4 ** MKV10Z128VLC7
5 ** MKV10Z128VLF7
6 ** MKV10Z128VLH7
7 ** MKV10Z64VFM7
8 ** MKV10Z64VLC7
9 ** MKV10Z64VLF7
10 ** MKV10Z64VLH7
11 **
12 ** Compilers: Freescale C/C++ for Embedded ARM
13 ** GNU C Compiler
14 ** IAR ANSI C/C++ Compiler for ARM
15 ** Keil ARM C/C++ Compiler
16 ** MCUXpresso Compiler
17 **
18 ** Reference manual: KV11P64M75RM Rev.2, April 2015
19 ** Version: rev. 1.1, 2017-03-22
20 ** Build: b181105
21 **
22 ** Abstract:
23 ** Provides a system configuration function and a global variable that
24 ** contains the system frequency. It configures the device and initializes
25 ** the oscillator (PLL) that is part of the microcontroller device.
26 **
27 ** Copyright 2016 Freescale Semiconductor, Inc.
28 ** Copyright 2016-2018 NXP
29 ** All rights reserved.
30 **
31 ** SPDX-License-Identifier: BSD-3-Clause
32 **
33 ** http: www.nxp.com
34 ** mail: support@nxp.com
35 **
36 ** Revisions:
37 ** - rev. 1.0 (2014-12-14)
38 ** Initial version.
39 ** - rev. 1.1 (2017-03-22)
40 ** Removed superfluous CAN macros.
41 **
42 ** ###################################################################
43 */
44
45 /*!
46 * @file MKV10Z1287
47 * @version 1.1
48 * @date 2017-03-22
49 * @brief Device specific configuration file for MKV10Z1287 (implementation file)
50 *
51 * Provides a system configuration function and a global variable that contains
52 * the system frequency. It configures the device and initializes the oscillator
53 * (PLL) that is part of the microcontroller device.
54 */
55
56 #include <stdint.h>
57 #include "fsl_device_registers.h"
58
59
60
61 /* ----------------------------------------------------------------------------
62 -- Core clock
63 ---------------------------------------------------------------------------- */
64
65 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
66
67 /* ----------------------------------------------------------------------------
68 -- SystemInit()
69 ---------------------------------------------------------------------------- */
70
SystemInit(void)71 void SystemInit (void) {
72
73 #if (DISABLE_WDOG)
74 /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
75 WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
76 /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
77 WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
78 /* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
79 WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
80 WDOG_STCTRLH_WAITEN_MASK |
81 WDOG_STCTRLH_STOPEN_MASK |
82 WDOG_STCTRLH_ALLOWUPDATE_MASK |
83 WDOG_STCTRLH_CLKSRC_MASK |
84 0x0100U;
85 #endif /* (DISABLE_WDOG) */
86
87 SystemInitHook();
88 }
89
90 /* ----------------------------------------------------------------------------
91 -- SystemCoreClockUpdate()
92 ---------------------------------------------------------------------------- */
93
SystemCoreClockUpdate(void)94 void SystemCoreClockUpdate (void) {
95
96 uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
97 uint16_t Divider;
98
99 if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) {
100 /* FLL is selected */
101 if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) {
102 /* External reference clock is selected */
103 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
104 if ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) {
105 switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
106 case 0x38U:
107 Divider = 1536U;
108 break;
109 case 0x30U:
110 Divider = 1280U;
111 break;
112 default:
113 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
114 break;
115 }
116 } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
117 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
118 }
119 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
120 } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
121 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
122 } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
123 /* Select correct multiplier to calculate the MCG output clock */
124 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
125 case 0x00U:
126 MCGOUTClock *= 640U;
127 break;
128 case 0x20U:
129 MCGOUTClock *= 1280U;
130 break;
131 case 0x40U:
132 MCGOUTClock *= 1920U;
133 break;
134 case 0x60U:
135 MCGOUTClock *= 2560U;
136 break;
137 case 0x80U:
138 MCGOUTClock *= 732U;
139 break;
140 case 0xA0U:
141 MCGOUTClock *= 1464U;
142 break;
143 case 0xC0U:
144 MCGOUTClock *= 2197U;
145 break;
146 case 0xE0U:
147 MCGOUTClock *= 2929U;
148 break;
149 default:
150 MCGOUTClock *= 640U;
151 break;
152 }
153 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) {
154 /* Internal reference clock is selected */
155 if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) {
156 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
157 } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
158 Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
159 MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
160 } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
161 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) {
162 /* External reference clock is selected */
163 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
164 } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
165 /* Reserved value */
166 return;
167 } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
168 SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
169
170 }
171
172 /* ----------------------------------------------------------------------------
173 -- SystemInitHook()
174 ---------------------------------------------------------------------------- */
175
SystemInitHook(void)176 __attribute__ ((weak)) void SystemInitHook (void) {
177 /* Void implementation of the weak function. */
178 }
179
