1 /*
2 ** ###################################################################
3 **     Processors:          MKM35Z256VLL7
4 **                          MKM35Z256VLL7R
5 **                          MKM35Z256VLQ7
6 **                          MKM35Z256VLQ7R
7 **                          MKM35Z512VLL7
8 **                          MKM35Z512VLL7R
9 **                          MKM35Z512VLQ7
10 **                          MKM35Z512VLQ7R
11 **
12 **     Compilers:           Freescale C/C++ for Embedded ARM
13 **                          GNU C Compiler
14 **                          IAR ANSI C/C++ Compiler for ARM
15 **                          Keil ARM C/C++ Compiler
16 **                          MCUXpresso Compiler
17 **
18 **     Reference manual:    KM35P144M75SF0RM, Rev.1, Dec 2019
19 **     Version:             rev. 2.0, 2019-12-20
20 **     Build:               b201012
21 **
22 **     Abstract:
23 **         Provides a system configuration function and a global variable that
24 **         contains the system frequency. It configures the device and initializes
25 **         the oscillator (PLL) that is part of the microcontroller device.
26 **
27 **     Copyright 2016 Freescale Semiconductor, Inc.
28 **     Copyright 2016-2020 NXP
29 **     All rights reserved.
30 **
31 **     SPDX-License-Identifier: BSD-3-Clause
32 **
33 **     http:                 www.nxp.com
34 **     mail:                 support@nxp.com
35 **
36 **     Revisions:
37 **     - rev. 1.0 (2019-08-01)
38 **         Initial version.
39 **     - rev. 2.0 (2019-12-20)
40 **         Based on RM Rev.1.
41 **
42 ** ###################################################################
43 */
44 
45 /*!
46  * @file MKM35Z7
47  * @version 2.0
48  * @date 2019-12-20
49  * @brief Device specific configuration file for MKM35Z7 (implementation file)
50  *
51  * Provides a system configuration function and a global variable that contains
52  * the system frequency. It configures the device and initializes the oscillator
53  * (PLL) that is part of the microcontroller device.
54  */
55 
56 #include <stdint.h>
57 #include "fsl_device_registers.h"
58 
59 
60 
61 /* ----------------------------------------------------------------------------
62    -- Core clock
63    ---------------------------------------------------------------------------- */
64 
65 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
66 
67 /* ----------------------------------------------------------------------------
68    -- SystemInit()
69    ---------------------------------------------------------------------------- */
70 
SystemInit(void)71 void SystemInit (void) {
72 
73 #if (DISABLE_WDOG)
74   /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
75   WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
76   /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
77   WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
78   /* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
79   WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
80                  WDOG_STCTRLH_STOPEN_MASK |
81                  WDOG_STCTRLH_ALLOWUPDATE_MASK |
82                  WDOG_STCTRLH_CLKSRC_MASK |
83                  0x0100U;
84 #endif /* (DISABLE_WDOG) */
85 
86   SystemInitHook();
87 }
88 
89 /* ----------------------------------------------------------------------------
90    -- SystemCoreClockUpdate()
91    ---------------------------------------------------------------------------- */
92 
SystemCoreClockUpdate(void)93 void SystemCoreClockUpdate (void) {
94 
95   uint32_t MCGOUTClock;                                                        /* Variable to store output clock frequency of the MCG module */
96   uint16_t Divider;
97 
98   if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) {
99     /* Output of FLL or PLL is selected */
100     if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) {
101       /* FLL is selected */
102       if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) {
103         /* External reference clock is selected */
104         if ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x00U) {
105           MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
106         } else {
107           MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
108         }
109         if (((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) {
110           switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
111           case 0x38U:
112             Divider = 1536U;
113             break;
114           case 0x30U:
115             Divider = 1280U;
116             break;
117           default:
118             Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
119             break;
120           }
121         } else {/* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x00U) */
122           Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
123         }
124         MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
125       } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
126         MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
127       } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
128       /* Select correct multiplier to calculate the MCG output clock  */
129       switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
130         case 0x00U:
131           MCGOUTClock *= 640U;
132           break;
133         case 0x20U:
134           MCGOUTClock *= 1280U;
135           break;
136         case 0x40U:
137           MCGOUTClock *= 1920U;
138           break;
139         case 0x60U:
140           MCGOUTClock *= 2560U;
141           break;
142         case 0x80U:
143           MCGOUTClock *= 732U;
144           break;
145         case 0xA0U:
146           MCGOUTClock *= 1464U;
147           break;
148         case 0xC0U:
149           MCGOUTClock *= 2197U;
150           break;
151         case 0xE0U:
152           MCGOUTClock *= 2929U;
153           break;
154         default:
155           MCGOUTClock *= 640U;
156           break;
157       }
158     }
159     else {/* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
160       /* PLL is selected */
161       if ((MCG->C7 & MCG_C7_PLL32KREFSEL_MASK) == 0x00U) {
162         /* RTC 32 kHz oscillator selected */
163         MCGOUTClock = CPU_XTAL32k_CLK_HZ;
164       } else if ((MCG->C7 & MCG_C7_PLL32KREFSEL_MASK) == 0x40U) {
165         /* 32kHz IRC selected */
166         MCGOUTClock = CPU_INT_SLOW_CLK_HZ;
167       } else if ((MCG->C7 & MCG_C7_PLL32KREFSEL_MASK) == 0x80U) {
168         /* FLL FRDIV selected */
169         if ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x00U) {
170           MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
171         } else {
172           MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
173         }
174         if (((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) {
175           switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
176           case 0x38U:
177             Divider = 1536U;
178             break;
179           case 0x30U:
180             Divider = 1280U;
181             break;
182           default:
183             Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
184             break;
185           }
186         } else {/* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x00U) */
187           Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
188         }
189         MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
190       } else { /* (MCG->C7 & MCG_C7_PLL32KREFSEL_MASK) == 0xB0U */
191         /* Reserved value */
192         return;
193       }
194       MCGOUTClock *= 375U; /* Calculate the MCG output clock */
195     }
196   } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) {
197     /* Internal reference clock is selected */
198     if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) {
199       MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
200     } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
201       Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
202       MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
203     } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
204   } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) {
205     /* External reference clock is selected */
206     if ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x00U) {
207       MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
208     } else {
209       MCGOUTClock = CPU_XTAL_CLK_HZ;   /* System oscillator drives MCG clock */
210     }
211   } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
212     /* Reserved value */
213     return;
214   } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
215   SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_CLKDIVSYS_MASK) >> SIM_CLKDIV1_CLKDIVSYS_SHIFT)));
216 }
217 
218 /* ----------------------------------------------------------------------------
219    -- SystemInitHook()
220    ---------------------------------------------------------------------------- */
221 
SystemInitHook(void)222 __attribute__ ((weak)) void SystemInitHook (void) {
223   /* Void implementation of the weak function. */
224 }
225