1 /*
2 ** ###################################################################
3 ** Processor: MKM34Z128ACLL5
4 ** Compilers: Freescale C/C++ for Embedded ARM
5 ** GNU C Compiler
6 ** IAR ANSI C/C++ Compiler for ARM
7 ** Keil ARM C/C++ Compiler
8 ** MCUXpresso Compiler
9 **
10 ** Reference manual: MKMxxZxxACxx5RM, Rev. 2, 10/2017
11 ** Version: rev. 1.0, 2014-07-22
12 ** Build: b201216
13 **
14 ** Abstract:
15 ** Provides a system configuration function and a global variable that
16 ** contains the system frequency. It configures the device and initializes
17 ** the oscillator (PLL) that is part of the microcontroller device.
18 **
19 ** Copyright 2016 Freescale Semiconductor, Inc.
20 ** Copyright 2016-2020 NXP
21 ** All rights reserved.
22 **
23 ** SPDX-License-Identifier: BSD-3-Clause
24 **
25 ** http: www.nxp.com
26 ** mail: support@nxp.com
27 **
28 ** Revisions:
29 ** - rev. 1.0 (2014-07-22)
30 ** Initial version.
31 **
32 ** ###################################################################
33 */
34
35 /*!
36 * @file MKM34ZA5
37 * @version 1.0
38 * @date 2014-07-22
39 * @brief Device specific configuration file for MKM34ZA5 (implementation file)
40 *
41 * Provides a system configuration function and a global variable that contains
42 * the system frequency. It configures the device and initializes the oscillator
43 * (PLL) that is part of the microcontroller device.
44 */
45
46 #include <stdint.h>
47 #include "fsl_device_registers.h"
48
49
50
51 /* ----------------------------------------------------------------------------
52 -- Core clock
53 ---------------------------------------------------------------------------- */
54
55 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
56
57 /* ----------------------------------------------------------------------------
58 -- SystemInit()
59 ---------------------------------------------------------------------------- */
60
SystemInit(void)61 void SystemInit (void) {
62
63 #if (DISABLE_WDOG)
64 /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
65 WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
66 /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
67 WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
68 /* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
69 WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
70 WDOG_STCTRLH_STOPEN_MASK |
71 WDOG_STCTRLH_ALLOWUPDATE_MASK |
72 WDOG_STCTRLH_CLKSRC_MASK |
73 0x0100U;
74 #endif /* (DISABLE_WDOG) */
75
76 SystemInitHook();
77 }
78
79 /* ----------------------------------------------------------------------------
80 -- SystemCoreClockUpdate()
81 ---------------------------------------------------------------------------- */
82
SystemCoreClockUpdate(void)83 void SystemCoreClockUpdate (void) {
84
85 uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
86 uint16_t Divider;
87
88 if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) {
89 /* Output of FLL or PLL is selected */
90 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) {
91 /* FLL is selected */
92 if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) {
93 /* External reference clock is selected */
94 if ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x00U) {
95 MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
96 } else {
97 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
98 }
99 if (((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) {
100 switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
101 case 0x38U:
102 Divider = 1536U;
103 break;
104 case 0x30U:
105 Divider = 1280U;
106 break;
107 default:
108 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
109 break;
110 }
111 } else {/* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x00U) */
112 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
113 }
114 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
115 } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
116 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
117 } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
118 /* Select correct multiplier to calculate the MCG output clock */
119 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
120 case 0x00U:
121 MCGOUTClock *= 640U;
122 break;
123 case 0x20U:
124 MCGOUTClock *= 1280U;
125 break;
126 case 0x40U:
127 MCGOUTClock *= 1920U;
128 break;
129 case 0x60U:
130 MCGOUTClock *= 2560U;
131 break;
132 case 0x80U:
133 MCGOUTClock *= 732U;
134 break;
135 case 0xA0U:
136 MCGOUTClock *= 1464U;
137 break;
138 case 0xC0U:
139 MCGOUTClock *= 2197U;
140 break;
141 case 0xE0U:
142 MCGOUTClock *= 2929U;
143 break;
144 default:
145 MCGOUTClock *= 640U;
146 break;
147 }
148 }
149 else {/* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
150 /* PLL is selected */
151 if ((MCG->C7 & MCG_C7_PLL32KREFSEL_MASK) == 0x00U) {
152 /* RTC 32 kHz oscillator selected */
153 MCGOUTClock = CPU_XTAL32k_CLK_HZ;
154 } else if ((MCG->C7 & MCG_C7_PLL32KREFSEL_MASK) == 0x40U) {
155 /* 32kHz IRC selected */
156 MCGOUTClock = CPU_INT_SLOW_CLK_HZ;
157 } else if ((MCG->C7 & MCG_C7_PLL32KREFSEL_MASK) == 0x80U) {
158 /* FLL FRDIV selected */
159 if ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x00U) {
160 MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
161 } else {
162 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
163 }
164 if (((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) {
165 switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
166 case 0x38U:
167 Divider = 1536U;
168 break;
169 case 0x30U:
170 Divider = 1280U;
171 break;
172 default:
173 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
174 break;
175 }
176 } else {/* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x00U) */
177 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
178 }
179 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
180 } else { /* (MCG->C7 & MCG_C7_PLL32KREFSEL_MASK) == 0xB0U */
181 /* Reserved value */
182 return;
183 }
184 MCGOUTClock *= 375U; /* Calculate the MCG output clock */
185 }
186 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) {
187 /* Internal reference clock is selected */
188 if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) {
189 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
190 } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
191 Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
192 MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
193 } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
194 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) {
195 /* External reference clock is selected */
196 if ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x00U) {
197 MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
198 } else {
199 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
200 }
201 } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
202 /* Reserved value */
203 return;
204 } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
205 SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_SYSDIV_MASK) >> SIM_CLKDIV1_SYSDIV_SHIFT)));
206 }
207
208 /* ----------------------------------------------------------------------------
209 -- SystemInitHook()
210 ---------------------------------------------------------------------------- */
211
SystemInitHook(void)212 __attribute__ ((weak)) void SystemInitHook (void) {
213 /* Void implementation of the weak function. */
214 }
215
