1 /*
2 ** ###################################################################
3 ** Processors: MKM34Z256VLL7
4 ** MKM34Z256VLQ7
5 **
6 ** Compilers: Freescale C/C++ for Embedded ARM
7 ** GNU C Compiler
8 ** IAR ANSI C/C++ Compiler for ARM
9 ** Keil ARM C/C++ Compiler
10 ** MCUXpresso Compiler
11 **
12 ** Reference manual: KM34P144M75SF0RM, Rev.1, Jan 2015
13 ** Version: rev. 1.2, 2015-03-06
14 ** Build: b201125
15 **
16 ** Abstract:
17 ** Provides a system configuration function and a global variable that
18 ** contains the system frequency. It configures the device and initializes
19 ** the oscillator (PLL) that is part of the microcontroller device.
20 **
21 ** Copyright 2016 Freescale Semiconductor, Inc.
22 ** Copyright 2016-2020 NXP
23 ** All rights reserved.
24 **
25 ** SPDX-License-Identifier: BSD-3-Clause
26 **
27 ** http: www.nxp.com
28 ** mail: support@nxp.com
29 **
30 ** Revisions:
31 ** - rev. 1.0 (2014-10-17)
32 ** Initial version.
33 ** - rev. 1.1 (2015-01-27)
34 ** Update according to reference manual rev. 1, RC.
35 ** - rev. 1.2 (2015-03-06)
36 ** Update according to reference manual rev. 1.
37 **
38 ** ###################################################################
39 */
40
41 /*!
42 * @file MKM34Z7
43 * @version 1.2
44 * @date 2015-03-06
45 * @brief Device specific configuration file for MKM34Z7 (implementation file)
46 *
47 * Provides a system configuration function and a global variable that contains
48 * the system frequency. It configures the device and initializes the oscillator
49 * (PLL) that is part of the microcontroller device.
50 */
51
52 #include <stdint.h>
53 #include "fsl_device_registers.h"
54
55 /* ----------------------------------------------------------------------------
56 -- Core clock
57 ---------------------------------------------------------------------------- */
58
59 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
60
61 /* ----------------------------------------------------------------------------
62 -- SystemInit()
63 ---------------------------------------------------------------------------- */
64
SystemInit(void)65 void SystemInit(void)
66 {
67 #if (DISABLE_WDOG)
68 /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
69 WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
70 /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
71 WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
72 /* WDOG->STCTRLH:
73 * ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0
74 */
75 WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) | WDOG_STCTRLH_STOPEN_MASK | WDOG_STCTRLH_ALLOWUPDATE_MASK |
76 WDOG_STCTRLH_CLKSRC_MASK | 0x0100U;
77 #endif /* (DISABLE_WDOG) */
78
79 SystemInitHook();
80 }
81
82 /* ----------------------------------------------------------------------------
83 -- SystemCoreClockUpdate()
84 ---------------------------------------------------------------------------- */
85
SystemCoreClockUpdate(void)86 void SystemCoreClockUpdate(void)
87 {
88 uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
89 uint16_t Divider;
90
91 if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U)
92 {
93 /* Output of FLL or PLL is selected */
94 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)
95 {
96 /* FLL is selected */
97 if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)
98 {
99 /* External reference clock is selected */
100 if ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x00U)
101 {
102 MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
103 }
104 else
105 {
106 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
107 }
108 if (((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U))
109 {
110 switch (MCG->C1 & MCG_C1_FRDIV_MASK)
111 {
112 case 0x38U:
113 Divider = 1536U;
114 break;
115 case 0x30U:
116 Divider = 1280U;
117 break;
118 default:
119 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
120 break;
121 }
122 }
123 else
124 { /* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x00U) */
125 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
126 }
127 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
128 }
129 else
130 { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
131 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
132 } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
133 /* Select correct multiplier to calculate the MCG output clock */
134 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK))
135 {
136 case 0x00U:
137 MCGOUTClock *= 640U;
138 break;
139 case 0x20U:
140 MCGOUTClock *= 1280U;
141 break;
142 case 0x40U:
143 MCGOUTClock *= 1920U;
144 break;
145 case 0x60U:
146 MCGOUTClock *= 2560U;
147 break;
148 case 0x80U:
149 MCGOUTClock *= 732U;
150 break;
151 case 0xA0U:
152 MCGOUTClock *= 1464U;
153 break;
154 case 0xC0U:
155 MCGOUTClock *= 2197U;
156 break;
157 case 0xE0U:
158 MCGOUTClock *= 2929U;
159 break;
160 default:
161 MCGOUTClock *= 640U;
162 break;
163 }
164 }
165 else
166 { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
167 /* PLL is selected */
168 if ((MCG->C7 & MCG_C7_PLL32KREFSEL_MASK) == 0x00U)
169 {
170 /* RTC 32 kHz oscillator selected */
171 MCGOUTClock = CPU_XTAL32k_CLK_HZ;
172 }
173 else if ((MCG->C7 & MCG_C7_PLL32KREFSEL_MASK) == 0x40U)
174 {
175 /* 32kHz IRC selected */
176 MCGOUTClock = CPU_INT_SLOW_CLK_HZ;
177 }
178 else if ((MCG->C7 & MCG_C7_PLL32KREFSEL_MASK) == 0x80U)
179 {
180 /* FLL FRDIV selected */
181 if ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x00U)
182 {
183 MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
184 }
185 else
186 {
187 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
188 }
189 if (((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U))
190 {
191 switch (MCG->C1 & MCG_C1_FRDIV_MASK)
192 {
193 case 0x38U:
194 Divider = 1536U;
195 break;
196 case 0x30U:
197 Divider = 1280U;
198 break;
199 default:
200 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
201 break;
202 }
203 }
204 else
205 { /* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x00U) */
206 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
207 }
208 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
209 }
210 else
211 { /* (MCG->C7 & MCG_C7_PLL32KREFSEL_MASK) == 0xB0U */
212 /* Reserved value */
213 return;
214 }
215 MCGOUTClock *= 375U; /* Calculate the MCG output clock */
216 }
217 }
218 else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U)
219 {
220 /* Internal reference clock is selected */
221 if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)
222 {
223 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
224 }
225 else
226 { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
227 Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
228 MCGOUTClock = (uint32_t)(CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
229 } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
230 }
231 else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)
232 {
233 /* External reference clock is selected */
234 if ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x00U)
235 {
236 MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
237 }
238 else
239 {
240 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
241 }
242 }
243 else
244 { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
245 /* Reserved value */
246 return;
247 } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
248 SystemCoreClock =
249 (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_CLKDIVSYS_MASK) >> SIM_CLKDIV1_CLKDIVSYS_SHIFT)));
250 }
251
252 /* ----------------------------------------------------------------------------
253 -- SystemInitHook()
254 ---------------------------------------------------------------------------- */
255
SystemInitHook(void)256 __attribute__((weak)) void SystemInitHook(void)
257 {
258 /* Void implementation of the weak function. */
259 }
260
