1 /*
2 ** ###################################################################
3 **     Processors:          MKM33Z128ACLH5
4 **                          MKM33Z128ACLL5
5 **                          MKM33Z64ACLH5
6 **                          MKM33Z64ACLL5
7 **
8 **     Compilers:           Freescale C/C++ for Embedded ARM
9 **                          GNU C Compiler
10 **                          IAR ANSI C/C++ Compiler for ARM
11 **                          Keil ARM C/C++ Compiler
12 **                          MCUXpresso Compiler
13 **
14 **     Reference manual:    MKMxxZxxACxx5RM, Rev. 2, 10/2017
15 **     Version:             rev. 1.0, 2014-07-22
16 **     Build:               b201216
17 **
18 **     Abstract:
19 **         Provides a system configuration function and a global variable that
20 **         contains the system frequency. It configures the device and initializes
21 **         the oscillator (PLL) that is part of the microcontroller device.
22 **
23 **     Copyright 2016 Freescale Semiconductor, Inc.
24 **     Copyright 2016-2020 NXP
25 **     All rights reserved.
26 **
27 **     SPDX-License-Identifier: BSD-3-Clause
28 **
29 **     http:                 www.nxp.com
30 **     mail:                 support@nxp.com
31 **
32 **     Revisions:
33 **     - rev. 1.0 (2014-07-22)
34 **         Initial version.
35 **
36 ** ###################################################################
37 */
38 
39 /*!
40  * @file MKM33ZA5
41  * @version 1.0
42  * @date 2014-07-22
43  * @brief Device specific configuration file for MKM33ZA5 (implementation file)
44  *
45  * Provides a system configuration function and a global variable that contains
46  * the system frequency. It configures the device and initializes the oscillator
47  * (PLL) that is part of the microcontroller device.
48  */
49 
50 #include <stdint.h>
51 #include "fsl_device_registers.h"
52 
53 
54 
55 /* ----------------------------------------------------------------------------
56    -- Core clock
57    ---------------------------------------------------------------------------- */
58 
59 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
60 
61 /* ----------------------------------------------------------------------------
62    -- SystemInit()
63    ---------------------------------------------------------------------------- */
64 
SystemInit(void)65 void SystemInit (void) {
66 
67 #if (DISABLE_WDOG)
68   /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
69   WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
70   /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
71   WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
72   /* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
73   WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
74                  WDOG_STCTRLH_STOPEN_MASK |
75                  WDOG_STCTRLH_ALLOWUPDATE_MASK |
76                  WDOG_STCTRLH_CLKSRC_MASK |
77                  0x0100U;
78 #endif /* (DISABLE_WDOG) */
79 
80   SystemInitHook();
81 }
82 
83 /* ----------------------------------------------------------------------------
84    -- SystemCoreClockUpdate()
85    ---------------------------------------------------------------------------- */
86 
SystemCoreClockUpdate(void)87 void SystemCoreClockUpdate (void) {
88 
89   uint32_t MCGOUTClock;                                                        /* Variable to store output clock frequency of the MCG module */
90   uint16_t Divider;
91 
92   if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) {
93     /* Output of FLL or PLL is selected */
94     if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) {
95       /* FLL is selected */
96       if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) {
97         /* External reference clock is selected */
98         if ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x00U) {
99           MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
100         } else {
101           MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
102         }
103         if (((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) {
104           switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
105           case 0x38U:
106             Divider = 1536U;
107             break;
108           case 0x30U:
109             Divider = 1280U;
110             break;
111           default:
112             Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
113             break;
114           }
115         } else {/* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x00U) */
116           Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
117         }
118         MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
119       } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
120         MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
121       } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
122       /* Select correct multiplier to calculate the MCG output clock  */
123       switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
124         case 0x00U:
125           MCGOUTClock *= 640U;
126           break;
127         case 0x20U:
128           MCGOUTClock *= 1280U;
129           break;
130         case 0x40U:
131           MCGOUTClock *= 1920U;
132           break;
133         case 0x60U:
134           MCGOUTClock *= 2560U;
135           break;
136         case 0x80U:
137           MCGOUTClock *= 732U;
138           break;
139         case 0xA0U:
140           MCGOUTClock *= 1464U;
141           break;
142         case 0xC0U:
143           MCGOUTClock *= 2197U;
144           break;
145         case 0xE0U:
146           MCGOUTClock *= 2929U;
147           break;
148         default:
149           MCGOUTClock *= 640U;
150           break;
151       }
152     }
153     else {/* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
154       /* PLL is selected */
155       if ((MCG->C7 & MCG_C7_PLL32KREFSEL_MASK) == 0x00U) {
156         /* RTC 32 kHz oscillator selected */
157         MCGOUTClock = CPU_XTAL32k_CLK_HZ;
158       } else if ((MCG->C7 & MCG_C7_PLL32KREFSEL_MASK) == 0x40U) {
159         /* 32kHz IRC selected */
160         MCGOUTClock = CPU_INT_SLOW_CLK_HZ;
161       } else if ((MCG->C7 & MCG_C7_PLL32KREFSEL_MASK) == 0x80U) {
162         /* FLL FRDIV selected */
163         if ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x00U) {
164           MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
165         } else {
166           MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
167         }
168         if (((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) {
169           switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
170           case 0x38U:
171             Divider = 1536U;
172             break;
173           case 0x30U:
174             Divider = 1280U;
175             break;
176           default:
177             Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
178             break;
179           }
180         } else {/* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x00U) */
181           Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
182         }
183         MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
184       } else { /* (MCG->C7 & MCG_C7_PLL32KREFSEL_MASK) == 0xB0U */
185         /* Reserved value */
186         return;
187       }
188       MCGOUTClock *= 375U; /* Calculate the MCG output clock */
189     }
190   } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) {
191     /* Internal reference clock is selected */
192     if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) {
193       MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
194     } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
195       Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
196       MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
197     } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
198   } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) {
199     /* External reference clock is selected */
200     if ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x00U) {
201       MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
202     } else {
203       MCGOUTClock = CPU_XTAL_CLK_HZ;   /* System oscillator drives MCG clock */
204     }
205   } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
206     /* Reserved value */
207     return;
208   } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
209   SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_SYSDIV_MASK) >> SIM_CLKDIV1_SYSDIV_SHIFT)));
210 }
211 
212 /* ----------------------------------------------------------------------------
213    -- SystemInitHook()
214    ---------------------------------------------------------------------------- */
215 
SystemInitHook(void)216 __attribute__ ((weak)) void SystemInitHook (void) {
217   /* Void implementation of the weak function. */
218 }
219