1 /*
2 ** ###################################################################
3 ** Processors: MK66FN2M0VLQ18
4 ** MK66FN2M0VMD18
5 ** MK66FX1M0VLQ18
6 ** MK66FX1M0VMD18
7 **
8 ** Compilers: Freescale C/C++ for Embedded ARM
9 ** GNU C Compiler
10 ** IAR ANSI C/C++ Compiler for ARM
11 ** Keil ARM C/C++ Compiler
12 ** MCUXpresso Compiler
13 **
14 ** Reference manual: K66P144M180SF5RMV2, Rev. 1, Mar 2015
15 ** Version: rev. 3.0, 2015-03-25
16 ** Build: b201013
17 **
18 ** Abstract:
19 ** Provides a system configuration function and a global variable that
20 ** contains the system frequency. It configures the device and initializes
21 ** the oscillator (PLL) that is part of the microcontroller device.
22 **
23 ** Copyright 2016 Freescale Semiconductor, Inc.
24 ** Copyright 2016-2020 NXP
25 ** All rights reserved.
26 **
27 ** SPDX-License-Identifier: BSD-3-Clause
28 **
29 ** http: www.nxp.com
30 ** mail: support@nxp.com
31 **
32 ** Revisions:
33 ** - rev. 1.0 (2013-09-02)
34 ** Initial version.
35 ** - rev. 2.0 (2014-02-17)
36 ** Register accessor macros added to the memory map.
37 ** Symbols for Processor Expert memory map compatibility added to the memory map.
38 ** Startup file for gcc has been updated according to CMSIS 3.2.
39 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
40 ** Update according to reference manual rev. 2
41 ** - rev. 2.1 (2014-04-16)
42 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
43 ** - rev. 2.2 (2014-10-14)
44 ** Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
45 ** - rev. 2.3 (2014-11-20)
46 ** Update according to reverence manual K65P169M180SF5RMV2_NDA, Rev. 0 Draft A, October 2014.
47 ** Update of SystemInit() to use 16MHz external crystal.
48 ** - rev. 2.4 (2015-02-19)
49 ** Renamed interrupt vector LLW to LLWU.
50 ** - rev. 3.0 (2015-03-25)
51 ** Registers updated according to the reference manual revision 1, March 2015
52 **
53 ** ###################################################################
54 */
55
56 /*!
57 * @file MK66F18
58 * @version 3.0
59 * @date 2015-03-25
60 * @brief Device specific configuration file for MK66F18 (implementation file)
61 *
62 * Provides a system configuration function and a global variable that contains
63 * the system frequency. It configures the device and initializes the oscillator
64 * (PLL) that is part of the microcontroller device.
65 */
66
67 #include <stdint.h>
68 #include "fsl_device_registers.h"
69
70
71
72 /* ----------------------------------------------------------------------------
73 -- Core clock
74 ---------------------------------------------------------------------------- */
75
76 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
77
78 /* ----------------------------------------------------------------------------
79 -- SystemInit()
80 ---------------------------------------------------------------------------- */
81
SystemInit(void)82 void SystemInit (void) {
83 #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
84 SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
85 #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
86 /* Watchdog disable */
87 #if (DISABLE_WDOG)
88 /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
89 WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
90 /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
91 WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
92 /* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
93 WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
94 WDOG_STCTRLH_WAITEN_MASK |
95 WDOG_STCTRLH_STOPEN_MASK |
96 WDOG_STCTRLH_ALLOWUPDATE_MASK |
97 WDOG_STCTRLH_CLKSRC_MASK |
98 0x0100U;
99 #endif /* (DISABLE_WDOG) */
100
101 SystemInitHook();
102 }
103
104 /* ----------------------------------------------------------------------------
105 -- SystemCoreClockUpdate()
106 ---------------------------------------------------------------------------- */
107
SystemCoreClockUpdate(void)108 void SystemCoreClockUpdate (void) {
109 uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
110 uint16_t Divider;
111 uint8_t tmpC7 = 0;
112
113 if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) {
114 /* Output of FLL or PLL is selected */
115 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) {
116 /* FLL is selected */
117 if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) {
118 /* External reference clock is selected */
119 switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
120 case 0x00U:
121 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
122 break;
123 case 0x01U:
124 MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
125 break;
126 case 0x02U:
127 default:
128 MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
129 break;
130 }
131 tmpC7 = MCG->C7;
132 if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((tmpC7 & MCG_C7_OSCSEL_MASK) != 0x01U)) {
133 switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
134 case 0x38U:
135 Divider = 1536U;
136 break;
137 case 0x30U:
138 Divider = 1280U;
139 break;
140 default:
141 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
142 break;
143 }
144 } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
145 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
146 }
147 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
148 } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
149 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
150 } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
151 /* Select correct multiplier to calculate the MCG output clock */
152 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
153 case 0x00U:
154 MCGOUTClock *= 640U;
155 break;
156 case 0x20U:
157 MCGOUTClock *= 1280U;
158 break;
159 case 0x40U:
160 MCGOUTClock *= 1920U;
161 break;
162 case 0x60U:
163 MCGOUTClock *= 2560U;
164 break;
165 case 0x80U:
166 MCGOUTClock *= 732U;
167 break;
168 case 0xA0U:
169 MCGOUTClock *= 1464U;
170 break;
171 case 0xC0U:
172 MCGOUTClock *= 2197U;
173 break;
174 case 0xE0U:
175 MCGOUTClock *= 2929U;
176 break;
177 default:
178 MCGOUTClock *= 640U;
179 break;
180 }
181 } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
182 if ((MCG->C11 & MCG_C11_PLLCS_MASK) == 0x00U) {
183 /* PLL is selected */
184 Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV_MASK) + 0x01U);
185 MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
186 Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV_MASK) + 16U);
187 MCGOUTClock *= Divider; /* Calculate the VCO output clock */
188 MCGOUTClock /= 2U; /* Calculate the MCG output clock */
189 } else {
190 /* External PLL is selected */
191 if ((USBPHY->ANACTRL & USBPHY_ANACTRL_PFD_CLK_SEL_MASK) == 0x00U) {
192 MCGOUTClock = CPU_XTAL_CLK_HZ;
193 } else {
194 Divider = (((uint16_t)USBPHY->ANACTRL & USBPHY_ANACTRL_PFD_FRAC_MASK) >> 4);
195 if ((USBPHY->ANACTRL & USBPHY_ANACTRL_PFD_CLK_SEL_MASK) == USBPHY_ANACTRL_PFD_CLK_SEL(1)) {
196 Divider *= 0x04U;
197 } else if ((USBPHY->ANACTRL & USBPHY_ANACTRL_PFD_CLK_SEL_MASK) == USBPHY_ANACTRL_PFD_CLK_SEL(2)) {
198 Divider *= 0x02U;
199 } else {
200 Divider *= 0x01U;
201 }
202 MCGOUTClock = (uint32_t)(480000000U / Divider);
203 MCGOUTClock *= 18U;
204 }
205 }
206 } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
207 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) {
208 /* Internal reference clock is selected */
209 if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) {
210 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
211 } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
212 Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
213 MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
214 } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
215 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) {
216 /* External reference clock is selected */
217 switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
218 case 0x00U:
219 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
220 break;
221 case 0x01U:
222 MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
223 break;
224 case 0x02U:
225 default:
226 MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
227 break;
228 }
229 } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
230 /* Reserved value */
231 return;
232 } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
233 SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
234 }
235
236 /* ----------------------------------------------------------------------------
237 -- SystemInitHook()
238 ---------------------------------------------------------------------------- */
239
SystemInitHook(void)240 __attribute__ ((weak)) void SystemInitHook (void) {
241 /* Void implementation of the weak function. */
242 }
243
