1 /*
2 ** ###################################################################
3 ** Processors: MK28FN2M0ACAU15R
4 ** MK28FN2M0AVMI15
5 **
6 ** Compilers: Freescale C/C++ for Embedded ARM
7 ** GNU C Compiler
8 ** IAR ANSI C/C++ Compiler for ARM
9 ** Keil ARM C/C++ Compiler
10 ** MCUXpresso Compiler
11 **
12 ** Reference manual: K28P210M150SF5RM, Rev. 4, Aug 2017
13 ** Version: rev. 1.3, 2018-01-09
14 ** Build: b181105
15 **
16 ** Abstract:
17 ** Provides a system configuration function and a global variable that
18 ** contains the system frequency. It configures the device and initializes
19 ** the oscillator (PLL) that is part of the microcontroller device.
20 **
21 ** Copyright 2016 Freescale Semiconductor, Inc.
22 ** Copyright 2016-2018 NXP
23 ** All rights reserved.
24 **
25 ** SPDX-License-Identifier: BSD-3-Clause
26 **
27 ** http: www.nxp.com
28 ** mail: support@nxp.com
29 **
30 ** Revisions:
31 ** - rev. 1.0 (2016-05-10)
32 ** Initial version
33 ** - rev. 1.1 (2016-10-20)
34 ** Update based on Rev1 RM.
35 ** - rev. 1.2 (2017-04-06)
36 ** Remove TSI.
37 ** Add ISD2FA, ISD3FA, ISD2FB and ISD3FB bits in QuadSPI0_MCR.
38 ** - rev. 1.3 (2018-01-09)
39 ** Add K28FA support.
40 **
41 ** ###################################################################
42 */
43
44 /*!
45 * @file MK28FA15
46 * @version 1.3
47 * @date 2018-01-09
48 * @brief Device specific configuration file for MK28FA15 (implementation file)
49 *
50 * Provides a system configuration function and a global variable that contains
51 * the system frequency. It configures the device and initializes the oscillator
52 * (PLL) that is part of the microcontroller device.
53 */
54
55 #include <stdint.h>
56 #include "fsl_device_registers.h"
57
58
59
60 /* ----------------------------------------------------------------------------
61 -- Core clock
62 ---------------------------------------------------------------------------- */
63
64 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
65
66 /* ----------------------------------------------------------------------------
67 -- SystemInit()
68 ---------------------------------------------------------------------------- */
69
SystemInit(void)70 void SystemInit (void) {
71 #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
72 SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
73 #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
74
75 #if (DISABLE_WDOG)
76 /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
77 WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
78 /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
79 WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
80 /* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
81 WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
82 WDOG_STCTRLH_WAITEN_MASK |
83 WDOG_STCTRLH_STOPEN_MASK |
84 WDOG_STCTRLH_ALLOWUPDATE_MASK |
85 WDOG_STCTRLH_CLKSRC_MASK |
86 0x0100U;
87 #endif /* (DISABLE_WDOG) */
88
89 SystemInitHook();
90 }
91
92 /* ----------------------------------------------------------------------------
93 -- SystemCoreClockUpdate()
94 ---------------------------------------------------------------------------- */
95
SystemCoreClockUpdate(void)96 void SystemCoreClockUpdate (void) {
97
98 uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
99 uint16_t Divider;
100 uint8_t tmpC7 = 0;
101
102 if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) {
103 /* Output of FLL or PLL is selected */
104 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) {
105 /* FLL is selected */
106 if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) {
107 /* External reference clock is selected */
108 switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
109 case 0x00U:
110 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
111 break;
112 case 0x01U:
113 MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
114 break;
115 case 0x02U:
116 default:
117 MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
118 break;
119 }
120 tmpC7 = MCG->C7;
121 if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((tmpC7 & MCG_C7_OSCSEL_MASK) != 0x01U)) {
122 switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
123 case 0x38U:
124 Divider = 1536U;
125 break;
126 case 0x30U:
127 Divider = 1280U;
128 break;
129 default:
130 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
131 break;
132 }
133 } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
134 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
135 }
136 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
137 } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
138 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
139 } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
140 /* Select correct multiplier to calculate the MCG output clock */
141 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
142 case 0x00U:
143 MCGOUTClock *= 640U;
144 break;
145 case 0x20U:
146 MCGOUTClock *= 1280U;
147 break;
148 case 0x40U:
149 MCGOUTClock *= 1920U;
150 break;
151 case 0x60U:
152 MCGOUTClock *= 2560U;
153 break;
154 case 0x80U:
155 MCGOUTClock *= 732U;
156 break;
157 case 0xA0U:
158 MCGOUTClock *= 1464U;
159 break;
160 case 0xC0U:
161 MCGOUTClock *= 2197U;
162 break;
163 case 0xE0U:
164 MCGOUTClock *= 2929U;
165 break;
166 default:
167 MCGOUTClock *= 640U;
168 break;
169 }
170 } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
171 /* PLL is selected */
172 Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV_MASK) + 0x01U);
173 MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
174 Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV_MASK) + 16U);
175 MCGOUTClock *= Divider; /* Calculate the VCO output clock */
176 MCGOUTClock /= 2U; /* Calculate the MCG output clock */
177 } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
178 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) {
179 /* Internal reference clock is selected */
180 if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) {
181 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
182 } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
183 Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
184 MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
185 } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
186 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) {
187 /* External reference clock is selected */
188 switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
189 case 0x00U:
190 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
191 break;
192 case 0x01U:
193 MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
194 break;
195 case 0x02U:
196 default:
197 MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
198 break;
199 }
200 } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
201 /* Reserved value */
202 return;
203 } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
204 SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
205 }
206
207 /* ----------------------------------------------------------------------------
208 -- SystemInitHook()
209 ---------------------------------------------------------------------------- */
210
SystemInitHook(void)211 __attribute__ ((weak)) void SystemInitHook (void) {
212 /* Void implementation of the weak function. */
213 }
214
