1 /*
2 ** ###################################################################
3 ** Processors: MK26FN2M0CAC18
4 ** MK26FN2M0VLQ18
5 ** MK26FN2M0VMD18
6 ** MK26FN2M0VMI18
7 **
8 ** Compilers: Freescale C/C++ for Embedded ARM
9 ** GNU C Compiler
10 ** IAR ANSI C/C++ Compiler for ARM
11 ** Keil ARM C/C++ Compiler
12 ** MCUXpresso Compiler
13 **
14 ** Reference manual: MK26P169M180SF5RM, Rev. 1, Mar 2015
15 ** Version: rev. 2.0, 2015-03-25
16 ** Build: b201013
17 **
18 ** Abstract:
19 ** Provides a system configuration function and a global variable that
20 ** contains the system frequency. It configures the device and initializes
21 ** the oscillator (PLL) that is part of the microcontroller device.
22 **
23 ** Copyright 2016 Freescale Semiconductor, Inc.
24 ** Copyright 2016-2020 NXP
25 ** All rights reserved.
26 **
27 ** SPDX-License-Identifier: BSD-3-Clause
28 **
29 ** http: www.nxp.com
30 ** mail: support@nxp.com
31 **
32 ** Revisions:
33 ** - rev. 1.0 (2014-12-04)
34 ** Initial version.
35 ** - rev. 1.1 (2015-02-19)
36 ** Renamed interrupt vector LLW to LLWU.
37 ** - rev. 2.0 (2015-03-25)
38 ** Registers updated according to the reference manual revision 1, March 2015
39 **
40 ** ###################################################################
41 */
42
43 /*!
44 * @file MK26F18
45 * @version 2.0
46 * @date 2015-03-25
47 * @brief Device specific configuration file for MK26F18 (implementation file)
48 *
49 * Provides a system configuration function and a global variable that contains
50 * the system frequency. It configures the device and initializes the oscillator
51 * (PLL) that is part of the microcontroller device.
52 */
53
54 #include <stdint.h>
55 #include "fsl_device_registers.h"
56
57
58
59 /* ----------------------------------------------------------------------------
60 -- Core clock
61 ---------------------------------------------------------------------------- */
62
63 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
64
65 /* ----------------------------------------------------------------------------
66 -- SystemInit()
67 ---------------------------------------------------------------------------- */
68
SystemInit(void)69 void SystemInit (void) {
70 #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
71 SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
72 #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
73 /* Watchdog disable */
74 #if (DISABLE_WDOG)
75 /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
76 WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
77 /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
78 WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
79 /* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
80 WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
81 WDOG_STCTRLH_WAITEN_MASK |
82 WDOG_STCTRLH_STOPEN_MASK |
83 WDOG_STCTRLH_ALLOWUPDATE_MASK |
84 WDOG_STCTRLH_CLKSRC_MASK |
85 0x0100U;
86 #endif /* (DISABLE_WDOG) */
87
88 SystemInitHook();
89 }
90
91 /* ----------------------------------------------------------------------------
92 -- SystemCoreClockUpdate()
93 ---------------------------------------------------------------------------- */
94
SystemCoreClockUpdate(void)95 void SystemCoreClockUpdate (void) {
96 uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
97 uint16_t Divider;
98 uint8_t tmpC7 = 0;
99
100 if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) {
101 /* Output of FLL or PLL is selected */
102 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) {
103 /* FLL is selected */
104 if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) {
105 /* External reference clock is selected */
106 switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
107 case 0x00U:
108 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
109 break;
110 case 0x01U:
111 MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
112 break;
113 case 0x02U:
114 default:
115 MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
116 break;
117 }
118 tmpC7 = MCG->C7;
119 if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((tmpC7 & MCG_C7_OSCSEL_MASK) != 0x01U)) {
120 switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
121 case 0x38U:
122 Divider = 1536U;
123 break;
124 case 0x30U:
125 Divider = 1280U;
126 break;
127 default:
128 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
129 break;
130 }
131 } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
132 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
133 }
134 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
135 } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
136 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
137 } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
138 /* Select correct multiplier to calculate the MCG output clock */
139 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
140 case 0x00U:
141 MCGOUTClock *= 640U;
142 break;
143 case 0x20U:
144 MCGOUTClock *= 1280U;
145 break;
146 case 0x40U:
147 MCGOUTClock *= 1920U;
148 break;
149 case 0x60U:
150 MCGOUTClock *= 2560U;
151 break;
152 case 0x80U:
153 MCGOUTClock *= 732U;
154 break;
155 case 0xA0U:
156 MCGOUTClock *= 1464U;
157 break;
158 case 0xC0U:
159 MCGOUTClock *= 2197U;
160 break;
161 case 0xE0U:
162 MCGOUTClock *= 2929U;
163 break;
164 default:
165 MCGOUTClock *= 640U;
166 break;
167 }
168 } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
169 if ((MCG->C11 & MCG_C11_PLLCS_MASK) == 0x00U) {
170 /* PLL is selected */
171 Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV_MASK) + 0x01U);
172 MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
173 Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV_MASK) + 16U);
174 MCGOUTClock *= Divider; /* Calculate the VCO output clock */
175 MCGOUTClock /= 2U; /* Calculate the MCG output clock */
176 } else {
177 /* External PLL is selected */
178 if ((USBPHY->ANACTRL & USBPHY_ANACTRL_PFD_CLK_SEL_MASK) == 0x00U) {
179 MCGOUTClock = CPU_XTAL_CLK_HZ;
180 } else {
181 Divider = (((uint16_t)USBPHY->ANACTRL & USBPHY_ANACTRL_PFD_FRAC_MASK) >> 4);
182 if ((USBPHY->ANACTRL & USBPHY_ANACTRL_PFD_CLK_SEL_MASK) == USBPHY_ANACTRL_PFD_CLK_SEL(1)) {
183 Divider *= 0x04U;
184 } else if ((USBPHY->ANACTRL & USBPHY_ANACTRL_PFD_CLK_SEL_MASK) == USBPHY_ANACTRL_PFD_CLK_SEL(2)) {
185 Divider *= 0x02U;
186 } else {
187 Divider *= 0x01U;
188 }
189 MCGOUTClock = (uint32_t)(480000000U / Divider);
190 MCGOUTClock *= 18U;
191 }
192 }
193 } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
194 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) {
195 /* Internal reference clock is selected */
196 if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) {
197 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
198 } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
199 Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
200 MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
201 } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
202 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) {
203 /* External reference clock is selected */
204 switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
205 case 0x00U:
206 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
207 break;
208 case 0x01U:
209 MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
210 break;
211 case 0x02U:
212 default:
213 MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
214 break;
215 }
216 } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
217 /* Reserved value */
218 return;
219 } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
220 SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
221 }
222
223 /* ----------------------------------------------------------------------------
224 -- SystemInitHook()
225 ---------------------------------------------------------------------------- */
226
SystemInitHook(void)227 __attribute__ ((weak)) void SystemInitHook (void) {
228 /* Void implementation of the weak function. */
229 }
230
