1 /*
2 ** ###################################################################
3 ** Processors: MK22FN1M0VLH12
4 ** MK22FN1M0VLK12
5 ** MK22FN1M0VLL12
6 ** MK22FN1M0VLQ12
7 ** MK22FN1M0VMC12
8 ** MK22FN1M0VMD12
9 ** MK22FX512VLH12
10 ** MK22FX512VLK12
11 ** MK22FX512VLL12
12 ** MK22FX512VLQ12
13 ** MK22FX512VMC12
14 ** MK22FX512VMD12
15 **
16 ** Compilers: Freescale C/C++ for Embedded ARM
17 ** GNU C Compiler
18 ** IAR ANSI C/C++ Compiler for ARM
19 ** Keil ARM C/C++ Compiler
20 ** MCUXpresso Compiler
21 **
22 ** Reference manuals: K22P100M120SF5V2RM, Rev.5, March 2015
23 ** K22P121M120SF5V2RM, Rev.5, March 2015
24 ** K22P144M120SF5V2RM, Rev.5, March 2015
25 ** K22P64M120SF5V2RM, Rev.5, March 2015
26 ** K22P80M120SF5V2RM, Rev.5, March 2015
27 **
28 ** Version: rev. 1.8, 2015-02-19
29 ** Build: b181105
30 **
31 ** Abstract:
32 ** Provides a system configuration function and a global variable that
33 ** contains the system frequency. It configures the device and initializes
34 ** the oscillator (PLL) that is part of the microcontroller device.
35 **
36 ** Copyright 2016 Freescale Semiconductor, Inc.
37 ** Copyright 2016-2018 NXP
38 ** All rights reserved.
39 **
40 ** SPDX-License-Identifier: BSD-3-Clause
41 **
42 ** http: www.nxp.com
43 ** mail: support@nxp.com
44 **
45 ** Revisions:
46 ** - rev. 1.0 (2012-06-06)
47 ** Initial version.
48 ** - rev. 1.1 (2012-11-12)
49 ** Update according to reference manual rev.1, draft B
50 ** - rev. 1.2 (2012-12-04)
51 ** Update according to reference manual rev.1
52 ** - rev. 1.3 (2013-03-11)
53 ** System initialization updated to add 120MHz clock option.
54 ** - rev. 1.4 (2013-04-05)
55 ** Changed start of doxygen comment.
56 ** - rev. 1.5 (2013-05-16)
57 ** Update according to reference manual rev.2
58 ** - rev. 1.6 (2013-10-29)
59 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
60 ** Access restriction of some registers fixed.
61 ** - rev. 1.7 (2014-02-18)
62 ** UART0 module - LON registers removed.
63 ** - rev. 1.8 (2015-02-19)
64 ** update of SystemInit() imlementation
65 ** Module access macro module_BASES replaced by module_BASE_PTRS.
66 ** Register accessor macros added to the memory map.
67 ** Renamed interrupt vector Watchdog to WDOG_EWM, LPTimer to LPTMR0 and LLW to LLWU
68 **
69 ** ###################################################################
70 */
71
72 /*!
73 * @file MK22F12
74 * @version 1.8
75 * @date 2015-02-19
76 * @brief Device specific configuration file for MK22F12 (implementation file)
77 *
78 * Provides a system configuration function and a global variable that contains
79 * the system frequency. It configures the device and initializes the oscillator
80 * (PLL) that is part of the microcontroller device.
81 */
82
83 #include <stdint.h>
84 #include "fsl_device_registers.h"
85
86
87
88 /* ----------------------------------------------------------------------------
89 -- Core clock
90 ---------------------------------------------------------------------------- */
91
92 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
93
94 /* ----------------------------------------------------------------------------
95 -- SystemInit()
96 ---------------------------------------------------------------------------- */
97
SystemInit(void)98 void SystemInit (void) {
99 #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
100 SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
101 #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
102
103 #if (DISABLE_WDOG)
104 /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
105 WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
106 /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
107 WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
108 /* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
109 WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
110 WDOG_STCTRLH_WAITEN_MASK |
111 WDOG_STCTRLH_STOPEN_MASK |
112 WDOG_STCTRLH_ALLOWUPDATE_MASK |
113 WDOG_STCTRLH_CLKSRC_MASK |
114 0x0100U;
115 #endif /* (DISABLE_WDOG) */
116
117 SystemInitHook();
118 }
119
120 /* ----------------------------------------------------------------------------
121 -- SystemCoreClockUpdate()
122 ---------------------------------------------------------------------------- */
123
SystemCoreClockUpdate(void)124 void SystemCoreClockUpdate (void) {
125
126 uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
127 uint16_t Divider;
128 uint8_t tmpC7 = 0;
129
130 if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) {
131 /* Output of FLL or PLL is selected */
132 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) {
133 /* FLL is selected */
134 if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) {
135 /* External reference clock is selected */
136 if((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x00U) {
137 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
138 } else {
139 MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
140 }
141 tmpC7 = MCG->C7;
142 if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((tmpC7 & MCG_C7_OSCSEL_MASK) != 0x01U)) {
143 switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
144 case 0x38U:
145 Divider = 1536U;
146 break;
147 case 0x30U:
148 Divider = 1280U;
149 break;
150 default:
151 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
152 break;
153 }
154 } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
155 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
156 }
157 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
158 } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
159 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
160 } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
161 /* Select correct multiplier to calculate the MCG output clock */
162 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
163 case 0x00U:
164 MCGOUTClock *= 640U;
165 break;
166 case 0x20U:
167 MCGOUTClock *= 1280U;
168 break;
169 case 0x40U:
170 MCGOUTClock *= 1920U;
171 break;
172 case 0x60U:
173 MCGOUTClock *= 2560U;
174 break;
175 case 0x80U:
176 MCGOUTClock *= 732U;
177 break;
178 case 0xA0U:
179 MCGOUTClock *= 1464U;
180 break;
181 case 0xC0U:
182 MCGOUTClock *= 2197U;
183 break;
184 case 0xE0U:
185 MCGOUTClock *= 2929U;
186 break;
187 default:
188 MCGOUTClock *= 640U;
189 break;
190 }
191 } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
192 /* PLL is selected */
193 Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U);
194 MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
195 Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U);
196 MCGOUTClock *= Divider; /* Calculate the MCG output clock */
197 } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
198 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) {
199 /* Internal reference clock is selected */
200 if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) {
201 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
202 } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
203 Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
204 MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
205 } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
206 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) {
207 /* External reference clock is selected */
208 if((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x00U) {
209 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
210 } else {
211 MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
212 }
213 } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
214 /* Reserved value */
215 return;
216 } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
217 SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
218 }
219
220 /* ----------------------------------------------------------------------------
221 -- SystemInitHook()
222 ---------------------------------------------------------------------------- */
223
SystemInitHook(void)224 __attribute__ ((weak)) void SystemInitHook (void) {
225 /* Void implementation of the weak function. */
226 }
227
