1 /*
2 ** ###################################################################
3 **     Processors:          MIMXRT798SGAWAR_cm33_core1
4 **                          MIMXRT798SGFOA_cm33_core1
5 **
6 **     Compilers:           GNU C Compiler
7 **                          IAR ANSI C/C++ Compiler for ARM
8 **                          Keil ARM C/C++ Compiler
9 **                          MCUXpresso Compiler
10 **
11 **     Reference manual:    iMXRT700RM Rev.2 DraftA, 05/2024
12 **     Version:             rev. 2.0, 2024-05-28
13 **     Build:               b240528
14 **
15 **     Abstract:
16 **         Provides a system configuration function and a global variable that
17 **         contains the system frequency. It configures the device and initializes
18 **         the oscillator (PLL) that is part of the microcontroller device.
19 **
20 **     Copyright 2016 Freescale Semiconductor, Inc.
21 **     Copyright 2016-2024 NXP
22 **     SPDX-License-Identifier: BSD-3-Clause
23 **
24 **     http:                 www.nxp.com
25 **     mail:                 support@nxp.com
26 **
27 **     Revisions:
28 **     - rev. 1.0 (2022-09-15)
29 **         Initial version.
30 **     - rev. 2.0 (2024-05-28)
31 **         Rev2 DraftA.
32 **
33 ** ###################################################################
34 */
35 
36 /*!
37  * @file MIMXRT798S_cm33_core1
38  * @version 1.0
39  * @date 2024-05-28
40  * @brief Device specific configuration file for MIMXRT798S_cm33_core1
41  *  (implementation file)
42  *
43  * Provides a system configuration function and a global variable that contains
44  * the system frequency. It configures the device and initializes the oscillator
45  * (PLL) that is part of the microcontroller device.
46  */
47 
48 #include <stdint.h>
49 #include <stdbool.h>
50 #include "fsl_device_registers.h"
51 
52 /* TBD. */
53 
54 /* ----------------------------------------------------------------------------
55    -- Core clock
56    ---------------------------------------------------------------------------- */
57 
58 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
59 
60 /* ----------------------------------------------------------------------------
61    -- SystemInit()
62    ---------------------------------------------------------------------------- */
63 
SystemInit(void)64 __attribute__((weak)) void SystemInit(void)
65 {
66 #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
67     SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2));    /* set CP10, CP11 Full Access in Secure mode */
68 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
69     SCB_NS->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access in Non-secure mode */
70 #endif                                                    /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
71 #endif                                                    /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
72 
73     SCB->CPACR |= ((3UL << 0 * 2) | (3UL << 1 * 2)); /* set CP0, CP1 Full Access in Secure mode (enable PowerQuad) */
74 
75 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
76     SCB_NS->CPACR |=
77         ((3UL << 0 * 2) | (3UL << 1 * 2));    /* set CP0, CP1 Full Access in Non-secure mode (enable PowerQuad) */
78 #endif                                        /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
79 
80     SCB->NSACR |= ((3UL << 0) | (3UL << 10)); /* enable CP0, CP1, CP10, CP11 Non-secure Access */
81 
82     SYSCON1->DSPSTALL |= SYSCON1_DSPSTALL_DSPSTALL_MASK;
83     SLEEPCON1->SHARED_MASK0_SET = 0xFF007FU; /* Mask all the shared modules. */
84 
85     SystemInitHook();
86 }
87 
88 /* ----------------------------------------------------------------------------
89    -- SystemCoreClockUpdate()
90    ---------------------------------------------------------------------------- */
getFro2MaxFreq(void)91 static uint32_t getFro2MaxFreq(void)
92 {
93     return CLK_FRO2_CLK;
94 }
95 
getFro1MaxFreq(void)96 static uint32_t getFro1MaxFreq(void)
97 {
98     return CLK_FRO1_MAX_CLK;
99 }
100 
getFro1Div3Freq(void)101 static uint32_t getFro1Div3Freq(void)
102 {
103     return getFro1MaxFreq() / 3U;
104 }
105 
getFro2Div3Freq(void)106 static uint32_t getFro2Div3Freq(void)
107 {
108     return getFro2MaxFreq() / 3U;
109 }
110 
getLpOscFreq(void)111 static uint32_t getLpOscFreq(void)
112 {
113     return CLK_LPOSC_1MHZ;
114 }
115 
getBaseClkSense(void)116 static uint32_t getBaseClkSense(void)
117 {
118     uint32_t freq = 0U;
119 
120     switch (CLKCTL3->SENSEBASECLKSEL & CLKCTL3_SENSEBASECLKSEL_SEL_MASK)
121     {
122         case CLKCTL3_SENSEBASECLKSEL_SEL(0):
123             freq = getFro1Div3Freq();
124             break;
125         case CLKCTL3_SENSEBASECLKSEL_SEL(1):
126             freq = getFro1MaxFreq();
127             break;
128         case CLKCTL3_SENSEBASECLKSEL_SEL(2):
129             freq = getFro2Div3Freq();
130             break;
131         case CLKCTL3_SENSEBASECLKSEL_SEL(3):
132             freq = getLpOscFreq();
133             break;
134         default:
135             freq = 0U;
136             break;
137     }
138 
139     return freq;
140 }
141 
getAudioPllFreq(void)142 static uint32_t getAudioPllFreq(void)
143 {
144     uint32_t freq = 0U;
145     uint64_t freqTmp;
146 
147     switch ((CLKCTL2->AUDIOPLL0CLKSEL) & CLKCTL2_AUDIOPLL0CLKSEL_SEL_MASK)
148     {
149         case CLKCTL2_AUDIOPLL0CLKSEL_SEL(0):
150             freq = getFro1MaxFreq() / 8U;
151             break;
152         case CLKCTL2_AUDIOPLL0CLKSEL_SEL(1):
153             freq = CLK_OSC_CLK;
154             break;
155         default:
156             freq = 0U;
157             break;
158     }
159 
160     if (((CLKCTL2->AUDIOPLL0CTL0) & CLKCTL2_AUDIOPLL0CTL0_BYPASS_MASK) == 0UL)
161     {
162         /* PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). */
163         freqTmp = ((uint64_t)freq * ((uint64_t)(CLKCTL2->AUDIOPLL0NUM))) / ((uint64_t)(CLKCTL2->AUDIOPLL0DENOM));
164         freq *= ((CLKCTL2->AUDIOPLL0CTL0) & CLKCTL2_AUDIOPLL0CTL0_MULT_MASK) >> CLKCTL2_AUDIOPLL0CTL0_MULT_SHIFT;
165         freq += (uint32_t)freqTmp;
166     }
167     return freq;
168 }
169 
getAudioPllPfd3Freq(void)170 static uint32_t getAudioPllPfd3Freq(void)
171 {
172     uint32_t freq = getAudioPllFreq();
173 
174     if (((CLKCTL2->AUDIOPLL0CTL0) & CLKCTL2_AUDIOPLL0CTL0_BYPASS_MASK) == 0UL)
175     {
176         freq =
177             (uint32_t)((uint64_t)freq * 18U /
178                        ((CLKCTL2->AUDIOPLL0PFD & CLKCTL2_AUDIOPLL0PFD_PFD3_MASK) >> CLKCTL2_AUDIOPLL0PFD_PFD3_SHIFT));
179     }
180     return freq;
181 }
182 
SystemCoreClockUpdate(void)183 void SystemCoreClockUpdate(void)
184 {
185     uint32_t freq = 0U;
186 
187     switch ((CLKCTL3->MAINCLKSEL) & CLKCTL3_MAINCLKSEL_SEL_MASK)
188     {
189         case CLKCTL3_MAINCLKSEL_SEL(0):
190             freq = getBaseClkSense();
191             break;
192 
193         case CLKCTL3_MAINCLKSEL_SEL(1):
194             freq = getFro2MaxFreq();
195             break;
196 
197         case CLKCTL3_MAINCLKSEL_SEL(2):
198             freq = getAudioPllPfd3Freq();
199             break;
200 
201         case CLKCTL3_MAINCLKSEL_SEL(3):
202             freq = getFro1MaxFreq();
203             break;
204 
205         default:
206             freq = 0U;
207             break;
208     }
209 
210     SystemCoreClock = freq / ((CLKCTL3->SENSEMAINCLKDIV & CLKCTL3_SENSEMAINCLKDIV_DIV_MASK) + 1U);
211 }
212 
213 /* ----------------------------------------------------------------------------
214    -- SystemInitHook()
215    ---------------------------------------------------------------------------- */
216 
SystemInitHook(void)217 __attribute__((weak)) void SystemInitHook(void)
218 {
219     /* Void implementation of the weak function. */
220 }
221