1 /*
2 ** ###################################################################
3 ** Processors: MIMXRT798SGAWAR_cm33_core0
4 ** MIMXRT798SGFOA_cm33_core0
5 **
6 ** Compilers: GNU C Compiler
7 ** IAR ANSI C/C++ Compiler for ARM
8 ** Keil ARM C/C++ Compiler
9 ** MCUXpresso Compiler
10 **
11 ** Reference manual: iMXRT700RM Rev.2 DraftA, 05/2024
12 ** Version: rev. 2.0, 2024-05-28
13 ** Build: b240528
14 **
15 ** Abstract:
16 ** Provides a system configuration function and a global variable that
17 ** contains the system frequency. It configures the device and initializes
18 ** the oscillator (PLL) that is part of the microcontroller device.
19 **
20 ** Copyright 2016 Freescale Semiconductor, Inc.
21 ** Copyright 2016-2024 NXP
22 ** SPDX-License-Identifier: BSD-3-Clause
23 **
24 ** http: www.nxp.com
25 ** mail: support@nxp.com
26 **
27 ** Revisions:
28 ** - rev. 1.0 (2022-09-15)
29 ** Initial version.
30 ** - rev. 2.0 (2024-05-28)
31 ** Rev2 DraftA.
32 **
33 ** ###################################################################
34 */
35
36 /*!
37 * @file MIMXRT798S_cm33_core0
38 * @version 1.0
39 * @date 2024-05-28
40 * @brief Device specific configuration file for MIMXRT798S_cm33_core0
41 * (implementation file)
42 *
43 * Provides a system configuration function and a global variable that contains
44 * the system frequency. It configures the device and initializes the oscillator
45 * (PLL) that is part of the microcontroller device.
46 */
47
48 #include <stdint.h>
49 #include <stdbool.h>
50 #include "fsl_device_registers.h"
51
52 /* ----------------------------------------------------------------------------
53 -- Core clock
54 ---------------------------------------------------------------------------- */
55
56 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
57
58 /* ----------------------------------------------------------------------------
59 -- SystemInit()
60 ---------------------------------------------------------------------------- */
61
SystemInit(void)62 __attribute__((weak)) void SystemInit(void)
63 {
64 #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
65 SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access in Secure mode */
66 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
67 SCB_NS->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access in Non-secure mode */
68 #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
69 #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
70
71 SCB->CPACR |= ((3UL << 0 * 2) | (3UL << 1 * 2)); /* set CP0, CP1 Full Access in Secure mode (enable PowerQuad) */
72
73 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
74 SCB_NS->CPACR |=
75 ((3UL << 0 * 2) | (3UL << 1 * 2)); /* set CP0, CP1 Full Access in Non-secure mode (enable PowerQuad) */
76 #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
77
78 SCB->NSACR |= ((3UL << 0) | (3UL << 10)); /* enable CP0, CP1, CP10, CP11 Non-secure Access */
79
80 SYSCON0->DSPSTALL = SYSCON0_DSPSTALL_DSPSTALL_MASK;
81
82 if ((XCACHE1->CCR & XCACHE_CCR_ENCACHE_MASK) == 0U) /* set XCACHE if not configured for code bus.*/
83 {
84 /* set command to invalidate all ways and write GO bit to initiate command */
85 XCACHE1->CCR = XCACHE_CCR_INVW1_MASK | XCACHE_CCR_INVW0_MASK;
86 XCACHE1->CCR |= XCACHE_CCR_GO_MASK;
87 /* Wait until the command completes */
88 while ((XCACHE1->CCR & XCACHE_CCR_GO_MASK) != 0U)
89 {
90 }
91 /* Enable cache */
92 XCACHE1->CCR = XCACHE_CCR_ENCACHE_MASK;
93
94 __ISB();
95 __DSB();
96 }
97
98 #if STARTUP_XSPI0_CACHE_POLICY
99 if ((CACHE64_CTRL0->CCR & CACHE64_CTRL_CCR_ENCACHE_MASK) == 0U)
100 {
101 /* Enable XSPI0 caches */
102 CACHE64_POLSEL0->REG0_TOP = 0x07FFFC00UL;
103 CACHE64_POLSEL0->POLSEL = STARTUP_XSPI0_CACHE_POLICY;
104 /* First, invalidate the entire cache. */
105 CACHE64_CTRL0->CCR = CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK;
106 CACHE64_CTRL0->CCR |= CACHE64_CTRL_CCR_GO_MASK;
107 while ((CACHE64_CTRL0->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0U)
108 {
109 }
110 CACHE64_CTRL0->CCR = CACHE64_CTRL_CCR_ENCACHE_MASK;
111
112 __ISB();
113 __DSB();
114 }
115 #endif
116
117 #if STARTUP_XSPI1_CACHE_POLICY
118 if ((CACHE64_CTRL1->CCR & CACHE64_CTRL_CCR_ENCACHE_MASK) == 0U)
119 {
120 /* Enable XSPI0 caches */
121 CACHE64_POLSEL1->REG0_TOP = 0x07FFFC00UL;
122 CACHE64_POLSEL1->POLSEL = STARTUP_XSPI1_CACHE_POLICY;
123 /* First, invalidate the entire cache. */
124 CACHE64_CTRL1->CCR = CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK;
125 CACHE64_CTRL1->CCR |= CACHE64_CTRL_CCR_GO_MASK;
126 while ((CACHE64_CTRL1->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0U)
127 {
128 }
129 CACHE64_CTRL1->CCR = CACHE64_CTRL_CCR_ENCACHE_MASK;
130
131 __ISB();
132 __DSB();
133 }
134 #endif
135
136 SystemInitHook();
137 }
138
139 /* ----------------------------------------------------------------------------
140 -- SystemCoreClockUpdate()
141 ---------------------------------------------------------------------------- */
142
getFro0MaxFreq(void)143 static uint32_t getFro0MaxFreq(void)
144 {
145 return CLK_FRO0_CLK;
146 }
147
getFro1MaxFreq(void)148 static uint32_t getFro1MaxFreq(void)
149 {
150 return CLK_FRO1_MAX_CLK;
151 }
152
getFro1Div3Freq(void)153 static uint32_t getFro1Div3Freq(void)
154 {
155 return getFro1MaxFreq() / 3U;
156 }
157
getFro0Div3Freq(void)158 static uint32_t getFro0Div3Freq(void)
159 {
160 return getFro0MaxFreq() / 3U;
161 }
162
getLpOscFreq(void)163 static uint32_t getLpOscFreq(void)
164 {
165 return CLK_LPOSC_1MHZ;
166 }
167
getBaseClkCmpt(void)168 static uint32_t getBaseClkCmpt(void)
169 {
170 uint32_t freq = 0U;
171
172 switch (CLKCTL0->CMPTBASECLKSEL & CLKCTL0_CMPTBASECLKSEL_SEL_MASK)
173 {
174 case CLKCTL0_CMPTBASECLKSEL_SEL(0):
175 freq = getFro1Div3Freq();
176 break;
177 case CLKCTL0_CMPTBASECLKSEL_SEL(1):
178 freq = getFro1MaxFreq();
179 break;
180 case CLKCTL0_CMPTBASECLKSEL_SEL(2):
181 freq = getFro0Div3Freq();
182 break;
183 case CLKCTL0_CMPTBASECLKSEL_SEL(3):
184 freq = getLpOscFreq();
185 break;
186 default:
187 freq = 0U;
188 break;
189 }
190
191 return freq;
192 }
193
getMainPllFreq(void)194 static uint32_t getMainPllFreq(void)
195 {
196 uint32_t freq = 0U;
197 uint64_t freqTmp;
198
199 switch ((CLKCTL2->MAINPLL0CLKSEL) & CLKCTL2_MAINPLL0CLKSEL_SEL_MASK)
200 {
201 case CLKCTL2_MAINPLL0CLKSEL_SEL(0):
202 freq = getFro1MaxFreq() / 8U;
203 break;
204 case CLKCTL2_MAINPLL0CLKSEL_SEL(1):
205 freq = CLK_OSC_CLK;
206 break;
207 default:
208 freq = 0U;
209 break;
210 }
211
212 if (((CLKCTL2->MAINPLL0CTL0) & CLKCTL2_MAINPLL0CTL0_BYPASS_MASK) == 0U)
213 {
214 /* PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). */
215 freqTmp = ((uint64_t)freq * ((uint64_t)(CLKCTL2->MAINPLL0NUM))) / ((uint64_t)(CLKCTL2->MAINPLL0DENOM));
216 freq *= ((CLKCTL2->MAINPLL0CTL0) & CLKCTL2_MAINPLL0CTL0_MULT_MASK) >> CLKCTL2_MAINPLL0CTL0_MULT_SHIFT;
217 freq += (uint32_t)freqTmp;
218 }
219 return freq;
220 }
221
getMainPllPfd0Freq(void)222 static uint32_t getMainPllPfd0Freq(void)
223 {
224 uint32_t freq = getMainPllFreq();
225
226 if (((CLKCTL2->MAINPLL0CTL0) & CLKCTL2_MAINPLL0CTL0_BYPASS_MASK) == 0U)
227 {
228 freq = (uint32_t)((uint64_t)freq * 18U /
229 ((CLKCTL2->MAINPLL0PFD & CLKCTL2_MAINPLL0PFD_PFD0_MASK) >> CLKCTL2_MAINPLL0PFD_PFD0_SHIFT));
230 }
231 return freq;
232 }
233
getAudioPllFreq(void)234 static uint32_t getAudioPllFreq(void)
235 {
236 uint32_t freq = 0U;
237 uint64_t freqTmp;
238
239 switch ((CLKCTL2->AUDIOPLL0CLKSEL) & CLKCTL2_AUDIOPLL0CLKSEL_SEL_MASK)
240 {
241 case CLKCTL2_AUDIOPLL0CLKSEL_SEL(0):
242 freq = getFro1MaxFreq() / 8U;
243 break;
244 case CLKCTL2_AUDIOPLL0CLKSEL_SEL(1):
245 freq = CLK_OSC_CLK;
246 break;
247 default:
248 freq = 0U;
249 break;
250 }
251
252 if (((CLKCTL2->AUDIOPLL0CTL0) & CLKCTL2_AUDIOPLL0CTL0_BYPASS_MASK) == 0UL)
253 {
254 /* PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). */
255 freqTmp = ((uint64_t)freq * ((uint64_t)(CLKCTL2->AUDIOPLL0NUM))) / ((uint64_t)(CLKCTL2->AUDIOPLL0DENOM));
256 freq *= ((CLKCTL2->AUDIOPLL0CTL0) & CLKCTL2_AUDIOPLL0CTL0_MULT_MASK) >> CLKCTL2_AUDIOPLL0CTL0_MULT_SHIFT;
257 freq += (uint32_t)freqTmp;
258 }
259 return freq;
260 }
261
getAudioPllPfd1Freq(void)262 static uint32_t getAudioPllPfd1Freq(void)
263 {
264 uint32_t freq = getAudioPllFreq();
265
266 if (((CLKCTL2->AUDIOPLL0CTL0) & CLKCTL2_AUDIOPLL0CTL0_BYPASS_MASK) == 0UL)
267 {
268 freq =
269 (uint32_t)((uint64_t)freq * 18U /
270 ((CLKCTL2->AUDIOPLL0PFD & CLKCTL2_AUDIOPLL0PFD_PFD1_MASK) >> CLKCTL2_AUDIOPLL0PFD_PFD1_SHIFT));
271 }
272 return freq;
273 }
274
SystemCoreClockUpdate(void)275 void SystemCoreClockUpdate(void)
276 {
277 uint32_t freq = 0U;
278
279 switch (CLKCTL0->MAINCLKSEL & CLKCTL0_MAINCLKSEL_SEL_MASK)
280 {
281 case CLKCTL0_MAINCLKSEL_SEL(0):
282 freq = getBaseClkCmpt();
283 break;
284
285 case CLKCTL0_MAINCLKSEL_SEL(1):
286 freq = getMainPllPfd0Freq();
287 break;
288
289 case CLKCTL0_MAINCLKSEL_SEL(2):
290 freq = getFro0MaxFreq();
291 break;
292
293 case CLKCTL0_MAINCLKSEL_SEL(3):
294 freq = getAudioPllPfd1Freq();
295 break;
296
297 default:
298 freq = 0U;
299 break;
300 }
301
302 SystemCoreClock = freq / ((CLKCTL0->MAINCLKDIV & CLKCTL0_MAINCLKDIV_DIV_MASK) + 1U);
303 }
304
305 /* ----------------------------------------------------------------------------
306 -- SystemInitHook()
307 ---------------------------------------------------------------------------- */
308
SystemInitHook(void)309 __attribute__((weak)) void SystemInitHook(void)
310 {
311 /* Void implementation of the weak function. */
312 }
313
