1 /*
2 ** ###################################################################
3 **     Processors:          MIMXRT1175AVM8A_cm7
4 **                          MIMXRT1175CVM8A_cm7
5 **                          MIMXRT1175DVMAA_cm7
6 **
7 **     Compilers:           Freescale C/C++ for Embedded ARM
8 **                          GNU C Compiler
9 **                          IAR ANSI C/C++ Compiler for ARM
10 **                          Keil ARM C/C++ Compiler
11 **                          MCUXpresso Compiler
12 **
13 **     Reference manual:    IMXRT1170RM, Rev 1, 02/2021
14 **     Version:             rev. 1.0, 2020-12-29
15 **     Build:               b230223
16 **
17 **     Abstract:
18 **         Provides a system configuration function and a global variable that
19 **         contains the system frequency. It configures the device and initializes
20 **         the oscillator (PLL) that is part of the microcontroller device.
21 **
22 **     Copyright 2016 Freescale Semiconductor, Inc.
23 **     Copyright 2016-2023 NXP
24 **     All rights reserved.
25 **
26 **     SPDX-License-Identifier: BSD-3-Clause
27 **
28 **     http:                 www.nxp.com
29 **     mail:                 support@nxp.com
30 **
31 **     Revisions:
32 **     - rev. 0.1 (2018-03-05)
33 **         Initial version.
34 **     - rev. 1.0 (2020-12-29)
35 **         Update header files to align with IMXRT1170RM Rev.0.
36 **
37 ** ###################################################################
38 */
39 
40 /*!
41  * @file MIMXRT1175_cm7
42  * @version 1.0
43  * @date 2023-02-23
44  * @brief Device specific configuration file for MIMXRT1175_cm7 (implementation
45  *        file)
46  *
47  * Provides a system configuration function and a global variable that contains
48  * the system frequency. It configures the device and initializes the oscillator
49  * (PLL) that is part of the microcontroller device.
50  */
51 
52 #include <stdint.h>
53 #include "fsl_device_registers.h"
54 
55 
56 
57 /* ----------------------------------------------------------------------------
58    -- Core clock
59    ---------------------------------------------------------------------------- */
60 
61 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
62 
63 /* ----------------------------------------------------------------------------
64    -- SystemInit()
65    ---------------------------------------------------------------------------- */
66 
SystemInit(void)67 void SystemInit (void) {
68 #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
69   SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2));    /* set CP10, CP11 Full Access */
70 #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
71 
72 #if defined(__MCUXPRESSO)
73     extern uint32_t g_pfnVectors[];  // Vector table defined in startup code
74     SCB->VTOR = (uint32_t)g_pfnVectors;
75 #endif
76 
77 /* Watchdog disable */
78 
79 #if (DISABLE_WDOG)
80     if ((WDOG1->WCR & WDOG_WCR_WDE_MASK) != 0U)
81     {
82         WDOG1->WCR &= ~(uint16_t) WDOG_WCR_WDE_MASK;
83     }
84     if ((WDOG2->WCR & WDOG_WCR_WDE_MASK) != 0U)
85     {
86         WDOG2->WCR &= ~(uint16_t) WDOG_WCR_WDE_MASK;
87     }
88     if ((RTWDOG3->CS & RTWDOG_CS_CMD32EN_MASK) != 0U)
89     {
90         RTWDOG3->CNT = 0xD928C520U; /* 0xD928C520U is the update key */
91     }
92     else
93     {
94         RTWDOG3->CNT = 0xC520U;
95         RTWDOG3->CNT = 0xD928U;
96     }
97     RTWDOG3->TOVAL = 0xFFFF;
98     RTWDOG3->CS = (uint32_t) ((RTWDOG3->CS) & ~RTWDOG_CS_EN_MASK) | RTWDOG_CS_UPDATE_MASK;
99     if ((RTWDOG4->CS & RTWDOG_CS_CMD32EN_MASK) != 0U)
100     {
101         RTWDOG4->CNT = 0xD928C520U; /* 0xD928C520U is the update key */
102     }
103     else
104     {
105         RTWDOG4->CNT = 0xC520U;
106         RTWDOG4->CNT = 0xD928U;
107     }
108     RTWDOG4->TOVAL = 0xFFFF;
109     RTWDOG4->CS = (uint32_t) ((RTWDOG4->CS) & ~RTWDOG_CS_EN_MASK) | RTWDOG_CS_UPDATE_MASK;
110 #endif /* (DISABLE_WDOG) */
111 
112     /* Disable Systick which might be enabled by bootrom */
113     if ((SysTick->CTRL & SysTick_CTRL_ENABLE_Msk) != 0U)
114     {
115         SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
116     }
117 
118    /* Enable instruction cache
119       Note: Data cache will be enabled in Board_ConfigMPU() function to avoid situations where instructions are lost. */
120 #if defined(__ICACHE_PRESENT) && __ICACHE_PRESENT
121     if (SCB_CCR_IC_Msk != (SCB_CCR_IC_Msk & SCB->CCR)) {
122         SCB_EnableICache();
123     }
124 #endif
125 
126     /* Clear bit 13 to its reset value since it might be set by ROM. */
127     IOMUXC_GPR->GPR28 &= ~IOMUXC_GPR_GPR28_CACHE_USB_MASK;
128 
129 #if defined(ROM_ECC_ENABLED)
130     /* When ECC is enabled, SRC->SRSR need to be cleared since only correct SRSR value can trigger ROM ECC preload procedure.
131        Save SRSR to SRC->GPR[10] so that application can still check SRSR value from SRC->GPR[10]. */
132     SRC->GPR[10] = SRC->SRSR;
133     /* clear SRSR */
134     SRC->SRSR = 0xFFFFFFFFU;
135 #endif
136 
137     /* Enable entry to thread mode when divide by zero */
138     SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk;
139     __DSB();
140     __ISB();
141 
142   SystemInitHook();
143 }
144 
145 /* ----------------------------------------------------------------------------
146    -- SystemCoreClockUpdate()
147    ---------------------------------------------------------------------------- */
148 
SystemCoreClockUpdate(void)149 void SystemCoreClockUpdate (void) {
150 
151 /* TBD */
152 
153 }
154 
155 /* ----------------------------------------------------------------------------
156    -- SystemInitHook()
157    ---------------------------------------------------------------------------- */
158 
SystemInitHook(void)159 __attribute__ ((weak)) void SystemInitHook (void) {
160   /* Void implementation of the weak function. */
161 }
162 
163