1 /*
2 ** ###################################################################
3 **     Processors:          MIMXRT1172AVM8A
4 **                          MIMXRT1172CVM8A
5 **                          MIMXRT1172DVMAA
6 **
7 **     Compilers:           Freescale C/C++ for Embedded ARM
8 **                          GNU C Compiler
9 **                          IAR ANSI C/C++ Compiler for ARM
10 **                          Keil ARM C/C++ Compiler
11 **                          MCUXpresso Compiler
12 **
13 **     Reference manual:    IMXRT1170RM, Rev 1, 02/2021
14 **     Version:             rev. 1.0, 2020-12-29
15 **     Build:               b211125
16 **
17 **     Abstract:
18 **         Provides a system configuration function and a global variable that
19 **         contains the system frequency. It configures the device and initializes
20 **         the oscillator (PLL) that is part of the microcontroller device.
21 **
22 **     Copyright 2016 Freescale Semiconductor, Inc.
23 **     Copyright 2016-2021 NXP
24 **     All rights reserved.
25 **
26 **     SPDX-License-Identifier: BSD-3-Clause
27 **
28 **     http:                 www.nxp.com
29 **     mail:                 support@nxp.com
30 **
31 **     Revisions:
32 **     - rev. 0.1 (2018-03-05)
33 **         Initial version.
34 **     - rev. 1.0 (2020-12-29)
35 **         Update header files to align with IMXRT1170RM Rev.0.
36 **
37 ** ###################################################################
38 */
39 
40 /*!
41  * @file MIMXRT1172
42  * @version 1.0
43  * @date 2021-11-25
44  * @brief Device specific configuration file for MIMXRT1172 (implementation file)
45  *
46  * Provides a system configuration function and a global variable that contains
47  * the system frequency. It configures the device and initializes the oscillator
48  * (PLL) that is part of the microcontroller device.
49  */
50 
51 #include <stdint.h>
52 #include "fsl_device_registers.h"
53 
54 
55 
56 /* ----------------------------------------------------------------------------
57    -- Core clock
58    ---------------------------------------------------------------------------- */
59 
60 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
61 
62 /* ----------------------------------------------------------------------------
63    -- SystemInit()
64    ---------------------------------------------------------------------------- */
65 
SystemInit(void)66 void SystemInit (void) {
67 #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
68   SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2));    /* set CP10, CP11 Full Access */
69 #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
70 
71 #if defined(__MCUXPRESSO)
72     extern uint32_t g_pfnVectors[];  // Vector table defined in startup code
73     SCB->VTOR = (uint32_t)g_pfnVectors;
74 #endif
75 
76 /* Watchdog disable */
77 
78 #if (DISABLE_WDOG)
79     if ((WDOG1->WCR & WDOG_WCR_WDE_MASK) != 0U)
80     {
81         WDOG1->WCR &= ~(uint16_t) WDOG_WCR_WDE_MASK;
82     }
83     if ((WDOG2->WCR & WDOG_WCR_WDE_MASK) != 0U)
84     {
85         WDOG2->WCR &= ~(uint16_t) WDOG_WCR_WDE_MASK;
86     }
87     if ((RTWDOG3->CS & RTWDOG_CS_CMD32EN_MASK) != 0U)
88     {
89         RTWDOG3->CNT = 0xD928C520U; /* 0xD928C520U is the update key */
90     }
91     else
92     {
93         RTWDOG3->CNT = 0xC520U;
94         RTWDOG3->CNT = 0xD928U;
95     }
96     RTWDOG3->TOVAL = 0xFFFF;
97     RTWDOG3->CS = (uint32_t) ((RTWDOG3->CS) & ~RTWDOG_CS_EN_MASK) | RTWDOG_CS_UPDATE_MASK;
98     if ((RTWDOG4->CS & RTWDOG_CS_CMD32EN_MASK) != 0U)
99     {
100         RTWDOG4->CNT = 0xD928C520U; /* 0xD928C520U is the update key */
101     }
102     else
103     {
104         RTWDOG4->CNT = 0xC520U;
105         RTWDOG4->CNT = 0xD928U;
106     }
107     RTWDOG4->TOVAL = 0xFFFF;
108     RTWDOG4->CS = (uint32_t) ((RTWDOG4->CS) & ~RTWDOG_CS_EN_MASK) | RTWDOG_CS_UPDATE_MASK;
109 #endif /* (DISABLE_WDOG) */
110 
111     /* Disable Systick which might be enabled by bootrom */
112     if ((SysTick->CTRL & SysTick_CTRL_ENABLE_Msk) != 0U)
113     {
114         SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
115     }
116 
117 /* Enable instruction and data caches */
118 #if defined(__ICACHE_PRESENT) && __ICACHE_PRESENT
119     if (SCB_CCR_IC_Msk != (SCB_CCR_IC_Msk & SCB->CCR)) {
120         SCB_EnableICache();
121     }
122 #endif
123 
124     /* Clear bit 13 to its reset value since it might be set by ROM. */
125     IOMUXC_GPR->GPR28 &= ~IOMUXC_GPR_GPR28_CACHE_USB_MASK;
126 
127 #if defined(ROM_ECC_ENABLED)
128     /* When ECC is enabled, SRC->SRSR need to be cleared since only correct SRSR value can trigger ROM ECC preload procedure.
129        Save SRSR to SRC->GPR[10] so that application can still check SRSR value from SRC->GPR[10]. */
130     SRC->GPR[10] = SRC->SRSR;
131     /* clear SRSR */
132     SRC->SRSR = 0xFFFFFFFFU;
133 #endif
134 
135     /* Enable entry to thread mode when divide by zero */
136     SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk;
137     __DSB();
138     __ISB();
139 
140   SystemInitHook();
141 }
142 
143 /* ----------------------------------------------------------------------------
144    -- SystemCoreClockUpdate()
145    ---------------------------------------------------------------------------- */
146 
SystemCoreClockUpdate(void)147 void SystemCoreClockUpdate (void) {
148 
149 /* TBD */
150 
151 }
152 
153 /* ----------------------------------------------------------------------------
154    -- SystemInitHook()
155    ---------------------------------------------------------------------------- */
156 
SystemInitHook(void)157 __attribute__ ((weak)) void SystemInitHook (void) {
158   /* Void implementation of the weak function. */
159 }
160 
161