1 /* 2 ** ################################################################### 3 ** Processors: MIMXRT1011CAE4A 4 ** MIMXRT1011DAE5A 5 ** 6 ** Compilers: Freescale C/C++ for Embedded ARM 7 ** GNU C Compiler 8 ** IAR ANSI C/C++ Compiler for ARM 9 ** Keil ARM C/C++ Compiler 10 ** MCUXpresso Compiler 11 ** 12 ** Reference manual: IMXRT1010RM Rev.1, 10/2021 | IMXRT1010SRM Rev.0 13 ** Version: rev. 1.2, 2021-08-10 14 ** Build: b210810 15 ** 16 ** Abstract: 17 ** Provides a system configuration function and a global variable that 18 ** contains the system frequency. It configures the device and initializes 19 ** the oscillator (PLL) that is part of the microcontroller device. 20 ** 21 ** Copyright 2016 Freescale Semiconductor, Inc. 22 ** Copyright 2016-2021 NXP 23 ** All rights reserved. 24 ** 25 ** SPDX-License-Identifier: BSD-3-Clause 26 ** 27 ** http: www.nxp.com 28 ** mail: support@nxp.com 29 ** 30 ** Revisions: 31 ** - rev. 0.1 (2019-02-14) 32 ** Initial version. 33 ** - rev. 1.0 (2019-08-01) 34 ** Rev.0 Header GA 35 ** - rev. 1.1 (2019-08-06) 36 ** Update header files to align with IMXRT1010RM Rev.B. 37 ** - rev. 1.2 (2021-08-10) 38 ** Update header files to align with IMXRT1010RM Rev.1. 39 ** 40 ** ################################################################### 41 */ 42 43 /*! 44 * @file MIMXRT1011 45 * @version 1.2 46 * @date 2021-08-10 47 * @brief Device specific configuration file for MIMXRT1011 (implementation file) 48 * 49 * Provides a system configuration function and a global variable that contains 50 * the system frequency. It configures the device and initializes the oscillator 51 * (PLL) that is part of the microcontroller device. 52 */ 53 54 #include <stdint.h> 55 #include "fsl_device_registers.h" 56 57 58 59 /* ---------------------------------------------------------------------------- 60 -- Core clock 61 ---------------------------------------------------------------------------- */ 62 63 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; 64 65 /* ---------------------------------------------------------------------------- 66 -- SystemInit() 67 ---------------------------------------------------------------------------- */ 68 SystemInit(void)69void SystemInit (void) { 70 #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) 71 SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */ 72 #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ 73 74 #if defined(__MCUXPRESSO) 75 extern uint32_t g_pfnVectors[]; // Vector table defined in startup code 76 SCB->VTOR = (uint32_t)g_pfnVectors; 77 #endif 78 79 /* Disable Watchdog Power Down Counter */ 80 WDOG1->WMCR &= ~(uint16_t) WDOG_WMCR_PDE_MASK; 81 WDOG2->WMCR &= ~(uint16_t) WDOG_WMCR_PDE_MASK; 82 83 /* Watchdog disable */ 84 85 #if (DISABLE_WDOG) 86 if ((WDOG1->WCR & WDOG_WCR_WDE_MASK) != 0U) 87 { 88 WDOG1->WCR &= ~(uint16_t) WDOG_WCR_WDE_MASK; 89 } 90 if ((WDOG2->WCR & WDOG_WCR_WDE_MASK) != 0U) 91 { 92 WDOG2->WCR &= ~(uint16_t) WDOG_WCR_WDE_MASK; 93 } 94 if ((RTWDOG->CS & RTWDOG_CS_CMD32EN_MASK) != 0U) 95 { 96 RTWDOG->CNT = 0xD928C520U; /* 0xD928C520U is the update key */ 97 } 98 else 99 { 100 RTWDOG->CNT = 0xC520U; 101 RTWDOG->CNT = 0xD928U; 102 } 103 RTWDOG->TOVAL = 0xFFFF; 104 RTWDOG->CS = (uint32_t) ((RTWDOG->CS) & ~RTWDOG_CS_EN_MASK) | RTWDOG_CS_UPDATE_MASK; 105 #endif /* (DISABLE_WDOG) */ 106 107 /* Disable Systick which might be enabled by bootrom */ 108 if ((SysTick->CTRL & SysTick_CTRL_ENABLE_Msk) != 0U) 109 { 110 SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; 111 } 112 113 /* Enable instruction and data caches */ 114 #if defined(__ICACHE_PRESENT) && __ICACHE_PRESENT 115 if (SCB_CCR_IC_Msk != (SCB_CCR_IC_Msk & SCB->CCR)) { 116 SCB_EnableICache(); 117 } 118 #endif 119 120 SystemInitHook(); 121 } 122 123 /* ---------------------------------------------------------------------------- 124 -- SystemCoreClockUpdate() 125 ---------------------------------------------------------------------------- */ 126 SystemCoreClockUpdate(void)127void SystemCoreClockUpdate (void) { 128 129 uint32_t freq; 130 uint32_t PLL2MainClock; 131 uint32_t PLL3MainClock; 132 133 /* Check if system pll is bypassed */ 134 if((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_MASK) != 0U) 135 { 136 PLL2MainClock = CPU_XTAL_CLK_HZ; 137 } 138 else 139 { 140 PLL2MainClock = (CPU_XTAL_CLK_HZ * (((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK) != 0U) ? 22U : 20U)); 141 } 142 PLL2MainClock += (uint32_t)(((uint64_t)CPU_XTAL_CLK_HZ * ((uint64_t)(CCM_ANALOG->PLL_SYS_NUM))) / ((uint64_t)(CCM_ANALOG->PLL_SYS_DENOM))); 143 144 /* Check if usb1 pll is bypassed */ 145 if((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_BYPASS_MASK) != 0U) 146 { 147 PLL3MainClock = CPU_XTAL_CLK_HZ; 148 } 149 else 150 { 151 PLL3MainClock = (CPU_XTAL_CLK_HZ * (((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) != 0U) ? 22U : 20U)); 152 } 153 154 /* Periph_clk2_clk ---> Periph_clk */ 155 if ((CCM->CBCDR & CCM_CBCDR_PERIPH_CLK_SEL_MASK) != 0U) 156 { 157 switch (CCM->CBCMR & CCM_CBCMR_PERIPH_CLK2_SEL_MASK) 158 { 159 /* Pll3_sw_clk ---> Periph_clk2_clk ---> Periph_clk ---> Core_clock */ 160 case CCM_CBCMR_PERIPH_CLK2_SEL(0U): 161 freq = PLL3MainClock; 162 break; 163 164 /* Osc_clk ---> Periph_clk2_clk ---> Periph_clk ---> Core_clock */ 165 case CCM_CBCMR_PERIPH_CLK2_SEL(1U): 166 freq = CPU_XTAL_CLK_HZ; 167 break; 168 169 /* Pll2_bypass_clk ---> Periph_clk2_clk ---> Periph_clk ---> Core_clock */ 170 case CCM_CBCMR_PERIPH_CLK2_SEL(2U): 171 freq = CPU_XTAL_CLK_HZ; 172 break; 173 174 case CCM_CBCMR_PERIPH_CLK2_SEL(3U): 175 default: 176 freq = 0U; 177 break; 178 } 179 } 180 /* Pre_Periph_clk ---> Periph_clk */ 181 else 182 { 183 switch (CCM->CBCMR & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK) 184 { 185 /* PLL2 ---> Pre_Periph_clk ---> Periph_clk ---> Core_clock */ 186 case CCM_CBCMR_PRE_PERIPH_CLK_SEL(0U): 187 freq = PLL2MainClock; 188 break; 189 190 /* PLL3 PFD3 ---> Pre_Periph_clk ---> Periph_clk ---> Core_clock */ 191 case CCM_CBCMR_PRE_PERIPH_CLK_SEL(1U): 192 freq = PLL3MainClock / ((CCM_ANALOG->PFD_480 & CCM_ANALOG_PFD_480_PFD3_FRAC_MASK) >> CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT) * 18U; 193 break; 194 195 /* PLL2 PFD3 ---> Pre_Periph_clk ---> Periph_clk ---> Core_clock */ 196 case CCM_CBCMR_PRE_PERIPH_CLK_SEL(2U): 197 freq = PLL2MainClock / ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD3_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT) * 18U; 198 break; 199 200 /* PLL6 ---> Pre_Periph_clk ---> Periph_clk ---> Core_clock */ 201 case CCM_CBCMR_PRE_PERIPH_CLK_SEL(3U): 202 freq = 500000000U; 203 break; 204 205 default: 206 freq = 0U; 207 break; 208 } 209 } 210 211 SystemCoreClock = (freq / (((CCM->CBCDR & CCM_CBCDR_AHB_PODF_MASK) >> CCM_CBCDR_AHB_PODF_SHIFT) + 1U)); 212 213 } 214 215 /* ---------------------------------------------------------------------------- 216 -- SystemInitHook() 217 ---------------------------------------------------------------------------- */ 218 SystemInitHook(void)219__attribute__ ((weak)) void SystemInitHook (void) { 220 /* Void implementation of the weak function. */ 221 } 222
