1 /* 2 ** ################################################################### 3 ** Processor: MIMX8QM6AVUFF 4 ** Compilers: Keil ARM C/C++ Compiler 5 ** GNU C Compiler 6 ** GNU C Compiler - CodeSourcery Sourcery G++ 7 ** IAR ANSI C/C++ Compiler for ARM 8 ** 9 ** Reference manual: IMX8QMRM, Rev. E, Jun. 2018 10 ** Version: rev. 4.0, 2018-08-30 11 ** Build: b180831 12 ** 13 ** Abstract: 14 ** Provides a system configuration function and a global variable that 15 ** contains the system frequency. It configures the device and initializes 16 ** the oscillator (PLL) that is part of the microcontroller device. 17 ** 18 ** Copyright 2016 Freescale Semiconductor, Inc. 19 ** Copyright 2016-2018 NXP 20 ** All rights reserved. 21 ** 22 ** SPDX-License-Identifier: BSD-3-Clause 23 ** 24 ** http: www.nxp.com 25 ** mail: support@nxp.com 26 ** 27 ** Revisions: 28 ** - rev. 1.0 (2016-06-02) 29 ** Initial version. 30 ** - rev. 2.0 (2017-05-04) 31 ** RevA Header ER 32 ** - rev. 3.0 (2018-01-29) 33 ** RevB Header ER 34 ** - rev. 4.0 (2018-08-30) 35 ** RevC Header EAR 36 ** 37 ** ################################################################### 38 */ 39 40 /*! 41 * @file MIMX8QM6_cm4_core0 42 * @version 4.0 43 * @date 2018-08-30 44 * @brief Device specific configuration file for MIMX8QM6_cm4_core0 (header file) 45 * 46 * Provides a system configuration function and a global variable that contains 47 * the system frequency. It configures the device and initializes the oscillator 48 * (PLL) that is part of the microcontroller device. 49 */ 50 51 #ifndef _SYSTEM_MIMX8QM6_cm4_core0_H_ 52 #define _SYSTEM_MIMX8QM6_cm4_core0_H_ /**< Symbol preventing repeated inclusion */ 53 54 #ifdef __cplusplus 55 extern "C" { 56 #endif 57 58 #include <stdint.h> 59 #include "main/rpc.h" 60 #include "svc/pm/pm_api.h" 61 62 #ifndef DISABLE_WDOG 63 #define DISABLE_WDOG 1 64 #endif 65 66 /** 67 * When downloading/debuging with Debugger, the Parity/ECC error check is disabled by debugger. 68 * Define ENABLE_ECC_DEBUG to non-zero value to re-enable the check during debugging. 69 */ 70 #ifndef ENABLE_ECC_DEBUG 71 #define ENABLE_ECC_DEBUG 0 72 #endif 73 74 #define DEFAULT_SYSTEM_CLOCK 264000000u /* Default System clock value */ 75 76 /** 77 * @brief System clock frequency (core clock) 78 * 79 * The system clock frequency supplied to the SysTick timer and the processor 80 * core clock. This variable can be used by the user application to setup the 81 * SysTick timer or configure other parameters. It may also be used by debugger to 82 * query the frequency of the debug timer or configure the trace clock speed 83 * SystemCoreClock is initialized with a correct predefined value. 84 */ 85 extern uint32_t SystemCoreClock; 86 87 /** 88 * @brief Setup the microcontroller system. 89 * 90 * Typically this function configures the oscillator (PLL) that is part of the 91 * microcontroller device. For systems with variable clock speed it also updates 92 * the variable SystemCoreClock. SystemInit is called from startup_device file. 93 */ 94 void SystemInit (void); 95 96 /** 97 * @brief Updates the SystemCoreClock variable. 98 * 99 * It must be called whenever the core clock is changed during program 100 * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates 101 * the current core clock. 102 */ 103 void SystemCoreClockUpdate (void); 104 105 /** 106 * @brief Open the SCFW IPC channel. 107 * 108 * Typically this function opens the IPC channel between current Subsystem and SCU. 109 * This function uses SCFW API to initialize the MU channel. SystemInitScfwIpc should 110 * be called before using SCFW API. 111 */ 112 void SystemInitScfwIpc (void); 113 114 /** 115 * @brief Get the SCFW IPC handle. 116 * 117 * This function gets the IPC handle which could be used to communicate with SCFW. 118 * SystemGetScfwIpcHandle should be called after SCFW IPC channel is initialized. 119 */ 120 sc_ipc_t SystemGetScfwIpcHandle (void); 121 122 #ifdef __cplusplus 123 } 124 #endif 125 126 #endif /* _SYSTEM_MIMX8QM6_cm4_core0_H_ */ 127
