1 /*
2 ** ###################################################################
3 ** Processors: MCXC141VFM
4 ** MCXC141VLH
5 **
6 ** Compilers: Freescale C/C++ for Embedded ARM
7 ** GNU C Compiler
8 ** IAR ANSI C/C++ Compiler for ARM
9 ** Keil ARM C/C++ Compiler
10 ** MCUXpresso Compiler
11 **
12 ** Reference manual: MCXC242RM, Rev.1, Mar 2024
13 ** Version: rev. 1.6, 2016-06-24
14 ** Build: b240516
15 **
16 ** Abstract:
17 ** Provides a system configuration function and a global variable that
18 ** contains the system frequency. It configures the device and initializes
19 ** the oscillator (PLL) that is part of the microcontroller device.
20 **
21 ** Copyright 2016 Freescale Semiconductor, Inc.
22 ** Copyright 2016-2024 NXP
23 ** SPDX-License-Identifier: BSD-3-Clause
24 **
25 ** http: www.nxp.com
26 ** mail: support@nxp.com
27 **
28 ** Revisions:
29 ** - rev. 1.0 (2014-05-12)
30 ** Initial version.
31 ** - rev. 1.1 (2014-07-10)
32 ** UART0 - UART0 module renamed to UART2.
33 ** - rev. 1.2 (2014-08-12)
34 ** CRC - CRC register renamed to DATA.
35 ** - rev. 1.3 (2014-09-02)
36 ** USB - USB0_CTL0 was renamed to USB0_OTGCTL register.
37 ** USB - USB0_CTL1 was renamed to USB0_CTL register.
38 ** USB - Two new bitfields (STOP_ACK_DLY_EN, AHB_DLY_EN) was added to the USB0_KEEP_ALIVE_CTRL register.
39 ** - rev. 1.4 (2014-09-22)
40 ** FLEXIO - Offsets of the SHIFTBUFBIS registers were interchanged with offsets of the SHIFTBUFBBS registers.
41 ** SIM - Changed bitfield value MCGIRCLK to LIRC_CLK of bitfield CLKOUTSEL in SOPT2 register.
42 ** SIM - Removed bitfield DIEID in SDID register.
43 ** UART2 - Removed ED register.
44 ** UART2 - Removed MODEM register.
45 ** UART2 - Removed IR register.
46 ** UART2 - Removed PFIFO register.
47 ** UART2 - Removed CFIFO register.
48 ** UART2 - Removed SFIFO register.
49 ** UART2 - Removed TWFIFO register.
50 ** UART2 - Removed TCFIFO register.
51 ** UART2 - Removed RWFIFO register.
52 ** UART2 - Removed RCFIFO register.
53 ** USB - Removed bitfield REG_EN in CLK_RECOVER_IRC_EN register.
54 ** USB - Renamed USBEN bitfield of USB0_CTL was renamed to USBENSOFEN.
55 ** - rev. 1.5 (2016-02-02)
56 ** FGPIO - Add FGPIO registers.
57 ** - rev. 1.6 (2016-06-24)
58 ** USB - OTGCTL register was removed.
59 ** USB - Bit RESUME was added in CTL register.
60 **
61 ** ###################################################################
62 */
63
64 /*!
65 * @file MCXC141
66 * @version 1.6
67 * @date 2016-06-24
68 * @brief Device specific configuration file for MCXC141 (implementation file)
69 *
70 * Provides a system configuration function and a global variable that contains
71 * the system frequency. It configures the device and initializes the oscillator
72 * (PLL) that is part of the microcontroller device.
73 */
74
75 #include <stdint.h>
76 #include "fsl_device_registers.h"
77
78
79
80 /* ----------------------------------------------------------------------------
81 -- Core clock
82 ---------------------------------------------------------------------------- */
83
84 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
85
86 /* ----------------------------------------------------------------------------
87 -- SystemInit()
88 ---------------------------------------------------------------------------- */
89
SystemInit(void)90 void SystemInit (void) {
91
92 #if (ACK_ISOLATION)
93 if((PMC->REGSC & PMC_REGSC_ACKISO_MASK) != 0U) {
94 PMC->REGSC |= PMC_REGSC_ACKISO_MASK; /* VLLSx recovery */
95 }
96 #endif
97
98 #if (DISABLE_WDOG)
99 /* SIM->COPC: ?=0,COPCLKSEL=0,COPDBGEN=0,COPSTPEN=0,COPT=0,COPCLKS=0,COPW=0 */
100 SIM->COPC = (uint32_t)0x00U;
101 #endif /* (DISABLE_WDOG) */
102
103 SystemInitHook();
104 }
105
106 /* ----------------------------------------------------------------------------
107 -- SystemCoreClockUpdate()
108 ---------------------------------------------------------------------------- */
109
SystemCoreClockUpdate(void)110 void SystemCoreClockUpdate (void) {
111
112 uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
113 uint16_t Divider;
114
115 if ((MCG->S & MCG_S_CLKST_MASK) == 0x00U) {
116 /* High internal reference clock is selected */
117 MCGOUTClock = CPU_INT_FAST_CLK_HZ; /* Fast internal reference clock selected */
118 } else if ((MCG->S & MCG_S_CLKST_MASK) == 0x04U) {
119 /* Internal reference clock is selected */
120 Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
121 MCGOUTClock = (uint32_t) (CPU_INT_SLOW_CLK_HZ / Divider); /* Slow internal reference clock 8MHz selected */
122 } else if ((MCG->S & MCG_S_CLKST_MASK) == 0x08U) {
123 /* External reference clock is selected */
124 MCGOUTClock = CPU_XTAL_CLK_HZ;
125 } else {
126 /* Reserved value */
127 return;
128 } /* (!((MCG->S & MCG_S_CLKST_MASK) == 0x08U)) */
129 SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
130 }
131
132 /* ----------------------------------------------------------------------------
133 -- SystemInitHook()
134 ---------------------------------------------------------------------------- */
135
SystemInitHook(void)136 __attribute__ ((weak)) void SystemInitHook (void) {
137 /* Void implementation of the weak function. */
138 }
139
