1 /*
2 ** ###################################################################
3 ** Processors: LPC54S016JBD100
4 ** LPC54S016JBD208
5 ** LPC54S016JET100
6 ** LPC54S016JET180
7 **
8 ** Compilers: GNU C Compiler
9 ** IAR ANSI C/C++ Compiler for ARM
10 ** Keil ARM C/C++ Compiler
11 ** MCUXpresso Compiler
12 **
13 ** Reference manual: LPC540xx/LPC54S0xx User manual Rev.0.8 5 June 2018
14 ** Version: rev. 1.0, 2018-04-20
15 ** Build: b230321
16 **
17 ** Abstract:
18 ** Provides a system configuration function and a global variable that
19 ** contains the system frequency. It configures the device and initializes
20 ** the oscillator (PLL) that is part of the microcontroller device.
21 **
22 ** Copyright 2016 Freescale Semiconductor, Inc.
23 ** Copyright 2016-2023 NXP
24 ** All rights reserved.
25 **
26 ** SPDX-License-Identifier: BSD-3-Clause
27 **
28 ** http: www.nxp.com
29 ** mail: support@nxp.com
30 **
31 ** Revisions:
32 ** - rev. 1.0 (2018-04-20)
33 ** Initial version.
34 **
35 ** ###################################################################
36 */
37
38 /*!
39 * @file LPC54S016
40 * @version 1.0
41 * @date 2018-04-20
42 * @brief Device specific configuration file for LPC54S016 (implementation file)
43 *
44 * Provides a system configuration function and a global variable that contains
45 * the system frequency. It configures the device and initializes the oscillator
46 * (PLL) that is part of the microcontroller device.
47 */
48
49 #include <stdint.h>
50 #include "fsl_device_registers.h"
51
52 #define NVALMAX (0x100)
53 #define PVALMAX (0x20)
54 #define MVALMAX (0x8000)
55 #define PLL_MDEC_VAL_P (0) /* MDEC is in bits 16:0 */
56 #define PLL_MDEC_VAL_M (0x1FFFFUL << PLL_MDEC_VAL_P)
57 #define PLL_NDEC_VAL_P (0) /* NDEC is in bits 9:0 */
58 #define PLL_NDEC_VAL_M (0x3FFUL << PLL_NDEC_VAL_P)
59 #define PLL_PDEC_VAL_P (0) /* PDEC is in bits 6:0 */
60 #define PLL_PDEC_VAL_M (0x7FUL << PLL_PDEC_VAL_P)
61
62 static const uint8_t wdtFreqLookup[32] = {0, 8, 12, 15, 18, 20, 24, 26, 28, 30, 32, 34, 36, 38, 40, 41, 42, 44, 45, 46,
63 48, 49, 50, 52, 53, 54, 56, 57, 58, 59, 60, 61};
64 /* Get WATCH DOG Clk */
getWdtOscFreq(void)65 static uint32_t getWdtOscFreq(void)
66 {
67 uint8_t freq_sel, div_sel;
68 if ((SYSCON->PDRUNCFG[0] & SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK) != 0UL)
69 {
70 return 0U;
71 }
72 else
73 {
74 div_sel = (uint8_t)((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_DIVSEL_MASK) + 1UL) << 1UL;
75 freq_sel = wdtFreqLookup[((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_FREQSEL_MASK) >> SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)];
76 return ((uint32_t) freq_sel * 50000U)/((uint32_t)div_sel);
77 }
78 }
79 /* Find decoded N value for raw NDEC value */
pllDecodeN(uint32_t NDEC)80 static uint32_t pllDecodeN(uint32_t NDEC)
81 {
82 uint32_t n, x, i;
83
84 /* Find NDec */
85 switch (NDEC)
86 {
87 case 0x3FF:
88 n = 0UL;
89 break;
90 case 0x302:
91 n = 1UL;
92 break;
93 case 0x202:
94 n = 2UL;
95 break;
96 default:
97 x = 0x080UL;
98 n = 0xFFFFFFFFUL;
99 for (i = NVALMAX; i >= 3UL; i--)
100 {
101 x = (((x ^ (x >> 2UL) ^ (x >> 3UL) ^ (x >> 4UL)) & 1UL) << 7UL) | ((x >> 1UL) & 0x7FUL);
102 if ((x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P)) == NDEC)
103 {
104 /* Decoded value of NDEC */
105 n = i;
106 }
107 if (n != 0xFFFFFFFFUL)
108 {
109 break;
110 }
111 }
112 break;
113 }
114 return n;
115 }
116
117 /* Find decoded P value for raw PDEC value */
pllDecodeP(uint32_t PDEC)118 static uint32_t pllDecodeP(uint32_t PDEC)
119 {
120 uint32_t p, x, i;
121 /* Find PDec */
122 switch (PDEC)
123 {
124 case 0x7F:
125 p = 0UL;
126 break;
127 case 0x62:
128 p = 1UL;
129 break;
130 case 0x42:
131 p = 2UL;
132 break;
133 default:
134 x = 0x10UL;
135 p = 0xFFFFFFFFUL;
136 for (i = PVALMAX; i >= 3UL; i--)
137 {
138 x = (((x ^ (x >> 2UL)) & 1UL) << 4UL) | ((x >> 1UL) & 0xFUL);
139 if ((x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P)) == PDEC)
140 {
141 /* Decoded value of PDEC */
142 p = i;
143 }
144 if (p != 0xFFFFFFFFUL)
145 {
146 break;
147 }
148 }
149 break;
150 }
151 return p;
152 }
153
154 /* Find decoded M value for raw MDEC value */
pllDecodeM(uint32_t MDEC)155 static uint32_t pllDecodeM(uint32_t MDEC)
156 {
157 uint32_t m, i, x;
158
159 /* Find MDec */
160 switch (MDEC)
161 {
162 case 0x1FFFF:
163 m = 0UL;
164 break;
165 case 0x18003:
166 m = 1UL;
167 break;
168 case 0x10003:
169 m = 2UL;
170 break;
171 default:
172 x = 0x04000UL;
173 m = 0xFFFFFFFFUL;
174 for (i = MVALMAX; i >= 3UL; i--)
175 {
176 x = (((x ^ (x >> 1UL)) & 1UL) << 14UL) | ((x >> 1UL) & 0x3FFFUL);
177 if ((x & (PLL_MDEC_VAL_M >> PLL_MDEC_VAL_P)) == MDEC)
178 {
179 /* Decoded value of MDEC */
180 m = i;
181 }
182 if (m != 0xFFFFFFFFUL)
183 {
184 break;
185 }
186 }
187 break;
188 }
189 return m;
190 }
191
192 /* Get predivider (N) from PLL NDEC setting */
findPllPreDiv(uint32_t ctrlReg,uint32_t nDecReg)193 static uint32_t findPllPreDiv(uint32_t ctrlReg, uint32_t nDecReg)
194 {
195 uint32_t preDiv = 1;
196
197 /* Direct input is not used? */
198 if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTI_MASK) == 0UL)
199 {
200 /* Decode NDEC value to get (N) pre divider */
201 preDiv = pllDecodeN(nDecReg & 0x3FFUL);
202 if (preDiv == 0UL)
203 {
204 preDiv = 1;
205 }
206 }
207 /* Adjusted by 1, directi is used to bypass */
208 return preDiv;
209 }
210
211 /* Get postdivider (P) from PLL PDEC setting */
findPllPostDiv(uint32_t ctrlReg,uint32_t pDecReg)212 static uint32_t findPllPostDiv(uint32_t ctrlReg, uint32_t pDecReg)
213 {
214 uint32_t postDiv = 1;
215
216 /* Direct input is not used? */
217 if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTO_MASK) == 0UL)
218 {
219 /* Decode PDEC value to get (P) post divider */
220 postDiv = 2UL * pllDecodeP(pDecReg & 0x7FUL);
221 if (postDiv == 0UL)
222 {
223 postDiv = 2;
224 }
225 }
226 /* Adjusted by 1, directo is used to bypass */
227 return postDiv;
228 }
229
230 /* Get multiplier (M) from PLL MDEC and BYPASS_FBDIV2 settings */
findPllMMult(uint32_t ctrlReg,uint32_t mDecReg)231 static uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg)
232 {
233 uint32_t mMult = 1;
234
235 /* Decode MDEC value to get (M) multiplier */
236 mMult = pllDecodeM(mDecReg & 0x1FFFFUL);
237 if (mMult == 0UL)
238 {
239 mMult = 1;
240 }
241 return mMult;
242 }
243
244
245
246 /* ----------------------------------------------------------------------------
247 -- Core clock
248 ---------------------------------------------------------------------------- */
249
250 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
251
252 /* ----------------------------------------------------------------------------
253 -- SystemInit()
254 ---------------------------------------------------------------------------- */
255
SystemInit(void)256 void SystemInit (void) {
257 #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
258 SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
259 #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
260
261 #if defined(__MCUXPRESSO)
262 extern void(*const g_pfnVectors[]) (void);
263 SCB->VTOR = (uint32_t) &g_pfnVectors;
264 #else
265 extern void *__Vectors;
266 SCB->VTOR = (uint32_t) &__Vectors;
267 #endif
268 SYSCON->ARMTRACECLKDIV = 0;
269 /* Optionally enable RAM banks that may be off by default at reset */
270 #if !defined(DONT_ENABLE_DISABLED_RAMBANKS)
271 SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL_SRAM1_MASK | SYSCON_AHBCLKCTRL_SRAM2_MASK | SYSCON_AHBCLKCTRL_SRAM3_MASK;
272
273 #endif
274 SYSCON->MAINCLKSELA = 0U;
275 SYSCON->MAINCLKSELB = 0U;
276 SystemInitHook();
277 }
278
279 /* ----------------------------------------------------------------------------
280 -- SystemCoreClockUpdate()
281 ---------------------------------------------------------------------------- */
282
SystemCoreClockUpdate(void)283 void SystemCoreClockUpdate (void) {
284 uint32_t clkRate = 0;
285 uint32_t prediv, postdiv;
286 uint64_t workRate;
287
288 switch (SYSCON->MAINCLKSELB & SYSCON_MAINCLKSELB_SEL_MASK)
289 {
290 case 0x00: /* MAINCLKSELA clock (main_clk_a)*/
291 switch (SYSCON->MAINCLKSELA & SYSCON_MAINCLKSELA_SEL_MASK)
292 {
293 case 0x00: /* FRO 12 MHz (fro_12m) */
294 clkRate = CLK_FRO_12MHZ;
295 break;
296 case 0x01: /* CLKIN Source (clk_in) */
297 clkRate = CLK_CLK_IN;
298 break;
299 case 0x02: /* Watchdog oscillator (wdt_clk) */
300 clkRate = getWdtOscFreq();
301 break;
302 default: /* = 0x03 = FRO 96 or 48 MHz (fro_hf) */
303 if ((SYSCON->FROCTRL & SYSCON_FROCTRL_SEL_MASK) == SYSCON_FROCTRL_SEL_MASK)
304 {
305 clkRate = CLK_FRO_96MHZ;
306 }
307 else
308 {
309 clkRate = CLK_FRO_48MHZ;
310 }
311 break;
312 }
313 break;
314 case 0x02: /* System PLL clock (pll_clk)*/
315 switch (SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK)
316 {
317 case 0x00: /* FRO 12 MHz (fro_12m) */
318 clkRate = CLK_FRO_12MHZ;
319 break;
320 case 0x01: /* CLKIN Source (clk_in) */
321 clkRate = CLK_CLK_IN;
322 break;
323 case 0x02: /* Watchdog oscillator (wdt_clk) */
324 clkRate = getWdtOscFreq();
325 break;
326 case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */
327 clkRate = CLK_RTC_32K_CLK;
328 break;
329 default:
330 clkRate = 0UL;
331 break;
332 }
333 if ((SYSCON->SYSPLLCTRL & SYSCON_SYSPLLCTRL_BYPASS_MASK) == 0UL)
334 {
335 /* PLL is not in bypass mode, get pre-divider, post-divider, and M divider */
336 prediv = findPllPreDiv(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLNDEC);
337 postdiv = findPllPostDiv(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLPDEC);
338 /* Adjust input clock */
339 clkRate = clkRate / prediv;
340
341 /* MDEC used for rate */
342 workRate = (uint64_t)(clkRate) * (uint64_t)findPllMMult(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLMDEC);
343 clkRate = (uint32_t)(workRate / ((uint64_t)postdiv));
344 clkRate = clkRate * 2UL; /* PLL CCO output is divided by 2 before to M-Divider */
345 }
346 break;
347 case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */
348 clkRate = CLK_RTC_32K_CLK;
349 break;
350 default:
351 clkRate = 0UL;
352 break;
353 }
354 SystemCoreClock = clkRate / ((SYSCON->AHBCLKDIV & 0xFFUL) + 1UL);
355 }
356
357 /* ----------------------------------------------------------------------------
358 -- SystemInitHook()
359 ---------------------------------------------------------------------------- */
360
SystemInitHook(void)361 __attribute__ ((weak)) void SystemInitHook (void) {
362 /* Void implementation of the weak function. */
363 }
364
